Apparatus and method for supplying power to a portion of an integrated circuit

Abstract

A power gating circuit includes a collection of weak-strong switch units and strong switch units chained together in a daisy chain. The layout (footprint) of each weak-strong unit is compatible with that of strong-only units such that replacing weak-strong units with strong-only units or vice versa during the design phase of the power gating circuit does not affect the routing or timing operation of the circuitry that the power gating circuit powers. This allows the ratio of weak switches to strong switches for minimizing inrush current to be optimally set during the design phase of the IC. Each weak-strong unit couples power rails together via weak transistors in response to a weak enable signal and via strong transistors in response to a strong enable signal. Each strong-only unit couples power rails together via weak and strong transistors in response to a strong enable signal.

Description

[0001] This application is a divisional application of a patent application for invention, with the international filing date of April 24, 2017, international application number PCT / US2017 / 029186, entering the Chinese national phase on November 16, 2018, Chinese national application number 201780030700.7, and the invention title of "Apparatus and Method for Supplying Power to a Portion of an Integrated Circuit via Weak-Strong and Strong-Only Switching Units".

[0002] Cross - Reference to Related Applications

[0003] This application claims the priority and benefit of non-provisional application No. 15 / 158,236, filed on May 18, 2016, with the United States Patent and Trademark Office, the entire content of which is incorporated herein by reference. Technical Field

[0004] Aspects of the present disclosure generally relate to power gating circuits, and more particularly, to apparatus and methods for supplying power to a portion of an integrated circuit (IC) using weak-strong and strong-only switching units, and methods of designing power gating circuits. Background Art

[0005] Power gating circuits are used to couple a terminal voltage rail (TVDD) to an internal voltage rail (VDD) of an integrated circuit (IC). The terminal voltage rail (TVDD) receives an external supply voltage from a battery, a regulator, or other type of source. The power gating circuit applies the external supply voltage to a portion (e.g., a core or a module) of the IC by electrically coupling the terminal voltage rail (TVDD) to the internal voltage rail (VDD).

[0006] Power gating circuits typically include a set of switching units for separately coupling the terminal voltage rail (TVDD) to the internal voltage rail (VDD). The set of switching units typically includes a subset of weak switching units and a subset of strong switching units. To limit inrush current, the weak switching units are first turned on to allow the internal power rail (VDD) to be partially charged. Then, the strong switching units are turned on to fully couple the terminal voltage rail (TVDD) to the internal voltage rail (VDD), such that the power gating circuit can supply the total current demand (e.g., dynamic current) of a portion (e.g., a core or a module) of the IC.

[0007] Typically, there is a specific ratio of weak switch units to strong switch units (or total switch units) that results in a minimized peak surge current. During the design phase of a power gating circuit, this ratio is estimated based on the design of that portion of the IC (e.g., a core or a module). If the estimated ratio proves to be inaccurate, the power gating circuit needs to be redesigned by swapping weak switch units for strong switch units or vice versa. Such swapping of units requires rerouting the connections of the power gating circuit to the IC portion and performing a timing analysis of the operations of the IC portion. This interaction among redesigning the power gating circuit, rerouting, and timing analysis complicates the design of the IC and often results in the inability to achieve the optimal ratio of weak switch units to strong switch units (or total switch units). SUMMARY OF THE INVENTION

[0008] A brief summary of one or more embodiments is presented below to provide a basic understanding of such embodiments. This "Summary of the Invention" is not an extensive overview of all contemplated embodiments, and is neither intended to identify key or critical elements of all embodiments nor to delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0009] One aspect of the present disclosure relates to an apparatus, comprising: a set of first type switch units, wherein each first type switch unit is configured to couple a first power rail to a second power rail via a first relatively weak transistor in response to a first enable signal and to couple the first power rail to the second power rail via a first relatively strong transistor in response to a second enable signal; and a set of second type switch units, wherein each second type switch unit is configured to couple the first power rail to the second power rail via a second relatively weak transistor and a second relatively strong transistor in response to the first enable signal.

[0010] Another aspect of the present disclosure relates to a method of designing a power gating circuit for supplying power to a specific circuit. The method includes: generating a first design of the power gating circuit by filling unit slots with at least one switch unit from a set of first type switch units or a set of second type switch units, wherein each first type switch unit is configured to weakly couple a first power rail to a second power rail in response to a first enable signal and wherein each first type switch unit and each second type switch unit are configured to strongly couple the first power rail to the second power rail in response to a second enable signal; determining a ratio of first type switch units to second type switch units; and generating a second design of the power gating circuit by swapping at least one first type switch unit for at least one second type switch unit or swapping at least one second type switch unit for at least one first type switch unit to achieve the above ratio.

[0011] Another aspect of the present disclosure relates to an apparatus including: a first component for coupling a first power rail to a second power rail via a first relatively weak transistor in response to a first enable signal and via a first relatively strong transistor in response to a second enable signal; and a second component for coupling the first power rail to the second power rail via a second relatively weak transistor and a second relatively strong transistor in response to the second enable signal.

[0012] To achieve the foregoing and related purposes, one or more embodiments include the features that are fully described hereinafter and particularly pointed out in the claims. The following description and the drawings set forth in detail certain illustrative aspects of one or more embodiments. However, these aspects merely indicate some of the various ways in which the principles of the various embodiments may be employed, and the description of the embodiments is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A A pair of graphs of the internal rail voltage VDD and the corresponding inrush current versus time are shown for a case where the ratio of the weak switch to the strong switch is too low, in accordance with one aspect of the present disclosure.

[0014] Figure 1B A pair of graphs of the internal rail voltage VDD and the corresponding inrush current versus time are shown for a case where the ratio of the weak switch to the strong switch is too high, in accordance with another aspect of the present disclosure.

[0015] Figure 1C A pair of graphs of the internal rail voltage VDD and the corresponding inrush current versus current are shown for a case where the ratio of the weak switch to the strong switch is set to produce substantially equal peak inrush currents, in accordance with another aspect of the present disclosure.

[0016] Figure 2 A block diagram of an exemplary power gating circuit for supplying power to a portion (e.g., a core or a module) of an integrated circuit (IC) is shown, in accordance with another aspect of the present disclosure.

[0017] Figure 3 A schematic diagram of an exemplary weak switch unit is shown, in accordance with another aspect of the present disclosure.

[0018] Figure 4 A schematic diagram of an exemplary strong switch unit is shown, in accordance with another aspect of the present disclosure.

[0019] Figure 5 A schematic diagram of an exemplary weak-strong switch unit is shown, in accordance with another aspect of the present disclosure.

[0020] Figure 6Shows a schematic diagram of an exemplary strong-only switch unit according to another aspect of the present disclosure.

[0021] Figure 7 Shows a top view of an exemplary weak-strong switch unit's coverage area (layout configuration) according to another aspect of the present disclosure.

[0022] Figure 8 Shows a top view of an exemplary strong-only switch unit's coverage area (layout configuration) according to another aspect of the present disclosure.

[0023] Figure 9 Shows a block diagram of an exemplary power gating circuit for supplying power to a portion (e.g., a core or a module) of an integrated circuit (IC) according to another aspect of the present disclosure.

[0024] Figure 10 Shows a block diagram of another exemplary power gating circuit for supplying power to a portion (e.g., a core or a module) of an integrated circuit (IC) according to another aspect of the present disclosure.

[0025] Figure 11 Shows a flowchart of an exemplary method for designing a power gating circuit according to another aspect of the present disclosure. Detailed Description

[0026] The following detailed description, presented in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0027] During the power-on operation of a portion (e.g., a core or a module) of an integrated circuit (IC), the supply voltage on the terminal power rail (TVDD) is applied to the internal power rail (VDD) via a power gating circuit. The power gating circuit typically includes a mixture of relatively weak switches (e.g., weak field effect transistors (FETs)) and relatively strong switches (e.g., strong FETs).

[0028] If all switches are turned on simultaneously during the power-on operation, the power gating circuit is configured in this way to prevent large inrush currents. Such large inrush currents can cause the IC to reset and may cause permanent damage to the IC due to, for example, electromigration.

[0029] During a power-up operation, the power gating circuit is configured to first turn on weak switches to keep the peak of an initial inrush current below a specific threshold. Once the initial inrush current reaches its peak and then stabilizes to a specific level well below the threshold, the power gating circuit is configured to turn on strong switches, such that the power gating circuit can meet the total (e.g., dynamic) current demand of the IC portion to which it supplies power.

[0030] During a power-up operation, two peaks of inrush current are observed. One peak occurs in response to the turning on of the weak switches, while the other peak occurs in response to the turning on of the strong switches. It is generally desirable for the two peaks of inrush current to be substantially equal, to achieve a peak below a desired safety threshold. As discussed in more detail below, the ratio of weak switches to strong switches determines the magnitude of the corresponding peaks.

[0031] Figure 1A A pair of graphs of the internal rail voltage VDD (e.g., from 0 to 1.1 V) and the corresponding inrush current (e.g., from 0 to 20 milliamps (ma)) versus time are shown for the case where the ratio of weak switches to strong switches is too low (in other words, there are not enough weak switches). In this case, when the weak switches are turned on, a small peak of inrush current appears, which is well below the defined safety threshold. However, when the strong switches are subsequently turned on, a large peak of inrush current appears, which may be well above the desired safety threshold. The large peak current occurs because there are too few weak switches to fully charge the internal power rail (VDD) before the strong switches are turned on.

[0032] Figure 1B A pair of similar graphs of the internal rail voltage VDD and the corresponding inrush current versus time are shown for the case where the ratio of weak switches to strong switches is too high (in other words, there are too many weak switches). In this case, when the weak switches are turned on, a large peak of inrush current appears, which is well above the defined safety threshold. However, the subsequent turning on of the strong switches results in a peak of inrush current well below the defined safety threshold.

[0033] Figure 1C A pair of similar graphs of the internal rail voltage VDD and the corresponding inrush current are shown for the case where the ratio of weak switches to strong switches is set to produce substantially equal peaks of inrush current. In this case, the turning on of the weak switches results in a peak of inrush current that is substantially equal to the peak of inrush current produced by the turning on of the strong switches. In this case, both current peaks may be below the defined safety threshold to prevent reset and damage of the IC.

[0034] Figure 2A block diagram of an exemplary power gating circuit 200 for supplying power to a portion (e.g., a core or a module) 210 of an IC is shown according to another aspect of the present disclosure. The power gating circuit 200 includes a set of weak switch units (represented by boxes labeled "W") chained together in a daisy chain. The weak switch unit W selectively couples the terminal power rail (TVDD) to the internal power rail (VDD) in response to an enable signal WK_EN (hereinafter referred to as the weak enable signal WK_EN as it is applied to the weak switch unit).

[0035] The weak enable signal WK_EN is directly applied to the first weak switch unit W (the lowest one as shown) and propagates along the daisy chain to the other weak switch units. Thus, when the weak enable signal WK_EN is generated (e.g., asserted), the first weak switch unit turns on, followed by the next weak switch unit, and so on until the last weak switch unit turns on. As discussed in further detail herein, each weak switch unit W includes a buffer (e.g., a pair of cascaded inverters) that produces a propagation delay of the weak enable signal WK_EN through each weak switch unit W. Thus, the weak switch units W sequentially couple the terminal power rail (TVDD) to the internal power rail (VDD) based on the propagated weak enable signal WK_EN.

[0036] The power gating circuit 200 also includes a set of strong switch units (represented by boxes labeled "S") chained together in a daisy chain. The strong switch unit S also selectively couples the terminal power rail TVDD to the internal power rail VDD based on an enable signal ST_EN (hereinafter referred to as the strong enable signal ST_EN as it is applied to the strong switch unit).

[0037] The strong enable signal ST_EN is directly applied to the first strong switch S (in the third row of the first column as shown) and propagates along the daisy chain to the other strong switch units. Thus, after the asserted weak enable signal WK_EN has turned on all the weak switch units W and the initial inrush current has reached its peak and then stabilized to well below a defined safety threshold, the strong enable signal ST_EN is generated (e.g., asserted), which starts the step-by-step turn-on of the strong switch units S. Similarly, each strong switch unit S includes a buffer (e.g., a pair of cascaded inverters) that produces a propagation delay of the strong enable signal ST_EN through each strong switch unit S. Thus, the strong switch units S sequentially couple the terminal power rail (TVDD) to the internal power rail (VDD) based on the propagated strong enable signal ST_EN. The turn-on of all the switch units (weak and strong) meets the total (e.g., dynamic) current demand of the portion 210 of the IC.

[0038] Figure 3FIG. shows a schematic diagram of an exemplary weak switch unit 300 according to another aspect of the present disclosure. The weak switch unit 300 is an exemplary detailed implementation of any one of the weak switch units W (such as the i-th weak switch unit) of the power gating circuit 200 discussed previously.

[0039] Specifically, the weak switch unit 300 includes an FET M3 (e.g., a p-channel metal oxide semiconductor (PMOS)), the source of the FET M3 is coupled to the terminal power rail (TVDD) and the drain is coupled to the internal power rail (VDD). The FET M3 is configured to be a relatively weak transistor (e.g., its on-resistance is higher than that of the relatively strong transistor M4 (discussed below)).

[0040] The weak switch unit 300 further includes a first inverter I 31 , the input of the first inverter I 31 is configured to receive the weak enable signal WK_EN(i) and the output is coupled to the gate of the FET M3. The weak switch unit 300 further includes a second inverter I 32 , the input of the second inverter I 32 is coupled to the output of the first inverter I 31 and the output is configured to regenerate the weak enable signal WK_EN(i + 1). If the inverter I 31 is the first unit in the daisy chain (i = 1), then the inverter I 31 directly receives the weak enable signal WK_EN(i) from a source (e.g., a power gating controller), or if the inverter I 31 is not the first unit in the daisy chain (if i ≠ 1), then the inverter I 31 receives the weak enable signal WK_EN(i) output by the previous weak switch unit. The inverter I 32 regenerates the weak enable signal WK_EN(i + 1) for the subsequent weak switch units in the daisy chain, or if the inverter I 32 is the last weak switch unit in the daisy chain, then the inverter I 32 may not be used. The pair of cascaded inverters I 31 and I 32 produce a propagation delay of the weak enable signal WK_EN.

[0041] Figure 4 FIG. shows a schematic diagram of an exemplary strong switch unit 400 according to another aspect of the present disclosure. The strong switch unit 400 is an exemplary detailed implementation of any one of the strong switch units S (such as the j-th strong switch unit) of the power gating circuit 200 discussed previously.

[0042] Specifically, the strong switch unit 400 includes a FET M4 (e.g., PMOS), the source of the FET M4 is coupled to the terminal power rail (TVDD) and the drain is coupled to the internal power rail (VDD). The FET M4 is configured as a relatively strong transistor (e.g., its on-resistance is lower than that of the weak transistor M3).

[0043] The strong switch unit 400 further includes a first inverter I 41 , the first inverter I 41 is configured such that its input receives a strong enable signal ST_EN(j) and its output is coupled to the gate of the FET M4. The strong switch unit 400 further includes a second inverter I 42 , the second inverter I 42 has its input coupled to the output of the first inverter I 41 and its output is configured to regenerate a strong enable signal ST_EN(j + 1). If the inverter I 41 is the first unit in the daisy chain (j = 1), then the inverter I 41 receives the strong enable signal ST_EN(j) directly from a source (e.g., a power gating controller), or if the inverter I 41 is not the first unit in the daisy chain (if j ≠ 1), then the inverter I 41 receives the strong enable signal ST_EN(j) output by the previous strong switch unit. The inverter I 42 regenerates the strong enable signal ST_EN(j + 1) for the subsequent strong switch unit in the daisy chain, or if the inverter I 42 is the last strong switch unit in the daisy chain, then the inverter I 42 may not be used. The pair of cascaded inverters I 41 and I 42 introduce a propagation delay for the strong enable signal ST_EN.

[0044] An issue with the power gating circuit 200 relates to setting an appropriate ratio of weak switches to strong switches during the design phase of the corresponding IC. The appropriate ratio is based on the final design of the portion of the IC (e.g., a core or a module) to which the power gating circuit 200 supplies power. However, the final design of the IC portion depends on the final design of the power gating circuit 200 because the IC portion must be properly routed to the power gating circuit, and the timing of the IC portion's operation depends on the routing to the power gating circuit.

[0045] Due to such dependencies, in the past, the ratio of weak switches to strong switches was estimated based on the predicted final design of the IC portion. During the design phase, the estimated power gating circuit design was then interfaced with the predicted IC portion design, and an analysis was performed to determine whether the estimated ratio resulted in an acceptable (but possibly unbalanced) peak surge current. If the peak surge current was acceptable, the final design was approved.

[0046] However, if the surge current is unacceptable because one of the peak surge currents exceeds a defined safety threshold (e.g., in cases where weak switches need to be added or removed), the power gating circuit needs to be redesigned. Therefore, the routing between the power gating circuit and the IC portion needs to be redesigned, and if necessary, the timing of the IC portion operation needs to be re-analyzed and re-optimized.

[0047] The reason for the need to redesign the routing between the power gating circuit and the IC portion is that the coverage area (layout configuration) of the weak switch unit 300 is different from that of the strong switch unit 400. For example, the weak switch unit 300 includes a weak enable signal WK_EN propagation line, and the strong switch unit 400 includes a strong enable signal ST_EN propagation line.

[0048] For example, if the initial ratio is too small, more weak switch units need to be added, which will make the weak enable signal WK_EN propagation line longer and the strong enable signal ST_EN propagation line shorter. This affects the routing of the IC portion (and thus its timing). Conversely, if the initial ratio is too large, some weak switch units need to be removed, which will make the weak enable signal WK_EN propagation line shorter and the strong enable signal ST_EN propagation line longer. This also affects the routing of the IC portion (and thus its timing).

[0049] Therefore, there is a need for a power gating circuit that can be redesigned or reconfigured to set an appropriate ratio of weak switches to strong switches, while not affecting the routing and timing of the final IC portion design.

[0050] Another problem with the power gating circuit 200 is that all weak switch units W are required to be daisy-chained as a group in a specific location of the portion 210 of the IC. For example, in Figure 2 the example, the weak switch units W are co-located along the lower left region of the IC portion 210. Therefore, the initial current generated by the conduction of the weak switch units W must propagate from the lower left region and disperse throughout the IC portion 210. This results in a high concentration of current in the lower left region of the IC portion 210, which may cause damage to the IC portion 210 due to, for example, electromigration.

[0051] Accordingly, there is also a need for a power gating circuit that includes weak switches (e.g., in a checkerboard pattern) distributed over an area of an IC portion.

[0052] Accordingly, an object of the present disclosure is to configure a weak switch unit and a strong switch unit to have substantially similar coverage areas (layout configurations) to allow swapping a strong switch unit with a weak switch unit (or vice versa) during the design phase without affecting the routing and timing of the portion of the IC to which power is to be supplied by the power gating circuit having those units.

[0053] Another object of the present disclosure is to configure a weak switch unit and a strong switch unit such that they can be daisy-chained together in a hybrid manner. That is, the hybrid of weak switch units and strong switch units daisy-chained together allows for more flexible placement of weak switch units between strong switch units; or, allows for more distributed (e.g., checkerboard) placement of weak switch units over the IC area to reduce local high current concentration; and thus, reduces the likelihood of damaging the IC due to electromigration.

[0054] The above objects are achieved by a new design of a weak switch unit (referred to herein as a weak-strong switch unit because it is capable of both weak coupling and strong coupling) and a new design of only a strong switch unit.

[0055] Figure 5 A schematic diagram of an exemplary weak-strong switch unit 500 according to another aspect of the present disclosure is shown. In this example, the weak-strong switch unit 500 can be the k-th unit in a daisy chain of power switch units of a power gating circuit.

[0056] Specifically, the weak-strong switch unit 500 includes a relatively strong FET M51 (e.g., PMOS), the source of the FET M51 is coupled to a terminal power rail (TVDD) and the drain is coupled to an internal power rail (VDD). The weak-strong switch unit 500 includes a relatively weak FET M52 (e.g., PMOS), the source of the FET M52 is coupled to the terminal power rail (TVDD) and the drain is coupled to the internal power rail (VDD).

[0057] The weak-strong switch unit 500 further includes a first buffer 510, the first buffer 510 includes a first inverter I 51 , the input of the first inverter I 51 is configured to receive a strong enable signal ST_EN(k) and its output is coupled to the control terminal (gate) of the strong FET M51. The first buffer 510 further includes a second inverter I 52 , the input of the second inverter I 52 is coupled to the output of the first inverter I 51 and the output is configured to regenerate a strong enable signal ST_EN(k + 1).

[0058] If the inverter I 51 is the first unit in the daisy chain (k = 1), then the inverter I 51 receives the strong enable signal ST_EN(k) directly from a source (e.g., a power gating controller), or if the inverter I 51 is not the first unit in the daisy chain (if k ≠ 1), then the inverter I 51 receives the strong enable signal ST_EN output by a previous weak-strong switch unit or a previous strong-only switch unit (depending on the type of the unit immediately preceding the weak-strong switch unit 500). The inverter I 52 regenerates the strong enable signal ST_EN(k+1) for a subsequent weak-strong switch unit or a subsequent strong-only switch unit in the daisy chain (depending on the type of the unit immediately following the weak-strong switch unit 500), or if the inverter I 52 is the last unit in the daisy chain, then the inverter I may not be used 52 .

[0059] The weak-strong switch unit 500 further includes a second buffer 520, and the second buffer 520 includes a third inverter I 53 , and the input of the third inverter I 53 is configured to receive the weak enable signal WK_EN(k) and its output is coupled to the control terminal (gate) of the weak FET M52. The second buffer 520 further includes a fourth inverter I 54 , and the input of the fourth inverter I 54 is coupled to the output of the first inverter I of the weak FET M5 53 and the output is configured to regenerate the weak enable signal WK_EN(k+1).

[0060] If the inverter I 53 is the first unit in the daisy chain (k = 1), then the inverter I 53 receives the weak enable signal WK_EN(k) directly from a source (e.g., a power gating controller), or if the inverter I 53 is not the first unit in the daisy chain (if k ≠ 1), then the inverter I 53 receives the weak enable signal WK_EN(k) output by a previous weak-strong switch unit or a previous strong-only switch unit (depending on the type of the unit immediately preceding the weak-strong switch unit 500). The inverter I 54 regenerates the weak enable signal WK_EN(k+1) for a subsequent weak-strong switch unit or a subsequent strong-only switch unit in the daisy chain (depending on the type of the unit immediately following the weak-strong switch unit 500), or if the inverter I 54 is the last weak switch in the daisy chain, then the inverter I may not be used54 。

[0061] In operation, when the asserted weak enable signal WK_EN(k) (e.g., at a high logic voltage level (e.g., TVDD)) propagates to the weak-strong switch unit 500, the asserted weak enable signal WK_EN(k) turns on the weak FET M52 during a first stage (time interval) of coupling the power rails together to weakly couple the terminal power rail (TVDD) to the internal power rail (VDD), as described above. When the asserted strong enable signal ST_EN(k) (e.g., at a high logic voltage level (e.g., TVDD)) subsequently propagates to the weak-strong switch unit 500, the asserted strong enable signal ST_EN(k) turns on the strong FET M51 during a second stage (time interval) of coupling the power rails together to strongly couple the terminal power rail (TVDD) to the internal power rail (VDD), as described above. Thus, the weak-strong switch unit 500 acts as a weak switch during the first coupling stage and as a strong switch during the second coupling stage.

[0062] Figure 6 A schematic diagram of an exemplary strong-only switch unit 600 according to another aspect of the present disclosure is shown. In this example, the strong-only switch unit 600 can be the first unit in a daisy chain of power switch units of a power gating circuit.

[0063] Specifically, the strong-only switch unit 600 includes a relatively strong FET M61 (e.g., PMOS), the source of FET M61 is coupled to the terminal power rail (TVDD) and the drain is coupled to the internal power rail (VDD). The strong-only switch unit 600 includes a relatively weak FET M62 (e.g., PMOS), the source of FET M62 is coupled to the terminal power rail (TVDD) and the drain is coupled to the internal power rail (VDD).

[0064] The strong-only switch unit 600 further includes a first buffer 610, the first buffer 610 includes a first inverter I 61 , the first inverter I 61 has an input configured to receive the strong enable signal ST_EN(l) and an output coupled to the control terminals (gates) of both the strong FET M61 and the weak FET M62. The first buffer 610 further includes a second inverter I 62 , the second inverter I 62 has an input coupled to the output of the first inverter I 61 and an output configured to regenerate the strong enable signal ST_EN(l+1).

[0065] If the inverter I 61 is the first unit in the daisy chain (l = 1), then the inverter I 61Receives the strong enable signal ST_EN(l) directly from a source (e.g., a power gating controller), or if the inverter I 61 is not the first cell in the daisy chain (if l ≠ 1), then the inverter I 61 receives the strong enable signal ST_EN(l) output by a previous weak-strong switch or a previous strong-only switch (depending on the type of the cell immediately preceding the strong-only switch unit 600). The inverter I 62 regenerates the strong enable signal ST_EN(l+1) for a subsequent weak-strong switch unit or a subsequent strong-only switch unit in the daisy chain (depending on the type of the cell immediately following the strong-only switch unit 600), or if the inverter I 62 is the last cell in the daisy chain, then the inverter I 62 may not be used.

[0066] The strong-only switch unit 600 further includes a second buffer 620, and the second buffer 620 includes a third inverter I 63 , and the input of the third inverter I 63 is configured to receive the weak enable signal WK_EN(l) and its output is coupled to the input of a fourth inverter I 64 , and the input of the third inverter I 63 is also the input of the second buffer 620. The fourth inverter I 64 further includes an output configured to regenerate the weak enable signal WK_EN(l+1).

[0067] If the inverter I 63 is the first cell in the daisy chain (l = 1), then the inverter I 63 receives the weak enable signal WK_EN(l) directly from a source (e.g., a power gating controller), or if the inverter I 63 is not the first cell in the daisy chain (if l ≠ 1), then the inverter I 63 receives the weak enable signal WK_EN(l) output by a previous weak-strong switch or a previous strong-only switch (depending on the type of the cell immediately preceding the strong-only switch unit 600). The inverter I 64 regenerates the weak enable signal WK_EN(l+1) for a subsequent weak-strong switch unit or a subsequent strong-only switch unit in the daisy chain (depending on the type of the cell immediately following the strong-only switch unit 600), or if the inverter I 64 is the last weak switch in the daisy chain, then the inverter I 64 may not be used.

[0068] In operation, the asserted weak enable signal WK_EN (e.g., at a high logic voltage level (e.g., TVDD)) propagates through only the strong switch unit 600 without affecting the operation of the strong and weak FETs M61 and M62. Thus, only the strong switch unit 600 is a delay element or path for the weak enable signal WK_EN(l). Accordingly, only the strong switch 600 can be used only in the second stage of coupling the terminal power rail (TVDD) to the internal power rail (VDD).

[0069] When the asserted strong enable signal ST_EN(l) (e.g., at a high logic voltage level (e.g., TVDD)) propagates to only the strong switch unit 600, the asserted strong enable signal ST_EN(l) turns on both the strong FET M61 and the weak FET M62 during the second stage of coupling the power rails together to strongly couple the terminal power rail (TVDD) to the internal power rail (VDD), as described above.

[0070] As discussed in more detail herein, since the configurations of the weak-strong switch unit 500 and the only-strong switch unit 600 are nearly identical, the corresponding coverage areas (layout configurations) can be made substantially the same. That is, from an input-output perspective, the weak-strong switch unit 500 is the same as the only-strong switch unit 600. For example, both units 500 and 600 include a first input for receiving the strong enable signal ST_EN, a first output for generating a regenerated strong enable signal ST_EN, a second input for coupling to the terminal power rail (TVDD), a second output for coupling to the internal power rail (VDD), a third input for receiving the weak enable signal WK_EN, and a third output for generating a regenerated weak enable signal WK_EN.

[0071] Thus, during the design phase of the power gating circuit, the only-strong switch unit 600 can be "hot swapped" with the weak-strong switch unit 500 (or vice versa), while designing the power gating circuit to achieve an appropriate ratio of weak switches to strong switches, without requiring rerouting and / or timing analysis of the portion of the IC (e.g., core or module) to be powered by the power gating circuit.

[0072] In addition, since the weak-strong switch unit 500 and the only-strong switch unit 600 have the same input and output configurations, the weak-strong switch unit 500 and the only-strong switch unit 600 can be daisy chained together. This allows the weak and strong switches to be placed on the IC area in a more flexible manner as needed. For example, the weak-strong switch units 500 can be distributed in a checkerboard pattern over the entire area of the corresponding core or module being powered.

[0073] Figure 7A top view showing the coverage area (layout configuration) of an exemplary weak-strong switching unit 700 according to another aspect of the present disclosure is shown. The layout configuration of the weak-strong switching unit 700 may be an example of the layout configuration of the weak-strong switching unit 500 discussed previously.

[0074] As shown, the weak-strong switching unit 700 includes top and bottom horizontal metallization traces serving as the power rail (VSS) 710 (e.g., ground) of the weak-strong switching unit 700. Via internal metallization traces (represented by dashed lines), the power rail (VSS) 710 can be coupled to the sources of n-channel metal-oxide-semiconductor (NMOS) FETs (not shown) used in inverters I 51 、I 52 、I 53 and I 54 .

[0075] The weak-strong switching unit 700 also includes a central horizontal metallization trace 730 serving as an internal power rail (VDD). Via internal metallization traces, the internal power rail (VDD) is coupled to the drains of the weak FET and the strong FETs M51 and M52. Moreover, via internal metallization traces, the internal power rail (VDD) is coupled to the sources of PMOS FETs (not shown) used in I 51 、I 52 、I 53 and I 54 .

[0076] The weak-strong switching unit 700 also includes a pair of horizontal metallization traces 720 serving as a terminal power rail (TVDD). One of the pair of metallization traces 720 is located between the top power rail (VSS) metallization trace 710 and the internal power rail (VDD) metallization trace 730. The other of the pair of metallization traces 720 is located between the bottom power rail (VSS) metallization trace 710 and the internal power rail (VDD) metallization trace 730. Via internal metallization traces, the terminal power rail (TVDD) is coupled to the sources of the weak and strong FETs M51 and M52.

[0077] The weak-strong switching unit 700 also includes a metallization trace 740 for receiving a strong enable signal ST_EN(k) and a metallization trace 750 for generating a regenerated strong enable signal ST_EN(k + 1). Via internal metallization traces, the strong enable signal ST_EN(k) is coupled to the corresponding PMOS and NMOS gates of inverter I 51 . Via internal metallization traces, the drains of the PMOS and NMOS of inverter I 51 are coupled to the control terminal (gate) of the strong FET M51. Via internal metallization traces, the PMOS and NMOS gates of inverter I 52 are coupled to inverter I51 The drains of the PMOS and NMOS. Moreover, the regenerated strong enable signal ST_EN(k+1) is generated at the drains of the PMOS and NMOS of inverter I 52 .

[0078] Similarly, the weak-strong switch unit 700 further includes a metallization trace 760 for receiving the weak enable signal WK_EN(k) and a metallization trace 770 for generating the regenerated weak enable signal WK_EN(k+1). Via internal metallization traces, the weak enable signal WK_EN(k) is coupled to the gates of the corresponding PMOS and NMOS of inverter I 53 . Via internal metallization traces, the drains of the PMOS and NMOS of inverter I 53 are coupled to the control terminal (gate) of the weak FET M52. Via internal metallization traces, the gates of the PMOS and NMOS of inverter I 54 are coupled to the drains of the PMOS and NMOS of inverter I 53 . Moreover, the regenerated weak enable signal WK_EN(k+1) is generated at the drains of the PMOS and NMOS of inverter I 54 .

[0079] Figure 8 A top view showing the coverage area (layout configuration) of an exemplary strong-only unit 800 according to another aspect of the present disclosure is shown. The layout configuration of the strong-only switch unit 800 can be an example of the layout configuration of the strong-only switch unit 600 discussed previously.

[0080] As shown, the strong-only switch unit 800 includes top and bottom horizontal metallization traces serving as the power rails (VSS) 810 (e.g., ground) of the strong-only switch unit 800. Via internal metallization traces (represented by dashed lines), the power rail (VSS) 810 can be coupled to the sources of NMOS FETs (not shown) used in inverters I 61 , I 62 , I 63 and I 64 .

[0081] The strong-only switch unit 800 further includes a central horizontal metallization trace 830 serving as an internal power rail (VDD). Via internal metallization traces, the internal power rail (VDD) is coupled to the drains of the weak FET and the strong FETs M61 and M62. Moreover, via internal metallization traces, the internal power rail (VDD) is coupled to the sources of PMOS FETs (not shown) used in I 61 , I 62 , I 63 and I 64 .

[0082] Only the strong switch unit 800 further includes a pair of horizontal metallization traces 820 serving as a terminal power rail (TVDD). One of the pair of metallization traces 820 is located between the top power rail (VSS) metallization trace 810 and the internal power rail (VDD) metallization trace 830. The other of the pair of metallization traces 820 is located between the bottom power rail (VSS) metallization trace 810 and the internal power rail (VDD) metallization trace 830. Via an internal metallization trace, the terminal power rail (TVDD) is coupled to the sources of the weak and strong FETs M61 and M62.

[0083] Only the strong switch unit 800 further includes a metallization trace 840 for receiving a strong enable signal ST_EN(l) and a metallization trace 850 for generating a regenerated strong enable signal ST_EN(l+1). Via an internal metallization trace, the strong enable signal ST_EN(l) is coupled to the gates of the PMOS and NMOS of inverter I 61 . Via an internal metallization trace, the drains of the PMOS and NMOS of inverter I 61 are coupled to the control terminals (gates) of the strong and weak FETs M61 and M62. Via an internal metallization trace, the gates of the PMOS and NMOS of inverter I 62 are coupled to the drains of the PMOS and NMOS of inverter I 61 . Moreover, the regenerated strong enable signal ST_EN(l+1) is generated at the drains of the PMOS and NMOS of inverter I 62 .

[0084] Similarly, only the strong switch unit 800 further includes a metallization trace 860 for receiving a weak enable signal WK_EN(l) and a metallization trace 870 for generating a regenerated weak enable signal WK_EN(l+1). Via an internal metallization trace, the weak enable signal WK_EN(l) is coupled to the gates of the PMOS and NMOS of inverter I 63 . Via an internal metallization trace, the gates of the PMOS and NMOS of inverter I 64 are coupled to the drains of the PMOS and NMOS of inverter I 63 . Moreover, the regenerated weak enable signal WK_EN(l+1) is generated at the drains of the PMOS and NMOS of inverter I 64 .

[0085] A comparison of the coverage area (layout configuration) of the weak-strong switch unit 700 with that of the strong-only switch unit 800 shows that the two units are substantially the same. For example, from the perspective of input and output, units 700 and 800 are the same. That is, both units 700 and 800 include: metallization traces 710 and 810 of the same configuration for the power rail (VSS); metallization trace 820 of the same configuration for the terminal power rail (TVDD); metallization traces 830 of the same configuration for the internal power rail (VDD); metallization traces of the same configuration for receiving the strong enable signals ST_EN(k) and ST_EN(l); metallization traces of the same configuration for generating the regenerated strong enable signals ST_EN(k+1) and ST_EN(l+1); metallization traces of the same configuration for receiving the weak enable signals WK_EN(k) and WK_EN(l); and metallization traces of the same configuration for generating the regenerated weak enable signals WK_EN(k+1) and WK_EN(l+1).

[0086] Therefore, replacing (“hot swapping”) the weak-strong switch unit 700 with the strong-only switch unit 800 or vice versa during the design phase of the power gating circuit will not affect the routing between the power gating circuit and the portion of the IC that is powered by the power gating circuit.

[0087] In addition, the sizes and layouts of the weak-strong switch unit 700 and the strong-only switch unit 800 are substantially similar, with the following minor differences in their respective internal metallization traces: (1) In the weak-strong switch unit 700, the internal metallization traces electrically connect the outputs of inverters I 51 and I 53 to the gates of FETs M51 and M52; (2) In the strong-only switch unit 800, the internal metallization trace only electrically connects the output of inverter I 61 to the gates of FETs M61 and M62 (instead of electrically connecting the output of inverter I 63 to the gates of FETs M61 and M62).

[0088] Because the sizes and layouts of units 700 and 800 are substantially similar, they exhibit substantially the same parasitic reactance from the perspective of the portion of the IC to which the units are connected. Therefore, replacing (“hot swapping”) the weak-strong switch unit 700 with the strong switch unit 800 or vice versa during the design phase of the power gating circuit will not affect the timing operation of the portion of the IC that is powered by the power gating circuit.

[0089] Figure 9FIG. shows a schematic diagram of an exemplary power gating circuit 900 for a portion 910 (e.g., a core or a module) of an IC according to another aspect of the present disclosure. The power gating circuit 900 includes a hybrid daisy chain having a mix of weak-strong switch units WS and strong-only switch units S. Each weak-strong switch unit WS may be configured to be similar to the previously discussed weak-strong switch units 500 and / or 700. Each strong-only switch unit S may be configured to be similar to the previously discussed strong-only switch units 600 and / or 800.

[0090] Each of the units WS and S is coupled between a terminal power rail (TVDD) and an internal power rail (VDD). Each of the units WS and S receives a strong enable signal ST_EN and a weak enable signal WK_EN, either from the power gating controller 920 if it is the first unit in the daisy chain, or from the previous unit if it is not the first unit in the daisy chain. Except for the last switch unit in the daisy chain, each of the units WS and S passes the strong enable signal ST_EN and the weak enable signal WK_EN to the subsequent unit in the daisy chain.

[0091] In this example, the power gating circuit 900 includes a total of 100 switch units S and WS. Among the 100 units, there are 90 strong-only switch units S and 10 weak-strong switch units WS. The total number of units (e.g., 100 units) is selected to meet the total current demand (e.g., dynamic current demand) of the IC portion 910. In this example, the ratio of weak switches to strong switches is 10%. Similarly, as discussed, this ratio is selected to substantially equalize the peak inrush current resulting from the turn-on of the weak switches followed by the turn-on of the strong switches.

[0092] In addition, in this example, the first unit in the daisy chain is a weak-strong unit WS. Thus, the strong enable signal ST_EN and WK_EN are applied to this first weak-strong unit WS. After the first unit in the daisy chain, there is a series of strong-only units (e.g., nine (9)) before another weak-strong switch unit WS is encountered. This daisy chain configuration (one (1) weak-strong switch unit WS, followed by nine (9) strong-only switch units S) is repeated 10 times in the power gating circuit 900 to achieve a total of 100 switch units, 10 of which are weak-strong switch units WS and 90 of which are strong-only switch units S.

[0093] As shown, the weak-strong switch units WS are substantially distributed over the entire area of the portion 910 of the IC. This reduces the current concentration that would occur if all the weak switch units were co-located in a particular area (such as in the previously discussed power gating circuit 200).

[0094] In operation, in response to receiving a command to power up a portion 910 of the IC, the power gating controller 920 generates (e.g., asserts) a weak enable signal (WK_EN) (e.g., sets the signal WK_EN to a logic high voltage level (e.g., TVDD)). The asserted weak enable signal WK_EN gradually turns on the weak FET M52 as it encounters each weak-strong switch unit WS as it propagates through the daisy chain. Only the strong unit S does not turn on in response to the asserted weak enable signal WK_EN because only the strong unit only allows the signal to pass through. The turning on of the weak-strong unit WS gradually couples the terminal power rail (TVDD) to the internal power rail (VDD) to limit the peak inrush current to below a defined safety threshold.

[0095] After a defined time interval of the assertion of the weak enable signal WK_EN (e.g., a sufficient time interval for the first inrush current to stabilize to a defined level below the defined safety threshold), the power gating controller 920 generates (e.g., asserts) a strong enable signal ST_EN (e.g., sets the signal ST_EN to a logic high voltage level (e.g., TVDD)). The asserted strong enable signal ST_EN gradually turns on the strong FET M51 as it encounters each weak-strong switch unit WS as it propagates through the daisy chain, and gradually turns on the strong and weak FETs M61 and M62 as it encounters each strong-only switch unit S as it propagates through the daisy chain. Since the internal power rail (VDD) has been pre-charged by turning on the weak FET M52 in the weak-strong switch unit WS in response to the asserted weak enable signal WK_EN, the turning on of the strong-only unit S gradually and fully couples the terminal power rail (TVDD) to the internal power rail (VDD) such that the second inrush current peak is also below the defined safety threshold.

[0096] Figure 10 A schematic diagram of an exemplary power gating circuit 1000 for supplying power to a portion 1010 (e.g., a core or module) of an IC in accordance with another aspect of the present disclosure is shown. The power gating circuit 1000 includes a hybrid daisy chain having 90 strong-only switch units S and 10 weak-strong switch units WS. As shown, the 10 weak-strong switch units WS are daisy chained together in a uniform group (lower left side), and the remaining strong-only switch units S are daisy chained in a uniform group after the weak-strong switches WS. This is to illustrate that the weak-strong switch units WS and the strong-only switches S can be placed across the entire area of the portion 1010 of the IC as needed.

[0097] The power - on operation is similar to the power - on operation of the power gating circuit 900. In response to receiving a command to power - on a portion 1010 of the IC, the power gating controller 1020 generates (e.g., asserts) a weak enable signal WK_EN, which causes the weak FET M52 of the weak - strong switch unit WS to gradually couple the terminal power rail (TVDD) to the internal power rail (VDD). Then, after a defined time interval of the assertion of the weak enable signal WK_EN, the power gating controller 1020 generates (e.g., asserts) a strong enable signal ST_EN, which causes the strong FETs M51 and M61 of the weak - strong switch unit WK and the only - strong unit (and the weak FET M62 of the only - strong switch unit S) to further gradually couple the terminal power rail (TVDD) to the internal power rail (VDD).

[0098] Figure 11 A flowchart of an exemplary method 1100 for designing a power gating circuit according to another aspect of the present disclosure is shown. Method 1100 includes determining the total number of switch units for the power gating circuit design (block 1102). The total number of switch units can be determined based on the total current demand (e.g., dynamic current) of the portion (e.g., core or module) of the IC to which the power gating circuit of the IC will supply power.

[0099] Additionally, method 1100 includes determining an estimated ratio of weak switches to strong switches for the power gating circuit design (block 1104). As previously described, this ratio can depend on various factors, including the size, circuit density, and routing congestion of the portion of the IC to which the power gating circuit will supply power. Design tools can be used to determine such an estimated ratio. As previously described, the ratio of weak switches to strong switches is estimated to achieve a substantially balanced peak surge current below a defined safety threshold.

[0100] Then, method 1100 further requires generating a preliminary design of the power gating circuit by filling unit slots with weak - strong switch units WS and only - strong switch units S based on the estimated ratio (block 1106). For example, if the estimated ratio is 10% and there are a total of 100 switch units in the power gating circuit design, then 10 unit slots are filled with weak - strong switch units WS, and 90 unit slots are filled with only - strong source switch units S. To achieve a balanced distribution of weak - strong switch units WS among the only - strong switch units S, every 10th slot can be filled with a weak - strong switch unit WS. The preliminary design of the power gating circuit can be in a format for generating a mask for manufacturing the IC, such as the Global Database System II (GDSII) format, OASIS, etc.

[0101] Then, according to method 1100, the design of the IC part (e.g., core or module) powered by the power gating circuit is completed (block 1108). This may require designing the routing between the power gating circuit and the IC part and performing timing analysis and optimization based on the designed routing.

[0102] Method 1100 also includes generating a temporary design of the power gating circuit by filling all cell slots with only strong switch units S (block 1110). Then, according to method 1100, the final ratio of weak switches to strong switches is determined based on the final design of the part of the IC (e.g., core or module) (block 1112). The final ratio may be different from the estimated ratio determined in block 1104.

[0103] Then, according to method 1100, based on the final ratio, some of the only strong switch units S are replaced ("hot swapped") with weak-strong switch units WS (block 1114). For example, if the final ratio is nine (9), then in order to achieve a balanced distribution of weak-strong switch units WS among the only strong switch units S, every 9th only strong switch unit is "hot swapped" with a weak-strong switch unit WS. Since both types of switch units S and WS are coverage area compatible, the hot swapping of only strong switch units S with weak-strong switch units WS does not affect the routing or timing operation of the part of the IC (e.g., core or module).

[0104] The foregoing description of the present invention has been provided to enable a person skilled in the art to make or use the present invention. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: A set of first type switch units (500), wherein each first type switch unit in the set of first type switch units is configured to couple a first power rail (TVDD) to a second power rail (VDD) via a first relatively weak transistor (M52) in response to a first enable signal (WK_EN), and to couple the first power rail to the second power rail via a first relatively strong transistor (M51) in response to a second enable signal (ST_EN), wherein the on-resistance of the first relatively weak transistor is higher than the on-resistance of the first relatively strong transistor, and wherein each first type switch unit in the set of first type switch units includes: The first inverter (I 51 ) of the first type of switch unit includes a first input configured to receive the second enable signal and a first output coupled to a control terminal of the first relatively strong transistor; and The second inverter (I 52 ) of the first type of switch unit includes a second input coupled to the first output of the first inverter and a second output configured to regenerate the second enable signal; and A set of second type switch units (600), wherein each second type switch unit in the set of second type switch units is configured to couple the first power rail to the second power rail via a second relatively weak transistor (M62) and a second relatively strong transistor (M61) in response to the second enable signal, and to transmit the first enable signal without applying the first enable signal to the second relatively weak transistor or the second relatively strong transistor, wherein the on-resistance of the second relatively weak transistor is higher than the on-resistance of the second relatively strong transistor, and wherein each second type switch unit in the set of second type switch units includes: The first inverter (I 61 ) of the second type of switching unit includes a first input configured to receive the second enable signal and a first output coupled to respective control terminals of the second relatively strong transistor and the second relatively weak transistor; and The second inverter (I 62 ) of the second type of switch unit includes a second input coupled to the first output of the first inverter and a second output configured to regenerate the second enable signal. wherein the layout configuration in the set of first type switch units is substantially the same as the layout configuration in the set of second type switch units, and wherein the substantially same layout configuration includes substantially similar coverage areas.

2. The apparatus according to claim 1, wherein each first type switch unit in the first type switch units includes a first metallization trace and a second metallization trace, the first metallization trace is configured to receive the first enable signal, the second metallization trace is configured to receive the second enable signal, each second type switch unit in the second type switch units includes a third metallization trace and a fourth metallization trace, the third metallization trace is configured to receive the first enable signal, the fourth metallization trace is configured to receive the second enable signal, the first metallization trace is configured to be substantially the same as the third metallization trace, and the second metallization trace is configured to be substantially the same as the fourth metallization trace.

3. The apparatus according to claim 1, wherein each first type switch unit in the first type switch units includes: The third inverter (I 53 ) of the first type of switch unit includes a first input configured to receive the first enable signal and a first output coupled to a control terminal of the first relatively weak transistor; And The fourth inverter (I 54 ) of the first type of switch unit includes a second input coupled to the first output of the first inverter and a second output configured to regenerate the first enable signal.

4. The apparatus according to claim 1, wherein each second type switch unit in the second type switch units includes a buffer configured to receive and transmit the first enable signal.

5. The apparatus according to claim 1, wherein each second type switch unit in the second type switch units includes: The third inverter (I 63 ) of the second type of switch unit includes a first input configured to receive the first enable signal; And The fourth inverter (I 64 ) of the second type of switch unit includes a second input coupled to a first output of the first inverter and a second output configured to regenerate the first enable signal.

6. The apparatus according to claim 5, wherein the first output of the third inverter is disconnected from the control terminals of the second relatively strong transistor and the second relatively weak transistor.

7. The apparatus according to claim 1, wherein the set of first type switch units and the set of second type switch units are daisy chained.

8. The apparatus according to claim 1, wherein a set of the first type of switch units and a set of the second type of switch units are daisy-chained such that a first subset of the second type of switch units is located before at least one of the first type of switch units in the first type of switch units, and a second subset of the second type of switch units is after the at least one of the first type of switch units in the first type of switch units.

9. The apparatus according to claim 1, wherein a set of the first type of switch units and a set of the second type of switch units are daisy-chained such that all of the first type of switch units in the set of the first type of switch units are located before all of the second type of switch units in the set of the second type of switch units.

10. The apparatus according to claim 1, further comprising a controller configured to generate the first enable signal and the second enable signal in response to a command.

11. The apparatus according to claim 10, wherein the controller is configured to generate the second enable signal after a defined time interval of the generation of the first enable signal.

12. A method of designing a power gating circuit for supplying power to a specific circuit, comprising: A first design of a power gating circuit is generated by filling a cell slot with at least one switch unit from the set of first type switch units (500) or the set of second type switch units (600), wherein each first type switch unit in the set of first type switch units is configured to weakly couple a first power rail (TVDD) to a second power rail (VDD) in response to a first enable signal (WK_EN), and to transmit a second enable signal (ST_EN), and wherein each switch unit in the set of first type switch units and the set of second type switch units is configured to strongly couple the first power rail to the second power rail in response to the second enable signal (ST_EN), and wherein each first type switch unit in the set of first type switch units includes: The first inverter (I 51 ) of the first type of switch unit includes a first input configured to receive the second enable signal and a first output coupled to a control terminal of a first relatively strong transistor; and The second inverter (I 52 ) of the first type of switch unit includes a second input coupled to the first output of the first inverter and a second output configured to regenerate the second enable signal; and wherein each second type switch unit in the set of second type switch units includes: The first inverter (I 61 ) of the second type of switch unit includes a first input configured to receive the second enable signal and a first output coupled to respective control terminals of a second relatively strong transistor and a second relatively weak transistor; and The second inverter (I 62 ) of the second type of switch unit includes a second input coupled to the first output of the first inverter and a second output configured to regenerate the second enable signal. wherein the layout configuration in the set of first type switch units is substantially the same as the layout configuration in the set of second type switch units, and wherein the substantially same layout configuration includes substantially similar coverage areas; Determining a ratio of the first type switch units to the second type switch units; and A second design of the power gating circuit is generated by replacing at least one first type switch unit in the first type switch units with at least one second type switch unit in the second type switch units or replacing at least one second type switch unit in the second type switch units with at least one first type switch unit in the first type switch units to achieve the ratio.

13. The method according to claim 12, wherein each of the first type of switch units in the first type of switch units includes a first metallization trace and a second metallization trace, the first metallization trace being configured to receive the first enable signal, the second metallization trace being configured to receive the second enable signal, each of the second type of switch units in the second type of switch units includes a third metallization trace and a fourth metallization trace, the third metallization trace being configured to receive the first enable signal, the fourth metallization trace being configured to receive the second enable signal, the first metallization trace being configured to be substantially the same as the third metallization trace, and the second metallization trace being configured to be substantially the same as the fourth metallization trace.

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