Apparatus and method for providing power in response to internal power usage

Abstract

The present disclosure relates to apparatuses and methods for providing power in response to internal power usage. Apparatuses and methods for controlling internal current are disclosed herein. An example apparatus includes a semiconductor device that includes a power node. The semiconductor device receives power as an internal current and further operates in a first mode and a second mode. The semiconductor device consumes more power in the second mode than in the first mode. The semiconductor device consumes a first portion of the internal current during the first mode and provides a second portion of the internal current at the power node as an external current. The semiconductor device consumes a third portion of the internal current that is greater than the first portion of the internal current during the second mode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices; in particular, to apparatuses and methods for providing power in response to internal power usage. BACKGROUND

[0002] Semiconductor devices, such as memory devices and processors, receive a supply of power from an external power source. Internal current in the semiconductor devices can depend on their internal operations. Wires are used as positive and negative power supply lines between the external power source and these devices. These wires have an inherent resistance or impedance. Due to changes in internal current between different internal operations that consume different amounts of power, there are voltage drops in the two power supply lines. These voltage drops through the wires cause inherent delays in clock signals and other timing critical signals.

[0003] To prevent these inherent delays, typical implementations have used voltage regulators or delay locked loop (DLL) circuits. DLL circuits lock the phase between these timing signals to control the inherent delays of these timing signals. However, another approach can be desired to compensate for fluctuations in internal current and can be implemented in a simpler way without the need for complex DLL circuits. SUMMARY

[0004] In one aspect, the present disclosure relates to an apparatus comprising: a semiconductor device comprising a power node, the semiconductor device configured to receive power as an internal current, and further configured to operate in a first mode and a second mode, wherein the semiconductor device is configured to consume more power in the second mode than in the first mode, wherein the semiconductor device is configured to consume a first portion of the internal current, and further configured to provide a second portion of the internal current at the power node as an external current during the first mode, and wherein the semiconductor device is further configured to consume a third portion of the internal current greater than the first portion of the internal current during the second mode.

[0005] In another aspect, the present disclosure relates to an apparatus comprising: a power source configured to provide power; a semiconductor device configured to receive the power from the power source as an internal current, and further configured to operate in a first mode and a second mode; and an electrical device configured to be coupled to the semiconductor device; wherein the semiconductor device is further configured to provide at least a portion of the internal current to the electrical device as an external current during the first mode.

[0006] In another aspect, the disclosure relates to a method comprising: receiving, by a semiconductor device, power from a power source as an internal current; operating the semiconductor device in a first mode and a second mode; and providing, during the first mode, at least a portion of the internal current to an electrical device configured to be coupled to the semiconductor device as an external current. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic block diagram of an apparatus including a semiconductor device according to an embodiment of the disclosure.

[0008] Figure 2 is a schematic block diagram of an apparatus including a memory device, a memory controller, and an electrical device according to an embodiment of the disclosure.

[0009] Figure 3A and 3B is a block diagram of an apparatus including a memory device including a command decoder, a memory controller, and an electrical device according to an embodiment of the disclosure.

[0010] Figure 4A and 4B is a block diagram of an apparatus including a semiconductor device, a power manager, and an electrical device according to an embodiment of the disclosure.

[0011] Figure 5A and 5B is a block diagram of an apparatus including a semiconductor device, a power manager, and an electrical device according to an embodiment of the disclosure.

[0012] Figure 6A and 6B is a block diagram of an apparatus including a semiconductor device including a sensor and an electrical device according to an embodiment of the disclosure.

[0013] Figure 7A , 7B and 7C is a block diagram of an apparatus including a semiconductor device, a power manager, and an energy storage device according to an embodiment of the disclosure.

[0014] Figure 8A is a block diagram of an apparatus including a memory device including a command decoder, a memory controller, and an electrical device according to an embodiment of the disclosure.

[0015] Figure 8B is a block diagram of an apparatus including a memory device including a command decoder, a memory controller, and an electrical device according to an embodiment of the disclosure. Figure 8A is a table of commands from a memory controller to a command decoder in DETAILED DESCRIPTION

[0016] Various embodiments of the present disclosure will be explained in detail below with reference to the drawings. The following detailed description references the drawings, wherein like numerals indicate like elements, and wherein the various detailed descriptions refer to specific aspects and embodiments of the present disclosure. The detailed description is included to provide a complete understanding of embodiments of the present disclosure, and is not limiting of the present disclosure. Embodiments of the present disclosure can be utilized in other embodiments and can undergo modifications and / or alterations, and can be used in other aspects, structures, and / or applications without departing from the scope of the present disclosure. Various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form a new embodiment.

[0017] Embodiments of the present disclosure can be used with and / or include devices that include semiconductor devices. The semiconductor devices can be processor units, such as central processing unit (CPU) units, graphics processing unit (GPU) units. In some embodiments of the present disclosure, the semiconductor devices can be memory devices. In some embodiments of the present disclosure, the memory devices can be dynamic random access memory (DRAM), such as double data rate (DDR) synchronous dynamic random access memory (SDRAM) interfaces of several generations with double data rate for high bandwidth. In some embodiments of the present disclosure, the memory devices can be graphics DDR SDRAM (GDDR) of several generations with less access latency and high bandwidth, or low power DDR SDRAM (LPDDR) of several generations. In some embodiments of the present disclosure, the memory devices can be high bandwidth memory of several generations as vertical integrated memory, such as three-dimensional stacked SDRAM including multiple stacked memory arrays operating as a single memory device.

[0018] Figure 1is a schematic block diagram of an apparatus 10 including a semiconductor device according to embodiments of the present disclosure. The apparatus 10 can be an electronic device including one or more devices and components that operate with supplied power. The apparatus 10 can include a power source 11, a semiconductor device 13, and wires 121 and 122. Each of the wires 121 and 122 can have one end coupled to the power source and another end coupled to the semiconductor device 13. Thus, the wires 121 and 122 can couple the semiconductor device 13 to the power source 11, and the power source 11 can provide power to the semiconductor device 13 via the wires 121 and 122. For example, the power source 11 can provide internal current to the semiconductor device 13 via the wires 121 and 122. Examples of the power source 11 include a battery that stores power and a power controller that receives external power and provides internal power. The apparatus 10 can further include an electrical device 15 that can be coupled to the semiconductor device 13. In some embodiments, the electrical device 15 can include a power consumer circuit that consumes power. In some embodiments, the electrical device 15 can include a power generator circuit that generates power. The apparatus 10 can also include wires 181 and 182 that can couple the electrical device 15 to power nodes 191 and 192 of the semiconductor device 13. By providing at least a portion of the internal current as external current from the power nodes 191 and 192 on the wires 181 and 182 to the electrical device 15 or not providing the internal current from the power nodes 191 and 192 to the electrical device 15, the load on the power source 11 can be adjusted to stabilize the internal current.

[0019] Different operations of the semiconductor device 13 can consume different amounts of power. For example, during an active period in which the semiconductor device 13 performs operations with high power consumption, the semiconductor device 13 can consume more power supplied by the power source 11 via the wires 121 and 122. On the other hand, during an inactive period in which the semiconductor device 13 performs operations with low power consumption, the semiconductor device 13 can consume less power. During the inactive period, the semiconductor device 13 can provide at least a portion of the internal current as external current to the wires 181 and 182 at the power nodes 191 and 192. The electrical device 15 can receive the external current from the wires 181 and 182 and can be driven to operate by the external current. Because the semiconductor device 13 and the electrical device 15 together become a load on the power source 11 in the inactive period, while only the semiconductor device 13 is the load of the power source 11 in the active period, the internal current between the semiconductor device 13 and the power source 11 can become stabilized. Even though the wires 121 and 122 can have resistance, because the internal current can be maintained relatively stable, the voltage drop of the wires 121 and 122 between the power source 11 and the semiconductor device 13 can be substantially the same between the active and inactive periods due to the stability of the internal current. Thus, the voltage drop at the wires 121 and 122 can be substantially constant across operations. Subsequently, the amount of delay of inherent delay within the semiconductor device 13 caused by the voltage drop at the wires 121 and 122 can be stabilized between the active and inactive periods.

[0020] In some embodiments of the disclosure, the electrical device 15 can be an electrical device that is operable to achieve the purpose of the apparatus regardless of the condition of the external current on the wires 181 and 182. For example, the electrical device 15 can be an electrical device in which the timing of receiving the external current or the amount of the external current can not be critical to its operation. In some embodiments of the disclosure, the electrical device 15 can be an electrical device that can radiate heat, such as a fan or a thermoelectric cooler (e.g., a Peltier element). In some embodiments of the disclosure, the electrical device 15 can be an electrical device that can emit light, such as a light emitting diode (LED). In some embodiments of the disclosure, the electrical device 15 can be an electrical device that can store energy, such as a capacitor or a battery.

[0021] Figure 2 is a schematic block diagram of an apparatus 20 including a memory device 23, a memory controller 24, and an electrical device 25 according to embodiments of the disclosure. In some embodiments of the disclosure, the apparatus 20 can be a personal computer (PC), such as a gaming PC, a desktop PC, a laptop PC, or a graphics PC or a mobile computer. However, the apparatus 20 can not be limited to a computer. The apparatus 20 can include a power supply 21 that can supply power to the device 23. The apparatus 20 can include wires 221 and 222 that can couple the semiconductor device 23 to the power supply 21. For example, the power supply 21 can provide an internal current to the semiconductor device 23 via the wires 221 and 222. The apparatus 20 can include one or more electrical devices 25 that can be coupled to the memory device 23. The apparatus 20 can also include wires 281 and 282 that can couple the electrical device 25 to power nodes 291 and 292 of the memory device 23. By providing at least a portion of the internal current as an external current from the power nodes 291 and 292 on the wires 281 and 282 to the electrical device 25 or not providing the internal current from the power nodes 291 and 292 to the electrical device 25, the load on the power supply 21 can be adjusted to stabilize the internal current. For example, the load on the power supply 21 can be adjusted to adjust the portion of the internal current as the external current to a greater amount or a lesser amount.

[0022] Memory device 23 can perform different operations that can consume different amounts of power. Memory controller 24 can provide commands CMD to instruct control of operations of memory device 23. Memory device 23 can receive commands CMD and, in response to commands CMD, can perform operations. For example, during an active period in which memory device 23 performs memory access operations that have high power consumption, memory device 23 can consume more power that is delivered as internal current supplied by power supply 21 via wires 221 and 222. Examples of memory access operations that have high power consumption include read or write operations in response to read or write commands and / or memory accesses to addresses included in commands that can consume relatively more power. On the other hand, during an inactive period in which memory device 23 performs operations that have low power consumption, memory device 23 can consume less power that is delivered as internal current. Examples of operations that have low power consumption include precharge or memory address accesses that can consume relatively less power. A portion of internal current used by memory device 23 during high power consumption operations is greater than a portion of internal current used by memory device 23 during low power consumption operations.

[0023] During an inactive period, memory device 23 can provide at least a portion of internal current as external current to wires 281 and 282. Electrical device 25 can receive external current from wires 281 and 282 and can be driven in operation by external current. Because memory device 23 and electrical device 25 together become a load on power supply 21 in an inactive period, whereas only or primarily semiconductor device 23 becomes a load of power supply 21 in an active period, internal current that memory device 23 can receive from power supply 21 can become stable. Accordingly, voltage drop at wires 221 and 222 can be substantially constant across operations. Subsequently, an amount of delay of inherent delay within semiconductor device 13 caused by voltage drop at wires 221 and 222 can be stable across operations.

[0024] In some embodiments of the disclosure, electrical device 25 can be any electrical device that can receive external current from wires 281 and 282. Electrical device 25 can further consume power by operating to achieve a purpose of the electrical device using received external current. Electrical device 25 can be an electrical device in which timing of receiving external current or an amount of external current can not be critical to electrical device 25. In some embodiments of the disclosure, electrical device 25 can radiate heat, such as a fan or a thermoelectric cooler. In some embodiments of the disclosure, electrical device 25 can emit light, such as a light emitting diode (LED). In some embodiments of the disclosure, electrical device 25 can store energy, such as a capacitor or a battery.

[0025] Figure 3A and 3Bis a block diagram of an apparatus 30 including a memory device 33 (which includes a command decoder 36), a memory controller 34, and an electrical device 35 according to embodiments of the present disclosure. The apparatus 30 can be the apparatus 20 in Figure 2 , and the memory device 33 can be the memory device 23 in Figure 2 . In the memory device 33, the command decoder 36 can receive a command from the memory controller 34 and control internal circuitry (not shown) according to an operation indicated by the command. The memory device 33 can receive internal current from the power supply 31 via the wires 321 and 322. The memory device 33 can provide external current from the power nodes 391 and 392 to the wires 381 and 382 coupled to the electrical device 35. The memory device 33 can further include switches 371 and 372. The switch 371 can connect the wire 321 to the power node 391 to provide power on the wire 321 to the power node 391, and the switch 372 can connect the wire 322 to the power node 392 to provide power on the wire 322 to the power node 392, respectively. The apparatus 30 can include the wires 381 and 382 that can couple the electrical device 35 to the power nodes 391 and 392 of the memory device 33. In some embodiments, the command decoder 36 acts as a power manager. The command decoder 36 can control turning on and off of the switches 371 and 372.

[0026] In one example shown in Figure 3A , the memory controller 34 can provide a first command CMD1 for a memory operation in a low power consumption. For example, the first command CMD1 can be a precharge command or a self-refresh command. In the memory device 33, the command decoder 36 can receive the first command CMD1, and in response to the first command CMD1, the command decoder 36 can control the internal circuitry to perform an operation indicated in the first command CMD1. For example, in a precharge operation, the memory device 33 can control the circuitry in a manner that a bit line to be accessed is precharged to a precharge voltage. In response to the first command CMD1, the command decoder 36 can further provide a control signal (CTRL ON) in an active state to the switches 371 and 372. In response to the control signal in the active state, the switch 371 can connect the wire 321 to the wire 381 coupled to the power node 391, and the switch 372 can connect the wire 322 to the wire 382 coupled to the power node 392, respectively. The internal current on the wires 321 and 322 from the power supply 31 can be further provided as the external current on the wires 381 and 382 to the electrical device 35. Thus, the power provided to the memory device 33 as the internal current can be used for the operation (e.g., precharge or self-refresh) in the memory device 33 as well as for the operation performed by the electrical device 35. In this way, the command decoder 36 is capable of providing the external current to the electrical device 35 in response to the first command CMD1.

[0027] exist Figure 3B In another example shown, the memory controller 34 can provide a second command CMD2 for memory operations at high power. For example, the second command CMD2 can be one of various types of read and / or write commands. In the memory device 33, the command decoder 36 can receive the second command CMD2, and in response to the second command CMD2, the command decoder 36 can control internal circuitry, such as row decoders (not shown) and column decoders (not shown), to perform the operations indicated in the second command CMD2. For example, the row decoder can activate a row by driving the word line corresponding to the row to be accessed (e.g., to be read or written) to a high voltage level. In response to the second command CMD2, the command decoder 36 can further provide a control signal (CTRL OFF) to switches 371 and 372 to be in an inactive state. In response to the control signal in an inactive state, switch 371 can disconnect power node 391 coupled to wiring 381 from wiring 321, and switch 372 can disconnect power node 392 coupled to wiring 382 from wiring 322. Therefore, the power supplied from power source 31 to memory device 33 as internal current via wirings 321 and 322 can be used for operations in memory device 33, such as read or write operations. However, external current may not be supplied to electrical device 35. In this way, command decoder 36 may respond to the second command CMD2 without supplying external current to electrical device 35.

[0028] In the manner described above, the command decoder 36 may or may not be able to supply external current to the electrical device 35 in response to the first command CMD1 and the second command CMD2 from the memory controller 34. (See earlier reference...) Figure 2 The load on power supply 31 can be adjusted by providing or not providing at least a portion of the internal current depending on the operation of different power consumption levels. The load on power supply 31 can be adjusted to convert a portion of the internal current into external current. The portion of the internal current used by memory device 33 during high-power operation is greater than the portion of the internal current used by memory device 33 during low-power operation. Therefore, for different low-power and high-power operations indicated by the first command CMD1 and the second command CMD2, the internal current can remain stable without significant fluctuations.

[0029] Figure 4A and 4B This is a block diagram of a device 40 including a semiconductor device 43, a power manager 44, and an electrical device 45 according to embodiments of the present disclosure. In one embodiment, device 40 may be... Figure 2 The device 20 and semiconductor device 43 in the middle can be Figure 2 The memory device 23 in the middle, and the power manager 44 can be a Figure 2The combination of device 40, semiconductor device 43, and power manager 44 can not be limited to device 20, memory device 23, and memory controller 24. In another embodiment, semiconductor device 43 can be another type of semiconductor device, such as a processor, etc.

[0030] Semiconductor device 43 can be coupled to power supply 41. Power supply 41 can supply power as internal current on wires 421 and 422. Semiconductor device 43 can receive internal current from power supply 41 on wires 421 and 422. Semiconductor device 43 can provide external current from power nodes 491 and 492 to wires 481 and 482 coupled to electrical device 45. Semiconductor device 43 can further include switches 471 and 472. When switch 471 is on, switch 471 can connect wire 421 to power node 491 to provide power on wire 481. Respectively, when switch 472 is on, switch 472 can connect wire 422 to power node 492 to provide power on wire 482. In one embodiment, power manager 44 can control the on and off of switches 471 and 472.

[0031] In one example shown in Figure 4A In one example shown in

[0032] In one example shown in Figure 4BIn another example shown in FIG. 4, the power manager 44 can provide or receive a second type of communication COMM2 related to the high power consumption mode. The second type of communication COMM2 from the power manager 44 can indicate that the semiconductor device 43 perform an operation that results in the high power consumption mode. For example, the second type of communication COMM2 can be one of various types of read commands and write commands from a memory controller to a memory device. Alternatively, the second type of communication COMM2 can be from the semiconductor device 43 indicating that a state of the semiconductor device 43 (e.g., a CPU) is in a busy mode. In response to the second type of communication COMM2, the power manager 44 can further provide a control signal (CTRLOFF) in an inactive state to the switches 471 and 472. In response to the control signal in the inactive state, respectively, the switch 471 can disconnect the power node 491 from the wire 421 and the switch 472 can disconnect the power node 492 from the wire 422. Thus, the power as the internal current provided from the power source 41 to the semiconductor device 43 via the wires 421 and 422 can be used by very active operations (e.g., read or write operations) in the semiconductor device 43. However, the external current can not be provided to the electrical device 45. In this way, the power manager 44 can be unable to provide the external current to the electrical device 45 in response to the second type of communication COMM2.

[0033] In the above manner, the power manager 44 can or can not provide the external current from the semiconductor device 43 to the electrical device 45 in response to the first type of communication COMM1 and the second type of communication COMM2 between the semiconductor device 43 and the power manager 44. As discussed earlier with reference to Figure 2 By providing or not providing the portion of the internal current depending on the different power consumption operations, the load on the power source 41 can be adjusted. Alternatively, by adjusting the portion of the internal current as the external current, the load on the power source 41 can also be adjusted. The portion of the internal current used by the semiconductor device 43 during the high power consumption mode is greater than the portion of the internal current used by the semiconductor device 43 during the low power consumption mode. Thus, the internal current between the power source 41 and the semiconductor device 43 on the wires 421 and 422 can be stable and without substantial fluctuation for different low power and high power operations performed by the semiconductor device 43 across the low and high power consumption modes during the first type of communication COMM1 and the second type of communication COMM2.

[0034] Figure 5A and 5B is a block diagram of an apparatus including a semiconductor device 53, a power manager 54, and an electrical device 55 according to an embodiment of the disclosure. In one embodiment, the apparatus 50 can be the apparatus 20 in Figure 2 , the semiconductor device 53 can be the memory device 53 in Figure 2 , and the power manager 54 can be the power manager 44 inFigure 2 The combination of device 50, semiconductor device 53, and power manager 54 can not be limited to device 20, memory device 23, and memory controller 24, however. In another embodiment, semiconductor device 53 can be another type of semiconductor device, such as a processor, for example.

[0035] Semiconductor device 53 can be coupled to power supply 51. Power supply 51 can supply power as internal current on wires 521 and 522. The internal current on wires 521 and 522 can be provided as external current on wires 581 and 582 from power nodes 591 and 592 of semiconductor device 53. In one embodiment, device 50 can further include power supply 51' and wires 585 and 586 coupled to power supply 51'. Device 50 can also include switches 571 and 572. Switches 571 and 572 can connect wires 583 and 584, which are coupled to power input nodes 593 and 594 of electrical device 55, to wires 581 and 582, which are coupled to power nodes 591 and 592 of semiconductor device 53. Alternatively, switches 571 and 572 can connect wires 583 and 584 to wires 585 and 586, respectively, which are coupled to power supply 51'.

[0036] In one example shown in Figure 5A In one example shown in

[0037] In one example shown in Figure 5BIn another example shown, the power manager 54 can provide or receive a second type of communication COMM2 related to the high power consumption second mode. The second type of communication COM2 from the power manager 54 instructs the semiconductor device 53 to perform an operation that results in the high power consumption second mode. For example, the second type of communication COMM2 can be one of various types of read commands and write commands from a memory controller to a memory device. Alternatively, the second type of communication COMM2 from the semiconductor device 53 can indicate that a state of the semiconductor device 53 (e.g., a CPU) is in a busy mode. In response to the second type of communication COMM2, the power manager 54 can further provide a control signal (CTRL2) to the switches 571 and 572 indicating the second mode. In response to the control signal CTRL2, respectively, the switch 571 can connect the wire 583 to the wire 585 and the switch 572 can connect the wire 584 to the wire 586. Thus, the power as the internal current provided from the power source 51 to the semiconductor device 53 via the wires 521 and 522 can be used by very active operations (e.g., read or write operations) in the semiconductor device 53. However, the internal current on the wires 581 and 582 can not be provided to the electrical device 55, but another external current from the power source 51'on the wires 585 and 586 can be provided to the electrical device 55. In this way, in response to the second type of communication COMM2, the power manager 54 is not able to provide the internal current to the electrical device 55, but is able to provide the external current to the electrical device 55.

[0038] As described above, the power manager 54 can or can not provide the internal current from the semiconductor device 53 to the electrical device 55 in response to the first type of communication COMM1 or the second type of communication COMM2 between the semiconductor device 53 and the power manager 54, respectively. The power manager 54 can further be able to provide the other external current from the power source 51'to the electrical device 55 on the wires 585 and 586 in response to the second type of communication COMM2 between the semiconductor device 53 and the power manager 54.

[0039] When a larger portion of the internal current is used by the semiconductor device 53 during the high power consumption operation, the other external current from the power source 51'can be provided to the electrical device 55. When a smaller portion of the internal current is used by the semiconductor device during the low power consumption operation, at least a portion of the internal current can be provided to the electrical device 55. Whether a portion of the internal current is provided from the semiconductor device 53 or not, a stable power supply can be provided to the electrical device 55 across the high and low power consumption operations by the semiconductor device 53. As earlier referenced Figure 2As discussed, depending on the different amount of power consumption of the semiconductor device 53 operation, the load on the power supply 51 can be adjusted to adjust the portion of the internal current as the external current. The portion of the internal current used by the semiconductor device 53 during high power consumption operation is greater than the portion of the internal current used by the semiconductor device 53 during low power consumption operation. Accordingly, the internal current between the power supply 51 and the semiconductor device 53 on the wires 521 and 522 can be stable and without substantial fluctuation for different low power consumption and high power consumption operations performed by the semiconductor device 53 across the first and second modes.

[0040] Figure 6A and 6B is a block diagram of an apparatus 60 including a semiconductor device 63 (which includes a sensor 66) and an electrical device 65 according to an embodiment of the disclosure. In one embodiment, the apparatus 60 can be the apparatus 20 in Figure 2 , and the semiconductor device 63 can be the memory device 23 in Figure 2 . In another embodiment, the semiconductor device 63 can be another type of semiconductor device, such as a processor, etc.

[0041] The semiconductor device 63 can receive internal current from the power supply 61 via wires 621 and 622. The semiconductor device 63 can provide external current to wires 681 and 682 coupled to the electrical device 65. The semiconductor device 63 can further include switches 671 and 672. Switch 671 can connect wire 621 to a power node 691 coupled to wire 681, and switch 672 can connect wire 622 to a power node 692 coupled to wire 682, respectively. In one embodiment, the sensor 66 functions as a power manager. The sensor 66 can control the turn on and turn off of the switches 671 and 672.

[0042] In one example shown in Figure 6A , the sensor 66 can detect an increase in internal current on the wires 621 and 622 indicative of low power consumption within the semiconductor device 63. In some embodiments, the sensor 66 can be a current sensor. The sensor 66 can have a threshold to determine the increase in internal current. When the internal current is greater than the threshold, the sensor 66 can detect a low power mode. In some embodiments, the sensor 66 can be a voltage sensor. The sensor 66 can have a reference voltage independent of the external supply voltage. The sensor 66 can compare the voltage between the wires 621 and 622 divided by a natural number to the reference voltage to detect the low power mode.

[0043] In response to detecting an increase in the low-power internal current within the indicating semiconductor device 63, the sensor 66 can provide an active control signal (CTRL ON) to switches 671 and 672. In response to the active control signal, switch 671 can connect wiring 621 to power node 691 coupled to wiring 681, and switch 672 can connect wiring 622 to power node 692 coupled to wiring 682. The internal current from power supply 61 on wirings 621 and 622 can be further supplied to electrical device 65 as external current on wirings 681 and 682. Therefore, the power supplied to semiconductor device 63 as internal current can be used for operation in semiconductor device 63 and operation performed by electrical device 65. In this way, sensor 66 can supply external current to electrical device 65 in response to detecting a low-power current in the indicating semiconductor device 63.

[0044] exist Figure 6B In another example shown, sensor 66 can detect a decrease in internal current on high-power wirings 621 and 622 within semiconductor device 63. For example, sensor 66 may have another threshold to determine the decrease in internal current. When the internal current is less than the other threshold, sensor 66 can detect a high-power mode. In response to detecting a decrease in the internal current indicating high power consumption within semiconductor device 63, sensor 66 can provide a control signal (CTRL OFF) to switches 671 and 672 to put them in an inactive state. In response to the inactive control signal, switch 671 can disconnect wiring 681 from wiring 621, and switch 672 can disconnect wiring 682 from wiring 622, respectively. Therefore, the power supplied from power source 61 to semiconductor device 63 as internal current via wirings 621 and 622 can be consumed for operation in semiconductor device 63. However, external current may not be supplied to electrical device 65. In this way, sensor 66 can be unable to supply external current to electrical device 65 in response to detecting a high-power current in semiconductor device 63.

[0045] In the manner described above, sensor 66 may or may not supply external current to electrical device 65 in response to the level of internal current detected by sensor 66. (See earlier reference...) Figure 2 The discussion states that the load on power supply 61 can be adjusted by providing or not providing at least a portion of the internal current depending on the different power consumption levels detected internally. Therefore, for different low-power and high-power operations within semiconductor device 63, the internal current can remain stable and without significant fluctuations, regardless of the power consumption level.

[0046] In the above example, the threshold used to determine an increase in internal current and another threshold used to determine a decrease in internal current are different current amounts. However, these thresholds can be the same current amount.

[0047] Figure 7A 、 7B and 7C is a block diagram of a device 70 including a semiconductor device 73, a power manager 74, and an energy storage device 75 according to an embodiment of the present disclosure. In one embodiment, the device 70 can be the device 20 in Figure 2 and the semiconductor device 73 can be the memory device 23 in Figure 2 . In another embodiment, the semiconductor device 73 can be another type of semiconductor device, such as a processor, etc. In one embodiment, the energy storage device can be a capacitor. In another embodiment, the energy storage device can be a battery. However, the energy storage device 75 is not limited to a capacitor or a battery.

[0048] The semiconductor device 73 can be coupled to a power supply 71. The power supply 71 can supply power as internal current on wires 721 and 722. The semiconductor device 73 can receive the internal current on the wires 721 and 722 from the power supply 71. When the semiconductor device 73 consumes less power in a low power consumption mode, the energy storage device 75 can receive external current from the semiconductor device 73 on wires 781 and 782 coupled to the energy storage device 75. When the semiconductor device 73 consumes high power provided by the internal current from the power supply 71 in a high power consumption mode, the energy storage device 75 can not receive or provide any external current on the wires 781 and 782. Further, when the semiconductor device 73 consumes excessive power that the power supply 71 can provide in an excessive power consumption mode, the energy storage device 75 can provide external current to the semiconductor device 73 on the wires 781 and 782. In one embodiment, the device 70 can be configured to operate in the low power consumption mode and the high power consumption mode. In another embodiment, in addition to the low power consumption mode and the high power consumption mode, the device 70 can be further configured to operate in the excessive power consumption mode. The power manager 74 can provide a control signal related to one of the above listed power consumption modes to control the power supply between the semiconductor device 73 and the energy storage device 75.

[0049] Device 70 can further include current controllers 771 and 772. In some embodiments, current controllers 771 and 772 can act as switches. Current controller 771 can connect wire 781 to a power node 791 of semiconductor device 73 coupled to wire 721 to provide internal current on wire 721 as external current on wire 781 to energy storage device 75 during a low power consumption mode. Current controller 771 can disconnect wire 781 from power node 791 of semiconductor device 73 coupled to wire 721 to stop providing external current on wire 781 during a high power consumption mode. Current controller 771 can connect wire 781 to power node 791 of semiconductor device coupled to wire 721 to provide external current from energy storage device 75 to semiconductor device 73, for example, during an excessive power consumption mode. Similarly, current controller 772 can connect wire 782 to a power node 792 of semiconductor device 73 coupled to wire 722 to provide internal current on wire 722 as external current on wire 782 to energy storage device 75 during a low power consumption mode. Current controller 772 can disconnect wire 782 from power node 792 of semiconductor device 73 coupled to wire 722 to stop providing external current on wire 782 during a high power consumption mode. Current controller 772 can connect wire 782 to power node 792 of semiconductor device coupled to wire 722 during an excessive power consumption mode. Thus, current controller 772 can provide external current from energy storage device 75 to semiconductor device 73, for example, during an excessive power consumption mode.

[0050] In Figure 7AIn one example shown, the power manager 74 can provide or receive a first type of communication COMM1 related to a low power mode on the communication path 76. The first type of communication COMM1 from the power manager 74 can indicate that the semiconductor device 73 perform an operation that results in a low power mode. For example, the first type of communication COMM1 can be a precharge command or a self-refresh command from a memory controller to a memory device. Alternatively, the first type of communication COMM1 can be from the semiconductor device 73 indicating that the state of the semiconductor device 73 (e.g., a CPU) is in an idle mode. In response to the first type of communication COMM1, the power manager 74 can further provide a control signal (CTRL OUT) to the current controllers 771 and 772 indicating a low power mode. In response to the control signal CTRL OUT, the current controllers 771 and 772 can connect the wires 781 and 782 to the power nodes 791 and 792, respectively, and provide the internal current on the wires 721 and 722 as the external current on the wires 781 and 782. The internal current received from the power source 71 via the wires 721 and 722 can be further provided as the external current through the current controllers 771 and 772 to the energy storage device 75 via the wires 781 and 782. Thus, the power provided as the internal current to the semiconductor device 73 can be used for internal operations (e.g., precharge or self-refresh) in the semiconductor device 73 as well as for charging the energy storage device 75. In this way, the power manager 74 is capable of providing the internal current to the energy storage device 75 during a low power mode in response to the first type of communication COMM1.

[0051] In Figure 7BIn another example shown in FIG. 7, the power manager 74 can provide or receive a second type of communication COMM2 related to the high power mode on the communication path 76. The second type of communication COMM2 from the power manager 74 instructs the semiconductor device 73 to perform an operation that results in the high power mode. For example, the second type of communication COMM2 can be one of various types of read commands and write commands from a memory controller to a memory device. Alternatively, the second type of communication COMM2 can be from the semiconductor device 73 indicating that the state of the semiconductor device 73 (e.g., a CPU) is in a moderately busy mode. In response to the second type of communication COMM2, the power manager 74 can further provide a control signal (CTRL STOP) to the current controllers 771 and 772 indicating the high power mode. In response to the control signal CTRL STOP, the current controllers 771 and 772 can disconnect the wires 781 and 782, respectively, from the power nodes 791 and 792. Thus, the power as the internal current provided from the power source 71 to the semiconductor device 73 via the wires 721 and 722 can be consumed by very active operations (e.g., read or write operations) in the semiconductor device 73. However, the internal current on the wires 721 and 722 can not be provided as the external current on the wires 781 and 782 to the energy storage device 75. In this way, the power manager 74 can be unable or stop providing the internal current to the energy storage device 75 in response to the second type of communication COMM2.

[0052] In Figure 7CIn another example shown, the power manager 74 can provide or receive a third type of communication COMM3 related to an excessive power consumption mode on the communication path 76. The third type of communication COMM3 from the power manager 74 instructs the semiconductor device 73 to perform an operation that results in the excessive power consumption mode. Alternatively, the third type of communication COMM3 can come from the semiconductor device 73, indicating that the state of the semiconductor device 73 (e.g., CPU) is excessively busy with operations. In response to the third type of communication COMM3, the power manager 74 can further provide control signals (CTRL IN) to the current controllers 771 and 772 indicating the excessive power consumption mode. In response to the control signals CTRL IN, the current controllers 771 and 772 can connect the wires 781 and 782 to the power nodes 791 and 792, respectively, to provide external currents to the power nodes 791 and 792 on the wires 781 and 782. Thus, the external currents received from the energy storage device 75 via the wires 781 and 782 can be provided to the semiconductor device 73 by the current controllers 771 and 772. Thus, the semiconductor device 73 can use the internal currents and the external currents for internal operations in the semiconductor device 73 in the excessive power consumption mode. In this way, the power manager 74 is capable of providing the external currents from the energy storage device 75 to the semiconductor device 73 during the excessive power consumption mode in response to the third type of communication COMM3.

[0053] As described above, the power manager 74 can or can not be capable of providing the internal currents from the semiconductor device 73 to the energy storage device 75 in response to the first type of communication COMM1 or the second type of communication COMM2 between the semiconductor device 73 and the power manager 74. The power manager 74 can further provide the external currents from the energy storage device 75 to the semiconductor device 73 on the wires 781 and 782 in response to the third type of communication COMM3 between the semiconductor device 73 and the power manager 74. Thus, the internal currents between the power source 71 and the semiconductor device 73 on the wires 721 and 722 can be stable and without large fluctuations, and the extra power stored during the low power consumption modes can be used when the semiconductor device 73 needs extra power in the excessive power consumption mode, for different low power consumption and high power consumption operations performed by the semiconductor device 73 across different power consumption modes.

[0054] Figure 8A is a block diagram of a device 80 including memory devices 831 and 832 (which include command decoders 861 and 862, respectively), a memory controller 84, and an electrical device 85, in accordance with an embodiment of the present disclosure. Figure 8B is a block diagram of a device 80 including memory devices 831 and 832 (which include command decoders 861 and 862, respectively), a memory controller 84, and an electrical device 85, in accordance with an embodiment of the present disclosure. Figure 8AThe memory controller 84 can provide the command CMD1 and CMD2 to the command decoders 861 and 862, respectively. In the memory device 831, the command decoder 861 can receive the command CMD1 from the memory controller 84 and control internal circuits (not shown) according to an operation indicated by the command CMD1. The memory device 831 can receive internal current from the power supply 81 via the wires 821 and 822. The memory device 831 can provide external current to the wires 823 and 824 coupled to the memory device 832. The memory device 831 can further include the switches 871 and 872. The switch 871 can connect the wire 821 to the wire 823 and the switch 872 can connect the wire 822 to the wire 824, respectively, to provide at least a portion of the internal current on the wires 821 and 822 to the wires 823 and 824. In one embodiment, the command decoder 861 can control the on and off of the switches 871 and 872. Similarly, in the memory device 832, the command decoder 862 can receive the command CMD2 from the memory controller 84 and control internal circuits (not shown) according to an operation indicated by the command CMD2. The memory device 832 can receive a portion of the internal current from the memory device 831 via the wires 823 and 824. The memory device 832 can provide external current to the wires 881 and 882 coupled to the power supply 85. The memory device 832 can further include the switches 891 and 892. The switch 891 can connect the wire 823 to the wire 881 and the switch 892 can connect the wire 824 to the wire 882, respectively. In one embodiment, the command decoder 862 can control the on and off of the switches 891 and 892.

[0055] In Figure 8A and 8B The memory controller 84 can provide the command CMD1 to the memory device 831 that is deselected (unable) to be used for the bulk operation. The memory controller 84 can also provide the command CMD2 to the memory device 832 that is selected to be used for the bulk operation. For example, the command CMD2 can be a refresh command REF indicating a refresh operation, a write command WR indicating a write operation, a read command RD indicating a read operation. The command CMD2 can also be a self-refresh command SREF indicating a self-refresh operation. In some embodiments, the refresh operation, the write operation, or the read operation can consume a bulk power, while the self-refresh operation can consume a relatively low power. The memory controller 84 can provide the self-refresh command SREF as the command CMD2 while providing the command CMD1 indicating a relatively power-consuming operation, such as the write command WR, the read command RD, or the refresh operation REF, as in Figure 8BIn another aspect, the memory controller 84 can provide a refresh command as the command CMD2 while providing a command CMD1 indicating a low power operation, such as a self refresh command SREF.

[0056] In the memory device 831, the command decoder 861 can receive the first command CMD1, and in response to the first command CMD1, the command decoder 861 can control internal circuitry to perform an operation indicated in the first command CMD1. When the CMD1 indicates that the memory device 831 is selected, the command decoder 861 can further provide a control signal (CTRL OFF) in an off state to the switches 871 and 872. In response to the control signal in the off state, the switch 871 can disconnect the wire 821 from the wire 823, and the switch 872 can disconnect the wire 822 from the wire 824, respectively. Internal current from the power supply 81 can be consumed within the memory device 831. When the CMD1 indicates that the memory device 831 is deselected, the command decoder 861 can further provide a control signal (CTRL ON) in an on state to the switches 871 and 872. In response to the control signal in the on state, the switch 871 can connect the wire 821 to the wire 823, and the switch 872 can connect the wire 822 to the wire 824, respectively. Thus, the internal current from the power supply 81 on the wires 821 and 822 can be further provided to the memory device 832 as the external current on the wires 823 and 824.

[0057] For example, if the command CMD1 is a self-refresh command, the memory device 831 can control the circuit in a manner that self-refreshes the bit lines. Meanwhile, in response to the command CMD2 being present and the command CMD2 being a refresh command REF, a write command WR, or a read command RD, the command decoder 862 can operate the refresh, write, or read operation that consumes a large amount of power. Thus, the power provided from the power source 81 can be used for the low-power consumption operation (e.g., self-refresh) in the memory device 831 as well as for the operation that can consume more power performed by the memory device 832. In the memory device 832, the command decoder 862 can receive the second command CMD2, and in response to the second command CMD2, the command decoder 862 can control the internal circuit, e.g., a row decoder (not shown) and a column decoder (not shown), to perform the operation indicated in the second command CMD2. For example, the row decoder can activate a row by driving a word line corresponding to the row to be accessed (e.g., to be read or to be written) to a high voltage level. Meanwhile, in response to the second command CMD2, the command decoder 862 can further provide the control signals (CTRL OFF) in the inoperative state to the switches 891 and 892. In response to the control signals in the inoperative state, respectively, the switch 891 can disconnect the wire 881 from the wire 823, and the switch 892 can disconnect the wire 882 from the wire 824. Thus, the power provided from the memory device 831 as the internal current via the wires 823 and 824 to the memory device 832 can be consumed for the operation, e.g., refresh, read, or write operation, in the memory device 832; however, the external current can not be provided to the electrical device 85. In this way, the command decoder 862 can not be able to provide the external current to the electrical device 85 in response to the second command CMD2.

[0058] When the memory controller 84 can provide the memory device 832 with the self-refresh command SREF as the command CMD2, the memory device 832 operates a low-power consumption operation, e.g., a self-refresh operation, when selected (enabled). The memory controller 84 can provide the memory device 831 with the command CMD1 having a higher power consumption (e.g., a refresh command), and the memory device 831 can operate a refresh operation. In addition, in response to the self-refresh command SREF, the command decoder 862 can further provide the control signals (CTRL ON) in the operative state to the switches 871 and 872. In response to the control signals in the operative state, respectively, the switch 891 can connect the wire 881 to the wire 823, and the switch 892 can connect the wire 882 to the wire 824. Thus, the power provided from the memory device 831 as the internal current via the wires 823 and 824 to the memory device 832 can be provided to the electrical device 85.

[0059] In the above-described manner, the command decoders 861 and 862 can or can not be instructed by the first and second commands CMD1 and CMD2 from the memory controller 84 to indicate a combination of higher and lower power consumption operations to provide current from the power supply 81 to the memory devices 832 and the electrical device 85. As a result, the internal current can be maintained steady and without large fluctuations across the states of each memory device (e.g., selected and deselected).

[0060] From the foregoing, it will be appreciated that, although specific embodiments of the application have been described herein for the purpose of illustration, various modifications are possible without deviating from the spirit and scope of the application. For example, although embodiments have been described with respect to providing power from a semiconductor chip in a personal computer such as a desktop PC, laptop PC, or game PC, other embodiments can involve using the semiconductor chip described herein in other devices including, but not limited to, any stationary device (e.g., game console, data storage device, electronic aid device, and digital media player), any portable device (e.g., portable game device, portable digital media player, cellular phone, tablet computer), various embedded systems, and any combination or sub-combination thereof. Accordingly, the application is not to be limited by what has been described in the above description.

Claims

1. An apparatus comprising: A semiconductor device including a power node, the semiconductor device being configured to receive power as internal current and further configured to operate in a first mode and a second mode. The semiconductor device is configured to consume more power in the second mode than in the first mode. The semiconductor device is configured to consume a first portion of the internal current during the first mode, and is further configured to provide a second portion of the internal current as external current at the power node during the first mode. The semiconductor device is further configured to consume a third portion of the internal current that is greater than the first portion of the internal current during the second mode.

2. The device according to claim 1, further comprising: Wiring that is coupled to the semiconductor device. The semiconductor device is configured to receive the power from the wiring as the internal current, and the semiconductor device includes a switch configured to connect the wiring to the power node in the first mode.

3. The device according to claim 2, further comprising: A sensor configured to detect the first mode when the internal current is greater than a first threshold amount, and further configured to detect the second mode when the internal current is less than a second threshold amount. The sensor is configured to provide a control signal to the switch indicating the first mode, and The switch is configured to connect the wiring to the power node in response to a control signal from the sensor indicating the first mode, thereby providing the power node with the second portion of the internal current.

4. The device of claim 2, wherein the switch is configured to receive an externally provided control signal and is configured to couple the wiring to the power node in response to the control signal indicating the first mode.

5. The device of claim 2, wherein the semiconductor device is a memory device, the semiconductor device comprising: A command decoder, configured to receive commands, configured to decode the commands, and further configured to control internal circuitry according to the operation of the memory device indicated by the commands. The command decoder is further configured to determine whether the operation is related to the first mode or the second mode, and is configured to provide a control signal to the switch indicating the determined mode. The switch is configured to connect the wiring to the power node in response to the control signal indicating the first mode.

6. The device according to claim 5, further comprising: The operation related to the first mode is one of a pre-charge operation and a self-refresh operation, and The operation associated with the second mode is either a write operation or a read operation.

7. The device of claim 5, wherein the memory device is a first memory device, the command decoder is a first command decoder, and the command is a first command, the device further comprising: A second memory device configured to receive the external current from the first memory device, the second memory device comprising: A second command decoder is configured to receive and decode a second command, and is further configured to control internal circuitry in the second memory device according to the operation of the memory device indicated by the second command. Specifically, the first command or the second command indicates a memory operation with high power consumption, and the second command or the first command indicates a memory operation with low power consumption.

8. An apparatus comprising: A power source, configured to provide power; A semiconductor device configured to receive power from the power source as internal current, and further configured to operate in a first mode and a second mode. and An electrical device configured to be coupled to the semiconductor device; The semiconductor device is further configured to provide at least a portion of the internal current to the electrical device as an external current during the first mode, and The semiconductor device is further configured to not provide at least a portion of the internal current as the external current during the second mode.

9. The device of claim 8, further comprising a power manager configured to provide at least a portion of the internal current as the external current during the first mode, and further configured not to provide at least a portion of the internal current as the external current during the second mode.

10. The device of claim 9, wherein the power manager includes a sensor contained in the semiconductor device, the sensor being configured to detect the first mode when the internal current is greater than a first threshold amount, and further configured to detect the second mode when the internal current is less than a second threshold amount.

11. The device of claim 9, wherein the semiconductor device is a memory device. The power manager includes a command decoder contained in the memory device, the command decoder being configured to receive commands, configured to decode the commands, and further configured to control internal circuitry according to the operation of the memory device indicated by the commands. The command decoder is further configured to determine whether the operation is associated with the first mode or the second mode, and is configured to provide control signals indicating the determined mode.

12. The device of claim 9, wherein the semiconductor device is a memory device. The power manager includes a memory controller configured to provide commands to the memory device, the commands instructing the operation of the memory device, and The memory controller is further configured to determine whether the operation is associated with the first mode or the second mode, and is configured to provide control signals indicating the determined mode.

13. The device according to claim 9, further comprising: A first wiring has a first end coupled to the power supply and a second end coupled to the semiconductor device; The second wiring has a third terminal coupled to the electrical device; and A switch configured to connect the first wiring to the second wiring, and further configured to disconnect the first wiring from the second wiring. The power manager is configured to provide control signals associated with the first mode during the first mode, and is further configured to provide the control signals associated with the second mode during the second mode. The switch is configured to connect the first wiring to the second wiring in response to the control signal indicating the first mode, and is further configured to disconnect the first wiring from the second wiring in response to the control signal indicating the second mode.

14. The device according to claim 13, further comprising: A second power source, wherein the power source includes a first power source; and The third wiring has a fourth terminal coupled to the second power supply; The switch is further configured to couple the third wiring to the second wiring in response to the control signal associated with the second mode.

15. The device of claim 13, wherein the electrical device includes an energy storage device.

16. The device of claim 15, wherein the switch includes a current controller configured to couple the first wiring to the second wiring to provide at least a portion of the internal current on the first wiring as the external current on the second wiring in response to the control signal associated with the first mode, and further configured to provide the external current on the second wiring as the internal current on the first wiring in response to the control signal associated with the third mode, which is different from the first and second modes.

17. A method comprising: The semiconductor device receives power from the power source as internal current. The semiconductor device is operated in both the first and second modes; During the first mode, at least a portion of the internal current is provided as an external current to an electrical device configured to couple to the semiconductor device; and During the second mode, at least a portion of the internal current is not provided as the external current to the electrical device configured to couple to the semiconductor device.

18. The method of claim 17, further comprising: The first mode is detected when the internal current is greater than a first threshold amount; and The second mode is detected when the internal current is less than the second threshold amount.

19. The method of claim 17, further comprising: Receive command; Decode the command; Control the internal circuitry according to the operation instructed by the command; Determine whether the operation indicated by the command is related to the first mode or the second mode; and Provide control signals that indicate the determined mode.

20. The method of claim 19, wherein the semiconductor device includes a memory device comprising a command decoder, and wherein determining and providing the control signal is performed by the command decoder.

21. The method of claim 19, wherein the semiconductor device includes a memory device and a memory controller is coupled to the memory device, and wherein determining and providing the control signal is performed by the memory controller.

22. The method of claim 19, further comprising: Receive status from the semiconductor device; Determine whether the state is related to the first mode or the second mode; and Provide control signals that indicate the determined mode.

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