Dual-phase etching process for optimizing semiconductor trench morphology

Abstract

A two-phase etching process method for optimizing semiconductor groove morphology is disclosed. The method mainly utilizes two etching processes under different conditions for cyclic etching, which can suppress the generation of micro grooves, improve the morphology of the bottom of the device groove, and obtain "V-shaped groove", "U-shaped groove" and groove morphology with a flat bottom.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more specifically, to a dual-phase etching process method for optimizing semiconductor groove morphology. Background Art

[0002] Silicon (Si)-based devices are currently the most commonly used power semiconductor devices. In recent years, due to the influence of Si material properties, the improvement of the operating voltage, operating temperature, operating frequency, operating loss and radiation resistance of Si-based devices has been severely limited. However, the technology of Si-based devices is relatively mature, and it is difficult to achieve innovative breakthroughs. Silicon carbide (SiC) is a material with unique physical and chemical properties. The strong covalent bonds between silicon and carbon atoms give this material high hardness, chemical inertness and high thermal conductivity, and also provide the material with a wide bandgap and a high critical breakdown electric field. With these excellent properties, SiC has received widespread attention and has been promoted and applied in high-power and high-temperature electronic devices.

[0003] The trench etching process is a key process in the preparation of semiconductor devices. The morphology of the trench affects the area of ​​the device's on-current and the distribution of the electric field during breakdown, which in turn affects the device's specific on-resistance and breakdown voltage. In traditional semiconductor etching processes, micro-grooves are easily generated at the bottom of the trench, especially for deep trench structures. Micro-grooves can cause the concentration effect of potential lines, generate high electric fields, and cause the device to break down prematurely, thereby reducing the device's breakdown voltage. Summary of the invention

[0004] The purpose of the present invention is to provide a process which adopts two different etching conditions for cyclic etching to optimize the morphology of the groove after etching, thereby improving the electrical performance of the device.

[0005] According to an embodiment of the present invention, a two-phase etching process method for optimizing semiconductor groove morphology includes: sample cleaning; mask layer growth; mask layer patterning; etching the groove under a first etching condition, wherein the first etching condition includes a first ICP power and a first RF bias voltage; etching the groove under a second etching condition, wherein the second etching condition includes a second ICP power and a second RF bias voltage, wherein the first ICP power is higher than the second ICP power, and the first RF bias voltage is lower than the second RF bias voltage; and etching the groove using the first etching condition and the second etching condition alternately.

[0006] Furthermore, the first ICP power is 800-2000W, the first RF bias voltage is -50V-0V, the second ICP power is 0-600W, and the second RF bias voltage is -300V--50V.

[0007] Furthermore, the first etching condition makes chemical etching dominant, and the second etching condition makes physical etching dominant.

[0008] Furthermore, the etching rate under the first etching condition is greater than the etching rate under the second etching condition.

[0009] Furthermore, the bottom of the groove after etching under the first etching condition is in a "V-shape".

[0010] Furthermore, after etching under the second etching condition, the sidewalls of the grooves are vertical and micro grooves appear at the bottom.

[0011] Furthermore, alternatingly using the first etching condition and the second etching condition to etch the groove includes: dividing the groove etching into multiple cycles according to the etching depth, each cycle includes etching the groove through the first etching condition and etching the groove through the second etching condition, the total etching time of each cycle is equal to the total etching time of the previous cycle, and the etching time under the second etching condition of each cycle is equal to the etching time under the second etching condition of the previous cycle.

[0012] According to another embodiment of the present invention, a two-phase etching process method for optimizing semiconductor groove morphology includes: dividing the groove etching into multiple cycles according to the etching depth, each cycle includes etching the groove through a first etching condition and etching the groove through a second etching condition, the first etching condition makes chemical etching dominant, the second etching condition makes physical etching dominant, the etching time under the second etching condition of each cycle accounts for the same proportion of the total etching time of the corresponding cycle as the etching time under the second etching condition of the previous cycle accounts for the total etching time of the corresponding cycle.

[0013] Furthermore, in each cycle, the groove is first etched using the first etching condition and then etched using the second etching condition.

[0014] Furthermore, the first etching condition includes a first ICP power and a first RF bias voltage, and the second etching condition includes a second ICP power and a second RF bias voltage, the first ICP power is 800~2000W, the first RF bias voltage is -50V~0V, the second ICP power is 0~600W, and the second RF bias voltage is -300V~-50V.

[0015] The dual-phase etching process method for optimizing semiconductor groove morphology can eliminate the micro-groove phenomenon and obtain grooves of various morphologies, thereby meeting the structural design requirements of the device and improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the process flow of the semiconductor trench optimized dual-phase etching process of the present invention.

[0017] Figures 2A-2F The main steps of a trench optimized dual-phase etching process according to an embodiment of the present invention are shown. DETAILED DESCRIPTION

[0018] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the embodiments described here are only used for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth to facilitate a thorough understanding of the present invention. However, it will be appreciated by those skilled in the art that these specific details are not necessary for the implementation of the present invention. In addition, in some embodiments, in order to avoid confusing the present invention, no specific description is given of known circuits, materials or methods. Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a specific feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, specific features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it will be appreciated by those skilled in the art that the drawings provided herein are for illustrative purposes, wherein the same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The semiconductor region materials in the semiconductor trench optimization two-phase etching process described in the present invention include but are not limited to silicon carbide, gallium nitride, and silicon. Throughout the specification, the semiconductor region in the present invention can be a silicon carbide region, a silicon region, or any other semiconductor material region applicable to the present invention, and the cross-sectional view of the example of the present invention can be any section of the device. The etching process in the present invention is mainly completed by inductively coupled plasma (ICP) etching, and the etching gas is mainly sulfur hexafluoride (SF6) or carbon tetrafluoride (CF4) and oxygen (O2).

[0019] Figure 1The process diagram of the semiconductor trench optimization dual-phase etching process of the present invention is shown. The process mainly includes: the first step S1: sample cleaning, the second step S2: mask layer growth, the third step S3: mask layer patterning, the fourth step S4: etching under the first etching condition, wherein the first etching condition includes the first ICP power and the first RF bias voltage, the fifth step S5: etching under the second etching condition, and the two etching processes are alternately cycled until the etching depth is met, wherein the second etching condition includes the second ICP power and the second RF bias voltage, the first ICP power is higher than the second ICP power, and the first RF bias voltage is lower than the second RF bias voltage. The morphology of the groove after etching is optimized by changing the time ratio of the two etchings (i.e., etching under the first etching condition and etching under the second etching condition), wherein the first etching condition and the second etching condition both etch to realize chemical etching and physical etching, the first etching condition makes chemical etching dominant, and the second etching condition makes physical etching dominant, the etching speed under the first etching condition can be greater than or equal to the etching speed under the second etching condition, and in one embodiment of the present invention, the groove etching can be divided into multiple cycles according to the etching depth, and each cycle includes etching the groove under the first etching condition. and etching the groove under the second etching condition, the total etching time of each cycle can be equal to the total etching time of the previous cycle, and the etching time under the second etching condition of each cycle can be equal to the etching time under the second etching condition of the previous cycle, each cycle can be set to first etch the groove under the first etching condition and then etch the groove under the second etching condition. In one embodiment of the present invention, the etching time under the second etching condition of each cycle accounts for a proportion of the total etching time of its corresponding cycle equal to the proportion of the etching time under the second etching condition of the previous cycle in the total etching time of its corresponding cycle.

[0020] During the production process, semiconductor wafers are inevitably polluted by the environment, mainly including particles, organic contamination, metal contamination and oxides. Therefore, before the device is prepared, the surface is cleaned through the first step S1. First, organic cleaning is performed to remove particles and most organic contaminants; then standard RCA cleaning is performed to remove stubborn organic impurities and metal contamination. The second step S2 is to grow a mask layer on the surface of the first semiconductor. The mask layer can be a dielectric material such as silicon oxide or silicon nitride grown by PECVD or LPCVD, or it can be a metal material grown by magnetron sputtering or evaporation. In the third step S3, if the mask layer is a dielectric material such as silicon oxide or silicon nitride, then the photoresist is first used as an etching mask for the mask layer, and then the mask layer is etched and wet-etched to form a film such as the following. Figure 2AIf the mask layer is a metal material, then you can first use the photoresist AZ5214E ​​for reverse lithography, then magnetron sputtering or evaporation to grow a layer of metal, and finally peel it off; or first use magnetron sputtering or evaporation to grow a layer of metal, then perform photolithography and wet etching to get it. Both methods can get Figure 2A The first etching condition in the fourth step S4 may be high ICP power (eg 800-2000W) and low RF bias voltage (eg -50V-0V), at which time chemical etching takes a dominant position, forming a Figure 2B The second etching condition in the fifth step S5 may be low ICP power (eg 0-600W) and high RF bias voltage (eg -300V--50V), at which time the physical etching effect takes the leading role, forming a groove morphology as shown in FIG. Figure 2C In the etching process, step S4 is performed first and then step S5. If the etching depth is met, there is no need to repeat steps S4 and S5. The etching time of each step S4 and S5 can also be adjusted, and the etching of steps S4 and S5 is repeated for multiple times until the etching depth requirement is met.

[0021] Figures 2A-2F The main steps of a trench optimized dual-phase etching process according to an embodiment of the present invention are shown.

[0022] Figure 2A A substrate 301, an epitaxial layer 302 and a mask layer 303 are shown. The substrate 301 may be an N-type, P-type or intrinsic semiconductor material. The epitaxial layer 302 may be a single layer or multiple layers of an N-type, P-type or intrinsic semiconductor material. The mask layer may be a dielectric material such as silicon oxide or silicon nitride, or a metal material such as nickel or aluminum. The epitaxial layer 302 is located on the substrate 301, and then the mask layer 303 is grown on the epitaxial layer 302 by deposition or sputtering, and patterned.

[0023] Figure 2B It shows the morphology of the groove after the first etching condition under the condition of the mask layer 303, and the bottom of the groove 304 presents a "V-shape". Figure 2C The morphology of the trench after the second etching condition is shown. The sidewall of the trench 305 is vertical but a micro-groove morphology appears at the bottom.

[0024] By using the two process conditions together, the morphology of the groove after etching can be optimized, and the proportion of the time of the second etching condition to the total etching time can be increased. Figure 2B The "V-shaped" groove 304 in Figure 2D The U-shaped groove 306 in the Figure 2E The groove 307 in the middle becomes flat and finally reaches Figure 2FThe bottom of the groove 308 in the embodiment is completely flat, which meets the structural design requirements of different devices. For example, if the target etching depth is 10 μm, it can be divided into 10 cycles for etching, and each cycle etches 1 μm. Assume that the etching rates of the first etching condition and the second etching condition are 200 nm / min and 100 nm / min respectively. In other embodiments of the present invention, the etching rates of the first etching condition and the second etching condition can be the same. If only the first etching condition is used for etching for 5 min in one cycle, then the result is Figure 2B The groove 304 in the embodiment; if the first etching condition is used for 4.5 min and the second etching condition is used for 1 min in one cycle, then the result is Figure 2D If the first etching condition is used for etching for 4.25 min and the second etching condition is used for etching for 1.5 min in one cycle, the result is Figure 2E The groove 307 in the embodiment; if the first etching condition is used for 4 min and the second etching condition is used for 2 min in one cycle, then the result is Figure 2F In the embodiment of the present invention, the time ratio and time length of different groove morphologies are different, but in the etching process of each groove morphology, the total etching time of each cycle is the same, and the etching time under the first condition and the etching time under the second condition are fixed.

[0025] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A dual-phase etching process method for optimizing semiconductor trench morphology, including: Sample cleaning; Mask layer growth; Mask layer patterning; Etching a groove using a first etching condition, wherein the first etching condition includes a first ICP power and a first RF bias voltage, wherein the first ICP power is 800 to 2000 W, and the first RF bias voltage is -50 V to 0 V. The first etching condition makes chemical etching dominant, and the bottom of the groove after etching using the first etching condition is "V-shaped"; Etching a groove under a second etching condition, wherein the second etching condition includes a second ICP power and a second RF bias voltage, wherein the first ICP power is higher than the second ICP power, the first RF bias voltage is lower than the second RF bias voltage, the second ICP power is 0 to 600 W, the second RF bias voltage is -300 V to -50 V, and the second etching condition makes physical etching dominant, and the sidewall of the groove etched under the second etching condition is vertical and micro grooves appear at the bottom; The first etching condition and the second etching condition are used alternately to etch the groove, and the groove etching is divided into multiple cycles according to the target etching depth, each cycle includes etching the groove through the first etching condition and etching the groove through the second etching condition, the total etching time of each cycle is equal to the total etching time of the previous cycle, and the etching time under the second etching condition of each cycle is equal to the etching time under the second etching condition of the previous cycle.

2. The dual-phase etching process method as claimed in claim 1, wherein the etching rate under the first etching condition is greater than the etching rate under the second etching condition.

3. The dual-phase etching process method as claimed in claim 1, wherein when the target etching depth is 10 μm, the etching is performed in 10 cycles, and each cycle etches 1 μm.

4. The dual-phase etching process method according to claim 2, wherein the etching rates of the first etching condition and the second etching condition are 200 nm / min and 100 nm / min respectively; When a U-shaped groove with an arc-shaped bottom is required, the first etching condition is used for etching for 4.5 minutes in one cycle of the multiple cycles, and then the second etching condition is used for etching for 1 minute; When a U-shaped groove with a flat groove bottom is required, the first etching condition is used for etching for 4.25 minutes in one cycle of the multiple cycles, and then the second etching condition is used for etching for 1.5 minutes; When it is necessary to obtain a trapezoidal groove with a flat bottom and a bottom that is nearly perpendicular to the sidewall, it is set that in one of the multiple cycles, the first etching condition is first used for etching for 4 minutes, and then the second etching condition is used for etching for 2 minutes.

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