Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a layer to be etched, comprising a first region and a second region arranged along a first direction, wherein the first region and the second region are adjacent to each other in the first direction; forming a sacrificial layer on the layer to be etched, wherein the sacrificial layer has a first conductive opening and a first isolation opening that are connected, wherein the first conductive opening is located on the first region, and wherein the first isolation opening penetrates the sacrificial layer on the second region along a second direction; forming a sidewall film on the surface of the sacrificial layer, wherein the sidewall film fills the first isolation opening; forming a first patterned layer on the sidewall film, wherein the first patterned layer has a second isolation opening, wherein the second isolation opening penetrates the sacrificial layer on the first region and the second region along a second direction, and wherein the second isolation opening on the second region exposes the sidewall film in the first isolation opening; and thinning the sidewall film using the first patterned layer as a mask. Thus, the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the improvement of circuit integration and the increase of scale, the size of unit devices in the circuit continues to shrink, and the requirements for integrated circuit manufacturing processes continue to increase. For example, the key size continues to decrease, and the chip manufacturing has higher and higher requirements for lithography resolution. As the design size continues to shrink, the minimum resolution of the design graphics has exceeded the limit of the existing optical lithography platform. The industry has adopted a variety of technical solutions to solve this technical problem. According to the international semiconductor technology blueprint, the industry has placed high hopes on technical solutions such as double patterning technology (DPT), extreme ultraviolet technology (EUV), and electron beam direct writing (EBL).

[0003] There are many existing double patterning processes, among which the double patterning process method using the LELE (Litho-Etch-Litho-Etch, lithography-etching-lithography-etching) process is a more common one among the existing multiple double patterning process methods. The LELE process method requires splitting the layout into two parts, and then generating a part of the pattern through two separate lithography and etching steps. However, the lithography, etching and deposition processes will produce EPE (Edge Placement Error), which will lead to vertical alignment deviation between layers. The appearance of EPE will eventually affect the performance of the formed semiconductor device. In order to reduce EPE, a patterning technology based on a sidewall process is proposed, such as a self-aligned LELE technology based on a sidewall process.

[0004] At present, when a metal line is formed by a sidewall-based self-aligned LELE process, a first groove is usually formed first, and then a sidewall is formed on the inner wall of the first groove. The sidewall is used as an alignment reference during the second photolithography, thereby achieving self-alignment of the second groove formed by the second photolithography and reducing EPE. The substrate is then patterned by relying on the sidewalls of the first groove and the inner wall of the first groove, as well as the second groove.

[0005] However, there are still problems with the metal lines formed in the prior art. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, so as to improve the reliability of the semiconductor structure while reducing the process difficulty.

[0007] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, the layer to be etched comprising a first area and a second area arranged along a first direction, the first area and the second area being adjacent to each other in the first direction; forming a sacrificial layer on the layer to be etched, the sacrificial layer having a first conductive opening and a first isolating opening that are connected, the first conductive opening being located on the first area, and the first isolating opening penetrating the sacrificial layer on the second area along a second direction, the second direction being perpendicular to the first direction; forming a sidewall film on the surface of the sacrificial layer, the sidewall film filling the first isolating opening; forming a first patterned layer on the sidewall film, the first patterned layer having a second isolating opening, the second isolating opening penetrating the sacrificial layers on the first area and the second area along the second direction, and the second isolating opening on the second area exposing the sidewall film in the first isolating opening; and thinning the sidewall film using the first patterned layer as a mask.

[0008] Optionally, it also includes: after thinning the side wall film using the first patterned layer as a mask, forming a second partition material layer on the surface of the side wall film in the second partition opening, and the second partition material layer fills the second partition opening; flattening the second partition material layer until the top surface of the side wall film in the first partition opening is exposed to form a second partition layer.

[0009] Optionally, the method further includes: removing the first patterned layer during planarizing the second isolation layer.

[0010] Optionally, it also includes: after forming the second isolation layer, using an anisotropic etching process to etch the sidewall film on the surface of the sacrificial layer until the surface of the sacrificial layer is exposed, and forming a sidewall on the sidewall surface of the first conductive opening and in the first isolation opening.

[0011] Optionally, it also includes: after forming the side wall, forming a second patterned layer on the surface of the sacrificial layer, and having a second conductive pattern opening extending along a second direction in the second patterned layer on the second area, the second conductive pattern opening exposing the side wall surface of the side wall on the first area, and the side wall on the second area passes through the second conductive pattern opening; using the second patterned layer and the side wall as a mask, etching the sacrificial layer until the surface of the layer to be etched is exposed, and forming a second conductive opening in the sacrificial layer.

[0012] Optionally, the method further includes: etching the layer to be etched using the sacrificial layer, the sidewalls and the second isolation layer as masks.

[0013] Optionally, the layer to be etched includes a substrate and a first mask material layer located on the substrate.

[0014] Optionally, the method for etching the layer to be etched includes: using the sacrificial layer, the sidewalls and the second isolation layer as masks, etching the first mask material layer until the substrate surface is exposed to form a mask layer.

[0015] Optionally, the method for etching the layer to be etched further includes: using the mask layer as a mask, etching the substrate to form a plurality of conductive openings in the substrate; the method for forming the semiconductor structure further includes: forming a conductive structure in the plurality of conductive openings.

[0016] Optionally, the layer to be etched further includes a second mask material layer located between the substrate and the first mask material layer.

[0017] Optionally, the method for etching the layer to be etched includes: using the sacrificial layer, the side wall and the second isolation layer as masks, etching the first mask material layer until the surface of the second mask material layer is exposed to form a first mask layer; using the first mask layer as a mask, etching the second mask material layer until the surface of the substrate is exposed to form a mask layer.

[0018] Optionally, the method for etching the layer to be etched further includes: using the mask layer as a mask, etching the substrate to form a plurality of conductive openings in the substrate; the method for forming the semiconductor structure further includes: forming a conductive structure in the plurality of conductive openings.

[0019] Optionally, in a direction perpendicular to the substrate surface, the reduced thickness of the spacer film in the second isolation opening is in a range of 3 angstroms to 10 angstroms.

[0020] Optionally, the process of etching the sidewall film using the first patterned layer as a mask includes a dry etching process.

[0021] Optionally, the parameters of the dry etching process include: the etching gas includes chlorine; the temperature range is 40 degrees Celsius to 50 degrees Celsius; and the pressure range is 40 mTorr to 60 mTorr.

[0022] Optionally, the material of the spacer film includes titanium oxide, and the material of the sacrificial layer includes silicon.

[0023] Optionally, the material of the second isolation layer includes a low-temperature oxide formed in a preset low-temperature environment, and the temperature range of the preset low-temperature environment is 50 degrees Celsius to 100 degrees Celsius.

[0024] Optionally, the surface of the sidewall film in the first isolation opening has a notch; using the first patterned layer as a mask, the method of thinning the sidewall film includes: using the first patterned layer as a mask, etching the sidewall film until the notch is removed, so that the surface of the sidewall film in the first isolation opening is flush.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the sidewall film in the first isolation opening is exposed through the second isolation opening on the second region, forming a second isolation opening with a larger size in the second direction, thereby increasing the process window for forming the first graphic layer, thereby reducing the process difficulty of forming the first graphic layer. At the same time, since the sidewall film is thinned by using the first graphic layer as a mask after the first graphic layer is formed, the depth of the depression or notch on the surface of the sidewall film in the first isolation opening can be reduced, or the depression or notch on the surface of the sidewall film in the first isolation opening can be removed, so that the surface of the sidewall film is smoother, so that the material subsequently deposited on the surface of the sidewall film is not easy to produce local residues after etching or flattening process, thereby improving the reliability of the semiconductor structure. In summary, through the method for forming a semiconductor structure, the reliability of the semiconductor structure is improved while reducing the process difficulty.

[0027] Furthermore, since the sidewall film is etched until the gap on the surface of the sidewall film in the first isolation opening is removed, the surface of the sidewall film in the first isolation opening is flush, thereby ensuring that the gap on the surface of the sidewall film in the first isolation opening is completely removed, so that the surface of the sidewall film in the first isolation opening is flush, thereby further improving the flatness of the sidewall film surface in the first isolation opening, so that the material subsequently deposited on the surface of the sidewall film will not produce local residue after the etching or planarization process, thereby better improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 5 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0029] Figures 6 to 21 It is a structural schematic diagram of each step of a formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, there are still problems with the metal lines formed in the prior art, which will be described in detail below with reference to the accompanying drawings.

[0031] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0032] Figures 1 to 5 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0033] Please refer to Figure 1 , providing a layer to be etched 100 (such as Figure 3 As shown), the layer to be etched 100 includes adjacent first region I and second region II; a sacrificial layer 110 is formed on the surface of the layer to be etched 100; the sacrificial layer 110 is etched to form a connected initial first conductive opening 111 and a first isolating opening 112 in the sacrificial layer 110, respectively, and the first isolating opening 112 spans across the second region II.

[0034] Please refer to Figure 2 and Figure 3 , Figure 3 yes Figure 2 The schematic diagram of the cross-sectional structure along the A-A1 direction shows that after the initial first conductive opening 111 and the first isolating opening 112 are formed, a sidewall film 120 is formed on the surface of the sacrificial layer 110 , and the sidewall film 120 fills the first isolating opening 112 .

[0035] Please refer to Figure 4 A patterned layer 130 is formed on the surface of the sidewall film 120, and the surface of the patterned layer 130 is higher than the surface of the sidewall film 120; a second isolation opening (not shown) is formed in the patterned layer 130, and the second isolation opening spans the first area I and the second area II, and the second isolation opening exposes the sidewall film 120 in the first isolation opening 112; an initial isolation layer 140 is formed in the second isolation opening.

[0036] In this embodiment, after the initial isolation layer 140 is formed, the patterned layer 130 is removed.

[0037] Please refer to Figure 5 , the initial isolation layer 140 is etched back until the top surface of the sidewall film 120 is exposed to form an isolation layer 141; after the isolation layer 141 is formed, the sidewall film 120 on the surface of the sacrificial layer 110 is etched by an anisotropic etching process until the sidewall film 120 in the horizontal direction is removed to form a sidewall 121 and a first conductive opening 113; after the sidewall 121 is formed, the sacrificial layer 110 is etched to form a second conductive opening 114 in the sacrificial layer 110 on the second region II, and the sidewall 121 on the second region II penetrates the second conductive opening 114; after the second conductive opening 114 is formed After the opening 114, the layer to be etched 100 is etched using the sacrificial layer 110, the side wall 121 and the isolation layer 141 as masks to form a plurality of conductive openings (not shown) in the layer to be etched 100; after the conductive openings are formed, the sacrificial layer 110, the isolation layer 141 and the side wall 121 are removed; after the sacrificial layer 110, the isolation layer 141 and the side wall 121 are removed, a conductive structure material layer (not shown) is formed on the surface of the layer to be etched 100 and in the conductive openings; the conductive structure material layer is planarized until the surface of the layer to be etched 100 is exposed, and a conductive structure (not shown) is formed in the conductive openings.

[0038] In the above embodiment, the conductive openings formed in the first region I are spaced apart by the isolation layer 141 , and the conductive openings formed in the second region II are spaced apart by the sidewalls 121 of the second region II to form a conductive structure that meets design requirements.

[0039] At the same time, in the process of forming the isolation layer 141, in order to increase the process window when forming the second isolation opening and reduce the process difficulty, a second isolation opening spanning the first area I and the second area II is formed to increase the size of the second isolation opening in at least one direction.

[0040] However, since the sidewall film 120 needs to be formed on the inner wall surface of the initial first conductive opening 111 of the first region I through a deposition process, the sidewall film 120 is filled with the material of the first isolation opening 112 to form the sidewall 121 of the second region II. Therefore, the sidewall film 120 is prone to produce concave or notch-shaped defects (such as Figure 3 At the same time, since the second isolation opening spans across the first region I and the second region II, and exposes the sidewall film 120 in the first isolation opening 112, after the initial isolation layer 140 is etched back to form the isolation layer 141, the material of the initial isolation layer 140 is likely to remain in the depression or gap, so that in the etching process of removing the sidewall 121, the material of the sidewall 121 below the depression or gap is also likely to remain on the surface of the layer to be etched 100 due to the blocking of the residual material of the initial isolation layer 140. The residual material of the initial isolation layer 140 causes a local difference to be easily generated in the area B with the depression or gap compared with other areas during the process of flattening the conductive structure material layer, resulting in a short circuit between the conductive structures, making the reliability of the semiconductor structure poor.

[0041] In order to solve the above problem, the present invention provides a method for forming a semiconductor structure, which uses the first patterned layer as a mask to thin the sidewall film, thereby improving the reliability of the semiconductor structure.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 6 to 21 It is a structural schematic diagram of each step of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 6 and Figure 7 , Figure 7 yes Figure 6 Schematic diagram of the cross-sectional structure along the direction A1-A2, Figure 6 yes Figure 7A schematic diagram of a top view structure along direction B is provided, providing a layer 200 to be etched, including a first region I and a second region II arranged along a first direction X, wherein the first region I and the second region II are adjacent to each other in the first direction X.

[0045] In this embodiment, the layer to be etched 200 includes a substrate 210 and a first mask material layer 220 located on the substrate 210 .

[0046] In this embodiment, the layer to be etched 200 further includes a second mask material layer 222 located between the substrate 210 and the first mask material layer 220 .

[0047] In another embodiment, the layer to be etched does not include the second mask material layer.

[0048] In this embodiment, the material of the substrate 210 includes aluminum oxide.

[0049] In other embodiments, the material of the substrate includes a low-K dielectric layer (K ​​is less than or equal to 3.9).

[0050] In other embodiments, the material of the substrate includes silicon oxide.

[0051] In this embodiment, the first mask material layer 220 provides material for subsequently forming a first mask layer.

[0052] On the other hand, the first mask material layer 220 can protect the substrate 210 and the second mask material layer 222 in the subsequent etching process of forming the first conductive opening, the second conductive opening, the first isolation opening and the second isolation opening, so as to reduce the damage caused by the etching process to the surface of the substrate 210 and the second mask material layer 222.

[0053] The second mask material layer 222 provides material for subsequently forming a mask layer.

[0054] In this embodiment, the second mask material layer 222 is a hard mask material layer.

[0055] Since the material of the second mask material layer 222 is a hard mask material, that is, the material of the mask layer is a hard mask material, the etching loss of the mask layer is small when the conductive opening is subsequently etched to form the conductive opening. Therefore, in the process of transferring the pattern in the mask layer to the substrate 210, the stability of the pattern transfer is higher.

[0056] The second mask material layer 222 may be a single-layer structure, or a multi-layer structure arranged in a direction perpendicular to the surface of the substrate 210. The material of the second mask material layer 222 includes one or more combinations of silicon oxide, titanium nitride, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide, or aluminum nitride. In this embodiment, the material of the second mask material layer 222 is titanium nitride.

[0057] It should be noted that the number of the first area I may be one or more, and the number of the second area II may be one or more. Figure 6 In the description, an example is given in which the number of the first zones I is 3 and the number of the second zones II is 2.

[0058] Next, a sacrificial layer is formed on the layer to be etched 200, wherein the sacrificial layer has a first conductive opening and a first isolation opening connected to each other, wherein the first conductive opening is located on the first region I, and the first isolation opening penetrates the sacrificial layer on the second region II along a second direction Y, wherein the second direction Y is perpendicular to the first direction X. For the specific steps of forming the sacrificial layer, please refer to Figures 8 to 9 .

[0059] Please refer to Figure 8 , forming a sacrificial material layer 230 on the layer to be etched 200; etching the sacrificial material layer 230 to form a first conductive opening 231 in the sacrificial material layer 230 on the first region I.

[0060] The sacrificial material layer 230 provides material for forming a sacrificial layer.

[0061] The material of the sacrificial material layer 230 includes silicon.

[0062] In this embodiment, the sacrificial material layer 230 is made of amorphous silicon.

[0063] In other embodiments, the material of the sacrificial material layer includes single crystal silicon or polycrystalline silicon.

[0064] In the present embodiment, the process of forming the sacrificial material layer 230 includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0065] In this embodiment, the first conductive opening 231 extends along the second direction Y.

[0066] In this embodiment, the method for forming the first conductive opening 231 includes: forming a first conductive opening patterned layer (not shown) on the surface of the sacrificial material layer 230, the first conductive opening patterned layer exposing the surface of the sacrificial material layer 230 on the first region I; using the first conductive opening patterned layer as a mask, etching the sacrificial material layer 230 until the surface of the layer to be etched 200 is exposed, and forming a first conductive opening 231 in the sacrificial material layer 230 on the first region I.

[0067] In this embodiment, the process of etching the sacrificial material layer 230 to form the first conductive opening 231 includes a dry etching process or a wet etching process.

[0068] In this embodiment, after the first conductive opening 231 is formed, the first conductive opening patterning layer is removed.

[0069] In this embodiment, the material of the first conductive opening patterned layer includes photoresist, and the process of removing the first conductive opening patterned layer includes a protective ashing process and the like.

[0070] Please refer to Fig. 9 After forming the first conductive opening 231 , the sacrificial material layer 230 is etched to form a first isolation opening 232 in the sacrificial material layer 230 on the second region II to form a sacrificial layer 233 .

[0071] In this embodiment, since the sacrificial material layer 230 provides material for the sacrificial layer 233 , the material of the sacrificial layer 233 includes silicon.

[0072] In this embodiment, the material of the sacrificial layer 233 is amorphous silicon.

[0073] In other embodiments, the material of the sacrificial layer includes single crystal silicon or polycrystalline silicon.

[0074] The first conductive opening 231 and the first isolating opening 232 are connected in the sacrificial layer 233 . The first conductive opening 231 is located on the first region I, and the first isolating opening 232 penetrates the sacrificial layer 233 on the second region II along the second direction Y.

[0075] In this embodiment, the method for forming the first isolation opening 232 includes: Figure 8A first isolation opening patterned layer (not shown) is formed on the surface of the first conductive opening 231, and the first isolation opening patterned layer exposes the surface of the sacrificial material layer 230 on the second region II; using the first isolation opening patterned layer as a mask, the sacrificial material layer 230 is etched until the surface of the layer to be etched 200 is exposed, and a first isolation opening 232 is formed in the sacrificial material layer 230 on the second region II.

[0076] In this embodiment, the process of etching the sacrificial material layer 230 to form the first isolation opening 232 includes a dry etching process or a wet etching process.

[0077] In this embodiment, after the first partition opening 232 is formed, the first partition opening patterning layer is removed.

[0078] In this embodiment, the material of the first isolation opening patterning layer includes photoresist, and the process of removing the first isolation opening patterning layer includes a protective ashing process and the like.

[0079] Please refer to Fig.10 and Fig.11 , Fig.11 yes Fig.10 Schematic diagram of the cross-sectional structure along the direction C1-C2, Fig.10 yes Fig.11 In the schematic diagram of the top view of the structure along the direction B, a sidewall film 240 is formed on the surface of the sacrificial layer 233 , and the sidewall film 240 fills the first isolation opening 232 .

[0080] The spacer film 240 provides material for the subsequent formation of spacers.

[0081] In this embodiment, the material of the spacer film 240 includes titanium oxide. Therefore, the material of the spacer also includes titanium oxide.

[0082] Specifically, in this embodiment, the material of the spacer film 240 is deposited on the surface of the sacrificial layer 233 on the to-be-etched layer 200 , the inner wall surface of the first conductive opening 231 , and the first isolation opening 232 to form the spacer film 240 .

[0083] In this embodiment, the deposition process for forming the spacer film 240 is an atomic layer deposition process.

[0084] In other embodiments, the deposition process for forming the spacer film includes a chemical vapor deposition process or a physical vapor deposition process.

[0085] When the spacer film 240 is filled completely into the first isolation opening 232 through a deposition process, the spacer film 240 may easily generate a concave or notch-shaped defect as shown in area D due to insufficient filling.

[0086] Specifically, in this embodiment, a surface of the sidewall film 240 in the first partition opening 232 has a notch (not shown).

[0087] Please refer to Fig.12 and Fig.13 , Fig.13 yes Fig.12 Schematic diagram of the cross-sectional structure along the direction C1-C2, Fig.12 yes Fig.13 A schematic diagram of the top-down structure along the middle direction B, wherein a first patterned layer 250 is formed on the side wall film 240, wherein the first patterned layer 250 has a second isolation opening 251 therein, wherein the second isolation opening 251 penetrates the sacrificial layer 233 on the first region I and the second region II along the second direction Y, and the second isolation opening 251 on the second region II exposes the side wall film 240 in the first isolation opening 232.

[0088] By allowing the second isolation opening 251 to penetrate the sacrificial layer 233 on the first area I and the second area II along the second direction Y and exposing the sidewall film 240 in the first isolation opening 232, a second isolation opening 251 with a larger size in the first direction X is formed, thereby increasing the process window for forming the first patterned layer 250, thereby reducing the process difficulty of forming the first patterned layer 250.

[0089] Specifically, in this embodiment, the method for forming the first patterned layer 250 includes: forming a photoresist material layer (not shown) on the sidewall film 240 ; and performing exposure and development processes on the photoresist material layer to form the first patterned layer 250 .

[0090] Please refer to Fig.14 , Fig.14 and Fig.13 The viewing direction is consistent with that of the embodiment, and the sidewall film 240 is thinned using the first patterned layer 250 as a mask.

[0091] Since the sidewall film 240 is thinned by using the first patterned layer 250 as a mask after the first patterned layer 250 is formed, the depth of the depression on the surface of the sidewall film 240 in the first isolation opening 232 can be reduced, or the depression or notch on the surface of the sidewall film 240 in the first isolation opening 232 can be removed, so that the surface of the sidewall film 240 is smoother, so that the material (second isolation layer) subsequently deposited on the surface of the sidewall film 240 is not easy to produce local residue after etching or flattening, thereby improving the reliability of the semiconductor structure. Therefore, through the method for forming the semiconductor structure, the reliability of the semiconductor structure is improved while reducing the process difficulty.

[0092] In this embodiment, in a direction perpendicular to the surface of the to-be-etched layer 200 , the spacer film 240 in the second partition opening 251 is thinned to a thickness ranging from 3 angstroms to 10 angstroms.

[0093] If the thickness of the sidewall film 240 is too small, the depth of the depression or notch on the surface of the sidewall film 240 in the first isolation opening 232 is still large, which increases the risk of residual material in the second isolation layer. If the thickness of the sidewall film 240 is too large, over-etching is likely to occur, resulting in damage to the surface of the layer 200 to be etched. Therefore, a suitable range of the thickness of the sidewall film 240 is selected, that is, when the thickness of the sidewall film 240 is in the range of 3 angstroms to 10 angstroms, on the one hand, the depth of the depression on the surface of the sidewall film 240 in the first isolation opening 232 is better reduced, or the depression or notch on the surface of the sidewall film 240 in the first isolation opening 232 is better removed, so as to better reduce the risk of residual material in the second isolation layer. On the other hand, the risk of damage to the surface of the layer 200 to be etched is also reduced.

[0094] Specifically, in this embodiment, the method of thinning the sidewall film 240 using the first patterned layer 250 as a mask includes: using the first patterned layer 250 as a mask, etching the sidewall film 240 until the gap is removed, so that the surface of the sidewall film 240 in the first isolation opening 250 is flush.

[0095] Since the sidewall film 240 is etched until the gap is removed, the surface of the sidewall film 240 in the first isolating opening 232 is flush. Therefore, it is ensured that the gap on the surface of the sidewall film 240 in the first isolating opening 232 is completely removed, so that the surface of the sidewall film 240 in the first isolating opening 232 is flush, thereby further improving the flatness of the surface of the sidewall film 240 in the first isolating opening 232, so that the material subsequently deposited on the surface of the sidewall film 240 will not produce local residue after the etching or planarization process, so as to better improve the reliability of the semiconductor structure.

[0096] In this embodiment, the process of etching the sidewall film 240 using the first patterned layer 250 as a mask includes a dry etching process.

[0097] The parameters of the dry etching process include: the etching gas includes chlorine; the temperature range is 40 degrees Celsius to 50 degrees Celsius; the pressure range is 40 mTorr to 60 mTorr.

[0098] Please refer to Fig.15 , Fig.15 and Fig.14In accordance with the viewing direction, after the sidewall film 240 is thinned using the first patterned layer 250 as a mask, a second partition material layer 260 is formed on the surface of the sidewall film 240 in the second partition opening 251, and the second partition material layer 260 fills the second partition opening 251.

[0099] The second partition material layer 260 provides material for subsequently forming a second partition layer.

[0100] The second partition material layer 260 is made of oxide.

[0101] In the present embodiment, the material of the second isolation material layer 260 includes a low temperature oxide formed in a preset low temperature environment, and the temperature range of the preset low temperature environment is 50 degrees Celsius to 100 degrees Celsius.

[0102] Specifically, the low temperature oxide includes low temperature silicon oxide.

[0103] The material of the second partition layer is the same as that of the second partition material layer 260 , and will not be described in detail herein.

[0104] In this embodiment, the process of forming the second partition material layer 260 includes a chemical vapor deposition process.

[0105] The chemical vapor deposition process is performed in a vacuum environment, and the temperature range of the chemical vapor deposition process is 50 degrees Celsius to 100 degrees Celsius.

[0106] Please refer to Fig.16 , Fig.16 and Fig.15 The second partition material layer 260 is planarized until the top surface of the sidewall film 240 in the first partition opening 232 is exposed to form a second partition layer 261.

[0107] In this embodiment, the process of planarizing the second isolation material layer 260 includes a chemical mechanical planarization process.

[0108] In other embodiments, the second isolation material layer is planarized by etching back the second isolation material layer.

[0109] In this embodiment, during the process of planarizing the second isolation layer 261 , the first patterned layer 250 is removed.

[0110] Specifically, in this embodiment, while the second partition material layer 260 is planarized, the first patterned layer 250 is also planarized to remove the first patterned layer 250 .

[0111] In other embodiments, during the process of etching back the second isolation material layer, the first patterned layer is also etched back to remove the first patterned layer.

[0112] In other embodiments, the method for removing the first patterned layer includes: flattening the second partition material layer until the surface of the first patterned layer is exposed; removing the first patterned layer using an ashing process; after removing the first patterned layer, continuing to flatten the second partition material layer until the top surface of the side wall film in the first partition opening is exposed.

[0113] Please refer to Fig.17 , Fig.17 and Fig.12 In accordance with the viewing direction, after forming the second isolation layer 261, an anisotropic etching process is used to etch the sidewall film 240 on the surface of the sacrificial layer 233 until the surface of the sacrificial layer 233 is exposed, and a sidewall 241 is formed on the sidewall surface of the first conductive opening 231 and the first isolation opening 232.

[0114] The sidewall spacer 241 on the first region I can play a role of spacing the first conductive opening 231 and the second conductive opening in the subsequent etching process for forming the second conductive opening, and realize etching self-alignment in the etching process.

[0115] Through the sidewall 241 on the second region II (the sidewall 241 in the first isolation opening 232), the conductive openings formed in the second region II are spaced apart. Through the second isolation layer 261 on the first region I, the conductive openings formed in the first region I are spaced apart. Thus, a conductive structure that meets the design requirements is formed.

[0116] In this embodiment, the anisotropic etching process includes a plasma etching process.

[0117] Please refer to the payment Fig.18 , Fig.18 and Fig.17 In the same viewing direction, after forming the sidewall 241, the sacrificial layer 233 is etched to form a second conductive opening 234 in the sacrificial layer 233 on the second region II.

[0118] Specifically, the method for forming the second conductive opening 234 includes: forming a second patterned layer (not shown) on the surface of the sacrificial layer 233, and having a second conductive pattern opening (not shown) extending along the second direction Y in the second patterned layer on the second region II, wherein the second conductive pattern opening exposes the side wall surface of the side wall 241 on the first region I, and the side wall 241 on the second region II passes through the second conductive pattern opening; using the second patterned layer and the side wall 241 as a mask, etching the sacrificial layer 233 until the surface of the layer to be etched 200 is exposed, thereby forming a second conductive opening 234 in the sacrificial layer 233.

[0119] In this embodiment, the process of etching the sacrificial layer 233 to form the second conductive opening 234 includes a dry etching process or a wet etching process.

[0120] In this embodiment, after the second conductive opening 234 is formed, the second patterned layer is removed.

[0121] In this embodiment, the material of the second patterned layer includes photoresist, and the process for removing the second patterned layer includes a protective ashing process and the like.

[0122] Next, the sacrificial layer 233, the sidewall 241 and the second partition layer 261 are used as masks to etch the layer 200 to be etched. For details on the process of etching the layer 200 to be etched, please refer to Figures 19 to 20 .

[0123] Please refer to Fig.19 , Fig.19 and Fig.18 The sacrificial layer 233 , the sidewall 241 and the second partition layer 261 are used as masks to etch the first mask material layer 220 until the surface of the second mask material layer 222 is exposed to form a first mask layer 221 .

[0124] In this embodiment, the process of etching the first mask material layer 220 includes a dry etching process or a wet etching process.

[0125] In this embodiment, after the first mask layer 221 is formed, the sacrificial layer 233 , the sidewall spacer 241 and the second isolation layer 261 are removed.

[0126] Please refer to Fig. 20 , Fig. 20 and Fig.19 In accordance with the viewing direction, the first mask layer 221 is used as a mask to etch the second mask material layer 222 until the surface of the substrate 210 is exposed to form a mask layer 224; the mask layer 224 is used as a mask to etch the substrate 210 to form a plurality of conductive openings 211 in the substrate 210.

[0127] The plurality of conductive openings provide space for subsequently forming a conductive structure.

[0128] In this embodiment, the process of etching the second mask material layer 222 includes a dry etching process or a wet etching process.

[0129] In this embodiment, the process of etching the substrate 210 includes a dry etching process or a wet etching process.

[0130] In this embodiment, after the mask layer 224 is formed, the first mask layer 221 is removed.

[0131] In this embodiment, after a plurality of conductive openings 211 are formed, the mask layer 224 is removed.

[0132] In another embodiment, the second mask material layer is not formed. The method for etching the layer to be etched includes: using the sacrificial layer, the sidewall and the second isolation layer as a mask, etching the first mask material layer until the surface of the substrate is exposed to form a mask layer; using the mask layer as a mask, etching the substrate to form a plurality of conductive openings in the substrate.

[0133] Please refer to Fig.21 , Fig.21 and Fig. 20 In the same viewing direction, a conductive structure 270 is formed in the plurality of conductive openings 211 .

[0134] The method for forming the conductive structure 270 includes: forming a conductive structure material layer in the plurality of conductive openings 211 and on the surface of the substrate 210, wherein the conductive structure material layer fills the plurality of conductive openings 211; flattening the conductive structure material layer until the surface of the substrate 210 is exposed, and forming a plurality of conductive structures in the substrate 210.

[0135] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, wherein the layer to be etched includes a first region and a second region arranged along a first direction, and the first region and the second region are adjacent to each other in the first direction; Forming a sacrificial layer on the layer to be etched, wherein the sacrificial layer has a first conductive opening and a first isolation opening that are connected, the first conductive opening is located on the first area, and the first isolation opening penetrates the sacrificial layer on the second area along a second direction, and the second direction is perpendicular to the first direction; forming a sidewall film on the surface of the sacrificial layer, wherein the sidewall film completely fills the first isolation opening; forming a first patterned layer on the sidewall film, wherein the first patterned layer has a second isolation opening, the second isolation opening penetrates the sacrificial layer on the first region and the second region along a second direction, and the second isolation opening on the second region exposes the sidewall film in the first isolation opening; The sidewall film is thinned using the first patterned layer as a mask.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After thinning the sidewall film using the first patterned layer as a mask, a second partition material layer is formed on the surface of the sidewall film in the second partition opening, and the second partition material layer fills the second partition opening; the second partition material layer is flattened until the top surface of the sidewall film in the first partition opening is exposed to form a second partition layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: In the process of planarizing the second isolation layer, the first patterned layer is removed.

4. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: After forming the second isolation layer, an anisotropic etching process is used to etch the sidewall film on the surface of the sacrificial layer until the surface of the sacrificial layer is exposed, and a sidewall is formed on the sidewall surface of the first conductive opening and in the first isolation opening.

5. The method for forming a semiconductor structure according to claim 4, wherein: Also includes: After forming the sidewall, a second patterned layer is formed on the surface of the sacrificial layer, and a second conductive pattern opening extending along a second direction is provided in the second patterned layer on the second area, the second conductive pattern opening exposes the sidewall surface of the sidewall on the first area, and the sidewall on the second area passes through the second conductive pattern opening; The sacrificial layer is etched using the second patterned layer and the sidewalls as masks until the surface of the layer to be etched is exposed, and a second conductive opening is formed in the sacrificial layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: Also includes: The layer to be etched is etched using the sacrificial layer, the sidewalls and the second partition layer as masks.

7. The method for forming a semiconductor structure according to claim 6, wherein: The layer to be etched includes a substrate and a first mask material layer located on the substrate.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for etching the layer to be etched comprises: using the sacrificial layer, the sidewall and the second isolation layer as masks, etching the first mask material layer until the substrate surface is exposed to form a mask layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for etching the layer to be etched also includes: using the mask layer as a mask to etch the substrate to form a plurality of conductive openings in the substrate; the method for forming the semiconductor structure also includes: forming a conductive structure in the plurality of conductive openings.

10. The method for forming a semiconductor structure according to claim 7, wherein: The layer to be etched further includes a second mask material layer located between the substrate and the first mask material layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for etching the layer to be etched includes: using the sacrificial layer, the side wall and the second isolation layer as masks, etching the first mask material layer until the surface of the second mask material layer is exposed to form a first mask layer; using the first mask layer as a mask, etching the second mask material layer until the surface of the substrate is exposed to form a mask layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for etching the layer to be etched also includes: using the mask layer as a mask to etch the substrate to form a plurality of conductive openings in the substrate; the method for forming the semiconductor structure also includes: forming a conductive structure in the plurality of conductive openings.

13. The method for forming a semiconductor structure according to claim 1, wherein: In a direction perpendicular to the substrate surface, the reduced thickness of the spacer film in the second isolation opening is in a range of 3 angstroms to 10 angstroms.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the sidewall film using the first patterned layer as a mask includes a dry etching process.

15. The method for forming a semiconductor structure according to claim 14, wherein: The parameters of the dry etching process include: the etching gas includes chlorine; the temperature range is 40 degrees Celsius to 50 degrees Celsius; the pressure range is 40 mTorr to 60 mTorr.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the spacer film includes titanium oxide, and the material of the sacrificial layer includes silicon.

17. The method for forming a semiconductor structure according to claim 2, wherein: The material of the second isolation layer includes a low-temperature oxide formed in a preset low-temperature environment, and the temperature range of the preset low-temperature environment is 50 degrees Celsius to 100 degrees Celsius.

18. The method for forming a semiconductor structure according to claim 1, wherein: The surface of the sidewall film in the first isolation opening has a notch; the method of thinning the sidewall film using the first patterned layer as a mask includes: using the first patterned layer as a mask, etching the sidewall film until the notch is removed, so that the surface of the sidewall film in the first isolation opening is flush.

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