A negative capacitance fin-type gallium nitride-based power transistor and its fabrication method

Abstract

This invention relates to a negative capacitance fin-gate gallium nitride (GaN)-based power transistor and its fabrication method. The negative capacitance fin-gate GaN-based power transistor includes, from bottom to top: a substrate, a gallium nitride (GaN) channel layer, an aluminum gallium nitride (AGaN) barrier layer, an oxide layer, a ferroelectric dielectric layer, and a gate. The gate has a three-dimensional fin structure, and from top to bottom, it covers the ferroelectric dielectric layer, oxide layer, AGaN barrier layer, and GaN channel layer. The oxide layer and ferroelectric dielectric layer form a three-dimensional fin structure within the area covered by the gate. A source is located at one end of the upper surface of the AGaN barrier layer, and a drain is located at the other end. The oxide layer and ferroelectric dielectric layer are located between the source and drain and connect the drain and source. This invention employs a negative capacitance fin-gate GaN-based power transistor, utilizing the negative capacitance characteristic of the ferroelectric dielectric to make the voltage applied to the oxide surface greater than the gate voltage, providing a higher power amplification factor with the same channel width and improving the gate control capability of the GaN-based power transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a negative capacitance fin-type gallium nitride-based power transistor and its fabrication method. Background Technology

[0002] Currently, fin-gate gallium nitride-based power transistors are mainly used to solve the problems of poor gate control capability and numerous parasitic effects in short-channel lateral devices. However, since the three-sided gate will deplete part of the two-dimensional electron gas, thereby reducing the channel current density, there is a design contradiction between gate control capability (corresponding to a smaller subthreshold swing) and power amplification capability in traditional fin-gate gallium nitride-based power transistors. In other words, a narrower channel width corresponds to stronger gate control capability, but at the same time corresponds to a smaller current density and power amplification factor. That is, there is a problem that gate control capability and power amplification capability cannot be optimized at the same time. Summary of the Invention

[0003] The purpose of this invention is to provide a negative capacitance fin-gate gallium nitride-based power transistor and its fabrication method, which can improve the amplification factor and gate control capability of the device when used for power amplification.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] This invention provides a negative capacitance fin-type gallium nitride-based power transistor, comprising, from bottom to top, a substrate, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, an oxide layer, a ferroelectric dielectric layer, and a gate. The gate has a three-dimensional fin structure, and the gate covers the ferroelectric dielectric layer, the oxide layer, the aluminum gallium nitride barrier layer, and the gallium nitride channel layer from top to bottom. The oxide layer and the ferroelectric dielectric layer form a three-dimensional fin structure in the region covered by the gate.

[0006] The upper surface of the aluminum gallium nitride barrier layer has a source at one end and a drain at the other end; the oxide layer and the ferroelectric layer are located between the source and the drain, and connect the drain and the source.

[0007] Optionally, it also includes:

[0008] A passivation layer is located on the aluminum gallium nitride barrier layer and between the gate and the source and between the gate and the drain.

[0009] Optionally, it also includes:

[0010] A buffer layer is located on the substrate.

[0011] Optionally, it also includes:

[0012] The 2DEG layer is located between the gallium nitride channel layer and the aluminum gallium nitride barrier layer.

[0013] Optionally, the substrate is made of silicon, sapphire, silicon carbide, or gallium nitride.

[0014] Optionally, the oxide layer is made of Al2O3 or SiO2.

[0015] Optionally, the ferroelectric dielectric layer is made of BaTiO3 or PbZr. x Ti 1-x O3 or Hf x Zr 1-x O2.

[0016] Optionally, the passivation layer is made of Si3N4, Si3N4 / AlN, or Si3N4 / SiON.

[0017] Optionally, the buffer layer is made of gallium nitride doped with carbon, gallium nitride doped with iron, aluminum nitride / gallium nitride superlattice structure, or aluminum gallium nitride / gallium nitride superlattice structure.

[0018] To achieve the above objectives, the present invention also provides a method for fabricating the aforementioned negative capacitance fin-gate gallium nitride-based power transistor, comprising:

[0019] S1: A buffer layer, a gallium nitride channel layer, and an aluminum gallium nitride barrier layer are sequentially deposited on the substrate;

[0020] S2: Etch the buffer layer, the gallium nitride channel layer and the aluminum gallium nitride barrier layer to form a buffer layer, gallium nitride channel layer and aluminum gallium nitride barrier layer with a three-dimensional fin structure;

[0021] S3: Perform mesa isolation on the substrate, the buffer layer, the gallium nitride channel layer and the aluminum gallium nitride barrier layer, and determine the dimensions of the substrate, the buffer layer, the gallium nitride channel layer and the aluminum gallium nitride barrier layer;

[0022] S4: Perform surface treatment on the substrate, the buffer layer, the gallium nitride channel layer, and the aluminum gallium nitride barrier layer after the mesa isolation is completed;

[0023] S5: A passivation layer is deposited on the aluminum gallium nitride barrier layer using a PECVD deposition process;

[0024] S6: The passivation layer of the gate coverage area is etched away using a wet etching process;

[0025] S7: Deposit an oxide layer on the passivation layer;

[0026] S8: Deposit a ferroelectric layer on the oxide layer;

[0027] S9: Wet etching process is used to remove the passivation layer, oxide layer and ferroelectric layer under the source and drain regions to form source region windows and drain region windows;

[0028] S10: The ohmic contact metal is evaporated on the source and drain regions using electron beam evaporation technology, and then annealed at high temperature to form the source and drain.

[0029] S11: A gate region window is obtained using photolithography. Schottky contact metal is evaporated on the gate region window to form a gate with a three-dimensional fin structure.

[0030] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] This invention provides a negative capacitance fin-gate gallium nitride-based power transistor and its fabrication method. The negative capacitance fin-gate gallium nitride-based power transistor includes, from bottom to top, a substrate, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, an oxide layer, a ferroelectric dielectric layer, and a gate. The gate has a three-dimensional fin structure, and the gate covers the ferroelectric dielectric layer, oxide layer, aluminum gallium nitride barrier layer, and gallium nitride channel layer from top to bottom. The oxide layer and ferroelectric dielectric layer form a three-dimensional fin structure within the area covered by the gate. One end of the upper surface of the aluminum gallium nitride barrier layer is provided with a source, and the other end is provided with a drain. The oxide layer and ferroelectric dielectric layer are located between the source and drain, and connect the drain and the source. This invention uses a negative capacitance fin-gate gallium nitride-based power transistor, utilizing the negative capacitance characteristic of the ferroelectric dielectric to make the voltage applied to the oxide layer surface greater than the gate voltage. This allows for a higher power amplification factor with the same channel width, and the fin gate parameter design tends to use a narrower channel width, thus improving the gate control capability of the gallium nitride-based power transistor. Attached Figure Description

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a two-dimensional structural schematic diagram of the negative capacitance fin gate gallium nitride-based power transistor of the present invention;

[0034] Figure 2 This is a schematic diagram of the XZ plane cross-section of the negative capacitance fin-gate gallium nitride-based power transistor of the present invention;

[0035] Figure 3 This is a schematic diagram of the YZ plane cross-section of the negative capacitance fin-gate gallium nitride-based power transistor of the present invention;

[0036] Figure 4 This is a schematic diagram of the three-dimensional structure of the negative capacitance fin gate gallium nitride-based power transistor of the present invention in the YZ plane cross section.

[0037] Figure 5 This is a flowchart illustrating the fabrication method of the negative capacitance fin gate gallium nitride-based power transistor of the present invention.

[0038] Symbol explanation:

[0039] Substrate-1, Buffer layer-2, Gallium nitride channel layer-3, Aluminum gallium nitride barrier layer-4, Passivation layer-5, Oxide layer-6, Ferroelectric layer-7, Source-8, Drain-9, Gate-10, 2DEG layer-11. Detailed Implementation

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0041] The purpose of this invention is to provide a negative capacitance fin-gate gallium nitride-based power transistor and its fabrication method, which can improve the amplification factor and gate control capability of the device when used for power amplification.

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] like Figures 1-4 As shown, the present invention provides a negative capacitance fin-type gallium nitride-based power transistor, comprising, from bottom to top, a substrate 1, a gallium nitride channel layer 3, an aluminum gallium nitride barrier layer 4, an oxide layer 6, a ferroelectric dielectric layer 7, and a gate 10. The gate 10 has a three-dimensional fin structure. The gate 10 covers the ferroelectric dielectric layer 7, the oxide layer 6, the aluminum gallium nitride barrier layer 4, and the gallium nitride channel layer 3 from top to bottom. The oxide layer 6 and the ferroelectric dielectric layer 7 form a three-dimensional fin structure in the area covered by the gate 10.

[0044] The upper surface of the aluminum gallium nitride barrier layer 4 has a source 8 at one end and a drain 9 at the other end; the oxide layer 6 and the ferroelectric layer 7 are located between the source 8 and the drain 9, and connect the drain 9 and the source 8. A finned gate structure is employed to achieve better linearity when used as a radio frequency device.

[0045] Preferably, if Figure 1As shown, it also includes: passivation layer 5.

[0046] The passivation layer 5 is located on the aluminum gallium nitride barrier layer 4, and is situated between the gate 10 and the source 8, and between the gate 10 and the drain 9. The passivation layer 5 is used to reduce surface traps and fill carbon vacancies. Further, the material of the passivation layer 5 is Si3N4, Si3N4 / AlN, or Si3N4 / SiON.

[0047] Preferably, if Figure 1 As shown, it also includes: buffer layer 2.

[0048] The buffer layer 2, located on the substrate 1, is introduced to achieve stress relief and dislocation filtering, thereby obtaining a more perfect crystal quality. Further, the buffer layer is made of iron-doped or carbon-doped gallium nitride or an Al(Ga)N / GaN superlattice structure. Specifically, in a specific embodiment of the present invention, the buffer layer 2 protrudes upwards and is covered by a three-dimensional fin-structured oxide layer. Alternatively, the buffer layer can also be a planar structure without an upwardly protruding portion.

[0049] Furthermore, it also includes: 2DEG layer 11.

[0050] The 2DEG layer is located between the gallium nitride channel layer 3 and the aluminum gallium nitride barrier layer 4, that is, above the contact surface between the gallium nitride channel layer 3 and the aluminum gallium nitride barrier layer 4. Through piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas 11 (2DEG) is generated on the side near the gallium nitride channel layer 3, which serves as the conductive channel of the device. It is the high electron concentration and high electron mobility of the 2DEG that enable the device to have a large output current and power gain.

[0051] Specifically, the substrate 1 is made of silicon, sapphire, silicon carbide or gallium nitride, and the substrate 1 is placed at the bottom of the entire structure to provide support.

[0052] Preferably, the oxide layer 6 is made of Al2O3 or SiO2.

[0053] Furthermore, the ferroelectric dielectric layer is made of BaTiO3 (BTO) or PbZr. x Ti 1-x O3 (PZT) or Hf x Zr 1-x Perovskite structure materials such as O2 (HZO) are used. Utilizing the negative capacitance characteristic of ferroelectric materials, the voltage applied to the oxide layer 6 surface is made greater than the gate voltage, thereby improving the power amplification capability of the transistor.

[0054] To achieve the above objectives, such as Figure 5As shown, the present invention also provides a method for fabricating the aforementioned negative capacitance fin-gate gallium nitride-based power transistor, comprising:

[0055] S1: A buffer layer, a gallium nitride channel layer, and an aluminum gallium nitride barrier layer are sequentially deposited on the substrate.

[0056] S2: Etch the buffer layer, the gallium nitride channel layer, and the aluminum gallium nitride barrier layer to form a buffer layer, gallium nitride channel layer, and aluminum gallium nitride barrier layer with a three-dimensional fin structure.

[0057] S3: Perform mesa isolation on the substrate, the buffer layer, the gallium nitride channel layer, and the aluminum gallium nitride barrier layer, and determine the dimensions of the substrate, the buffer layer, the gallium nitride channel layer, and the aluminum gallium nitride barrier layer.

[0058] S4: Perform surface treatment on the substrate, buffer layer, gallium nitride channel layer, and aluminum gallium nitride barrier layer after mesa isolation is completed. For example, acid treatment: HCl, H2SO4+H2O2, BOE.

[0059] S5: A passivation layer is deposited on the aluminum gallium nitride barrier layer using a PECVD deposition process.

[0060] S6: The passivation layer of the gate coverage area is etched away using a wet etching process.

[0061] S7: Deposit an oxide layer on the passivation layer.

[0062] S8: Deposit a ferroelectric layer on the oxide layer.

[0063] S9: Wet etching process is used to remove the passivation layer, oxide layer and ferroelectric layer under the source and drain regions to form source region windows and drain region windows.

[0064] S10: Using electron beam evaporation, ohmic contact metals (such as Ti / Al / Ni / Au or Ti / Al / Mo / Au) are evaporated on the source and drain regions, and then annealed at high temperature to form the source and drain.

[0065] S11: A gate region window is obtained using photolithography. Schottky contact metals (Ni and Au) are evaporated on the gate region window to form a gate with a three-dimensional fin structure.

[0066] Technical effects of the present invention:

[0067] This invention, based on conventional three-sided gate-surrounded Fin-HEMT, forms a ferroelectric dielectric material between the gate oxide (e.g., Al2O3 / SiO2) and the gate metal. The resulting fin-gate gallium nitride power transistor exhibits a higher power amplification factor than traditional fin-gate gallium oxide transistors and achieves a higher microwave cutoff frequency f. T (or current cutoff frequency) and maximum oscillation frequency f MAX (or gain cutoff frequency) and also has good RF linearity.

[0068] The higher power amplification factor stems from the characteristics of the ferroelectric layer between the gate and the oxide layer, which allows the voltage applied to the oxide layer surface to be greater than the gate voltage, thereby increasing the amplification factor of the device when used for power amplification. The microwave cutoff frequency f... T and maximum oscillation frequency f MAX The linearity will also improve with the increase of the amplification factor. The improved linearity is due to the fin gate structure. In the fin gate structure, the gate surrounds the conductive channel on three sides, and the two side gates also form a metal-oxide-semiconductor (MOS) channel with the semiconductor. When the gate voltage is greater than a certain value, the two side MOS channels also contribute current, so that the transconductance of the device remains at a high value over a large range of gate voltages, thereby improving the linearity of the device as an RF power amplifier.

[0069] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0070] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A negative capacitance fin-gate gallium nitride-based power transistor, characterized in that, include: The structure consists of, from bottom to top, a substrate, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, an oxide layer, a ferroelectric dielectric layer, and a gate. The gate has a three-dimensional fin structure. The gate covers the ferroelectric dielectric layer, the oxide layer, the aluminum gallium nitride barrier layer, and the gallium nitride channel layer from top to bottom. The oxide layer and the ferroelectric dielectric layer form a three-dimensional fin structure within the area covered by the gate. The upper surface of the aluminum gallium nitride barrier layer has a source at one end and a drain at the other end; the oxide layer and the ferroelectric layer are located between the source and the drain, and connect the drain and the source. The ferroelectric dielectric layer is made of BaTiO3 and PbZr. x Ti 1-x O3 or Hf x Zr 1-x O2.

2. The negative capacitance fin-gate gallium nitride-based power transistor according to claim 1, characterized in that, Also includes: A passivation layer is located on the aluminum gallium nitride barrier layer and between the gate and the source and between the gate and the drain.

3. The negative capacitance fin-gate gallium nitride-based power transistor according to claim 1, characterized in that, Also includes: A buffer layer is located on the substrate.

4. The negative capacitance fin-gate gallium nitride-based power transistor according to claim 1, characterized in that, Also includes: The 2DEG layer is located between the gallium nitride channel layer and the aluminum gallium nitride barrier layer.

5. A negative capacitance fin-gate gallium nitride-based power transistor according to claim 1, characterized in that, The substrate is made of silicon, sapphire, silicon carbide, or gallium nitride.

6. A negative capacitance fin-gate gallium nitride-based power transistor according to claim 1, characterized in that, The oxide layer is made of Al2O3 or SiO2.

7. A negative capacitance fin-gate gallium nitride-based power transistor according to claim 2, characterized in that, The passivation layer is made of Si3N4, Si3N4 / AlN, or Si3N4 / SiON.

8. A negative capacitance fin-gate gallium nitride-based power transistor according to claim 3, characterized in that, The buffer layer is made of gallium nitride doped with carbon, gallium nitride doped with iron, aluminum nitride / gallium nitride superlattice structure, or aluminum gallium nitride / gallium nitride superlattice structure.

9. A method for fabricating a negative capacitance fin-gate gallium nitride-based power transistor according to any one of claims 1-8, characterized in that, include: S1: A buffer layer, a gallium nitride channel layer, and an aluminum gallium nitride barrier layer are sequentially deposited on the substrate; S2: Etch the buffer layer, the gallium nitride channel layer and the aluminum gallium nitride barrier layer to form a buffer layer, gallium nitride channel layer and aluminum gallium nitride barrier layer with a three-dimensional fin structure; S3: Perform mesa isolation on the substrate, the buffer layer, the gallium nitride channel layer and the aluminum gallium nitride barrier layer, and determine the dimensions of the substrate, the buffer layer, the gallium nitride channel layer and the aluminum gallium nitride barrier layer; S4: Perform surface treatment on the substrate, the buffer layer, the gallium nitride channel layer, and the aluminum gallium nitride barrier layer after the mesa isolation is completed; S5: A passivation layer is deposited on the aluminum gallium nitride barrier layer using a PECVD deposition process; S6: The passivation layer of the gate coverage area is etched away using a wet etching process; S7: Deposit an oxide layer on the passivation layer; S8: Deposit a ferroelectric dielectric layer on the oxide layer; the ferroelectric dielectric layer is made of BaTiO3 and PbZr. x Ti 1-x O3 or Hf x Zr 1-x O 2； S9: Wet etching process is used to remove the passivation layer, oxide layer and ferroelectric layer under the source and drain regions to form source region windows and drain region windows; S10: The ohmic contact metal is evaporated on the source and drain regions using electron beam evaporation technology, and then annealed at high temperature to form the source and drain. S11: A gate region window is obtained using photolithography. Schottky contact metal is evaporated on the gate region window to form a gate with a three-dimensional fin structure.

Images