Switching power supply and control circuit and control method thereof

Abstract

The application discloses a control circuit of a switching power supply, comprising: a slope generation circuit, which generates a slope signal according to a feedback signal representing an output voltage and a first reference voltage; a comparison circuit, which generates a set signal according to the slope signal and a second reference voltage; and a switch control circuit, which outputs a switch control signal and triggers the switch control signal to be valid according to the set signal; wherein the slope generation circuit integrates a difference between the feedback signal and the first reference voltage to generate the slope signal. The application does not need to sample inductance current, the circuit is simple to realize, and the difference between the output voltage and the first reference voltage is integrated to generate a slope signal for comparison, thus avoiding directly using inductance current of a switch circuit to participate in comparison and enhancing the anti-interference capability of the switching power supply.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, in particular to a switching power supply and a control circuit and control method thereof. BACKGROUND

[0002] In the field of consumer electronics, various electronic devices need power supply to maintain, and switching power supply management chip is an indispensable part of electronic system. The switching power supply of constant on-time control mode (COT) is well applied in the field of power supply due to its superior load transient response and smooth working mode switching.

[0003] The switching power supply of constant on-time control mode in the prior art needs a separate current sampling circuit to sample the inductor current as a feedback signal, which increases the complexity of switching power supply control. In addition, when the sampling voltage of inductor current is disturbed by noise, the control signal is easy to be triggered in advance, resulting in unstable system. SUMMARY

[0004] In view of the above, the purpose of the present application is to provide a switching power supply and a control circuit and control method thereof, which enhances the anti-interference ability of the switching power supply.

[0005] According to a first aspect of the present application, a control circuit of a switching power supply is provided, comprising: a slope generation circuit, configured to generate a slope signal according to a feedback signal representing an output voltage and a first reference voltage; a comparison circuit, configured to generate a set signal according to the slope signal and a second reference voltage; and a switch control circuit, configured to output a switch control signal and trigger the switch control signal to be valid according to the set signal; wherein the slope generation circuit is configured to integrate a difference between the feedback signal and the first reference voltage to generate the slope signal.

[0006] Preferably, the control circuit further comprises:

[0007] an error amplification circuit, configured to generate the first reference voltage according to the feedback signal and a third reference voltage.

[0008] Preferably, the slope generation circuit is further configured to generate a first reset signal according to the switch control signal or the set signal, wherein the first reset signal is used to reset the slope signal.

[0009] Preferably, when the slope generation circuit generates the first reset signal according to the switch control signal, the slope signal is reset at a rising edge, a falling edge, an active level or a certain fixed time during the active level of the switch control signal.

[0010] Preferably, the ramp signal is reset at a rising edge of the set signal when the ramp generation circuit generates the first reset signal according to the set signal.

[0011] Preferably, the comparison circuit generates the set signal when the ramp signal reaches a second reference voltage, triggering the switch control signal to be at an active level; and the switch control signal is reset to be at an inactive level when a time duration of the active level of the switch control signal reaches a preset value.

[0012] Preferably, the ramp generation circuit integrates a difference between the feedback signal and the first reference voltage when the feedback signal is less than the first reference voltage, and does not integrate when the feedback signal is greater than or equal to the first reference voltage.

[0013] Preferably, the ramp signal rises when the feedback signal is less than the first reference voltage, and remains unchanged when the feedback signal is greater than or equal to the first reference voltage after the ramp generation signal is reset.

[0014] Preferably, the ramp generation circuit integrates a difference between the feedback signal and the first reference voltage at each moment.

[0015] Preferably, the ramp signal rises when the feedback signal is less than the first reference voltage, and falls when the feedback signal is greater than or equal to the first reference voltage after the ramp generation signal is reset.

[0016] Preferably, the ramp generation circuit comprises a first voltage-controlled current source, a ramp reset control circuit, a first capacitor and a first switch, the first voltage-controlled current source has a first input end receiving a first reference voltage, a second input end receiving the feedback signal, and an output end outputting a current compensation signal; the ramp reset control circuit receives the switch control signal or the set signal, and outputs the first reset signal; the first capacitor and the first switch are connected in parallel between the output end of the first voltage-controlled current source and a ground end; a node between the first capacitor and the first voltage-controlled current source outputs the ramp signal; and the control end of the first switch receives the first reset signal and is turned on or turned off according to the first reset signal.

[0017] Preferably, the first voltage-controlled current source charges the first capacitor when the feedback signal is less than the first reference voltage, and the ramp generation circuit integrates a difference between the feedback signal and the first reference voltage; and the first capacitor neither charges nor discharges the first voltage-controlled current source when the feedback signal is greater than or equal to the first reference voltage, and the ramp generation circuit does not integrate the difference between the feedback signal and the first reference voltage.

[0018] Preferably, the first voltage-controlled current source charges the first capacitor when the feedback signal is less than the first reference voltage; the first capacitor discharges the first voltage-controlled current source when the feedback signal is greater than or equal to the first reference voltage; the ramp generation circuit integrates the difference between the feedback signal and the first reference voltage at each moment.

[0019] Preferably, the switch control circuit comprises: a conduction time control circuit, which generates a second reset signal when the duration of the switch control signal at the active level reaches a preset value; and an RS flip-flop, which generates the switch control signal according to the set signal and the second reset signal.

[0020] According to a second aspect of the present application, a switching power supply is provided, comprising: a plurality of switching circuits for converting an input voltage into an output voltage; a control circuit as described above; wherein each of the switching circuits comprises a drive circuit, a switching bridge arm and an inductor; the switching bridge arm comprises a first power switch and a second power switch, wherein the first power switch and the second power switch are connected in series between the input voltage and a ground terminal; and the inductor is connected between a node between the first power switch and the second power switch and the output voltage.

[0021] Preferably, the control circuit further comprises: a frequency division circuit, which generates a plurality of frequency-divided set signals according to the set signal; and a plurality of switch control circuits, which respectively generate a plurality of switch control signals according to the corresponding frequency-divided set signals.

[0022] Preferably, the drive circuit generates a drive signal according to the corresponding switch control signal, the drive signal comprising a first drive signal and a second drive signal which are completely opposite to each other, wherein the first drive signal of each switching circuit is used to control the conduction and turn-off of the first power switch of the corresponding switching circuit, and the second drive signal of each switching circuit is used to control the conduction and turn-off of the second power switch of the corresponding switching circuit.

[0023] Preferably, when the switch control signal is at the active level, the first power switch of the corresponding switching circuit is turned on, and the second power switch is turned off; and when the switch control signal is at the inactive level, the first power switch of the corresponding switching circuit is turned off, and the second power switch is turned on.

[0024] Preferably, the frequency division number of the frequency division circuit is N, the period of the frequency-divided set signal is N times the period of the set signal, and the phase difference between adjacent frequency-divided set signals is 360° / N, wherein N is an integer greater than or equal to 1.

[0025] According to a third aspect of the present application, a control method of a switching power supply is provided, comprising: generating a ramp signal according to a feedback signal representing an output voltage and a first reference voltage; generating a set signal according to the ramp signal and a second reference voltage; triggering a switch control signal to be active according to the set signal; wherein the ramp signal is generated by integrating a difference between the feedback signal and the first reference voltage.

[0026] Preferably, the control method further comprises: generating the first reference voltage according to the feedback signal and a third reference voltage.

[0027] Preferably, the control method further comprises: generating a first reset signal according to the switch control signal or the set signal, wherein the first reset signal is used to reset the ramp signal.

[0028] Preferably, when the first reset signal is generated according to the switch control signal, the ramp signal is reset at a rising edge, a falling edge, an active level of the switch control signal, or at a fixed time during the active level of the switch control signal.

[0029] Preferably, when the first reset signal is generated according to the set signal, the ramp signal is reset at a rising edge of the set signal.

[0030] Preferably, when the ramp signal reaches the second reference voltage, the set signal triggers the switch control signal to be active; when a duration of the active level of the switch control signal reaches a preset value, the switch control signal is reset to be inactive.

[0031] Preferably, the difference between the feedback signal and the first reference voltage is integrated when the feedback signal is less than the first reference voltage, and the integration is not performed when the feedback signal is greater than or equal to the first reference voltage.

[0032] Preferably, after the ramp signal is reset, the ramp signal rises when the feedback signal is less than the first reference voltage, and the ramp signal remains unchanged when the feedback signal is greater than or equal to the first reference voltage.

[0033] Preferably, the difference between the feedback signal and the first reference voltage is integrated at each time.

[0034] Preferably, after the ramp signal is reset, the ramp signal rises when the feedback signal is less than the first reference voltage, and the ramp signal falls when the feedback signal is greater than or equal to the first reference voltage.

[0035] Preferably, the control method further comprises: generating a second reset signal when the duration of the switch control signal being at the active level reaches a preset value; and generating the switch control signal according to the set signal and the second reset signal.

[0036] The switch power supply, the control circuit and the control method provided by the embodiments of the present application do not need to sample the inductance current, the circuit is simple to implement, and the difference between the output voltage and the first reference voltage is integrated to generate a ramp signal for comparison, so that the inductance current of the switch circuit is not directly used for comparison, and thus even if the inductance current fluctuates, the ramp signal for comparison will not fluctuate.

[0037] Further, since the ramp generation circuit integrates the difference between the output voltage and the first reference voltage, the integration has the effect of eliminating jitter, filtering and enhancing the anti-interference capability of the switch power supply. BRIEF DESCRIPTION OF DRAWINGS

[0038] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings.

[0039] Figure 1 Fig. 1 shows a schematic circuit diagram of a switch power supply according to a first embodiment of the present application;

[0040] Figure 2 Fig. 2 shows a schematic circuit diagram of a switch control circuit according to the first embodiment of the present application;

[0041] Figure 3 Fig. 3 shows a schematic circuit diagram of a ramp generation circuit according to a second embodiment of the present application;

[0042] Figure 4 Fig. 4 shows a schematic circuit diagram of a switch control circuit according to the second embodiment of the present application;

[0043] Figure 5 Fig. 5 shows a schematic circuit diagram of a ramp generation circuit according to an embodiment of the present application;

[0044] Figure 6 Fig. 6 shows a waveform diagram of various signals of a switch power supply according to an embodiment of the present application when a power conversion circuit works in an inductance current continuous state;

[0045] Figure 7 Fig. 7 shows a waveform diagram of various signals of a switch power supply according to an embodiment of the present application when a power conversion circuit works in an inductance current continuous state;

[0046] Figure 8 Fig. 8 shows a waveform diagram of various signals of a switch power supply according to an embodiment of the present application when a power conversion circuit works in an inductance current discontinuous state;

[0047] Figure 9 Fig. 3 shows a waveform diagram of various signals of the switching power supply according to the embodiment of the present application when the power conversion circuit operates in the discontinuous state of inductor current;

[0048] Figure 10 Fig. 4 shows a schematic circuit diagram of the switching power supply according to the third embodiment of the present application;

[0049] Figure 11 Fig. 5 shows a waveform diagram of various signals of the switching power supply according to the third embodiment of the present application;

[0050] Figure 12 Fig. 6 shows a flow chart of the control method of the switching power supply according to the embodiment of the present application. DETAILED DESCRIPTION

[0051] Various embodiments of the present application will be described in detail with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, each portion in the drawings is not drawn to scale.

[0052] The switching power supply 100 in the prior art comprises a switching circuit 110 and a control circuit 120, and an output capacitor Cout and a load 130.

[0053] The input terminal of the switching circuit 110 receives an input voltage Vin and a switching control signal PWM, and outputs an output voltage Vout at the output terminal under the control of the switching control signal PWM, and provides a current sampling signal Isense representing inductor current to the control circuit 120. The switching circuit 110 can adopt any direct current / direct current (DC / DC) or alternating current / direct current (AC / DC) conversion topology, such as synchronous or non-synchronous boost, buck converter, and forward, flyback converter, etc. The switching circuit 110 comprises a first power switch QH and a second power switch QL, an inductor L and an output capacitor Cout. The first power switch QH and the second power switch QL are connected in series between the input voltage Vin and the ground terminal to form a switching bridge arm, the inductor L and the output capacitor Cout are connected in series between the first node between the first power switch QH and the second power switch QL and the ground terminal, the second node between the inductor L and the output capacitor Cout provides the output voltage Vout, and the load is connected between the second node between the inductor L and the output capacitor Cout and the ground terminal. The output capacitor Cout is coupled between the output terminal of the switching circuit 110 and the reference ground, and the load 130 is connected in parallel with the output capacitor Cout.

[0054] The control circuit 120 receives the output voltage Vout and the current sampling signal Isense respectively, and generates the switching control signal Vg.

[0055] The control circuit 120 comprises an error amplification circuit 121, a comparison circuit 122 and a switch control circuit 123. The error amplification circuit 121 obtains a feedback signal VFB of the output voltage Vout from the positive terminal of the output capacitor Cout, i.e. the output terminal of the switch circuit 110, and compares the feedback signal VFB with a first reference voltage Vrefl to generate a compensation signal Vc. The comparison circuit 122 compares the current sampling signal Isense with the compensation signal Vc, and generates a set signal SET when the current sampling signal Isense is less than the compensation signal Vc. The set signal SET is output to the switch control circuit 123, so that the switch control circuit 123 outputs a switch control signal PWM at an active level (e.g. high level) to control the switch circuit 110 to be turned on. When the duration of the switch control signal PWM at the active level reaches a preset value, the switch control circuit 123 controls the switch control signal PWM to be at an inactive level (e.g. low level) to control the switch circuit 110 to be turned off.

[0056] In the prior art, the switch power supply 100 uses the comparison between the current sampling signal Isense and the compensation signal Vc to generate the set signal SET. However, the current sampling signal Isense needs to be sampled by a separate current sampling circuit, which increases the complexity of the switch power supply control. In addition, when the current sampling signal Isense is disturbed by noise, the switch control signal is easily triggered in advance, which causes the system to be unstable.

[0057] Figure 1 A schematic circuit diagram of a switch power supply according to a first embodiment of the present application is shown. As shown in the figure, the control circuit 220 of the switch power supply comprises a ramp generation circuit 221, a comparison circuit 223 and a switch control circuit 224. Figure 1

[0058] The ramp generation circuit 221 generates a ramp signal Vramp according to a feedback signal VFB representing the output voltage Vout and a first reference voltage Vrefl.

[0059] In this embodiment, the ramp generation circuit 221 is connected to the output terminal of the switch circuit 210, i.e. the positive terminal of the output capacitor Cout, and obtains the output voltage Vout from the positive terminal of the output capacitor Cout as the feedback signal VFB. The ramp generation circuit 221 integrates the difference between the first reference voltage Vrefl and the feedback signal VFB to generate the ramp signal Vramp.

[0060] The ramp generation circuit 221 also generates a first reset signal RESETl according to the switch control signal PWM or the set signal SET, wherein the first reset signal RESETl is used to reset the ramp signal Vramp. ​

[0061] Specifically, when the ramp generation circuit 221 generates the first reset signal RESET1 according to the switch control signal PWM, the first reset signal RESET1 is active at the rising edge, the falling edge, the active level or a certain fixed time during the active level of the switch control signal PWM, and the ramp signal Vramp is reset.

[0062] When the ramp generation circuit 221 generates the first reset signal RESET1 according to the set signal SET, the first reset signal RESET1 is active at the rising edge of the set signal SET, and the ramp signal Vramp is reset.

[0063] The ramp generation circuit 221 integrates the difference between the feedback signal VFB and the first reference voltage Vref1 when the feedback signal VFB is less than the first reference voltage Vref1, and does not integrate when the feedback signal VFB is greater than or equal to the first reference voltage Vref1. Specifically, after the ramp generation signal Vramp is reset, when the feedback signal VFB is less than the first reference voltage Vref1, the ramp signal Vramp rises, and when the feedback signal VFB is greater than or equal to the first reference voltage Vref1, the ramp signal Vramp remains unchanged.

[0064] The ramp generation circuit 221 integrates the difference between the feedback signal VFB and the first reference voltage Vref1 at each time. Specifically, after the ramp generation signal Vramp is reset, when the feedback signal VFB is less than the first reference voltage Vref1, the ramp signal Vramp rises, and when the feedback signal VFB is greater than or equal to the first reference voltage Vref1, the ramp signal Vramp falls.

[0065] The comparison circuit 223 generates the set signal SET according to the ramp signal Vramp and the second reference voltage Vref2.

[0066] Specifically, the set signal SET is generated when the ramp signal Vramp reaches the second reference voltage Vref2, and is output to the input terminal of the switch control circuit 224, so that the switch control signal PWM output by the switch control circuit 224 is active. In this embodiment, the non-inverting input terminal of the comparison circuit 223 receives the ramp signal Vramp, the inverting input terminal receives the second reference voltage Vref2, and the output terminal outputs the set signal SET.

[0067] The switch control signal PWM is effective (for example, high level) when the switch circuit 210 is turned on. When the duration of the switch control signal PWM is preset, the switch control circuit 224 resets the switch control signal PWM to an invalid level (for example, low level), controls the switch circuit 210 to be turned off.

[0068] Referring to Figure 2 The switch control circuit 224 includes a turn-on time control circuit 2241 and a flip-flop 2242. The turn-on time control circuit 2241 generates a second reset signal RESET2 when the duration of the switch control signal PWM is preset. The RS flip-flop 2242 generates the switch control signal PWM according to the set signal SET and the second reset signal RESET2.

[0069] In this embodiment, the turn-on time control circuit 2241 generates the second reset signal RESET2 when the duration of the switch control signal PWM is preset, and outputs to the reset end of the flip-flop 224, so that the switch control signal PWM output by the flip-flop 224 is invalid. The switch control signal PWM is used for turning on and off the switch circuit 210. Specifically, the switch control signal PWM is set to an effective level when the set signal SET is effective, and is reset to an invalid level when the second reset signal RESET2 is effective. The switch control signal PWM output by the flip-flop 2242 controls the switch circuit 210 to be turned on and off.

[0070] In this embodiment, when the switch control signal PWM is effective, the switch circuit is turned on; otherwise, when the switch control signal PWM is invalid, the switch circuit is turned off.

[0071] Referring to Figure 5, the slope generation circuit 221 comprises a first voltage-controlled current source Gm1, a slope reset control circuit 2211, a first capacitor C1 and a first switch S1. Wherein, the first input terminal of the first voltage-controlled current source Gm1 receives a first reference voltage Vref1, the second input terminal receives a feedback signal VFB representing the output voltage Vout, and the output terminal outputs a current compensation signal Icharge, which is in a positive proportional relationship with the difference between the first reference voltage Vref1 and the feedback signal VFB. The first capacitor C1 and the first switch S1 are connected in parallel between the output terminal of the first voltage-controlled current source Gm1 and the ground terminal. The third node between the first capacitor C1 and the first voltage-controlled current source Gm1 outputs a ramp signal Vramp. The slope reset control circuit 2211 generates a first reset signal RESET1 according to a switch control signal PWM or a set signal SET, and the control terminal of the first switch S1 receives the first reset signal RESET1, which is turned on when the first reset signal RESET1 is valid, and is turned off otherwise. The slope reset control circuit is not limited to the rising edge triggered monostable pulse generator and the falling edge triggered monostable pulse trigger.

[0072] In this embodiment, when the first reset signal RESET1 is at a valid level, the first switch S1 is closed, the voltage on the first capacitor C1 is cleared, and the ramp signal Vramp is reset.

[0073] When the first reset signal RESET1 is at an invalid level, the first voltage-controlled current source Gm1 charges or discharges the first capacitor C1. Specifically, when the feedback signal VFB is less than the first reference voltage Vref1, the first voltage-controlled current source Gm1 charges the first capacitor C1; when the feedback signal VFB is equal to the first reference voltage Vref1, the first voltage-controlled current source Gm1 neither charges nor discharges the first capacitor C1; and when the feedback signal VFB is greater than the first reference voltage Vref1, the first voltage-controlled current source Gm1 discharges the first capacitor C1. Optionally, the first voltage-controlled current source Gm1 can also have an output current limiting capability. Specifically, when the feedback signal VFB is equal to or greater than the first reference voltage Vref1, the first voltage-controlled current source Gm1 neither charges nor discharges the first capacitor C1.

[0074] Referring to Figure 6, the switch control signal PWM is active level, the first reset signal RESET1 flips to active level, the ramp signal Vramp is cleared; meanwhile the switch circuit 210 is turned on, the inductor current sampling signal Isense linearly increases; when the active level maintaining time of the switch control signal PWM reaches a preset value, i.e. at t2, the switch control circuit 224 resets the switch control signal PWM to inactive level, the first reset signal RESET1 flips to inactive level, the ramp generation circuit 221 integrates the difference between the first reference voltage Vref1 and the feedback signal VFB to generate the ramp signal Vramp, the ramp signal Vramp rises, meanwhile the switch circuit 210 is turned off, the inductor current sampling signal Isense linearly decreases. When the ramp signal Vramp reaches the second reference voltage Vref2 again, the set signal SET is generated, the switch control signal PWM is active level, and the next cycle is entered. At t4, although the output voltage Vout feedback signal VFB superimposes noise, the ramp signal Vramp basically has no fluctuation, and misjudgment does not occur, and the anti-interference ability is strong.

[0075] The control circuit of the switch power supply provided by the embodiment does not need to sample the inductor current, the circuit is simple to implement, and the difference between the feedback signal representing the output voltage and the first reference voltage is integrated to generate a ramp signal for comparison, so that the output voltage of the switch circuit is not directly used for comparison, so that even if the output voltage fluctuates, the ramp signal for comparison does not fluctuate, and the anti-interference ability of the switch power supply is enhanced.

[0076] In a preferred embodiment, at the moment when the switch control signal PWM changes from inactive level to active level or from active level to inactive level, the first reset signal RESET1 is active, and the first switch S1 is closed to clear the voltage on the first capacitor C1.

[0077] Referring to Figure 7 , the switch control signal PWM is active level, the first reset signal RESET1 flips to active level, the ramp signal Vramp is cleared; meanwhile the switch circuit 210 is turned on, the inductor current sampling signal Isense linearly increases; when the active level maintaining time of the switch control signal PWM reaches a preset value, i.e. at t2, the switch control circuit 224 resets the switch control signal PWM to inactive level, the first reset signal RESET1 flips to inactive level, the ramp generation circuit 221 integrates the difference between the first reference voltage Vref1 and the feedback signal VFB to generate the ramp signal Vramp, the ramp signal Vramp rises, meanwhile the switch circuit 210 is turned off, the inductor current sampling signal Isense linearly decreases. When the ramp signal Vramp reaches the second reference voltage Vref2 again, the set signal SET is generated, the switch control signal PWM is active level, and the next cycle is entered. At t4, although the output voltage Vout feedback signal VFB superimposes noise, the ramp signal Vramp basically has no fluctuation, and misjudgment does not occur, and the anti-interference ability is strong.

[0078] Referring toFigure 8 The switch power supply works in discontinuous current mode (DCM). When the ramp signal Vramp reaches the second reference voltage Vref2, the switch control signal PWM is at an active level, the first reset signal RESET1 is active at the time when the switch control signal PWM changes from an inactive level to an active level or from an active level to an inactive level, and the ramp signal Vramp is reset to zero. When the active level maintaining time of the switch control signal PWM reaches a preset value, the switch control signal PWM is reset to an inactive level.

[0079] During the inactive level of the switch control signal PWM, the inductor current sampling signal Isense linearly decreases and reaches 0A at t6 and maintains at 0A. Between t4 and t5, the feedback signal VFB is greater than the first reference voltage Vref1, and the ramp signal Vramp remains unchanged. Between t5 and t3, when the feedback signal VFB is less than the first reference voltage Vref1, the difference between the first reference voltage Vref1 and the output voltage Vout is integrated from t5, and the ramp signal Vramp rises.

[0080] Referring to Figure 9 The ramp generation circuit 211 generates the first reset signal RESET1 according to a set signal. When the ramp signal Vramp reaches the second reference voltage Vref2, the set signal SET changes from an inactive level to an active level, the first reset signal RESET1 is active, and the ramp signal Vramp is reset to zero. Meanwhile, the difference between the first reference voltage Vref1 and the output voltage Vout is integrated from the time when the set signal SET changes from an active level to an inactive level, and the ramp signal Vramp rises. Between t1 and t4 and between t5 and t3, when the feedback signal VFB is less than the first reference voltage Vref1, the ramp signal Vramp rises. Between t4 and t5, when the feedback signal VFB is greater than or equal to the first reference voltage Vref1, the ramp signal Vramp decreases.

[0081] The control circuit of the switch power supply provided by the embodiment of the application does not need to sample the inductor current, the circuit is simple to implement, and the difference between the feedback signal representing the output voltage and the first reference voltage is integrated to generate a ramp signal for comparison, thereby avoiding directly using the output voltage of the switch circuit to participate in comparison, and thus the anti-interference capability of the switch power supply is enhanced.

[0082] Figure 3 A schematic circuit diagram of a switch power supply according to a second embodiment of the application is shown; Figure 4A schematic circuit diagram of a switch control circuit according to a second embodiment of the present invention is shown. Compared with the first embodiment, the control circuit 220 of this embodiment further includes an error amplifier circuit 222, which generates a first reference voltage Vref1 based on the output voltage Vout and the third reference voltage Vref3.

[0083] In this embodiment, the non-inverting input of the error amplifier circuit 222 receives the third reference voltage Vref3, the inverting input receives the feedback signal VFB representing the output voltage Vout, and the output outputs the first reference voltage Vref1. Compared with the first embodiment, the error amplifier circuit 222 in this embodiment is used to eliminate the error between the feedback signal FB and the third reference voltage Vref3. The rest is the same as the first embodiment and will not be described again here.

[0084] The control circuit of the switching power supply provided in this embodiment of the invention does not require sampling the inductor current, the circuit implementation is simple, and the difference between the feedback signal representing the output voltage and the first reference voltage is integrated to generate a ramp signal for comparison, avoiding the direct use of the output voltage of the switching circuit for comparison, thereby enhancing the anti-interference capability of the switching power supply.

[0085] Figure 10 A schematic circuit diagram of a switching power supply according to a third embodiment of the present invention is shown. Figure 10 As shown, the switching power supply includes a switching circuit 310, a control circuit 320, an output capacitor Cout, and a load 330.

[0086] The switching circuit 310 includes multiple switching units (311, 312, ..., 31n). The input terminals of these n switching circuits respectively receive the input voltage Vin, and their output terminals are coupled together to provide the output voltage Vout.

[0087] Compared with the first embodiment, the control circuit 320 of this embodiment further includes a frequency divider circuit 325, which receives the set signal SET and generates n frequency divider set signals, namely the first frequency divider set signal SET1, the second frequency divider set signal SET2, ..., the nth frequency divider set signal SETn, which are respectively connected to n switch control circuits 324.

[0088] Each switch control circuit 324 generates a corresponding switch control signal PWM based on the corresponding frequency division set signal. For example, the first switch control circuit generates a first switch control signal PWM1 based on the first frequency division set signal SET1, and the first switch control signal PWM1 is used to control the on and off of the first switch unit 311. Generally, the n switch units operate in staggered phases, and the n frequency division set signals are effective sequentially. In this embodiment, the rest is the same as in the first embodiment, and will not be repeated here.

[0089] Each switch unit comprises a drive circuit, a first power switch QH and a second power switch QL, and a corresponding inductor L, wherein the first power switch QH and the second power switch QL are connected in series between an input voltage Vin and a ground terminal, and the inductor L is connected between a first node between the first power switch QH and the second power switch QL and an output voltage Vout.

[0090] The drive circuit is configured to generate a first drive signal DH and a second drive signal DL according to the corresponding switch control circuit, the first drive signal DH and the second drive signal DL being completely opposite signals. The first drive signal DH controls the conduction and the turn-off of the first power switch QH, and the second drive signal DL controls the conduction and the turn-off of the second power switch QL; the first power switch QH is turned on while the second power switch QL is turned off, and the first power switch QH is turned off while the second power switch QL is turned on.

[0091] In the embodiment, when the switch control signal VG is at an effective level, the first drive signal D1 is at an effective level, and the second drive signal D2 is at an ineffective level, the first power switch QH is turned on, and the second power switch QL is turned off; conversely, when the switch control signal VG is at an ineffective level, the first drive signal D1 is at an ineffective level, and the second drive signal D2 is at an effective level, the first power switch QH is turned off, and the second power switch QL is turned on.

[0092] The embodiment takes the switch circuit comprising only the switch circuit 311 and the switch circuit 312 as an example for illustration, but is not limited thereto.

[0093] Referring to Figure 11 , the switch circuit 310 operates in a continuous current mode. At t1, when the ramp signal Vramp reaches a second reference voltage Vref2, a set signal SET is generated, the first switch control signal PWM1 becomes at an effective level, the switch circuit 311 is turned on, and the corresponding inductor current sampling signal Isense1 linearly increases; at the same time, at the moment when the first switch control signal PWM1 changes from an ineffective level to an effective level, the ramp signal Vramp is cleared, the ramp generation circuit 321 starts to perform integral operation on the difference between the first reference voltage Vref1 and the output voltage Vout again, and the ramp signal Vramp rises.

[0094] At t2, the effective level maintaining time of the first switch control signal PWM1 reaches a preset value, the first switch control signal PWM1 is reset to an ineffective level, the switch circuit 311 is turned off, and the corresponding inductor current sampling signal Isense1 linearly decreases.

[0095] At the moment t3, when the ramp signal Vramp reaches the second reference voltage Vref2 again, a set signal SET is generated, the second switch control signal PWM2 becomes effective, the switch circuit 312 is turned on, and the corresponding inductor current sampling signal Isense2 linearly increases; meanwhile, at the moment when the second switch control signal PWM2 changes from the ineffective level to the effective level, the ramp signal Vramp is cleared, the ramp generation circuit 321 starts to perform the integral operation on the difference between the first reference voltage Vref1 and the output voltage Vout again, and the ramp signal Vramp rises.

[0096] At the moment t4, the effective level maintaining time of the second switch control signal PWM2 reaches a preset value, the second switch control signal PWM2 is reset to the ineffective level, the switch circuit 312 is turned off, and the corresponding inductor current sampling signal Isense2 linearly decreases.

[0097] At the moment t5, when the ramp signal Vramp reaches the second reference voltage Vref2, a set signal SET is generated, the first switch control signal PWM1 becomes effective, and the above control process is repeated thereafter.

[0098] At this time, the period of the first switch control signal PWM1 and the period of the second switch control signal PWM2 are 2 times of the period of the set signal SET, and the phase difference between the first switch control signal PWM1 and the second switch control signal PWM2 is 180°.

[0099] If the switch circuit 310 includes n switch units, the period of the first switch control signal PWM1 to the nth switch control signal PWMn is n times of the period of the set signal SET, and the phase difference between adjacent switch control signals is 360° / n.

[0100] The remaining contents are the same as those of the above embodiment, and will not be described here again.

[0101] The control circuit of the switching power supply provided by the embodiment of the present application does not need to sample the inductor current, the circuit is simple to realize, and the difference between the feedback signal representing the output voltage and the first reference voltage is integrated to generate a ramp signal used for comparison, so that the output voltage of the switch circuit is avoided to be directly used for comparison, thereby enhancing the anti-interference capability of the switching power supply.

[0102] Figure 12 A flow chart of a control method of a switching power supply according to an embodiment of the present application is shown. Referring to Figure 12 , the control method of the switching power supply comprises the following steps.

[0103] In step S101, a ramp signal is generated according to a feedback signal representing an output voltage and a first reference voltage.

[0104] In the embodiment, the difference between the first reference voltage Vref1 and the feedback signal VFB is integrated to generate the ramp signal Vramp. The first reset signal RESET1 is active at the rising edge, the falling edge, the active level or a fixed time during the active level of the switch control signal PWM, and the ramp signal Vramp is reset. Alternatively, the first reset signal RESET1 is active at the rising edge of the set signal SET, and the ramp signal Vramp is reset.

[0105] In step S102, a set signal is generated according to the ramp signal and the second reference voltage, and the switch control signal is triggered to be active according to the set signal, and the switch circuit is turned on. The switch control signal is used to control the turn-on and turn-off of the switch circuit.

[0106] In step S103, when the duration of the active level of the switch control signal reaches a preset value, the switch control signal is inactive, and the switch circuit is turned off.

[0107] In the embodiment, the set signal SET is generated when the ramp signal Vramp reaches the second reference voltage Vref2, the switch control signal PWM is controlled to be active, the switch circuit is turned on, and the inductor current linearly increases. When the duration of the active level of the switch control signal PWM reaches a preset value, the switch control signal PWM is inactive, the switch circuit is turned off, and the inductor current linearly decreases.

[0108] In a preferred embodiment, the control method further comprises the following steps.

[0109] In step S101, the first reference voltage Vref1 is generated according to the feedback signal VFB and the third reference voltage Vref3.

[0110] The control method of the switching power supply provided by the embodiment avoids directly using the output voltage of the switching circuit for comparison, thereby enhancing the anti-interference capability of the switching power supply.

[0111] The embodiments of the present application have been described above with the preferred embodiments, and the embodiments do not exhaustively describe all the details, nor limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. The embodiments are selected and specifically described in the specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The protection scope of the present application should be subject to the scope defined by the claims of the present application.

Claims

1. A control circuit for a switching power supply, characterized in that, include: The ramp generation circuit generates a ramp signal based on the feedback signal characterizing the output voltage and the first reference voltage; The comparator circuit generates a set signal based on the ramp signal and the second reference voltage; A switch control circuit outputs a switch control signal and triggers the switch control signal to be active based on the set signal. The ramp generating circuit generates the ramp signal by integrating the difference between the feedback signal and the first reference voltage. The control circuit does not require sampling the inductor current. The ramp generating circuit includes a first voltage-controlled current source, a ramp reset control circuit, a first capacitor, and a first switch. The first input terminal of the first voltage-controlled current source receives the first reference voltage, the second input terminal receives the feedback signal, and the output terminal outputs a current compensation signal. The ramp reset control circuit receives the switch control signal or the set signal and outputs a first reset signal. The first capacitor and the first switch are connected in parallel between the output terminal of the first voltage-controlled current source and the ground terminal. The node between the first capacitor and the first voltage-controlled current source outputs a ramp signal; The control terminal of the first switch receives the first reset signal and turns the switch on or off according to the first reset signal.

2. The control circuit according to claim 1, characterized in that, Also includes: The error amplifier circuit generates a first reference voltage based on the feedback signal and the third reference voltage.

3. The control circuit according to claim 1 or 2, characterized in that, The ramp generation circuit also generates a first reset signal based on the switch control signal or the set signal, wherein the first reset signal is used to reset the ramp signal.

4. The control circuit according to claim 3, characterized in that, When the ramp generation circuit generates a first reset signal according to the switch control signal, the ramp signal is reset at a fixed moment during the rising edge, falling edge, active level, or active level of the switch control signal.

5. The control circuit according to claim 4, characterized in that, When the ramp generation circuit generates a first reset signal according to the set signal, the ramp signal is reset on the rising edge of the set signal.

6. The control circuit according to claim 1 or 2, characterized in that, When the ramp signal reaches the second reference voltage, the comparator circuit generates the set signal, triggering the switch control signal to be at an active level; when the active level of the switch control signal is maintained for a preset time, the switch control signal is reset to an inactive level.

7. The control circuit according to claim 6, characterized in that, The ramp generating circuit integrates the difference between the feedback signal and the first reference voltage when the feedback signal is less than the first reference voltage, and does not integrate when the feedback signal is greater than or equal to the first reference voltage.

8. The control circuit according to claim 7, characterized in that, After the ramp signal is reset, when the feedback signal is less than the first reference voltage, the ramp signal rises; when the feedback signal is greater than or equal to the first reference voltage, the ramp signal remains unchanged.

9. The control circuit according to claim 6, characterized in that, The ramp generation circuit integrates the difference between the feedback signal and the first reference voltage at each moment.

10. The control circuit according to claim 9, characterized in that, After the ramp signal is reset, the ramp signal rises when the feedback signal is less than the first reference voltage, and falls when the feedback signal is greater than or equal to the first reference voltage.

11. The control circuit according to claim 7 or 9, characterized in that, When the feedback signal is less than the first reference voltage, the first voltage-controlled current source charges the first capacitor, and the ramp generation circuit integrates the difference between the feedback signal and the first reference voltage; when the feedback signal is greater than or equal to the first reference voltage, the first capacitor neither charges nor discharges to the first voltage-controlled current source, and the ramp generation circuit does not integrate the difference between the feedback signal and the first reference voltage.

12. The control circuit according to claim 7 or 9, characterized in that, When the feedback signal is less than the first reference voltage, the first voltage-controlled current source charges the first capacitor; when the feedback signal is greater than or equal to the first reference voltage, the first capacitor discharges to the first voltage-controlled current source; the ramp generation circuit integrates the difference between the feedback signal and the first reference voltage at each moment.

13. The control circuit according to claim 1, characterized in that, The switch control circuit includes: The conduction time control circuit generates a second reset signal when the duration of the switch control signal being at an effective level reaches a preset value; An RS flip-flop generates the switch control signal based on the set signal and the second reset signal.

14. A switching power supply, characterized in that, include: Multiple switching circuits are used to convert the input voltage into the output voltage; The control circuit as described in any one of claims 1-13 above; Each of the aforementioned switching circuits includes a driving circuit, a switching bridge arm, and an inductor. The switching bridge arm includes a first power switch and a second power switch, wherein the first power switch and the second power switch are connected in series between the input voltage and the ground terminal; The inductor is connected between the node between the first power switch and the second power switch and the output voltage.

15. The switching power supply according to claim 14, characterized in that, The control circuit also includes: The frequency divider circuit generates multiple frequency divider set signals based on the set signal; Multiple switch control circuits generate multiple switch control signals according to the corresponding frequency division set signal.

16. The switching power supply according to claim 15, characterized in that, The driving circuit generates a driving signal according to the corresponding switch control signal. The driving signal includes a first driving signal and a second driving signal that are completely opposite to each other. The first driving signal of each switching circuit is used to control the first power switch of the corresponding switching circuit to turn on and off, and the second driving signal of each switching circuit is used to control the second power switch of the corresponding switching circuit to turn on and off.

17. The switching power supply according to claim 16, characterized in that, When the switch control signal is at an active level, the first power switch of the corresponding switch circuit is turned on and the second power switch is turned off; when the switch control signal is at an inactive level, the first power switch of the corresponding switch circuit is turned off and the second power switch is turned on.

18. The switching power supply according to claim 15, characterized in that, The frequency divider circuit has a frequency division number of N, the period of the frequency divider set signal is N times the period of the set signal, and the phase difference between adjacent frequency divider set signals is 360° / N, where N is an integer greater than or equal to 1.

19. A control method for a switching power supply according to any one of claims 14-18, characterized in that, include: A ramp signal is generated based on the feedback signal characterizing the output voltage and the first reference voltage; A set signal is generated based on the ramp signal and the second reference voltage; The set signal triggers the switch control signal to become valid; The ramp signal is generated by integrating the difference between the feedback signal and the first reference voltage.

20. The control method according to claim 19, characterized in that, Also includes: A first reference voltage is generated based on the feedback signal and the third reference voltage.

21. The control method according to claim 19, characterized in that, Also includes: A first reset signal is generated based on the switch control signal or the set signal, wherein the first reset signal is used to reset the ramp signal.

22. The control method according to claim 21, characterized in that, When a first reset signal is generated according to the switch control signal, the ramp signal is reset at a fixed moment during the rising edge, falling edge, active level, or active level of the switch control signal.

23. The control method according to claim 21, characterized in that, When a first reset signal is generated based on the set signal, the ramp signal is reset at the rising edge of the set signal.

24. The control method according to claim 19, characterized in that, When the ramp signal reaches the second reference voltage, the set signal triggers the switch control signal to an active level; when the active level of the switch control signal is maintained for a preset time, the switch control signal is reset to an inactive level.

25. The control method according to claim 24, characterized in that, When the feedback signal is less than the first reference voltage, the difference between the feedback signal and the first reference voltage is integrated; when the feedback signal is greater than or equal to the first reference voltage, no integration is performed.

26. The control method according to claim 24, characterized in that, After the ramp signal is reset, when the feedback signal is less than the first reference voltage, the ramp signal rises; when the feedback signal is greater than or equal to the first reference voltage, the ramp signal remains unchanged.

27. The control method according to claim 24, characterized in that, Integrate the difference between the feedback signal and the first reference voltage at each moment.

28. The control method according to claim 27, characterized in that, After the ramp signal is reset, the ramp signal rises when the feedback signal is less than the first reference voltage, and falls when the feedback signal is greater than or equal to the first reference voltage.

29. The control method according to claim 27, characterized in that, Also includes: A second reset signal is generated when the duration of the switch control signal being at an active level reaches a preset value; The switch control signal is generated based on the set signal and the second reset signal.

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