Fractional-n phase-locked loop with noise cancellation

Abstract

Embodiments of the present disclosure relate to fractional N phase-locked loop (PLL) with noise cancellation. A PLL circuit includes a fractional N divider that generates a feedback signal, a first phase frequency detector that compares the feedback signal to a reference signal to generate first up / down control signals that control a charge pump to generate a charge pump output current. A noise cancellation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up / down control signals that differ in pulse width by an integer number of PLL cycles. A current digital-to-analog converter circuit is controlled in response to the second up / down control signals to apply a noise cancellation source current and a sink current to the charge pump output current.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 120,852, filed December 3, 2020, the disclosure of which is incorporated by reference. TECHNICAL FIELD

[0003] The present invention relates generally to a fractional-N phase-locked loop (PLL) circuit, and more particularly to noise cancellation in the operation of a fractional-N PLL circuit. BACKGROUND

[0004] Referring to Figure 1 , a block diagram of a fractional-N phase-locked loop (PLL) circuit 10 is shown. A phase frequency detector (PFD) circuit 12 has a first input for receiving a reference clock signal CLKref(t) and a second input for receiving a feedback clock signal CLKfb(t). The PFD circuit 12 measures the difference between like edges (i.e., rising or falling edges) of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t). In the event that the PFD circuit 12 detects that like edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t) are aligned, a pulse-generating up signal U(t) and a pulse-generating down signal D(t) are generated (both pulses are synchronous and have the same duration). If the PFD circuit 12 detects that an edge of the reference clock signal CLKref(t) leads a like edge of the feedback clock signal CLKfb(t), the pulse-generating up signal U(t) is generated for a first duration, and the pulse-generating down signal D(t) is generated for a second duration (less than the first duration), where the length of the first duration depends on the phase error between the like edges. Conversely, if an edge of the feedback clock signal CLKfb(t) leads a like edge of the reference clock signal CLKref(t), the PFD circuit 12 pulse-generates the down signal D(t) for a third duration, and the pulse-generating up signal U(t) is generated for a fourth duration (less than the third duration), where the length of the third duration depends on the phase error between the like edges.

[0005] Figure 2An embodiment block diagram of the PFD circuit 12 is shown. The PFD circuit 12 also includes a first D-type flip-flop (FF) circuit 14 having a data input (D) for receiving a logic high voltage (Vdd) and a clock input (CLK) for receiving the reference clock signal CLKref(t). An output (Q) of the FF circuit 14 generates the up signal U(t). The PFD circuit 12 also includes a second D-type flip-flop (FF) circuit 16 having a data input (D) for receiving the logic high voltage (Vdd) and a clock input (CLK) for receiving the feedback clock signal CLKfb(t). An output (Q) of the FF circuit 16 generates the down signal D(t). A logic AND gate 18 has a first input for receiving the up signal U(t) and a second input for receiving the down signal D(t). The gate 18 performs a logical AND on these signals to generate a reset signal that is applied to a reset input of the first FF circuit 14 and the second FF circuit 16.

[0006] Figure 2 Waveforms for the up signal U(t) and the down signal D(t) are further shown for the following operating conditions: a) aligning similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t); b) an edge of the reference clock signal CLKref(t) leading a similar edge of the feedback clock signal CLKfb(t); and c) an edge of the feedback clock signal CLKfb(t) leading a similar edge of the reference clock signal CLKref(t). In conditions a), b) and c), the smaller pulse width of the up signal U(t) and the down signal D(t) is controlled by the operating delay (td) of the AND gate 18 to reset the first FF circuit 14 and the second FF circuit 16. This is the minimum pulse width of the up signal U(t) and the down signal D(t). In conditions b) and c), the longer pulse width of the up signal U(t) and the down signal D(t), respectively, is controlled as a function of the minimum pulse width (td) plus the sum of the time difference between the similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t) (i.e., the phase difference - pd).

[0007] Referring again to Figure 1 , the charge pump (CP) circuit 20 generates an output current Icp(t) in response to the pulse duration (i.e., width) of the up signal U(t) and the down signal D(t). The CP circuit 20 includes a current source (path) circuit (not explicitly shown, see Figure 4 ) for operating in response to the up signal U(t) to provide a source current contribution to the charge pump output current Icp(t). The CP circuit 20 also includes a current sink (path) circuit (not explicitly shown, see Figure 4), for operating in response to the down signal D(t) to provide an absorption current contribution to the output current Icp(t) of the charge pump. The output current Icp(t) is the difference between the source current contribution and the absorption current contribution. When the up signal and the down signal have the same pulse, as in case a) described above, the output current Icp(t) is zero because the source current contribution and the absorption current contribution caused by the pulses of the up signal U(t) and the down signal D(t) cancel out. In case the up signal U(t) pulse duration is longer than the down signal D(t) pulse duration, as in case b) described above, the output current Icp(t) comprises a transient source current with a duration that is the difference in pulse width of the up signal U(t) and the down signal D(t). Conversely, in case the down signal D(t) pulse duration is longer than the up signal U(t) pulse duration, as in case c) described above, the output current Icp(t) comprises a transient absorption current with a duration that is the difference in pulse width of the up signal U(t) and the down signal D(t).

[0008] A loop filter (LF) circuit 22 filters the output current Icp(t) from the charge pump circuit 20 to generate a control voltage Vctrl(t). In one embodiment, the LF circuit 22 is implemented as an analog integration circuit, and thus, the control voltage Vctrl(t) is generated by integrating the source current and the absorption current. Therefore, the control voltage Vctrl(t) will incrementally rise in response to each transient increase in the output current Icp(t) and incrementally fall in response to each transient decrease in the output current Icp(t).

[0009] A voltage controlled oscillator (VCO) circuit 30 generates an oscillating output signal Vout(t) whose frequency is controlled by the level of the control voltage Vctrl(t). An increase in the level of the control voltage Vctrl(t) caused by a transient increase in the output current Icp(t) results in a corresponding increase in the frequency of the oscillating output signal Vout(t). Conversely, a decrease in the level of the control voltage Vctrl(t) caused by a transient decrease in the output current Icp(t) results in a corresponding decrease in the frequency of the oscillating output signal Vout(t).

[0010] The programmable frequency divider circuit 34 divides the oscillating output signal Vout(t) to generate a feedback clock signal CLKfb(t). The programmable frequency divider circuit 34 implements a fractional division ratio between the frequency of the oscillating output signal Vout(t) and the frequency of the feedback clock signal CLKfb(t). The fractional division ratio equals N + y[n], where y[n] is an integer represented by one or more bits. The programmable frequency divider circuit 34 operates to divide the oscillating output signal Vout(t) by N + y[n] at each time period. For example, where y[n] is a single bit, the programmable frequency divider circuit 34 operates to divide the oscillating output signal Vout(t) by N + 1 for each logical 1 integer value of the single bit, and divide the oscillating output signal Vout(t) by N for each logical 0 integer value of the single bit.

[0011] The y[n] integer value of the digital signal 38 can be generated, for example, by a fractional delta-sigma modulator (DSM) circuit 44. The fractional delta-sigma modulator (DSM) circuit 44 receives the feedback clock signal CLKfb(t) and a control signal a, which specifies a fractional value between 0 and 1. In response to the inputs, the DSM circuit 44 generates the integer y[n] and controls the length of each time period in the sequence. The programmable frequency divider circuit 34 responds to the integer by performing N + y[n] division at each time period. In this case, avg(y[n]) = a, where "avg" is the average function. As a result, the frequency f PLL The average equals (N + a) * f CLK where f CLK is the frequency of the reference clock signal CLKref(t).

[0012] A problem associated with the PLL circuit 10 of Equation Figure 1 is that quantization noise from the DSM circuit 44 is injected into the programmable frequency divider circuit 34 and passes through the PFD circuit 12 and CP circuit 20 before being integrated by the LF circuit 22. A conventional solution to this noise problem is to reduce the bandwidth (BW) of the PLL circuit 10, thereby filtering out the noise. This is an acceptable tradeoff for the PLL circuit designer in certain circuit applications. However, in cases where a high bandwidth PLL circuit is required, noise cancellation techniques must be used instead.

[0013] Accordingly, there is a need in the art for improved noise cancellation techniques. SUMMARY

[0014] A phase-locked loop (PLL) circuit includes a fractional-N divider that generates a feedback clock signal. A noise cancellation circuit for a PLL circuit includes a synchronization circuit that receives a voltage-controlled clock signal and the feedback clock signal of the PLL circuit and is configured to generate a first synchronized feedback clock signal and a second synchronized feedback clock signal, where the second synchronized feedback clock signal is delayed by an integer number of cycles of the voltage-controlled clock signal; a first phase-frequency detector circuit that receives the first synchronized feedback clock signal and the second synchronized feedback clock signal and is configured to generate a first up control signal and a first down control signal, where a pulse width of the first up control signal differs from a pulse width of the first down control signal by the integer number of cycles; a logic circuit configured to generate an up digital control signal and a down digital control signal in response to the first up control signal, the first down control signal, and a digital code signal indicative of a noise cancellation correction magnitude; and a current digital-to-analog converter circuit that receives the up digital control signal and the down digital control signal and includes a current source circuit that operates in response to the up digital control signal to provide a noise cancellation source current to the PLL circuit and a current sink circuit that operates in response to the down digital control signal to provide a noise cancellation sink current to the PLL circuit.

[0015] A phase-locked loop (PLL) circuit includes a fractional-N divider that generates a feedback clock signal; a first phase-frequency detector configured to compare the feedback clock signal to a reference clock signal and generate a first up control signal and a first down control signal; and a charge pump circuit controlled by the first up control signal and the first down control signal to generate a charge pump output current. A noise cancellation circuit for a PLL circuit includes a synchronization circuit that receives a voltage-controlled clock signal and the feedback clock signal of the PLL circuit and is configured to generate a first synchronized feedback clock signal and a second synchronized feedback clock signal, where the second synchronized feedback clock signal is delayed by an integer number of cycles of the voltage-controlled clock signal; a second phase-frequency detector circuit that receives the first synchronized feedback clock signal and the second synchronized feedback clock signal and is configured to generate a second up control signal and a second down control signal, where a pulse width of the second up control signal differs from a pulse width of the second down control signal by the integer number of cycles; and a current digital-to-analog converter circuit controlled in response to the second up control signal to apply a noise cancellation source current to the charge pump output current and in response to the second down control signal to apply a noise cancellation sink current to the charge pump output current.

[0016] In one embodiment, a method for a noise cancellation circuit for a phase-locked loop (PLL) circuit is presented, the PLL circuit including a fractional-N divider for receiving a voltage-controlled clock signal of the PLL circuit and generating a feedback clock signal of the PLL circuit. The method includes generating a first synchronized feedback clock signal and a second synchronized feedback clock signal from the voltage-controlled clock signal and the feedback clock signal of the PLL circuit, the second synchronized feedback clock signal being delayed from the first synchronized feedback clock signal by an integer number of cycles of the voltage-controlled clock signal; processing the first synchronized feedback clock signal and the second synchronized feedback clock signal to generate a first up control signal and a first down control signal, wherein a pulse width of the first up control signal differs from a pulse width of the first down control signal by the integer number of cycles; generating a digital code signal indicative of a noise cancellation correction magnitude; applying a noise cancellation source current to the PLL circuit, wherein a magnitude of the noise cancellation source current is dependent on the digital code signal and an up digital control signal derived from the first up control signal and the first down control signal; and applying a noise cancellation sink current to the PLL circuit, wherein a magnitude of the noise cancellation sink current is dependent on the digital code signal and a down digital control signal derived from the first up control signal and the first down control signal.

[0017] In one embodiment, the method includes synchronizing the feedback clock signal with the voltage-controlled clock signal to generate a first synchronized feedback clock signal and a second synchronized feedback clock signal, the second synchronized feedback clock signal being delayed from the first synchronized feedback clock signal by an integer number of cycles of the voltage-controlled clock signal; phase comparing the first synchronized feedback clock signal and the second synchronized feedback clock signal to generate an up control signal and a down control signal, wherein a pulse width of the up control signal differs from a pulse width of the down control signal by the integer number of cycles; and in response to the up control signal, applying a noise cancellation source current to the PLL circuit; and in response to the down control signal, applying a noise cancellation sink current to the PLL circuit. BRIEF DESCRIPTION OF DRAWINGS

[0018] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings in which:

[0019] Figure 1 is a block diagram of a fractional-N divide phase-locked loop (PLL) circuit;

[0020] Figure 2 is a block diagram of a PFD circuit for the PLL circuit of Figure 1

[0021] Figure 3 is a block diagram of a fractional-N divide PLL circuit implementing a quantized noise cancellation technique;

[0022] Figure 4 is a block diagram of a fractional-N divide PLL circuit implementing another quantized noise cancellation technique; ​

[0023] Figure 5 is a block diagram of a SYNC circuit for the PLL circuit of Figure 4

[0024] Figure 6 is a block diagram of a replica PFD circuit for the PLL circuit of Figure 4

[0025] Figure 7 is a block diagram of a logic circuit;

[0026] Figures 8A-8B , 9A to 9D and 10A to 10D are timing diagrams illustrating the operation of the logic circuit of Figure 7

[0027] Figures 11A-11C is an operation timing diagram of a charge pump and current digital-to-analog (D / C) converter circuit for the PLL circuit of Figure 4 DETAILED DESCRIPTION

[0028] Figure 3 A block diagram of a fractional-N phase-locked loop (PLL) circuit 50 implementing a quantization noise cancellation technique is shown. Figure 1 and Figure 3 Like reference numerals in FIGS. 1 through 8 and 9A to 10D indicate like parts, circuits, portions, signals, etc., and repeated discussion is omitted herein for the sake of brevity. See the above discussion. The PLL circuit 50 differs from the PLL circuit 10 in that a quantization noise cancellation circuit 54 is added. The quantization noise cancellation circuit 54 includes a digital-to-analog (D / A) converter circuit having an input for receiving the digital code signal Dig[n] output by the DSM circuit 44. This digital code signal Dig[n] is converted by the D / A converter circuit to generate an analog noise cancellation current Ican(t) that is applied to the output current Icp(t) from the charge pump circuit 20. In effect, this noise cancellation current Ican(t) corresponds to the SDM quantization noise and is subtracted from the output current Icp(t). Thus, the noise cancellation current Ican(t) is a variable current that is applied as a source current or sink current for a fixed duration in either case, and the noise cancellation current Ican(t) is the charge equivalent that will cancel the quantization noise present in the output current Icp(t). In this embodiment, it should be recognized that the accuracy of the noise cancellation is highly dependent on the implementation of the D / A circuit.

[0029] Due to the quantization noise generated by the DSM circuit 44, the charge noise in the output current Icp(t) generated by the charge pump circuit 20 is given by:

[0030] ​​​​

[0031] where: Icpis the charge pump current; Tvcois the period of the oscillating output signal Vout(t). Q[n] depends on the period of the oscillating output signal Vout(t) (or some function thereof) because the frequency divider 34 will add or subtract a number of clock cycles from its output (i.e. the feedback clock signal CLKfb(t)) based on the value of y[n].

[0032] To cancel this noise, the D / A converter circuit generates a noise cancellation current Ican(t). The idea here is to cancel the noise in the shortest possible time period. Since the smallest and most accurate time available in a PLL system corresponds to Tvco, this period is used to generate the ON time of the noise cancellation. Direct use of Tvco can not be feasible considering the time lag, so instead an integer multiple of Tvco is used for the noise cancellation current Ican(t). As a result, the DC and transient switching behavior of the D / A converter circuit must be closely matched to that of the CP circuit 20. This is difficult because there are multiple sources of mismatch that cause differences in transient behavior: SDM quantization noise passes through the PFD circuit and the CP circuit, while cancellation charge only passes through the D / A converter circuit; the current source and current sink paths of the CP circuit are turned ON for different widths in response to the phase error, and the turning ON of both the current source path and the current sink path effectively cancels the charge injection for VCO control due to switching; and the noise cancellation current Ican(t) from the D / A converter circuit is typically applied to only one of the source current path and the sink current path. Due to these mismatches, the overall effect of noise cancellation is limited, and can cause an increase in PLL clock jitter.

[0033] To reduce the impact of switching in the D / A converter circuit, the ON time of the applied cancellation current Ican(t) can be increased. It is helpful to implement path matching by logic circuitry to ensure that the D / A converter circuit is turned ON for exactly the fixed duration when the cancellation current Ican(t) that cancels quantization noise is applied. Since this cancellation technique involves cancellation of charge, to maintain the same resolution in the D / A converter circuit, the current associated with the least significant bit (LSB) needs to be reduced in case of increased current ON time. This acts as a constraint on the design of the D / A converter circuit for low current support. Furthermore, to address and reduce jitter, the duration of the cancellation current Ican(t) that is injected to provide noise cancellation should be the same as the duration of the partial (quantization) noise injected into the LF circuit by the CP circuit 20. However, increasing the current ON time will increase the amount of injection time, in turn increasing jitter. Delay matching in the quantization noise cancellation circuit 54 is also a challenge as it is not robust over process, voltage, and temperature (PVT) variations.

[0034] Reference is now made to Figure 4 , showing a block diagram of a fractional N phase-locked loop (PLL) circuit 110 implementing another quantization noise cancellation technique. The PLL circuit 110 differs from the PLL circuits 10 and 50 in that a quantization noise cancellation circuit 112 is used. Figure 1 、 Figure 3 and Figure 4 like reference numerals refer to like or similar components, circuits, parts, signals, etc., and repeated discussion is omitted for brevity. See the above discussion.

[0035] The quantization noise cancellation circuit 112 includes a synchronization (SYNC) circuit 120 having a first input for receiving the feedback clock signal CLKfb(t) and a second input for receiving the oscillation output signal Vout(t) or a derivative thereof from the VCO circuit 30. The SYNC circuit 120 generates a synchronized feedback signal (CLKfb_sync) 122 that is identical to the feedback clock signal CLKfb(t) with edges synchronized to similar edges of the oscillation output signal Vout(t). The SYNC circuit 120 also generates a delayed synchronized feedback signal (CLKfb_sync_dly) 124 that is identical to the synchronized feedback signal CLKfb_sync delayed by a desired number of clock cycles of the oscillation output signal Vout(t). In the particular example shown, the delay is by one clock cycle.

[0036] Figure 5 An embodiment block diagram of the SYNC circuit 120 is shown. The SYNC circuit 120 includes a first D-type flip-flop (FF) circuit 126 having a data (D) input for receiving the feedback clock signal CLKfb(t) and a clock (CLK) input for receiving the oscillation output signal Vout(t). The output (Q) of the FF circuit 126 generates the synchronized feedback signal CLKfb_sync that is applied to the data (D) input of a second D-type flip-flop (FF) circuit 128. The clock (CLK) input of the FF circuit 128 receives the oscillation output signal Vout(t). The output (Q) of the FF circuit 128 generates the delayed synchronized feedback signal (CLKfb_sync_dly) 124.

[0037] It should be noted that Figure 5 the circuit of Figure 5The circuitry of the noise cancellation circuit 112 can be implemented with additional FF circuitry 128 in series as needed to provide integer multiples of Tvco required for the noise cancellation current Ican(t).

[0038] Referring again to Figure 4 , the quantizing noise cancellation circuit 112 also includes a replica phase frequency detector (PFD) circuit 130. By "replica" it is meant that the circuitry used for the PFD circuit 130 is a replication of the circuitry used for the PFD circuit 12 (compare Figure 2 and Figure 6 and the use of identical circuit architecture).

[0039] Now also referring to Figure 6 , the replica PFD circuit 130 has a first input for receiving the synchronized feedback signal (CLKfb_sync) 122 and a second input for receiving a delayed synchronized feedback signal (CLKfb_sync_dly) 124. The synchronized feedback signal (CLKfb_sync) 122 is applied to the clock (CLK) input of a first D-type flip-flop (FF) circuit 134, which also has a data (D) input for receiving a logic high voltage (Vdd). The output (Q) of the FF circuit 134 generates the upper signal Urep(t). The delayed synchronized feedback signal (CLKfb_sync_dly) 124 is applied to the clock (CLK) input of a second D-type flip-flop (FF) circuit 136, which also has a data (D) input for receiving a logic high voltage (Vdd). The output (Q) of the FF circuit 136 generates the lower signal Drep(t). A logic AND gate 138 has a first input for receiving the upper signal Urep(t) and a second input for receiving the lower signal Drep(t). The gate 138 performs a logical AND on these signals to generate a reset signal, which is applied to the reset inputs (RST) of the first FF circuit 134 and the second FF circuit 136.

[0040] Because of the configuration of the synchronization circuit 120, the synchronization feedback signal (CLKfb_sync) 122 and the delayed synchronization feedback signal (CLKfb_sync_dly) 124 always have a phase relationship in which an edge of the synchronization feedback signal (CLKfb_sync) 122 leads a similar edge of the delayed synchronization feedback signal (CLKfb_sync_dly) 124 by one period of the oscillation output signal Vout(t) (or an integer multiple thereof as set by the number of FF circuits 128 as described above). As a result, the pulse generation upper signal Urep(t) has a first duration and the pulse generation lower signal Drep(t) has a second duration (less than the first duration). The smaller pulse width of the lower signal Drep(t) is controlled by the operating delay (td) of the AND gate 138 to cause the first FF circuit 134 and the second FF circuit 136 to reset. The larger pulse width of the upper signal Urep(t) is controlled as a function of the minimum pulse width (td) plus the sum of the time difference (i.e., phase difference - pdo) between similar edges of the synchronization feedback signal (CLKfb_sync) 122 and the delayed synchronization feedback signal (CLKfb_sync_dly) 124. This phase difference (pdo) depends on the delay imposed by the synchronization circuit 120 (one or more second flip-flops 128) which is equal to one (or more) clock period (cc) of the oscillation output signal Vout(t) (i.e., one or more periods Tvco).

[0041] Referring again to Figure 4 , the CP circuit 20 includes a current source (path) circuit 20a operative to provide a source current contribution to the charge pump output current Icp(t) in response to assertion of the upper signal U(t). The CP circuit 20 also includes a current sink (path) circuit 20b operative to provide a sink current contribution to the charge pump output current Icp(t) in response to assertion of the lower signal D(t). The output current Icp(t) is the difference between the source current contribution and the sink current contribution. As previously described, this charge pump output current Icp(t) is subject to SDM quantization noise. The quantization noise cancellation circuit 112 is operative to cancel the SDM quantization noise to generate a corrected (or compensated) output current Icp(t)' substantially free of SDM quantization noise for application to the input of the LF circuit 22.

[0042] The quantization noise cancellation circuit 112 includes a current digital-to-analog (D / A) converter circuit 150 configured to generate a noise cancellation current Ican(t) for application to cancel the quantization noise present in the output current Icp(t) of the CP circuit 20. The current D / A converter circuit 150 includes a current source (path) circuit 150a operative to provide a source current contribution to the noise cancellation current Ican(t) in response to an N-bit signal (UP_DAC <n-1:0>)142 to provide a controllable-amplitude source current contribution to the noise cancellation current Ican(t). The current source (path) circuit 150a can be implemented, for example, by N individual current sources, which are controlled by an N-bit signal (UP_DAC <n-1:0>corresponding bit of the 142 is asserted. Each current source in the current source (path) circuit 150a can generate the same magnitude of current in response to assertion of the bit. The current D / A converter circuit 150 also includes a current sink (path) circuit 150b for sinking the current in response to the N-bit signal (DN_DAC <n-1:0>)144 to provide an amplitude controllable sink current contribution to the noise cancellation current Ican(t). The current sink (path) circuit 150b can be implemented, for example, by N individual current sinks which are controlled by N-bit signals (DN_DAC <n-1:0>The current sink (path) circuit 150b can generate the same magnitude of current in response to assertion of the bit.

[0043] The quantization noise cancellation circuit 112 also includes a logic circuit 140 configured to generate an N-bit signal (UP_DAC <n-1:0>)142 to control operation of the current source (path) circuit 150a (of individual current sources). The logic circuit 140 is also configured to generate an N-bit signal (DN_DAC <n-1:0>)144 to control operation of the current sink (path) circuit 150b (of the individual current sinks). The N-bit signal (UP_DAC <n-1:0>)142 and N-bit signal (DN_DAC <n-1:0>)144 in response to the upper signal Urep(t) and the lower signal Drep(t) output by the replica PFD circuit 130 and the digital code signal Dig[n] with the sign bit (Sign) output by the DSM circuit 44. In this context, in response to , the digital code signal Dig[n] provides information about the noise cancellation current amplitude and the sign bit provides information about the polarity (e.g. to perform current sourcing or current sinking).

[0044] Reference is now made to Figure 7 , a block diagram of the logic circuit 140 is shown. The logic circuit 140 comprises n = N sub-circuits 140 where each sub-circuit operates to convert one bit of the digital code signal Dig[n] to a corresponding bit of the UP_DAC signal 142 and a corresponding bit of the DN_DAC signal 144. The logic within each sub-circuit is identical. The first logic AND gate 160 has a first input for receiving the i-th bit of the digital code signal Dig[n] and a second input for receiving the down signal Drep(t) from a copy of the output of the PFD circuit 130. The second logic AND gate 162 has a first input for receiving the i-th bit of the logical inversion of the digital code signal Dig[n] and a second input for receiving the up signal Urep(t) from a copy of the output of the PFD circuit 130. The signals output by the AND gates 160 and 162 are processed by a logical OR gate 164 to generate the DAC_CONT The i-th bit of the signal. The logic provided by gates 160, 162 and 164 generates DAC_CONT signal, to be converted into a digital code signal Dig The logic of the i-th bit of the digital code signal Dig is low Figure 8A ) when the bit is not asserted, i.e. when the digital code signal Dig has a pulse equal to the upper signal Urep(t). Conversely, when the digital code signal Dig The logic of the i-th bit is logic high ( Figure 8B When DAC_CONT asserts the bits of the digital code signal Dig, that is, when the bits of DAC_CONT are asserted. The signal has a pulse equal to the lower signal Drep(t).

[0045] The third logic AND gate 166 has inputs for receiving DAC_CONT The first input of the i-th bit of the signal and the second input for receiving the logically inverted sign bit. The fourth logical AND gate 168 has a first input for receiving the up signal Urep(t) output by the replica PFD circuit 130 and a second input for receiving the sign bit. The signals output by the AND gates 166 and 168 are processed by a logical OR gate 170 to generate the i-th bit of the UP_DAC signal 142. The logic provided by the gates 166, 168, and 170 generates the UP_DAC signal 142, to be converted into a digital code signal Dig the i-th bit is logic low (i.e. not asserted, see Figure 9A and 9C ) has a pulse equal to the up signal Urep(t), regardless of the logic state of the sign bit. Conversely, when the digital code signal Dig The logic provided by gates 166, 168, and 170 generates UP_DAC when the i-th bit of the UP_DAC control word is logic high (i.e., asserted) The signal 142 has a pulse equal to the upper signal Urep(t) when the sign bit is asserted (logic 1), as shown in Figure 9B or a pulse equal to the lower signal Drep(t) when the sign bit is not asserted (logic 0), as shown in Figure 9D .

[0046] The fifth logic AND gate 172 has inputs for receiving the DAC_CONT The first input of the i-th bit of the signal and the second input for receiving the sign bit. The sixth logic AND gate 174 has a first input for receiving the up signal Urep(t) output by the replica PFD circuit 130 and a second input for receiving the logically inverted sign bit. The signals output by the AND gates 172 and 174 are processed by a logic OR gate 176 to generate the i-th bit of the DN_DAC signal 144. The logic provided by the gates 172, 174, and 176 generates the DN_DAC signal 144, to be converted into a digital code signal Dig the i-th bit is logic low (i.e. not asserted, see Figure 10A and 10C ) has a pulse equal to the up signal Urep(t), regardless of the logic state of the sign bit. Conversely, when the digital code signal Dig The logic provided by gates 172, 174, and 176 generates the DN_DAC when the i-th bit of the DN is logic high (i.e., asserted) the signal 144, with a pulse equal to the upper signal Urep(t) when the sign bit is not asserted (logic 0), as shown in Figure 10B , or with a pulse equal to the lower signal Drep(t) when the sign bit is asserted (logic 1), as shown in Figure 10D .

[0047] Reference is now made to Figure 11A , Figure 11A , in case a) of alignment of the similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t), the operating timing diagrams of the CP circuit 20 and the current D / A converter circuit 150. As mentioned above, in this case the PFD circuit 12 will generate the upper signal U(t) and the lower signal D(t) with the same pulse (labeled 200), the width (smaller) of which is controlled by the operating delay (td) of the AND gate 18, to reset the first FF circuit 14 and the second FF circuit 16. As a result, the source current i(20a) and the sink current i(20b) are identical, and the output current Icp(t) is zero, since the source current contribution cancels the sink current contribution.

[0048] The noise to be eliminated by the D / A converter circuit 150, due to the phase difference between the upper signal U(t) and the lower signal D(t), appears in the form of a difference in the pulse width of the upper signal U(t) and the lower signal D(t). In this case a), since the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t) are aligned, the upper signal U(t) and the lower signal D(t) have the same width (labeled 200). In this case the digital code signal Dig[n] generated by the DSM circuit 44 will not have an asserted bit, in Figure 11A , noted "not asserted", and the value of the sign bit is irrelevant. In this regard, it should be noted that the digital code signal Dig[n] output by the DSM circuit 44 is proportional to , and when this expression is equal to 0, the code is also 0 and no bit of the code is asserted. The current D / A converter circuit 150 is controlled by the logic circuit 140 so that for the same pulse width (labeled 206) equal to the sum of the minimum pulse width (td) plus the phase difference (pdo) provided by the replica PFD circuit 130 output of the upward signal Urep(t), all the current source (path) circuits 150a (of each current source) and all the current sinks (path) circuits 150b (of each current sink) are not actuated in response to any bit of the code being asserted (see Figure 8A , 9A , 9C, 10A and 10C). As a result, the source current i(150a) and the sink current i(150b) used to actuate the current source and the current sink, respectively, are identical and the output current Ican(t) is zero because the offset of the source current contribution from the sink current contribution is zero.

[0049] Reference is now made to Figure 11B , Fig. 4 shows the operation timing diagram of the CP circuit 20 and the current D / A converter circuit 150 in case b) where the edge of the reference clock signal CLKref(t) leads the similar edge of the feedback clock signal CLKfb(t). As mentioned above, in this case the PFD circuit 12 will generate a down signal D(t) (as indicated by marker 210) whose width (smaller) is controlled by the operation delay (td) of the AND gate 18 so that the first FF circuit 14 and the second FF circuit 16 are reset and generate an up signal U(t) whose width (larger) is controlled as a function of the minimum pulse width (td) plus the time difference (i.e. phase difference - pd) between the similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t). As a result, the source current i(20a) and the sink current i(20b) are not identical and the output current Icp(t) includes a source current contribution (i.e. a current input pulse).

[0050] Due to the phase difference between the up signal U(t) and the down signal D(t), the noise to be eliminated by the D / A converter circuit 150 appears in the form of the difference in the pulse width of the up signal U(t) and the down signal D(t). In this case b) where the edge of the reference clock signal CLKref(t) leads the similar edge of the feedback clock signal CLKfb(t), the up signal U(t) has a larger width than the down signal D(t). In this case, the compensation operation is to actuate more sink current i(150b) than source current i(150a) so as to compensate for the shorter actuation of the sink current i(20b). The digital code signal Dig[n] generated by the DSM circuit 44 will have a certain number of asserted bits (this number is 1-N) and a sign bit (i.e. the sign bit is a logic 0) indicating that the compensation is a current sink operation. In this regard, it should be noted that the digital code signal Dig[n] is proportional to the difference between the up signal U(t) and the down signal D(t) and when this difference is non-zero, the code is also non-zero and at least some of the bits of the code (proportional to the non-zero value) are asserted and the sign bit is set to correspond to the sign of the non-zero value. Thus, the number of asserted bits in the digital code signal Dig[n] depends on the magnitude of the phase difference between the up signal U(t) and the down signal D(t). The current D / A converter circuit 150 is controlled by the logic circuit 140. For the bits of the digital code signal Dig[n] that are not asserted (in the case of a positive phase difference), the current D / A converter circuit 150 is controlled to actuate the source current i(150a) and for the bits of the digital code signal Dig[n] that are asserted (in the case of a negative phase difference), the current D / A converter circuit 150 is controlled to actuate the sink current i(150b). Figure 11B ​For the purposes of "not asserted", the respective current source (path) circuit 150a (each current source) and the respective current sink (path) circuit 150b (each current sink) are actuated to the same pulse width (denoted as 216), which is equal to the minimum pulse width (td) plus the sum of the phase difference (pdo) provided by the upper signal Urep(t) output by the replica PFD circuit 130 (see Figure 8A , 9A 9C, 10A, and 10C). As a result, due to the cancellation of the source current contribution and the absorption current contribution, the source current i(150a) and the absorption current i(150b) of these current source / absorber paths are the same, and the contribution of the output current Ican(t) from these current source / absorber circuits is zero. Conversely, for the digital code signal Dig[n] bits, it has been asserted (in Figure 11B In the case of an assertion (referred to as "assertion"), the corresponding current source (path) circuit 150a (each current source) is actuated with the same pulse width (denoted as 216u), which is equal to the minimum pulse width (td) provided by the lower signal Drep(t) output by the replica PFD circuit 130 (see...). Figure 8B and 9D And actuates the corresponding current sink (path) circuit 150b (each current sink) with the same pulse width (labeled 216d), which is equal to the minimum pulse width (td) plus the sum of the phase difference (pdo) provided by the upper signal Urep(t) output by the replica PFD circuit 130 (see...). Figure 8B and 10B As a result, the source current i(150a) and the absorption current i(150b) of these current source / absorber paths are different, and the contribution of the output current Ican(t) from these current source / absorber circuits is the absorption current pulse used to compensate for the shorter actuation of the absorption current i(20b).

[0051] Now for reference Figure 11C The figure shows the timing diagram of the operation of the CP circuit 20 and the current D / A converter circuit 150 in case c), where the edge of the feedback clock signal CLKfb(t) leads the similar edge of the reference clock signal CLKref(t). As described above, in this case, the PFD circuit 12 generates an upper signal U(t) (as indicated by label 220), the width of which is smaller and controlled by the operating delay (td) of the AND gate 18, so that the first FF14 and the second FF circuit 16 are reset and a lower signal D(t) is generated, the width of which is larger and controlled as a function of the minimum pulse width (td) plus the sum of the time difference (i.e., the phase difference -pd) between the similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t). As a result, the source current i(20a) and the sink current i(20b) are not the same, and the output current Icp(t) includes a contribution from the sink current (i.e., a current sink pulse).

[0052] Due to the phase difference between the upper signal U(t) and the lower signal D(t), the noise to be eliminated by the D / A converter circuit 150 appears in the form of the pulse width difference between the upper signal U(t) and the lower signal D(t). In this case c), the edge of the feedback clock signal CLKfb(t) leads the similar edge of the reference clock signal CLKref(t), and the lower signal D(t) has a larger width than the upper signal U(t). In this case, the compensation operation is to actuate a source current i(150a) more than the sink current i(150b), thereby compensating for the shorter actuation of the source current i(20a). The digital code signal Dig[n] generated by the DSM circuit 44 will have a certain number of assertion bits (the number is 1-N) and a sign bit indicating that the compensation is a current input operation (i.e., the sign bit is logic 1). It should be noted that the output of the DSM circuit 44 is related to the current input operation. The digital code signal Dig[n] is proportional to the non-zero value, and the code is also non-zero when the expression is non-zero. At least some bits of the code (proportional to the non-zero value) are asserted, and the sign bit is set to correspond to the sign of the non-zero value. Therefore, the number of asserted bits in the digital code signal Dig[n] depends on the magnitude of the phase difference between the upper signal U(t) and the lower signal D(t). The current D / A converter circuit 150 is controlled by the logic circuit 140. For the unasserted bits of the digital code signal Dig[n] (in Figure 11C For the purposes of "not asserted", the respective current source (path) circuit 150a (each current source) and the respective current sink (path) circuit 150b (each current sink) are actuated to the same pulse width (denoted as 226), which is equal to the minimum pulse width (td) plus the sum of the phase difference (pdo) provided by the upper signal Urep(t) output by the replica PFD circuit 130 (see [link to relevant documentation]). Figure 8A , 9A As a result, the source current i (150a) and sink current i (150b) of these current source / sink paths are identical, and the contribution to the output current Ican(t) from these current source / sink circuits is zero due to the source current contribution canceling out the sink current contribution. In contrast, for the case where the digital code signal Dig[n] bit has been asserted (denoted as "asserted" in Figure 11C ), the respective current sink (path) circuits 150b are actuated for the same pulse width (denoted as 226d) that is equal to the minimum pulse width (td) provided by the lower signal Drep(t) output by the replica PFD circuit 130 (see Figure 8B and 10D ), and the respective current source (path) circuits 150a are actuated for the same pulse width (denoted as 226u) that is equal to the sum of the minimum pulse width (td) plus the phase difference (pdo) provided by the upper signal Urep(t) output by the replica PFD circuit 130 (see Figure 8B and 9B ). As a result, the source current i (150a) and sink current i (150b) of these current source / sink paths are different, and the contribution to the output current Ican(t) from these current source / sink circuits is a shorter actuated source current pulse for compensating the source current i (20a).

[0053] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the application is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A noise cancellation circuit for a phase-locked loop (PLL) circuit, the PLL circuit including a fractional-N divider generating a feedback clock signal, the noise cancellation circuit comprising: a synchronization circuit receiving a voltage-controlled clock signal of the PLL circuit and the feedback clock signal, and configured to generate a first synchronized feedback clock signal and a second synchronized feedback clock signal, wherein the second synchronized feedback clock signal is delayed by an integer number of cycles of the voltage-controlled clock signal; a first phase-frequency detector circuit receiving the first synchronized feedback clock signal and the second synchronized feedback clock signal, and configured to generate a first up control signal and a first down control signal, wherein a pulse width of the first up control signal differs from a pulse width of the first down control signal by the integer number of cycles; a logic circuit configured to generate an up digital control signal and a down digital control signal in response to the first up control signal, the first down control signal, and a digital code signal indicative of a noise cancellation correction magnitude; and a current digital-to-analog converter circuit receiving the up digital control signal and the down digital control signal, and including: a current source circuit operating in response to the up digital control signal to provide a noise cancellation source current to the PLL circuit; and a current sink circuit operating in response to the down digital control signal to provide a noise cancellation sink current to the PLL circuit.

2. The noise cancellation circuit of claim 1, wherein the PLL circuit includes a charge pump circuit generating a charge pump output current, and wherein the noise cancellation source current and the noise cancellation sink current are applied to cancel noise in the charge pump output current.

3. The noise cancellation circuit of claim 2, wherein the noise cancellation source current is added to the charge pump output current, and the noise cancellation sink current is subtracted from the charge pump output current.

4. The noise cancellation circuit of claim 2, wherein the current digital-to-analog converter circuit further receives a sign signal indicative of a polarity of the noise cancellation correction, and wherein the up digital control signal and the down digital control signal are generated in response to the sign signal.

5. The noise cancellation circuit of claim 4, wherein the PLL circuit includes a delta-sigma modulator circuit configured to control the fractional-N divider, and wherein the delta-sigma modulator circuit is configured to generate the digital code signal and the sign signal from a modulation applied to control the fractional-N divider. ​ ​ 6. The noise cancellation circuit of claim 4, wherein the PLL circuit includes a second phase frequency detector circuit that receives a reference clock signal and the feedback clock signal, and the second phase frequency detector circuit is configured to generate a second up control signal and a second down control signal for controlling the charge pump circuit, and wherein the first phase frequency detector circuit is a circuit replica of the second phase frequency detector circuit.

7. The noise cancellation circuit of claim 1, wherein the PLL circuit includes a delta-sigma modulator circuit that is configured to control the fractional-N divider, and wherein the delta-sigma modulator circuit is configured to generate the digital code signal from a modulation applied to control the fractional-N divider.

8. A noise cancellation circuit for a phase-locked loop (PLL) circuit, wherein the PLL circuit comprises: a fractional-N divider that generates a feedback clock signal; a first phase frequency detector that is configured to compare the feedback clock signal to a reference clock signal and generate a first up control signal and a first down control signal; and a charge pump circuit that is controlled by the first up control signal and the first down control signal to generate a charge pump output current, the noise cancellation circuit comprising: a synchronization circuit that receives a voltage-controlled clock signal of the PLL circuit and the feedback clock signal, and the synchronization circuit is configured to generate a first synchronized feedback clock signal and a second synchronized feedback clock signal, wherein the second synchronized feedback clock signal is delayed by an integer number of cycles of the voltage-controlled clock signal; a second phase frequency detector circuit that receives the first synchronized feedback clock signal and the second synchronized feedback clock signal, and the second phase frequency detector circuit is configured to generate a second up control signal and a second down control signal, wherein a pulse width of the second up control signal differs from a pulse width of the second down control signal by the integer number of cycles; and a current digital-to-analog converter circuit that is controlled to apply a noise cancellation source current to the charge pump output current in response to the second up control signal, and the current digital-to-analog converter circuit is controlled to apply a noise cancellation sink current to the charge pump output current in response to the second down control signal.

9. The noise cancellation circuit of claim 8, wherein a noise cancellation current due to the noise cancellation source current and the noise cancellation sink current has a polarity opposite to a polarity of the charge pump output current.

10. The noise cancellation circuit of claim 8, wherein a pulse width of the noise cancellation current due to the noise cancellation source current and the noise cancellation sink current is equal to the integer number of cycles of the voltage-controlled clock signal.

11. The noise cancellation circuit of claim 9, further comprising a logic circuit configured to logically combine the second upper control signal and the second lower control signal with a digital code signal, the digital code signal indicative of a magnitude of a noise cancellation current due to the noise cancellation source current and the noise cancellation sink current, and the logic circuit configured to generate an upper digital control signal and a lower digital control signal that control the noise cancellation source current and the noise cancellation sink current, respectively.

12. The noise cancellation circuit of claim 11, wherein the PLL circuit comprises a delta-sigma modulator circuit configured to control the fractional-N divider, and wherein the delta-sigma modulator circuit is configured to generate the digital code signal from a modulation applied to control the fractional-N divider.

13. The noise cancellation circuit of claim 8, further comprising a logic circuit configured to logically combine the second upper control signal and the second lower control signal with a sign signal, the sign signal indicative of a polarity of a noise cancellation current due to the noise cancellation source current and the noise cancellation sink current, and the logic circuit configured to generate an upper digital control signal and a lower digital control signal that control the noise cancellation source current and the noise cancellation sink current to apply the polarity to the noise cancellation current.

14. The noise cancellation circuit of claim 13, wherein the polarity of the noise cancellation current is opposite to a polarity of the charge pump output current.

15. The noise cancellation circuit of claim 13, wherein the PLL circuit comprises a delta-sigma modulator circuit configured to control the fractional-N divider, and wherein the delta-sigma modulator circuit is configured to generate the sign signal from a modulation applied to control the fractional-N divider.

16. The noise cancellation circuit of claim 8, wherein the second phase frequency detector circuit is a circuit copy of the first phase frequency detector circuit.

17. The noise cancellation circuit of claim 8, wherein the noise cancellation source current is added to the charge pump output current, and the noise cancellation sink current is subtracted from the charge pump output current.

18. A method for a noise cancellation circuit in a phase-locked loop (PLL) circuit, the PLL circuit comprising a fractional-N divider that receives a voltage-controlled clock signal of the PLL circuit and generates a feedback clock signal of the PLL circuit, the method comprising: generating a first synchronized feedback clock signal and a second synchronized feedback clock signal from the voltage-controlled clock signal and the feedback clock signal of the PLL circuit, the second synchronized feedback clock signal delayed from the first synchronized feedback clock signal by an integer number of cycles of the voltage-controlled clock signal; processing the first and second synchronized feedback clock signals to generate a first up control signal and a first down control signal, wherein a pulse width of the first up control signal differs from a pulse width of the first down control signal by the integer number of cycles; generating a digital code signal indicative of a noise cancellation correction amplitude; applying a noise cancellation source current to the PLL circuit, wherein an amplitude of the noise cancellation source current depends on the digital code signal and an up digital control signal derived from the first up control signal and the first down control signal; and applying a noise cancellation sink current to the PLL circuit, wherein an amplitude of the noise cancellation sink current depends on the digital code signal and a down digital control signal derived from the first up control signal and the first down control signal.

19. The method of claim 18: wherein applying the noise cancellation source current to the PLL circuit comprises applying the noise cancellation source current to a charge pump output current; and wherein applying the noise cancellation sink current to the PLL circuit comprises applying the noise cancellation sink current to the charge pump output current.

20. The method of claim 18, further comprising: generating a sign signal indicative of a polarity of the noise cancellation correction, and wherein applying the noise cancellation source current and applying the noise cancellation sink current comprises controlling current application in response to the sign signal.

21. A method for a noise cancellation circuit in a phase-locked loop (PLL) circuit, the PLL circuit comprising a fractional-N divider that receives a voltage-controlled clock signal of the PLL circuit and generates a feedback clock signal of the PLL circuit, the method comprising: synchronizing the feedback clock signal with the voltage-controlled clock signal to generate a first synchronized feedback clock signal and a second synchronized feedback clock signal, the second synchronized feedback clock signal being delayed from the first synchronized feedback clock signal by an integer number of cycles of the voltage-controlled clock signal; phase comparing the first and second synchronized feedback clock signals to generate an up control signal and a down control signal, wherein a pulse width of the up control signal differs from a pulse width of the down control signal by the integer number of cycles; and in response to the up control signal, applying a noise cancellation source current to the PLL circuit; and in response to the down control signal, applying a noise cancellation sink current to the PLL circuit.

22. The method of claim 21: wherein applying the noise cancellation source current to the PLL circuit comprises applying the noise cancellation source current to a charge pump output current; and wherein applying the noise cancellation sink current to the PLL circuit comprises applying the noise cancellation sink current to the charge pump output current.

23. The method of claim 21, further comprising: generating a sign signal indicative of a polarity of the noise cancellation correction, and wherein applying the noise cancellation source current and applying the noise cancellation sink current comprises controlling current application in response to the sign signal.

24. The method of claim 21, further comprising: Generating a digital code signal indicative of the noise cancellation correction magnitude, applying the noise cancellation source current and applying the noise cancellation sink current includes controlling the magnitude of the current application in response to the digital code.

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