Semiconductor element and method for manufacturing semiconductor element

Abstract

A semiconductor element having gallium nitride, comprising a semiconductor layer having a first surface, wherein the first surface includes a first region and a second region which is a band-shaped convex portion protruding from the first region or a band-shaped concave portion recessed from the first region, wherein in the first surface, at least one of the surfaces of the first region or the second region has a crystal plane having a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

Description

Technical Field

[0001] The present invention relates to a semiconductor element composed of a GaN-based semiconductor and a method for manufacturing the semiconductor element. Background Art

[0002] Conventional semiconductor devices and methods for manufacturing semiconductor devices are described in Patent Document 1, for example.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2011-66398 Summary of the invention

[0006] The semiconductor element of the present invention is a semiconductor element having gallium nitride, wherein the semiconductor layer has a first surface, wherein the first surface includes: a first region; and a second region which is a band-shaped convex portion protruding from the first region or a band-shaped concave portion recessed from the first region, wherein at least one of the surfaces of the first region or the second region in the first surface has a crystal plane having a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0007] In addition, the manufacturing method of the semiconductor element of the present invention comprises: a step of preparing a substrate, a step of forming a semiconductor layer having gallium nitride on the first surface of the substrate, and a step of peeling the semiconductor layer from the substrate, wherein when peeling the semiconductor layer from the substrate, the peeling is performed in a manner such that the peeling surface becomes a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0008] In addition, the semiconductor element of the present invention is a semiconductor element having gallium nitride, and has a semiconductor layer that is epitaxially grown starting from a substrate, the semiconductor layer having a first surface including a first region and a second region adjacent to the first region, the second region being a peeling surface formed when separated from the substrate, the peeling surface having a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The objects, features and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings.

[0010] Figure 1 It is a cross-sectional view schematically showing a semiconductor element according to one embodiment of the present invention.

[0011] Figure 2 It is a diagram for explaining the method for manufacturing a semiconductor element of the present invention.

[0012] Figure 3 This is an enlarged photograph showing the cross-sectional shape of the base substrate 1 near the opening.

[0013] Figure 4 This is an enlarged photograph showing the cross-sectional shape of the base substrate 1 near the opening.

[0014] Figure 5A The cross-sectional view schematically shows a state where a deposition inhibiting mask is stacked on the first base surface of the base substrate 1 .

[0015] Figure 5B It is a cross-sectional view schematically showing a state where a semiconductor layer is formed on a deposition inhibiting mask.

[0016] Figure 5C It is a cross-sectional view schematically showing a state where a protrusion is formed on a semiconductor layer.

[0017] Figure 5D It is a cross-sectional view schematically showing a state in which an n-type insulating layer is formed on a planar portion of a semiconductor layer having a protrusion.

[0018] Figure 5E It is a cross-sectional view schematically showing a state where a p-type electrode is stacked on a protrusion and an insulating layer.

[0019] Fig. 5F It is a cross-sectional view schematically showing a state where an electrode pad is stacked on a p-type electrode.

[0020] Figure 5G It is a cross-sectional view schematically showing a state where the deposition inhibiting mask is removed.

[0021] Figure 5H This is a cross-sectional view schematically showing a state in which the semiconductor laser element separated from the base substrate is turned over.

[0022] Fig.5I It is a cross-sectional view schematically showing a state where an n-type electrode is stacked on the second base surface of the semiconductor laser element.

[0023] Figure 5J It is a cross-sectional view schematically showing a pair of resonator faces in a state where the end faces are coated.

[0024] Figure 5K It is a cross-sectional view schematically showing a state in which a semiconductor laser element is bonded to a mounting substrate via an n-type electrode.

[0025] Figure 6 is from Figure 5H A magnified photograph of the semiconductor layer viewed from above.

[0026] Figure 7 It is a cross-sectional view schematically showing a semiconductor element according to one embodiment of the present invention. DETAILED DESCRIPTION

[0027] First, the basic configuration of the semiconductor element and the method for manufacturing the semiconductor element according to the present invention will be described.

[0028] Conventionally, semiconductor elements and methods for manufacturing semiconductor elements, for example, as described in the aforementioned Patent Document 1, a mask layer having a plurality of stripe-shaped openings is formed on a base substrate composed of a material different from GaN-based semiconductors, such as a C-plane sapphire substrate and a silicon substrate with a (111) crystal plane orientation, and a GaN-based semiconductor layer is selectively grown along the (0001) crystal plane orientation on the surface of the base substrate exposed from the openings, thereby manufacturing a GaN-based semiconductor element.

[0029] An electrode is formed on the GaN-based semiconductor layer manufactured by such a method for manufacturing a semiconductor element, but there is still room for improvement in the ohmic contact property of the electrode with the GaN-based semiconductor.

[0030] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The accompanying drawings are schematically shown for the sake of illustration.

[0031] (First embodiment)

[0032] Figure 1 1 is a cross-sectional view showing a semiconductor element according to an embodiment of the present invention. The semiconductor element S of this embodiment is composed of a GaN-based semiconductor and has a crystal structure formed by crystal growth along the (0001) crystal plane orientation (a direction perpendicular to the (0001) plane 32) of the GaN-based semiconductor. In addition, as described later Figure 2 As shown, the first surface 31 has a (000-1) crystal plane orientation of the GaN-based semiconductor, which is opposite to the planar first base surface 1a as one main surface of the base substrate 1. The first surface 31 has a planar first region W1 and a second region W2 protruding from the first region W1. Therefore, the first surface 31 has: three crystal planes 10a, 10b, 10c (second region W2) having a crystal plane orientation different from the (000-1) plane; a second region W2 located in the <11-20> direction ( Figure 1 There are two nitrogen polarity surfaces (hereinafter also referred to as “N surfaces”) 10d and 10e (the first region W1) in the left-right direction.

[0033] As described later, such multiple crystal planes are composed of the fracture surface 10a, one side surface 10b, and the other side surface 10c of the band-shaped protrusion 9 formed by peeling the semiconductor layer 3 from the base substrate 1, and have three or more crystal planes with different crystal plane orientations. Because such multiple crystal planes 10a, 10b, and 10c are formed by the protrusion 9, they protrude from the (000-1) plane to the (000-1) crystal plane orientation (direction perpendicular to the (000-1) plane).

[0034] Since the convex portion 9 is realized as a structure formed by protruding GaN semiconductor on the N-face of the semiconductor layer 3 which is a GaN semiconductor epitaxially grown (ELO; Epitaxial Lateral Overgrowth) from the base substrate 1, it is possible to expose the crystal plane other than the N-face (000-1). The convex portion 9 contains GaN that already exists when the deposition suppression mask is formed, and the ohmic contact can be improved by adjusting the doping amount of impurities, such as Si, on the base substrate 1 side.

[0035] As mentioned above, in the convex portion 9, since three crystal planes 10a, 10b, and 10c with different orientations are exposed, it is easier to obtain ohmic contact. The three crystal planes 10a, 10b, and 10c are crystal planes other than the nitrogen polarity planes 10d and 10e, for example, the M plane (1-100), the A plane (11-20), and the R plane (1-102) are exposed. Then, the n-type electrode 12 is formed continuously on multiple crystal planes 10a, 10b, 10c and the nitrogen polarity planes 10d and 10e. As a result, the ohmic contact with the n-type electrode 12 can be greatly improved, and the adhesion and stability of the n-type electrode 12 can be improved. On the second surface 32 opposite to the first surface 31 of the semiconductor layer 3, a p-type electrode 14 described later is arranged as a second electrode.

[0036] The ohmic resistance for determining the ohmic contact can be measured by, for example, the TLM (Transmission Line Model) method or the CTLM (Circular Transmission Line Model) method.

[0037] The semiconductor element in the present embodiment may include the protrusion 9 in the central portion of the first surface 31. In other words, the first surface 31 includes a plurality of first regions W1 sandwiching the second region W2.

[0038] In addition, the surface of the first region W1 may have a crystal plane having the same crystal plane orientation as the surface of the second region W2. In this case, for example, by polishing a portion of the surface of the second region W2 (e.g., 10a), the first region W1 and the second region W2 may have a crystal plane having a (000-1) crystal plane orientation.

[0039] In addition, in the semiconductor element of the present embodiment, the contact area between the first electrode 12 and the first region W1 may be larger than the contact area between the first electrode 12 and the second region W2 .

[0040] In the contact region between the first electrode 12 and the second region W2, the area of ​​the crystal plane including the (000-1) crystal plane orientation or the (1-100) crystal plane orientation may be smaller than the area of ​​the crystal plane including the crystal plane orientation other than the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0041] Figure 2 This is a diagram for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention. In the same figure, steps (a), (b), (c), and (d) are shown as the manufacturing steps of the semiconductor device.

[0042] The method for manufacturing a semiconductor device according to the embodiment is configured such that the substrate reuse step of repeating the above steps (a) to (d) is performed one or more times.

[0043] exist Figure 2 In the embodiment, step (a) is a mask forming step, step (b) is a device forming step, step (c) is a mask removing step, and step (d) is a device separating step.

[0044] The base substrate 1 used in each step (a) to (d) has a flat main surface, i.e., a first base surface 1a, which is a starting point for crystal growth of the semiconductor, and another flat main surface, i.e., a second base surface 1b, which is the back surface thereof. At least the surface of the first base surface 1a is covered with a nitride semiconductor. The base substrate 1 used in the embodiment is, for example, a GaN substrate cut from a single crystal ingot of gallium nitride (GaN).

[0045] The GaN substrate can be either an n-type substrate or a p-type substrate in which impurities such as Si are doped in the semiconductor. For example, a substrate with an impurity density of 1×10 19 cm －3 As the base substrate 1, in addition to the GaN substrate, a substrate having a GaN semiconductor layer formed on the surface of a substrate other than GaN, such as a sapphire substrate, a silicon substrate, or a SiC substrate may be used.

[0046] The surface of the base substrate 1 is not limited to a GaN layer, and any substrate composed of a GaN-based semiconductor can be used. The "GaN-based semiconductor" mentioned here refers to, for example, a substrate composed of Al x Ga y In z N(0≤x≤1-1≤y≤1-1≤z≤1; x+y+z=1).

[0047] In addition, in addition to the first base surface 1a which is the starting point of crystal growth of the semiconductor, a protective layer 4 may be formed on the second base surface 1b and the substrate end surface 1c of the base substrate 1 located on the opposite side (lower side) relative to the first base surface 1a. The protective layer 4 is formed to suppress the deterioration of the base substrate 1 caused by the steps described later and the decomposition of the nitride semiconductor. The protective layer 4 may be formed of a layer containing aluminum oxide or aluminum oxide, for example. However, the protective layer 4 may not be present on the substrate end surface 1c.

[0048] Without the protective layer 4, the back side of the base substrate 1 is prone to gradual pyrolysis and deterioration. Therefore, the thermal emissivity changes and the in-plane distribution of the thermal emissivity due to the deterioration of the second base surface 1b on the back side of the base substrate 1 occur. As a result, the growth conditions of the semiconductor crystal are prone to deviate from the optimal conditions, which becomes a factor that reduces mass productivity. As in the present embodiment, by coating the second base surface 1b of the base substrate 1 with the protective layer 4, the deterioration of the second base surface 1b of the base substrate 1 can be suppressed, the growth conditions of the semiconductor crystal can be stabilized, and the mass productivity can be improved.

[0049] The first method for manufacturing a semiconductor element using the base substrate 1 includes: Figure 2 Steps (a) to (d) are shown. In step (a), a deposition suppressing mask 2 is formed on the first base surface 1a of the base substrate 1. In step (b), a semiconductor layer 3 is formed on the masked first base surface 1a of the base substrate 1. In step (c), the deposition suppressing mask 2 is removed by etching. In step (d), the semiconductor layer 3 is separated from the first base surface 1a of the base substrate 1.

[0050] (1) Step (a) (first time)

[0051] In step (a) as a mask forming step, a deposition inhibiting mask 2 for inhibiting growth of semiconductor crystals (semiconductor layer 3 ) is formed in a predetermined pattern on a first base surface 1 a of a base substrate 1 (GaN substrate).

[0052] As a specific example, a SiO2 layer with a thickness of about 100 to 1000 nm is formed as the deposition inhibiting mask 2. To form the SiO2 layer, first, silicon oxide (SiO2) as the material of the deposition inhibiting mask 2 is stacked on the first base surface 1a by a PCVD (Plasma Chemical Vapor Deposition) method or the like to a thickness of about 100 to 1000 nm.

[0053] Next, the excess SiO2 layer is removed by photolithography and HF (hydrofluoric acid) wet etching or dry etching using fluorine-based gas such as CF4. Thus, a predetermined patterned SiO2 layer can be formed as a deposition suppression mask 2 on the first base surface 1a.

[0054] The exposed surface E between the masks 2 and 2, which is exposed from the band-shaped groove (opening upward), is the first crystal growth region exposed from the aforementioned first base surface 1a, and is the region serving as the growth starting point of the semiconductor crystal in the subsequent step (b).

[0055] The opening width or groove width, which is the width of the (11-20) crystal plane orientation, that is, the juxtaposition direction (horizontal direction in the figure) of the exposed surface E, is, for example, 2 to 20 μm. In the embodiment, the width of the deposition inhibiting mask 2 in the juxtaposition direction is, for example, set to 50 to 200 μm.

[0056] The relationship between the width of the deposition inhibition mask 2 in the parallel direction and the width of the exposed surface E in the parallel direction can be set by considering the ratio of the crystal growth rate shown below and the thickness of the semiconductor layer 3 to be grown. In other words, the so-called crystal growth rate ratio is the ratio of the crystal growth rate in the direction perpendicular to the first base surface 1a of the base substrate 1 and the crystal growth rate in the direction parallel to the first base surface 1a of the base substrate 1 of the semiconductor layer 3 formed in step (b).

[0057] In addition, the mask pattern of the deposition suppression mask 2 may be a grid pattern in which multiple strips are arranged vertically and horizontally, in addition to strips or stripes. Any pattern may be used as long as the openings that are disconnected at a certain interval (repetition pitch) are repeated multiple times.

[0058] The surface of the deposition suppression mask 2 may be made uneven by etching, etc. Thus, the back surface of the semiconductor element S separated by step (d) can be provided with unevenness, which has the effect of improving the ohmic contact and adhesion between the first surface 31 of the semiconductor element S (the peeling surface after the semiconductor element S is separated) and the n-type electrode 12.

[0059] In addition, considering the ease of peeling and separation of the semiconductor layer 3 described later, the edge region near the substrate end face 1c of the base substrate 1 in the first base face 1a of the base substrate 1 is also covered with the aforementioned deposition suppression mask 2. Thus, the semiconductor layer 3 located near the edge portion of the end of the base substrate 1 can also be completely and reliably peeled off.

[0060] In addition, as a mask material constituting the deposition inhibiting mask 2, for example, a material containing silicon oxide such as SiO2 is used. The deposition inhibiting mask 2 may be made of any material as long as the semiconductor layer 3 does not grow from the surface of the mask material by vapor phase growth. In addition to the material containing silicon oxide, for example, zirconium oxide (ZrO X ), titanium oxide (TiO X ), aluminum oxide (AlOX ) or other oxides. Alternatively, a transition metal selected from chromium (Cr), tungsten (W), molybdenum (Mo), tantalum (Ta), and niobium (Nb) or the like may be used. In addition, the deposition method of the mask material may be appropriately a method suitable for the mask material, such as evaporation, sputtering, and coating hardening.

[0061] (2) Step (b) (first time)

[0062] In step (b) as an element formation step, semiconductor crystals are grown in a manner extending from the exposed surface E as the first crystal growth region to the top of the adjacent deposition inhibition mask 2, thereby forming a semiconductor layer 3 as an element. The semiconductor layer 3 of the present embodiment is a nitride semiconductor, and the nitride semiconductor is grown by epitaxial growth from the first base surface 1a over the upper edge opening of the groove of the deposition inhibition mask 2 to the top of the deposition inhibition mask 2.

[0063] As a specific example, in the element formation process, a vapor phase growth method such as a hydride vapor phase epitaxy (HVPE) method using chlorides for Group III (Group 13 elements) raw materials, a metal organic chemical vapor deposition (MOCVD) method using organic metals for Group III raw materials, or a molecular beam epitaxy (MBE) method can be used.

[0064] For example, when a GaN layer serving as a semiconductor layer 3 is grown by the MOCVD method, first, a base substrate 1 having a deposition inhibition mask 2 pattern formed thereon is inserted into a reaction chamber of an epitaxial device, and while supplying hydrogen, nitrogen, or a mixed gas of hydrogen and nitrogen, ammonia or other Group V raw material (containing Group 15 elements) gas, the base substrate 1 is heated to a prescribed growth temperature, for example, 1050 to 1100°C.

[0065] Next, after the temperature of the base substrate 1 is stabilized, a Group III (containing Group 13 elements) raw material such as trimethylgallium (TMG) is supplied in addition to the above-mentioned gases to vapor-grow the semiconductor layer 3 from the exposed surface E serving as a crystal growth region.

[0066] At this time, by supplying raw material gas such as Si and other n-type impurities, or Mg and other p-type impurities to modulate the doping amount, a desired conductive type GaN layer can be obtained. In addition, before the growing crystal crosses the upper edge opening of the groove between the deposition inhibition mask 2 or fills the groove, the raw material supply can be temporarily stopped to stop the growth of the semiconductor crystal, and before the raw material supply is resumed, the "fragile part" of the semiconductor layer 3 that is easily peeled off, which will be described later, is formed into a local layer or film.

[0067] As an example of a fragile portion, for example, when a GaN layer is crystal grown, a layer composed of mixed crystals of GaN and BN, AlN, InN, etc. can be formed as a fragile portion between the upper semiconductor layer 3 on the opening side of the aforementioned groove and the lower semiconductor layer 3 on the exposed surface E side.

[0068] In addition, a thin film made of Al having a lattice constant different from that of the crystal growth layer may be formed as the fragile portion. x Ga y In z N (0≤x≤1-1≤y<1-1≤z≤1; x+y+z=1) semiconductor layer 3. In addition, a fragile portion of a superlattice structure in which AlGaN layers and GaN layers are alternately stacked can also be formed. The crystal growth conditions can be changed periodically, layers with large GaN grains and layers with small GaN grains can be alternately stacked, or the concentration of silicon (Si) used as an n-type impurity of GaN can be changed, etc., to form a layer with a changing impurity concentration, thereby forming a fragile portion.

[0069] By utilizing these fragile portions, when the semiconductor element S is separated and peeled off from the base substrate 1, stress is concentrated on the fragile portions and cracks are easily generated, so that the semiconductor element S can be easily separated from the base substrate 1. In addition, by utilizing these fragile portions, the n-type electrode 12 is formed in a manner covering the three crystal planes 10a, 10b, and 10c of the protrusion 9 that is a part of the first surface 31 of the semiconductor element S, which can improve the ohmic contact.

[0070] When making the aforementioned fragile portion, GaN is grown laterally (ELO; Epitaxial Lateral Over-Growth) starting from the upper surface (surface) of the fragile portion. If no fragile portion is made, GaN is grown laterally starting from the exposed surface E between the aforementioned masks (the first base surface 1a of the base substrate 1). For example, by MOCVD, an n+ type GaN layer doped with Si as an n-type impurity is grown in an island shape along the (0001) crystal plane orientation. The thickness of the n+ type GaN layer is, for example, 10 μm, and the impurity concentration is, for example, 1×10 18 cm －3 The interval between the n+ type GaN layers in the <11-20> direction is, for example, approximately 10 μm.

[0071] The growth of the n+ type GaN layer is performed, for example, at a temperature of 1100°C and a pressure of 30 kPa. When the n+ type GaN layer is grown, for example, TMG and NH3 are used as raw material gases, H2 and N2 are used as carrier gases, and SiH4 diluted with nitrogen is used as an n-type dopant. An island-shaped n+ type GaN layer is grown from a stripe window.

[0072] Next, the crystal growth conditions are adjusted in such a way as to promote the vertical growth, and an n-type GaN layer is grown on the n+-type GaN layer by MOCVD. The thickness of the n-type GaN layer is, for example, 5 μm, and the impurity concentration is, for example, 1×10 16 cm －3 In this way, the distance between the n+ type GaN layer after the growth of the n type GaN layer and the entire n type GaN layer in the <11-20> direction is set to, for example, about 5 μm.

[0073] After the crystal growth plane of the semiconductor layer 3 passes over the upper edge of the deposition inhibiting mask 2, the semiconductor layer 3 grows laterally (left-right direction in the figure) along the upper surface of the deposition inhibiting mask 2. Therefore, the semiconductor layer 3 can be a semiconductor layer with few threading dislocations and suitable for use in light emitting diodes (LEDs) and laser diodes (LDs) elements.

[0074] Then, step (b) (first time) may be terminated after each semiconductor layer 3 grown from the exposed surface E between the masks comes into contact with the adjacent semiconductor layer 3 or before overlapping with each other, or may be terminated after coming into contact with each other.

[0075] (3) Step (c) (first time)

[0076] After the above-mentioned step (b) (first time) is completed, step (c) as a mask removal step is performed. In step (c), the base substrate 1 is taken out from the vapor phase growth device (epitaxial device), and the deposition inhibition mask 2 is removed using an etchant that does not substantially corrode the grown semiconductor layer 3.

[0077] For example, if the mask is composed of a SiO2 film, HF-based wet etching is performed. Each deposition suppression mask 2 is removed by etching, and the semiconductor layer 3 becomes Figure 2 As shown in (c), only the connection portion consisting of fine semiconductor walls or pillars is left in a generally T-shaped form on the exposed surface E between the adjacent deposition inhibiting masks 2. With this shape, the semiconductor layer 3 can be separated smoothly.

[0078] (4) Step (d) (first time)

[0079] In step (d) serving as an element separation step, a component or fixture such as a supporting substrate 6 having an adhesive layer 5 formed of solder made of a material such as AuSn on one surface of the semiconductor layer 3 (the second surface 32 in the present embodiment) is used to separate the semiconductor layer 3 from the base substrate 1 to form separate semiconductor elements S.

[0080] In step (d), first, for example, a supporting substrate 6 having an adhesive layer 5 on its lower surface is placed opposite to the surface of the base substrate 1 on which the semiconductor layer 3 is formed (i.e., the first base surface 1a), and the adhesive layer 5 is pressurized and heated to adhere to the semiconductor layer 3.

[0081] Thereafter, an external force is applied to the semiconductor layer 3 integrally bonded to the adhesive layer 5 so as to peel upward, and the semiconductor layer 3 is pulled up from the first base surface 1a of the base substrate 1. Thus, the main body of the semiconductor element S can be separated.

[0082] In step (d), instead of performing separation using the adhesive layer 5 formed of solder made of a material such as AuSn, separation may be performed using an adhesive tape such as a dicing tape or a double-sided tape.

[0083] After the semiconductor element is separated, the base substrate 1 is polished to remove the damage of the semiconductor element S during the peeling process in the epitaxial growth process, and the same process (a) as the mask forming process, process (b) as the element forming process, process (c) as the mask removing process, and process (d) as the element separating process as the first manufacturing are performed. Thus, the same base substrate 1 can be used to repeatedly manufacture high-quality semiconductor elements S with excellent ohmic contact properties that are the same as the elements obtained in the first manufacturing. The types of damage include pits formed by the reaction between the SiO2 mask and Ga; the surface roughness of GaN caused by the formation, heating, and removal process of the SiO2 mask; and dislocations caused by peeling.

[0084] In this damage removal step, wet etching or dry etching may be used in addition to polishing. Alternatively, instead of removing damage, steps (a) to (d) may be repeated by shifting the mask openings.

[0085] Figure 3 and Figure 4 This is an enlarged photograph showing the cross-sectional shape near the opening of the base substrate 1. The cross-sectional shape of the opening of the base substrate 1 after the semiconductor element S is peeled off becomes concave, and the damage depth Δd is 1 μm or less.

[0086] Therefore, by polishing or wet etching the first base surface 1 a of the used base substrate 1 to a thickness of 1 μm or less, the above-mentioned pits, surface roughness, dislocations and other crystal lattice defects can be removed.

[0087] (Second embodiment)

[0088] Figure 5A to Figure 5K It is a cross-sectional view schematically showing a manufacturing step of a semiconductor laser element according to the second embodiment of the present invention. Figure 5A2 shows a state where a deposition inhibiting mask 2 is stacked on the first base surface 1 a of the base substrate 1. Figure 5B The state where the semiconductor layer 3 is formed on the deposition inhibiting mask 2 is shown. Figure 5C It shows a state where a protrusion 3c is formed on the semiconductor layer 3. Figure 5D FIG. 1 shows a state where the insulating film 15 is formed on the planar portion 3 b of the semiconductor layer 3 having the protrusion 3 c. Figure 5E 1 shows a state where the p-type electrode 14 is stacked on the protrusion 3 c and the insulating film 15 . Fig. 5F The state where the electrode pad 16 is stacked on the p-type electrode 14 is shown. Figure 5G shows a state where the deposition inhibiting mask 2 is removed, Figure 5H The semiconductor laser element separated from the base substrate 1 is shown in a state where the front and back surfaces are reversed. Fig.5I 1 shows a state where an n-type electrode 12 is formed on the first surface 31 of the semiconductor layer 3. Figure 5J Indicates the state of a pair of resonator faces after end-face coating, Figure 5K FIG. 1 shows a state where the semiconductor laser element is bonded to the mounting substrate 17 via the n-type electrode 12 . Figure 6 is from Figure 5H The enlarged photograph of the semiconductor layer 3 viewed from above. In addition, the same reference numerals are added to the parts corresponding to the aforementioned embodiments, and the repeated description is omitted.

[0089] The semiconductor laser element as the semiconductor element of the present embodiment is in the shape of a substantially rectangular parallelepiped with a length of 50 to 1300 μm, a width of 30 to 250 μm, and a height of 5 to 150 μm, and is configured so as to Figure 5K The two resonator surfaces are formed to face each other in the longitudinal direction perpendicular to the paper surface, and laser light is emitted from one of the resonator surfaces.

[0090] The base substrate 1 is composed of n-type gallium nitride (GaN), for example, a transparent substrate in which the normal lines of the first base surface 1a and the second base surface 1b have an angle relative to the c-axis or the c-axis, and the thickness is about 40 to 600 μm. The base substrate 1 can be formed of a GaN wafer with a diameter of about 2 inches. The base substrate 11 is doped with an n-type dopant such as Si and can have conductivity.

[0091] On the first base surface 1a of the base substrate 1, as Figure 5A As shown, a deposition inhibiting mask 2 having a plurality of grooves 2a in a stripe shape is stacked, and a nitride semiconductor is epitaxially grown on the deposition inhibiting mask 2. Figure 5BThe semiconductor layer 3 is stacked as shown. As a deposition inhibiting mask 2, for example, a SiO2 layer with a thickness of about 100 to 1000 nm is formed. To form the SiO2 layer, first, on the first base surface 1a, silicon oxide (SiO2) of about 100 to 1000 nm, which is the material of the deposition inhibiting mask 2, is stacked by a PCVD (Plasma Chemical Vapor Deposition) method or the like. Then, excess SiO2 layer portions are removed by photolithography and HF (hydrofluoric acid) wet etching, or dry etching using a fluorine-based gas such as CF4. In this way, a SiO2 layer of a predetermined pattern can be formed as a deposition inhibiting mask 2. From the band-shaped groove 2a of the deposition inhibiting mask 2, the first base surface 1a is partially exposed, and a region E serving as a starting point for semiconductor crystal growth is exposed.

[0092] Semiconductor layer 3, such as Figure 5C As shown in FIG. 1 , a protrusion 3c is provided on the opposite side of the base substrate 1. In the plane portion 3b other than the upper surface of the protrusion 3c of the semiconductor layer 3, as shown in FIG. Figure 5D As shown, an insulating film 15 is provided. In addition, a p-type electrode 14 is provided on the semiconductor layer 3 as a second electrode. In this example, an insulating film 15 is provided on the semiconductor layer 3 other than the protrusion 3c, and at this position, the p-type electrode 14 is provided on the semiconductor layer 3 via the insulating film 15. In this way, the semiconductor layer 3 and the p-type electrode 14 do not need to be fully electrically connected, and the portion other than the protrusion 3c under the p-type electrode 14 may be covered by the insulating film 15 as in the present embodiment.

[0093] In addition, the semiconductor layer 3, such as Figure 5C As shown, a band-shaped protrusion 9 is provided in a region facing the base substrate 1. On the first surface 31 of the semiconductor layer 3, as shown in FIG. Figure 5J As shown in FIG. 1 , an n-type electrode 12 is provided as a first electrode. In this example, the n-type electrode 12 is provided on the first surface 31 of the semiconductor layer 3 including the protrusion 9 .

[0094] The semiconductor layer 3 has a thickness of about 2 to 5 μm and is formed into a thin film stacked structure of nitride semiconductors. For example, the semiconductor layer 3 is composed of a first n-type nitride semiconductor layer, a second n-type nitride semiconductor layer, an active layer, a first p-type nitride semiconductor layer, a second p-type nitride semiconductor layer, a third p-type nitride semiconductor layer, and a fourth p-type nitride semiconductor layer stacked in order on the first base surface 1a of the base substrate 1. These semiconductor layers 3 can be represented by a composition formula of In x Al y Ga 1－x－ yN (0≤x≤1-1≤y≤1-1≤x+y≤1), mixed crystals of indium nitride (InN), aluminum nitride (AlN), and gallium nitride (GaN) are the main components. In addition, as n-type impurities contained in the semiconductor layer 3, silicon (Si), germanium (Ge), tin (Sn), sulfur (S), oxygen (O), titanium (Ti), zinc (Zr), cadmium (Cd), etc. can be used. In addition, as p-type impurities, magnesium (Mg), zinc (Zn), beryllium (Be), manganese (Mn), calcium (Ca), strontium (Sr), etc. can be used. The active layer can be, for example, a multi-quantum well structure in which barrier layers and well layers are repeatedly stacked by changing the composition ratio of In and Ga of InGaN. Impurities may be added to the active layer or not.

[0095] The 3rd p-type nitride semiconductor layer and the 4th p-type nitride semiconductor layer are formed by etching to form a protrusion 3c in the form of a belt. The width of the protrusion 3c is about 2 to 20 μm, and the height is about -1.3 to 0.6 μm. The protrusion 3c exists in the entire range from one resonator surface to another resonator surface of the semiconductor layer 3 in the length direction. The two end surfaces of the protrusion 3c in the longitudinal direction are respectively included in the resonator surface of the semiconductor laser element. On each resonator surface, aluminum oxynitride (AlO x N y (0≤x≤1-1≤y≤1.5)), thin films of silicon dioxide (SiO2), tantalum pentoxide (Ta2O5), etc. form a reflective layer.

[0096] Thus, the semiconductor layer 3 of the semiconductor laser element is a stacked body formed by stacking a plurality of semiconductor layers, and is a semiconductor layer 3 as a stacked body having a convex portion 9 (second region W2) protruding compared to the first region W1, and having an n-type electrode 12 located on the first region W1 and the second region W2. The first region W1 has a rough surface region a having a surface roughness greater than that of other regions b in the contact region with the n-type electrode 12. In addition, the surface roughness can be measured, for example, by an atomic force microscope (AFM). In this example, the other region b is located between the rough surface region a and the convex portion 9.

[0097] The other region b extends in a strip shape along the convex portion 9 near the convex portion 9, and the rough surface region a extends in a strip shape along the other region b. Such a rough surface region a can adjust the surface roughness of a portion (rough surface region a) of the first region W1 of the semiconductor layer 3 located on the surface of the deposition inhibiting mask 2 by making the surface of at least a portion of the deposition inhibiting mask 2 disposed on the base substrate 1 rough. By making the surface roughness of a portion of the first region W1 large, the connection with the electrode 12 can be maintained well.

[0098] In addition, since the surface roughness of a part of the first region W1 is large, a crystal plane having a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation can be located on the first region W1. That is, the surface of the first region W1 can have a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation. In this case, the rough surface region a may also have a crystal plane such as the A plane (11-20) and the R plane (1-102).

[0099] Furthermore, in the contact region between the first electrode 12 and the first region W1, the area of ​​the crystal plane including the (000-1) crystal plane orientation or the (1-100) crystal plane orientation may be smaller than the area of ​​the crystal plane including the crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0100] In the direction perpendicular to the longitudinal direction of the protrusion 9 (side by side direction), when the total width of the first region W1 is set to B0, the width of other regions b is set to B1, and the width of the rough surface region a is set to B2, the width B1 of other regions b is greater than 10% and less than 80% of the total width B0, and the width B2 of the rough surface region a is greater than 20% and less than 90% of the total width B0.

[0101] In this example, the semiconductor layer 3 as a stacked body is composed of a GaN-based semiconductor, and the other regions a and the rough surface region b of the first region W1 are the three crystal planes 10a, 10b, and 10c of the first surface 31 located in the <11-20> direction ( Figure 5C There are two nitrogen polarity surfaces (hereinafter also referred to as “N surfaces”) in the left and right directions.

[0102] The surface roughness of the other region b is not less than 0.05 nm and less than 1 nm, and the surface roughness of the rough surface region a is not less than 1 nm and less than 1000 nm.

[0103] Projection 9, such as Figure 7 As shown, there is a first convex region 9a located on the semiconductor layer 3 side, and a second convex region 9b located on the base substrate 1 side (the front end side of the convex portion 9) relative to the first convex region 9a. The impurity concentration of the second convex region 9b is lower than the impurity concentration of the first convex region 9a. The first convex region 9a can also be located on the front end side of the convex portion 9 relative to the second convex region 9b. This first convex region 9a and the second convex region 9b constitute a connecting portion in a connected state. Such a convex portion 9 can be formed by separating the semiconductor layer 3 together with a part of the base substrate 1 from the base substrate 1.

[0104] The dislocation density of the second convex region 9b may be smaller than the dislocation density of the first convex region 9a. The convex portion 9 is formed by crystal growth of a nitride semiconductor on the exposed surface E of the first base surface 1a of the base substrate 1, and the first convex region 9a and the second convex region 9b are connected. In this case, the dislocation density of the first convex region 9a is, for example, 1×10 4 Above and 1×10 7 Hereinafter, the dislocation density of the second convex region 9b is, for example, 1×10 3 Above and 5×10 6 Below. In addition, the dislocation defects in the connection portion may be more than the dislocation defects in the second convex region 9b. In addition, the dislocation defects in the connection portion may be more than the dislocation defects in the first convex region 9a. The dislocation density can be adjusted by changing the growth conditions during the growth of the semiconductor layer 3. That is, the dislocation density may also be greater than the regions located above and below the connection portion.

[0105] The density of dislocations, which are crystal defects in such a semiconductor crystal, can be adjusted by appropriately controlling the growth conditions of the semiconductor layer 3 .

[0106] The length of the first convex region 9a in the protruding direction of the convex portion 9 may be greater than the length of the second convex region 9b in the protruding direction of the convex portion 9. In addition, the surface area of ​​the first convex region 9a may be greater than the surface area of ​​the second convex region 9b.

[0107] In the first region W1, the entire surface may be a rough surface, or only a part of the surface may be a rough surface. In addition, when only a part of the surface is a rough surface, the rough surface region a may be located near the convex portion 9. That is, in the parallel direction, the area of ​​the region between the outer edge of the rough surface region a and the convex portion 9 may be smaller than the area of ​​the region between the outer edge of the other side of the rough surface region a and the outer edge of the semiconductor layer 3.

[0108] A plurality of rough surface regions a may be provided on both sides of the convex portion 9. In this example, the convex portion 9 is located between two rough surface regions a. In this case, the n-type electrode 12 may cover only one of the rough surface regions a on both sides of the convex portion 9.

[0109] In the aforementioned embodiment, the semiconductor layer 3 is described as having a band-shaped protrusion 9, but in other embodiments, the first surface 31 may be provided with a band-shaped recess 9' (second region W2) that is recessed compared to the flat first region W1, in place of the protrusion 9. In such a structure, since at least one of the first region W1 or the second region W2 has a crystal plane with a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation, a crystal plane having a high ohmic contact with a conductor layer such as an electrode can also appear, thereby improving the interlayer bonding reliability. In addition, by adjusting the direction in which stress occurs when the semiconductor layer 3 is peeled off, it is possible to Figure 7 As shown by the virtual line, the recess 9' is formed in this way so that the crystal plane 10a is revealed.

[0110] The semiconductor element S of this embodiment has a first surface 31 with a (000-1) crystal plane orientation of a GaN-based semiconductor, which is opposed to a planar first base surface 1a as one of the main surfaces of a base substrate 1. The first surface 31 has a planar first region W1 and a second region W2 that is recessed compared to the first region W1. Therefore, the first surface 31 has a plurality of crystal planes (second region W2) having a crystal plane orientation different from the (000-1) plane, and a <11-20> direction ( Figure 1 Two nitrogen polarity planes (hereinafter also referred to as "N planes") 10d and 10e (first region W1) are exposed in the left and right directions. In addition, a plurality of crystal planes are crystal planes other than the nitrogen polarity planes 10d and 10e, such as the M plane (1-100), the A plane (11-20), and the R plane (1-102).

[0111] The present invention can be implemented in the following aspects (1) to (32).

[0112] (1) A semiconductor device comprising gallium nitride, wherein:

[0113] A semiconductor layer having a first surface, wherein the first surface includes a first region and a second region which is a belt-shaped convex portion protruding from the first region or a concave portion concave.

[0114] In the first surface, at least one of the surfaces of the first region or the second region has a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0115] (2) A semiconductor element, wherein the semiconductor layer further has a second surface facing the first surface,

[0116] In the first surface, at least one of the surfaces of the first region or the second region has a crystal plane having a crystal plane orientation different from a crystal plane orientation opposite to a crystal plane orientation of the second surface.

[0117] (3) A semiconductor element, wherein the projection has three or more crystal planes having mutually different crystal plane orientations.

[0118] (4) A semiconductor element, wherein one of the three or more crystal planes of the convex portion is a crystal plane including a (000-1) crystal plane orientation and a (1-100) crystal plane orientation.

[0119] (5) A semiconductor element, wherein a surface of the first region has a crystal plane having a crystal plane orientation different from that of a surface of the second region.

[0120] (6) A semiconductor element, wherein a surface of the first region has a crystal plane having the same crystal plane orientation as that of a surface of the second region.

[0121] (7) A semiconductor element further comprising a first electrode disposed in the first region and the second region of the first surface.

[0122] (8) A semiconductor element, wherein the first electrode is an n-type electrode.

[0123] (9) A semiconductor element, wherein the semiconductor layer further has a second surface opposite to the first surface,

[0124] It also includes a second electrode disposed on the second surface.

[0125] (10) A semiconductor device, wherein a surface of the first region has a (000-1) crystal plane orientation.

[0126] (11) A semiconductor device, wherein a surface of the second region has a (000-1) crystal plane orientation.

[0127] (12) A semiconductor element, wherein the first surface includes the second region and a plurality of second regions sandwiching the two regions.

[0128] (13) A semiconductor element, wherein surfaces of the plurality of second regions have crystal planes including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0129] (14) A semiconductor device, wherein a surface of the first region has a crystal plane including a crystal plane orientation different from a (000-1) crystal plane orientation and a (1-100) crystal plane orientation.

[0130] (15) A semiconductor element, wherein a contact area between the first electrode and the first region is larger than a contact area between the first electrode and the second region.

[0131] (16) In the contact region between the first electrode and the first region, the area of ​​a crystal plane including a (000-1) crystal plane orientation or a (1-100) crystal plane orientation is smaller than the area of ​​a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0132] (17) In the contact region between the first electrode and the second region, the area of ​​a crystal plane including a (000-1) crystal plane orientation or a (1-100) crystal plane orientation is smaller than the area of ​​a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0133] (18) A semiconductor element, wherein the recess has a plurality of crystal planes having mutually different crystal plane orientations.

[0134] (19) A semiconductor element, wherein one of the plurality of crystal planes of the recessed portion is a crystal plane including a (000-1) crystal plane orientation and a (1-100) crystal plane orientation.

[0135] (20) A method for manufacturing a semiconductor element, wherein when the semiconductor layer is peeled off from the substrate, the semiconductor layer is peeled off together with a portion of the substrate connected to the semiconductor layer.

[0136] (21) A method for manufacturing a semiconductor element, wherein when the semiconductor layer is peeled off from the substrate, the semiconductor layer is peeled off in such a manner that a part of the semiconductor layer remains on the substrate.

[0137] (22) A method for manufacturing a semiconductor element, comprising, before forming the semiconductor layer, a step of forming a mask on the first surface of the substrate while exposing a region serving as a growth starting point of the semiconductor layer,

[0138] The semiconductor layer grows from the region along the surface of the mask.

[0139] (23) A method for manufacturing a semiconductor element, wherein a surface of the mask on which the semiconductor layer is grown has irregularities.

[0140] (24) A semiconductor device comprising gallium nitride, wherein:

[0141] A semiconductor layer epitaxially grown with a substrate as a starting point, the semiconductor layer having a first surface including a first region and a second region adjacent to the first region,

[0142] The second region is a peeling surface formed when the substrate is separated.

[0143] The peeled surface has a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

[0144] (25) A semiconductor element, wherein the convex portion includes a first convex region and a second convex region having an impurity concentration lower than that of the first convex region.

[0145] (26) A semiconductor element, wherein the first convex region is located at a front end relative to the second convex region.

[0146] (27) A semiconductor element, wherein the convex portion includes a first convex region and a second convex region having a lower dislocation density than the first convex region.

[0147] (28) A semiconductor element, wherein the convex portion has a connection portion formed by connecting the first convex region and the second convex region,

[0148] The connection portion has a higher dislocation density than the first convex region.

[0149] (29) A semiconductor element, wherein the convex portion has a connection portion formed by connecting the first convex region and the second convex region,

[0150] The convex portion includes a first convex region and a second convex region having a lower dislocation density than the first convex region.

[0151] (30) A semiconductor element, wherein the convex portion has a connection portion formed by connecting the first convex region and the second convex region,

[0152] The connection portion has a higher dislocation density than the first convex region.

[0153] (31) A semiconductor element, wherein the convex portion 7 has a connection portion formed by connecting the first convex region and the second convex region,

[0154] The connection portion has a larger dislocation density than the second convex region.

[0155] (32) A semiconductor element, wherein the first convex region is wider than the second convex region.

[0156] According to the semiconductor element of the present invention, since the semiconductor element has the planar portions 10a to 10e with high ohmic contact, it is possible to obtain high bonding reliability without performing a treatment process for improving the ohmic contact between the semiconductor layer 3 and the insulating film 15 and between the semiconductor layer 3 and the n-type electrode 12, and the semiconductor element can be realized as a semiconductor laser element, for example. Thus, the productivity of the semiconductor element can be improved, and a semiconductor element with excellent mass productivity can be provided.

[0157] According to the method for manufacturing a semiconductor element of the present invention, a semiconductor element having a surface with high ohmic contact can be realized without increasing the number of steps, thereby facilitating mass production of semiconductor elements with high bonding reliability.

[0158] The present invention has been described in detail above, but the present invention can be implemented in various other ways without departing from its spirit or main features. Therefore, the various aspects of the aforementioned embodiments are merely illustrative, and the scope of the present invention is shown in the scope of the claims and is not subject to any restrictions in the specification. In addition, all modifications and changes within the scope of the claims are within the scope of the present invention.

[0159] Explanation of symbols

[0160] 1 Basic substrate

[0161] 1a First basic surface

[0162] 1b Second basic surface

[0163] 1d Edge

[0164] 2 Deposition Inhibit Mask

[0165] 3 Semiconductor layer

[0166] 3a Remains of the semiconductor layer

[0167] 3b Flat surface

[0168] 3c Elevation

[0169] 4. Protective layer

[0170] 5 Adhesive layer

[0171] 6 Support substrate

[0172] 9 Connection

[0173] 9a The first convex area

[0174] 9b Second convex area

[0175] 10a, 10b, 10c Multiple crystal planes

[0176] 12 n-type electrode

[0177] 14 p-type electrode

[0178] 15 Insulation layer

[0179] 16 Mounting substrate

[0180] 31 Page 1

[0181] 32 Page 2

[0182] E Show face

[0183] S Semiconductor components

Claims

1. A semiconductor device comprising gallium nitride, wherein: A semiconductor layer having a first surface, the semiconductor layer having gallium nitride, the first surface including a first region and a second region which is a band-shaped convex portion protruding from the first region or a band-shaped concave portion recessed from the first region, In the first surface, at least one of the surfaces of the first region or the second region has a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation. The semiconductor layer further has a second surface opposite to the first surface, The second surface has a protrusion.

2. The semiconductor element according to claim 1, wherein In the first surface, at least one of the surfaces of the first region or the second region has a crystal plane having a crystal plane orientation different from a crystal plane orientation opposite to a crystal plane orientation of the second surface.

3. The semiconductor element according to claim 1, wherein The protrusion has three or more crystal planes having mutually different crystal plane orientations.

4. The semiconductor element according to claim 2, wherein: The protrusion has three or more crystal planes having mutually different crystal plane orientations.

5. The semiconductor element according to claim 3 or 4, wherein: One of the three or more crystal planes of the convex portion is a crystal plane including a (000-1) crystal plane orientation and a (1-100) crystal plane orientation.

6. The semiconductor device according to any one of claims 1 to 4, wherein The surface of the first region has a crystal plane having a crystal plane orientation different from that of the surface of the second region.

7. The semiconductor device according to any one of claims 1 to 4, wherein The surface of the first region has a crystal plane having the same crystal plane orientation as that of the surface of the second region.

8. The semiconductor device according to any one of claims 1 to 4, wherein The invention further includes a first electrode disposed in the first region and the second region of the first surface.

9. The semiconductor element according to claim 8, wherein The first electrode is an n-type electrode.

10. The semiconductor device according to any one of claims 1 to 4, wherein The device further includes a second electrode disposed on the second surface.

11. The semiconductor device according to any one of claims 1 to 4, wherein The surface of the first region has a (000-1) crystal plane orientation.

12. The semiconductor device according to any one of claims 1 to 4, wherein The surface of the second region has a (000-1) crystal plane orientation.

13. The semiconductor device according to any one of claims 1 to 4, wherein The first surface includes the second region and a plurality of first regions sandwiching the second region.

14. The semiconductor device according to any one of claims 1 to 4, wherein The surfaces of the plurality of first regions have a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

15. The semiconductor device according to any one of claims 1 to 4, wherein The surface of the first region has a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

16. The semiconductor device according to claim 8, wherein A contact area between the first electrode and the first region is larger than a contact area between the first electrode and the second region.

17. The semiconductor device according to claim 8, wherein In the contact region between the first electrode and the first region, an area of ​​a crystal plane including a (000-1) crystal plane orientation or a (1-100) crystal plane orientation is smaller than an area of ​​a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

18. The semiconductor device according to claim 8, wherein In the contact region between the first electrode and the second region, an area of ​​a crystal plane including a (000-1) crystal plane orientation or a (1-100) crystal plane orientation is smaller than an area of ​​a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

19. The semiconductor device according to claim 18, wherein The recessed portion has a plurality of crystal planes having crystal plane orientations that are different in phase from each other.

20. The semiconductor device according to claim 19, wherein One of the plurality of crystal planes of the recessed portion is a crystal plane including a (000-1) crystal plane orientation and a (1-100) crystal plane orientation.

21. The semiconductor device according to any one of claims 1 to 4, wherein The first region further has a rough surface region.

22. A method for manufacturing a semiconductor element, wherein: have: A process for preparing a substrate; forming a semiconductor layer having gallium nitride on the first surface of the substrate, wherein the semiconductor layer has a band-shaped convex portion or a band-shaped concave portion; a step of peeling the semiconductor layer from the substrate, When the semiconductor layer is peeled off from the substrate, the peeling is performed so that the peeling surface becomes a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation. Before forming the semiconductor layer, a step of forming a mask on the first surface of the substrate while exposing a region serving as a growth starting point of the semiconductor layer, is further included. The semiconductor layer grows from the region along the surface of the mask.

23. The method for manufacturing a semiconductor element according to claim 22, wherein: When the semiconductor layer is peeled off from the substrate, the semiconductor layer is peeled off together with a portion of the substrate connected to the semiconductor layer.

24. The method for manufacturing a semiconductor element according to claim 23, wherein: When the semiconductor layer is peeled off from the substrate, the semiconductor layer is peeled off in a manner that a part of the semiconductor layer remains on the substrate.

25. The method for manufacturing a semiconductor device according to claim 22, wherein: The surface of the mask on which the semiconductor layer is grown has irregularities.

26. A semiconductor device comprising gallium nitride, wherein: A semiconductor layer having gallium nitride epitaxially grown from a substrate, the semiconductor layer having a first surface including a first region and a second region adjacent to the first region, wherein the second region has a band-shaped convex portion protruding from the first region or a band-shaped concave portion recessed from the first region, The second region is a peeling surface formed when the substrate is separated. The peeled surface has a crystal plane including a crystal plane orientation different from the (000-1) crystal plane orientation and the (1-100) crystal plane orientation.

27. The semiconductor device according to claim 26, wherein: The convex portion includes a first convex region and a second convex region having an impurity concentration lower than that of the first convex region.

28. The semiconductor device according to claim 27, wherein: The first convex region is located at a front end relative to the second convex region.

29. The semiconductor device according to claim 27, wherein The convex portion includes a first convex region and a second convex region having a lower dislocation density than the first convex region.

30. The semiconductor device according to claim 27, wherein The convex portion has a connection portion formed by connecting the first convex region and the second convex region, The connection portion has a greater dislocation density than the first convex region.

31. The semiconductor device according to claim 28, wherein The convex portion has a connection portion formed by connecting the first convex region and the second convex region, The connection portion has a greater dislocation density than the second convex region.

32. The semiconductor device according to claim 27, wherein: The first convex region is wider than the second convex region.

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