Semiconductor superconductor hybrid devices

Abstract

A semiconductor superconductor hybrid device (100) comprises a semiconductor layer (10) arranged between a first insulating layer and a second insulating layer (16a, 16b) in a sandwich structure, and a superconductor layer (12) arranged on an edge (14) of the semiconductor layer to achieve energy level hybridization between the semiconductor and the superconductor. Preferably, it also comprises a gate electrode (20) for electrostatic control of energy level hybridization. The device may be very useful in quantum computers. A method for manufacturing the device and a method for inducing topological behavior in the device are also provided.

Description

Background Art

[0001] Topological quantum computing is based on the phenomenon that non-Abelian anyons can be formed in the region where a semiconductor is coupled to a superconductor in the form of "Majorana zero modes" (MZMs). A non-Abelian anyon is a quasiparticle, meaning that it is not a particle itself, but an excitation in an electron liquid that behaves at least partially like a particle. MZMs are specific bound states of such quasiparticles. Under certain conditions, these states can form near the semiconductor-superconductor interface in nanowires, which are formed by a section of semiconductor coated with a superconductor. When an MZM is induced in a nanowire, it can be said to be in a "topological regime". In order to induce this situation, a magnetic field, usually applied from the outside, is required, and the nanowire also needs to be cooled to a temperature that induces superconducting behavior in the superconducting material. This may also involve controlling a portion of the nanowire with an electrostatic potential.

[0002] By forming a network of such nanowires and inducing topological states in parts of the network, it is possible to create quantum bits (qubits) that can be manipulated for quantum computing. A quantum bit, or qubit, is an element on which a measurement with two possible outcomes can be performed, but which at any given time (when not being measured) can actually be in a quantum superposition of two states corresponding to different outcomes.

[0003] To induce an MZM, the device is cooled to a temperature at which a superconductor (e.g., aluminum Al) exhibits superconducting behavior. The superconductor induces a proximity effect in an adjacent semiconductor, whereby the semiconductor region near the interface with the superconductor also exhibits superconducting properties. That is, topological phase behavior is induced in the adjacent semiconductor as well as the superconductor. It is in this region of the semiconductor that an MZM is formed.

[0004] Another condition for inducing a topological phase in which an MZM can be formed is the application of a magnetic field to promote spin degeneracy in the semiconductor. Degeneracy in a quantum system refers to a situation where different quantum states have the same energy level. Promoting degeneracy means causing these states to adopt different energy levels. Spin degeneracy refers to a situation where different spin states have the same energy level. Spin degeneracy can be promoted by a magnetic field, resulting in energy level spillover between electrons of different spin polarizations. This is called the Zeeman effect. The g factor refers to the coefficient between the applied magnetic field and the spin splitting. Typically, the magnetic field is applied by an external electromagnet. However, US16 / 246287 also discloses a heterostructure in which a ferromagnetic insulator layer is provided between the superconductor and the semiconductor so that a magnetic field can be applied internally to promote spin degeneracy without the need for an external magnet. Examples of ferromagnetic insulators given include EuS, GdN, Y3Fe5O 12 、Bi3Fe5O 12, heavy element compounds in the form of europium, gadolinium, yttrium, iron, strontium and rhenium.

[0005] Inducing MZMs also typically requires gating the nanowire with an electrostatic potential. However, US16 / 120433 also discloses a structure that can exhibit topological behaviors including MZMs without gating. In this case, the nanowire has a complete superconductor shell around the perimeter of the nanowire, which eliminates the need for gating.

[0006] like Figure 8 As shown, in order to create a high-quality MZM device with a long lifetime, it is preferred to have a large topological gap E g , for example. A material in a topological phase (whether a superconductor or a proximity-induced superconducting region in a semiconductor) exhibits different energy bands: a lower band 811 and an upper band 812. The lower band 811 is the band where the quasiparticle energy E drops to a lower range, and the upper band (or "excitation band") 812 is the band where the quasiparticle energy is higher. The topological gap E g It is the energy window between the lower energy band 811 and the upper energy band 812. Due to the quantized (discrete) nature of the quasiparticle energy levels, there are no quasiparticles in this window. g Analogous to the valence band, conduction band, and band gap of electrons in semiconductors. In the upper excitation band 812, quasiparticles can freely propagate through the superconductor (or proximity induction region in semiconductors), similar to electrons in the valence band of semiconductors.

[0007] The Majoranas, whose states form the MZM, form the lower band 811. The Majoranas are part of the computational space, i.e., properties of the system that are used for the quantum computing application in question. In other words, the MZM is the operating element of the qubit. On the other hand, the particle-like excitations (quasiparticles) in the upper band 812 are not part of the computational space. If these quasiparticles cross the topological energy gap E due to thermal fluctuations, g If they enter the lower band 811, they will destroy at least some of the MZMs. This is sometimes referred to as "poisoning" the MZMs. g The MZM is protected from such poisoning. The quasiparticles exist in the upper band and cross the gap E from the upper band. g The probability of reaching the lower energy band is , where T is the temperature and k is the Boltzmann constant. Therefore, the larger the topological gap, the more protection the MZM is provided from being poisoned by harmful quasiparticles in the upper band 812.

[0008] Stanescu et al. (Physical Review B 84, 144522 (2011)) and Winkler et al. (Physical Review B 99, 245408 (2019)) provide a more detailed treatment of the theory of operation of semiconductor superconductor hybrid devices. The contents of these documents are incorporated herein by reference. Summary of the invention

[0009] It is desirable to provide a semiconductor superconductor hybrid device with a larger topological gap, more specifically a topological gap as close to the theoretical limit as possible. It is also desirable to provide a semiconductor superconductor hybrid device with improved tolerance to manufacturing variations.

[0010] A semiconductor superconductor hybrid device includes a semiconductor layer and a superconductor layer. The superconductor layer is arranged on the edge of the semiconductor layer to achieve energy level hybridization between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged between a first insulating layer and a second insulating layer in a sandwich structure, and each insulating layer is in contact with the opposite surface of the corresponding semiconductor layer. This configuration can allow good control of the geometry of the semiconductor layer and can improve the tolerance of manufacturing variations. The device may be very useful in quantum computers. A method for manufacturing the device and a method for inducing topological behavior in the device are also provided.

[0011] This Summary is provided to introduce a selection of concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is also not limited to implementations that solve any or all disadvantages noted herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To assist in understanding the embodiments of the present disclosure and to show how these embodiments may be implemented, reference is made, by way of example only, to the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view of an example of a semiconductor superconductor hybrid device;

[0014] Figure 2 is a cross-sectional view of another example of a semiconductor superconductor hybrid device;

[0015] Figure 3 is a graph showing the calculated variation of the topological gap in μeV as a function of the semiconductor layer thickness d for a device with a band offset (energy level difference) between the conduction band of the semiconductor and the conduction band of the insulating layer of 50 meV and an α value (a measure of the strength of spin-orbit coupling, see Stanescu et al. and Winkler et al.) of 0.1 eVnm;

[0016] Figure 4 is a graph showing the calculated number of occupied energy levels at the semiconductor superconductor interface as a function of the applied gate voltage V_gate for devices with different semiconductor layer thicknesses d;

[0017] Figure 5 (a) to (c) are a set of heat maps showing the topological gap as a function of band offset and α value for devices with semiconductor layer thicknesses of 10 nm, 25 nm, and 40 nm, respectively;

[0018] Figure 6 is a flow chart of a method for manufacturing a semiconductor superconductor hybrid device;

[0019] Figure 7 is a flow chart of a method for using a semiconductor superconductor hybrid device; and

[0020] Figure 8 is a diagram illustrating the concept of a topological gap.

[0021] Figure 1 and Figure 2 are schematic and not to scale. For ease of representation, the relative proportions of the components shown in these figures may be exaggerated. DETAILED DESCRIPTION

[0022] As used herein, the verb "to comprise" is used as shorthand for "to include or to consist of." In other words, while the verb "to comprise" is intended to be an open term, replacement of the term with the closed term "to consist of" is expressly contemplated, particularly when used in conjunction with chemical components.

[0023] Directional terms such as "top", "bottom", "left", "right", "above", "below", "horizontal" and "vertical" are used herein for convenience of description and are not intended to be construed in conjunction with the present invention. Figure 1 and Figure 2 For the avoidance of any doubt, the term is not intended to limit the orientation of the device in an external reference frame.

[0024] As used herein, the term "superconductor" refers to a material that can be cooled to below its critical temperature T c A material that becomes superconducting at a temperature of 10000 ℃. The use of this term is not intended to limit the temperature of the device.

[0025] "Nanowires" as referred to herein are elongated members having a nanometer-scale width and an aspect ratio of at least 100, or at least 500, or at least 1000. The width of the nanowire is in the range of 10 nm to 500 nm, alternatively 50 nm to 100 nm or 75 nm to 125 nm. The length is typically in the order of micrometers, for example at least 1 μm, or at least 10 μm. In this context, the nanowire is typically formed of a semiconductor material.

[0026] In the context of the present disclosure, the term "coupling" refers in particular to the hybridization of energy levels.

[0027] The contents of all documents cited herein are incorporated by reference in their entirety.

[0028] Now refer to Figure 1 A first example of the semiconductor superconductor hybrid device 100 will be described.

[0029] The semiconductor superconductor device 100 includes a semiconductor layer 10 and a superconductor layer 12. The semiconductor layer has an edge 14 and two opposite faces. In this example, the edge 14 of the semiconductor layer 10 is in direct contact with the superconductor layer 12. At least when the device is in use, there is energy level hybridization between the semiconductor layer 10 and the superconductor layer 12 in the region near the edge 14.

[0030] The semiconductor layer 10 in this example is a material layer having the following general formula:

[0031] InAs x Sb 1-x (Formula 1)

[0032] Where x is in the range of 0 to 1. In other words, the semiconductor layer 10 may include indium antimonide (x=0), indium arsenide alone (x=1), or 50% indium (on a molar basis) and a variable ratio of a ternary mixture of arsenic and antimony (0 <x<1)。

[0033] It has been found that indium arsenide InAs has good processing properties during device manufacturing and provides good performance for the device. Indium antimonide (InSb) also improves device performance, but may be more difficult to use during manufacturing. The properties of the ternary mixture are between the properties of the binary compounds InAs and InSb. When x is in the range of 0 to 0.7 or 0.01 to 0.7, an improvement in device performance compared to InAs can be observed. A particularly good balance of device performance and processing performance can be provided in the range of x from 0.35 to 0.45. This example uses indium antimonide as the semiconductor layer 10.

[0034] The thickness d of the semiconductor layer 10 is in the range of 5 nm to 50 nm. When a semiconductor layer with a thickness in this range is used, an increase in the topological gap is observed. Without wishing to be bound by theory, the inventors believe that changing the thickness d can change the number of occupied energy levels ("subbands") and the degree of hybridization between the semiconductor layer 10 and the superconductor layer 12.

[0035] In this example, the superconductor layer 12 is an aluminum layer. Winkler et al. (cited above) report that aluminum has strong coupling to InAs and InSb, and that the strength of the coupling can vary depending on the thickness of the superconductor layer. For example, the thickness can be in the range of 4 nm to 10 nm.

[0036] The semiconductor superconductor hybrid device 100 further includes a first insulating layer 16a and a second insulating layer 16b. The first insulating layer 16a and the second insulating layer 16b are arranged to sandwich the semiconductor layer 10. The first insulating layer 16a extends from a substrate 18 on which the device is arranged. In this example, the first insulating layer 16a is formed integrally with the substrate 18. The second insulating layer 16b is arranged as a cap covering the semiconductor layer 10. The first insulating layer 16a, the second insulating layer 16b and the semiconductor layer 10 are referred to as a sandwich structure herein.

[0037] The first insulating layer 16a separates the semiconductor layer 10 from the substrate 18 and from the bottom corners 26a, 26b between the device and the substrate 18. The second insulating layer 16b separates the semiconductor layer from the top surface and corners of the device.

[0038] In this example, the first insulating layer and the second insulating layer are formed of indium phosphide. Indium phosphide is a semiconductor material, but its semiconductor properties are not used in the context of the present device. Instead, indium phosphide is used as an insulator. Indium phosphide has a high band gap. The energy difference between the conduction band of the semiconductor layer 10 and the conduction band of indium phosphide is large. When the device is in use, electrons are trapped in the semiconductor layer 10 and do not escape into the insulating layers 16a, 16b.

[0039] Other exemplary materials that can be used to form the first insulating layer and the second insulating layer are materials having the formula InAl x As 1-x A material wherein x is at least 0.1, such as wherein x is in the range of 0.1 to 0.4. Another illustrative material is InGa x As 1-x A material wherein x is at least 0.15, for example wherein x is in the range of 0.15 to 0.4.

[0040] In the present example, substrate 18 is formed of indium phosphide.

[0041] Semiconductor layer 10 and superconductor layer 12 are the active working parts of the device, and useful excitations (such as Majorana zero mode) are induced at this part during operation. The top and corner of the semiconductor device are usually difficult to manufacture reproducibly. There may be slight changes in the device structure in these areas. Similarly, the substrate surface may have small changes. It is easier to consistently manufacture devices by separating the active semiconductor layer from the difficult-to-copy area. Assuming that the thickness d and edge 14 of the device are well controlled, larger manufacturing variations in other parts of the semiconductor structure can be well tolerated.

[0042] The first insulating layer 16a and the second insulating layer 16b may also serve to capture electrons in the semiconductor layer. This may increase the lifetime of useful excitations when the device is in use.

[0043] The device 100 also includes a protective layer 22 disposed on the top and sides of the sandwich structure. This layer can protect the device from oxidation, especially during the manufacturing process. The protective layer 22 can act as an electrical insulator to prevent current from flowing from the gate electrode 20 into the device. The material forming the protective layer 22 is not particularly limited and can be any of a variety of protective materials known in the semiconductor manufacturing field. The protective layer 22 is typically an oxide, such as hafnium oxide.

[0044] In the example shown, the protective layer 22 covers only a portion of the device. In a variant, the protective layer may cover the entire device.

[0045] The gate electrode 20 is disposed on one side of the sandwich structure including the second edge of the semiconductor layer 10. The gate electrode 20 is separated from the semiconductor layer 10 by the protective layer 22. In this way, the protective layer 22 prevents or reduces current leakage from the gate electrode 20 into the semiconductor layer 10.

[0046] The gate electrode 20 may be formed of any suitable material. The gate electrode is generally not superconducting. For example, the gate electrode may be gold or a gold-titanium alloy.

[0047] Arranging the gate electrode 20 on the side and / or top of the sandwich structure (referred to herein as a "side-gate semiconductor superconductor hybrid device" or a "top-gate semiconductor superconductor hybrid device," respectively) can make the device easier to manufacture compared to the case where the gate electrode is arranged below the substrate 18 ("bottom-gate semiconductor superconductor hybrid device").

[0048] exist Figure 1 In the example shown, the gate electrode 20 is depicted as being above the sandwich structure. However, the gate electrode 20 may be separated from the sandwich structure by an air gap. If an air gap is present, the air gap may help prevent current from flowing from the gate electrode to the semiconductor and superconductor components.

[0049] The gate electrode 20 is used to apply an electrostatic field to the semiconductor layer 10. Providing such gating allows the degree of energy level hybridization between the semiconductor and the superconductor to be controlled. This may be useful for inducing excitation in the device. The configuration of the gate electrode is not particularly limited as long as the gate electrode is capable of gating the device.

[0050] Figure 1 A mask layer 24 is further shown disposed on the substrate 18. The present device may be manufactured using selective area growth. Such a method may involve the use of a mask during device fabrication. The mask may remain in the finished device.

[0051] Now we will discuss the difference between this example and the first example. Figure 2 A second example of the semiconductor superconductor hybrid device 200 will be described.

[0052] The second example differs from the first example in that the second example is a bottom-gate semiconductor superconductor hybrid device. In this arrangement, the gate electrode 220 is arranged below the substrate 18 and the first insulating layer 16a. The substrate 18 and the first insulating layer 16a provide electrical insulation between the gate electrode 220 and the semiconductor layer 10. In the second example, the protective layer 22 present in the first example is omitted, although in a variant, a protective layer may be provided over all or part of the top surface of the device.

[0053] Figure 2 The device further comprises a ferromagnetic insulator layer 210 disposed between the semiconductor layers. The ferromagnetic insulator layer may be as described in US 16 / 246287, the contents of which are incorporated herein by reference. The ferromagnetic insulator layer may be selected from EuS, GdN, Y3Fe5O 12 、Bi3Fe5O 12 The ferromagnetic insulator layer is configured to apply a magnetic field to the semiconductor and the superconductor.

[0054] Figures 3 to 5 The effect of varying the thickness d of the semiconductor component of the devices provided herein is shown.

[0055] Figure 3 is a graph showing the calculated topological gap in μeV as a function of semiconductor layer thickness for a conceptual example device with a band offset of 50 meV between the conduction band of the semiconductor and the conduction band of the insulating layer and an α value (a measure of the strength of spin-orbit coupling, see Stanescu et al. and Winkler et al.) of 0.1 eV nm. In this example, the maximum topological gap is achieved for a semiconductor layer thickness of 25 nm. Therefore, the topological gap can be optimized by choosing the semiconductor layer thickness.

[0056] Illustrative examples of materials for forming an insulating layer that can provide a band offset of at least 50 meV to an InAs semiconductor include materials selected from the group consisting of: (i) indium phosphide; (ii) InAl x As 1-x wherein x is at least 0.1, such as in the range of 0.1 to 0.4; and (iii) InGa x As 1-x , wherein x is at least 0.15, such as in the range of 0.15 to 0.4.

[0057] Figure 4 is a graph of the number of occupied states of a device with varying semiconductor layer thickness versus the applied gate voltage. The figure shows that the applied gate voltage controls the degree of hybridization between the semiconductor and the superconductor. It is further illustrated that the number of occupied energy states in the device varies according to the thickness of the semiconductor layer. For example, when the gate voltage V_gate is 2V, more energy states are occupied in a device with a 40nm semiconductor layer (dotted line) compared to a device with a 25nm semiconductor layer (dashed line) or a device with a 10nm semiconductor layer (solid line).

[0058] Figure 5 (a) to Figure 5 (c) is a set of heat maps showing the topological gap as a function of band offset and α value for devices with semiconductor layer thicknesses of 10 nm, 25 nm, and 40 nm. These plots show that the semiconductor layer thickness used to obtain the maximum topological gap depends on the properties of the material chosen. For a given α value, when the band offset is large (e.g., greater than 60 meV), a thinner semiconductor layer may be preferred (see Figure 5 (a)), whereas for smaller band offsets, thicker semiconductor layers may be preferred (see Figure 5 (b) and Figure 5 (c)).

[0059] Figure 6 is a flow chart outlining the steps of an illustrative method for making a semiconductor superconductor hybrid device as described herein.

[0060] The method generally includes manufacturing a sandwich structure and then forming a superconducting component. At box 601, a first insulating layer is formed. At box 602, a semiconductor layer is formed on the first insulating layer. At box 603, a second insulating layer is formed on the semiconductor layer. At box 604, a superconductor is formed on the edge of the semiconductor layer to achieve energy level hybridization between the semiconductor layer and the superconductor layer. Additional components can be formed between any one of steps 601 to 604 or in subsequent steps.

[0061] The specific techniques used to form the various components are not particularly limited and may be appropriately selected. A person skilled in the art will be aware of various suitable techniques. Examples include selective area growth; chemical vapor deposition; photolithography, etc. Techniques that result in epitaxial growth of components can achieve good contact between these components and may be preferred.

[0062] Figure 7 is a flow chart outlining an illustrative method of using a semiconductor superconductor hybrid device as provided herein.

[0063] The use of devices generally involves introducing topological behavior (i.e., a specific type of electronic excitation) into the device. This can be achieved by hybridization of energy levels between semiconductors and superconductors, thereby producing energy bands with a mixture of semiconductor and superconducting properties. In the context of the present disclosure, hybridization may also be referred to as "coupling". Such excitations may be useful in quantum computing. For example, they can be used to encode quantum bits (also known as qubits). Without wishing to be bound by theory, it is believed that the semiconductor superconductor hybrid devices provided herein generate Majorana zero modes.

[0064] In block 701, the semiconductor superconductor hybrid device is cooled to a temperature at which the superconductor layer is superconducting. In other words, the device is cooled to a temperature below the critical temperature T of the superconductor layer. c The temperature at which the layer exhibits superconducting behavior (e.g., behaves as if it has zero electrical resistance) is typically on the order of tens of Kelvin or less. c Depends on the material used and in some cases may be affected by the thickness of the material. The temperature can be selected at your discretion.

[0065] At block 702, a magnetic field is applied to the semiconductor layer. The magnetic field increases spin degeneracy in the device, thereby changing the band structure at the interface between the semiconductor and the superconductor. The magnetic field can be applied externally, for example using an electromagnet. Alternatively, in an example where the semiconductor superconductor hybrid device includes a ferromagnetic insulator layer as described above, the magnetic field can be the magnetic field of the ferromagnetic insulator layer.

[0066] In box 703, an electrostatic field is applied to the semiconductor layer. Typically, the semiconductor superconductor hybrid device includes a gate electrode, and the gate electrode is used to apply the electrostatic field. In an alternative, the electrostatic field can be applied from the outside. The electrostatic field can change the degree of energy level hybridization between the semiconductor and the superconductor. For example, when electrons are sucked away from the superconductor by the electrostatic field, the hybridization may be reduced. This may make the low-energy state, i.e., the state of interest, more susceptible to the influence of the magnetic field. This in turn can allow the formation of a topological phase at a smaller magnetic field, thereby enhancing the characteristics of quantum computing.

[0067] It should be understood that the above embodiments are described by way of example only.

[0068] More generally, according to one aspect disclosed herein, there is provided a semiconductor superconductor hybrid device, comprising: a semiconductor layer; and a superconductor layer; wherein the superconductor layer is arranged on the edge of the semiconductor layer to achieve energy level hybridization between the semiconductor layer and the superconductor layer; wherein the semiconductor layer is arranged between a first insulating layer and a second insulating layer in a sandwich structure, each insulating layer being in contact with the opposite surface of the corresponding semiconductor layer. The first insulating layer and the second insulating layer separate the semiconductor layer from the corners of the device and from the surface of any underlying substrate. This can improve the tolerance of the device to manufacturing variations because the working semiconductor portion of the device is away from the portion of the device that is more difficult to manufacture reliably. The thickness of the semiconductor layer can be precisely controlled. This can allow the number of sub-bands in the device to be controlled.

[0069] The semiconductor superconductor hybrid device may further include a gate electrode for applying an electrostatic field to the semiconductor layer. The structure of the gate electrode is not particularly limited. Examples of materials for forming the gate electrode include materials selected from gold and gold alloys (eg, gold-titanium).

[0070] The device may be a side-gate superconductor semiconductor device. For example, the gate electrode may be arranged above the second edge of the semiconductor layer, and the gate electrode may be separated from the semiconductor layer by a gate insulating layer to prevent current from flowing from the gate electrode to the semiconductor layer. Side-gate devices may be easier to manufacture than bottom-gate devices. The nature of the insulating layer is not particularly limited as long as it limits current leakage from the gate electrode to the semiconductor layer. Usefully, the insulating layer may also be configured to protect the device from oxygen and / or water vapor. The insulating layer may include an oxide, such as hafnium oxide. A top-gate arrangement in which the gate electrode is arranged above the second insulating layer is also possible.

[0071] Alternatively, the semiconductor superconductor hybrid device may be bottom-gate. In other words, the gate electrode may be arranged below the first insulating layer. In this arrangement, a separate gate insulating layer is not necessarily required.

[0072] Any of the devices provided herein can include a protective oxide layer, for example, a hafnium oxide layer, to protect one or more portions of the device from water vapor and / or oxygen.

[0073] The first insulating layer may extend from the surface of the substrate. For example, the first insulating layer may be integrally formed with the surface of the substrate. In such a configuration, the first insulating layer separates the semiconductor layer from the surface of the substrate and from the corner where the substrate meets the first insulating layer. This may allow for improved reproducibility of the semiconductor layer during manufacturing, as the corner and / or substrate surface may be difficult to accurately reproduce.

[0074] The thickness of the first insulating layer and the second insulating layer may be independently selected appropriately. The thickness of each insulating layer may be at least 5 nm, for example 5 nm to 50 nm, or 20 nm to 50 nm.

[0075] The thickness of the semiconductor layer can be in the range of 5nm to 50nm, optionally 10nm to 40nm, further optionally 20nm to 30nm. Changing the thickness of the semiconductor layer can change the number of occupied energy levels (subbands) at the interface between the semiconductor and the superconductor. This is useful for adjusting the quantum mechanical behavior of the device.

[0076] The thickness of the semiconductor layer can be optimized based on the properties of the selected materials to maximize the topological gap. In a specific example where the band offset between the conduction band of the semiconductor and the conduction band of the insulating layer is about 50 meV and the alpha value of the device is 0.1 eV nm, it is particularly preferred that the semiconductor layer thickness is in the range of 20 to 30 nm, optionally in the range of 23 to 27 nm, or about 25 nm. Simulation is a useful method for determining the optimal semiconductor layer thickness for a given device. For example, these ranges can be particularly applicable to arrangements where the semiconductor layer includes a material of Formula 1 (below), more particularly when the semiconductor layer includes InAs; wherein the material of the first insulating layer and the second insulating layer is selected from: (i) indium phosphide; (ii) InAl x As 1-x wherein x is at least 0.1, for example in the range of 0.1 to 0.4; (iii) the formula is InGa x As 1-x A material wherein x is at least 0.15, such as in the range of 0.15 to 0.4.

[0077] The semiconductor layer may include a material of Formula 1:

[0078] (1) InAs x Sb 1-x

[0079] Wherein X is in the range of 0 to 1, for example in the range of 0 to 0.7, more particularly in the range of 0.35 to 0.45. The material may be InAs, InSb, or a ternary mixture of In, As and Sb. InAs has good handling properties during manufacturing. InSb has excellent electronic properties, for example, it couples particularly well with certain semiconductors (such as Al), but may be more difficult to use in manufacturing. The properties of alloys of InAs and InSb are between the properties of InAs and InSb.

[0080] More generally, the principles of the disclosed technology can be applied to any semiconductor, particularly III-V semiconductors.

[0081] The first insulating layer and the second insulating layer may be semiconductor materials, the energy level of the conduction band of the semiconductor material of the first insulating layer and the second insulating layer being at least 30 meV higher, preferably 50 meV higher, more preferably at least 100 meV higher than the conduction band of the semiconductor material of the semiconductor layer. It may be convenient to use high bandgap semiconductors as the first insulating layer and the second insulating layer. If the conduction band of the insulating layer material is at least 50 meV higher than the conduction band of the semiconductor layer, electrons may be prevented from flowing from the semiconductor layer to the insulating layer.

[0082] The first insulating layer and the second insulating layer may each be a material selected from the group consisting of: indium phosphide, gallium antimonide, indium gallium arsenide, and indium aluminum arsenide. In a specific example, indium phosphide InP is used as the insulating material.

[0083] Some examples of materials that can be used as the first insulating layer and the second insulating layer include materials of Formula II:

[0084] InAl x As 1-x

[0085] wherein x is at least 0.1, for example, x is in the range of 0.1 to 0.4.

[0086] Other examples of indium gallium arsenide materials that can be used as the first insulating layer and the second insulating layer are materials of formula III:

[0087] InGa x As 1-x

[0088] wherein x is at least 0.15, for example in the range of 0.15 to 0.4.

[0089] The nature of the superconductor is not particularly limited and may be appropriately selected. The superconductor is typically an s-wave superconductor. Any of various s-wave superconductors known in the art may be used. Examples include aluminum and lead, with aluminum being preferred.

[0090] The thickness of the superconductor can also be selected appropriately. An illustrative thickness range is 4 nm to 10 nm.

[0091] In one example, the semiconductor layer has a material of formula 1, preferably InSb, and the first insulating layer and the second insulating layer have a material selected from the group consisting of indium phosphide, indium gallium arsenide (e.g., indium gallium arsenide of formula III) and indium aluminum arsenide (e.g., indium aluminum arsenide of formula II), preferably indium phosphide. In this example, the superconductor is preferably aluminum.

[0092] In another example, the semiconductor material is InAs, and the first insulating layer and the second insulating layer have a material selected from the group consisting of indium phosphide, indium gallium arsenide (e.g., indium gallium arsenide of formula III) and indium aluminum arsenide (e.g., indium aluminum arsenide of formula II), preferably indium phosphide. In this example, the superconductor is preferably aluminum.

[0093] In another example, the semiconductor layer has the material of Formula 1, and the insulating layer is gallium antimonide GaSb.

[0094] The semiconductor superconductor hybrid device may also include a ferromagnetic insulator layer disposed between the superconductor and the semiconductor. Examples of suitable ferromagnetic insulators include those selected from EuS, GdN, Y3Fe5O 12 、Bi3Fe5O 12 , YFeO3, Fe2O3, Fe3O4, GdN, Sr2CrReO6, CrBr3 / CrI3, and YTiO3. Use of the device typically involves applying a magnetic field to the semiconductor layer. Including a ferromagnetic insulator can avoid the need to use an external device to apply the magnetic field.

[0095] The semiconductor superconductor hybrid devices provided herein can be configured as nanowires. The semiconductor superconductor hybrid devices provided herein can be incorporated into quantum computer devices.

[0096] It will be appreciated that the above features may be used in any combination.

[0097] Also provided herein is a method for manufacturing a semiconductor superconductor hybrid device, the method comprising: forming a first insulating layer; forming a semiconductor layer on the first insulating layer; forming a second insulating layer on the semiconductor layer; and forming a superconductor layer on the edge of the semiconductor layer to achieve energy level hybridization between the semiconductor layer and the superconductor layer. Because the semiconductor layer is separated from the corners and the top and bottom of the device, better control of the geometry of the semiconductor layer can be achieved. This can improve the reliability of the method.

[0098] The specific techniques used to form the various components can be appropriately selected. For example, at least one of the first insulating layer, the second insulating layer, and the semiconductor layer can be formed by selective area growth. Selective area growth and other techniques involving epitaxial crystal growth achieve very close contact between components. In the case of semiconductors and superconductors, epitaxial growth can improve energy level hybridization.

[0099] The method may also include forming any of the various additional components described above with reference to the device.For example, the method may also include forming a gate electrode for applying an electrostatic field to the semiconductor layer.

[0100] The semiconductor layer may have a thickness in the range of 10 nm to 50 nm. As described above, a thickness in this range allows the number of occupied energy bands to be controlled when the device is used.

[0101] The semiconductor layer may include a material having the following general formula:

[0102] InAs x Sb 1-x

[0103] Wherein X is in the range of 0 to 1. The first insulating layer and the second insulating layer can each have a material selected from the following: indium phosphide, indium gallium arsenide, and indium aluminum arsenide. More generally, it should be understood that the method can be practiced using any of the various materials (or combinations of materials) described above with respect to the device.

[0104] Further provided is a method of inducing topological behavior in a semiconductor superconductor hybrid device as provided herein, the method comprising: cooling the semiconductor superconductor hybrid device to a temperature at which the superconductor layer is superconducting; applying a magnetic field to the semiconductor layer and the superconductor layer; applying an electrostatic field to the semiconductor layer. The method may include introducing anyons, especially Majorana zero modes, in the semiconductor superconductor hybrid device. Without wishing to be bound by theory, the device provided herein may be capable of generating Majorana zero modes. The device may be used in a quantum computer, more particularly a topological quantum computer.

[0105] This disclosure provides the following terms:

[0106] Item 1. A semiconductor superconductor hybrid device, comprising: a semiconductor layer; and a superconductor layer; wherein the superconductor layer is arranged on the edge of the semiconductor layer to achieve energy level hybridization between the semiconductor layer and the superconductor layer; wherein the semiconductor layer is arranged between a first insulating layer and a second insulating layer in a sandwich structure, and each insulating layer is in contact with the opposite surface of the corresponding semiconductor layer.

[0107] Item 2. The semiconductor superconductor hybrid device according to Item 1, further comprising a gate electrode for applying an electrostatic field to the semiconductor layer.

[0108] Item 3. The semiconductor superconductor hybrid device according to Item 2, wherein the gate electrode is arranged on the second edge of the semiconductor layer, and wherein the gate electrode is separated from the semiconductor layer by a gate insulating layer to prevent current from flowing from the gate electrode to the semiconductor layer.

[0109] Item 4. The semiconductor superconductor hybrid device of Item 2, wherein the gate electrode is disposed below the first insulating layer.

[0110] Clause 5. The semiconductor superconductor hybrid device according to any one of Clauses 1 to 4, wherein the first insulating layer extends from a surface of the substrate.

[0111] Item 6. The semiconductor superconductor hybrid device of Item 5, wherein the first insulating layer is formed integrally with the surface of the substrate.

[0112] Clause 7. The semiconductor superconductor hybrid device according to any one of Clauses 1 to 6, wherein the thickness of the semiconductor layer is in the range of 5 nm to 50 nm.

[0113] Clause 8. The semiconductor superconductor hybrid device according to any one of clauses 1 to 7, wherein the semiconductor layer comprises a material having the following general formula:

[0114] InAs x Sb 1-x

[0115] Where X is in the range of 0 to 1.

[0116] Item 9. A semiconductor superconductor hybrid device according to any one of Items 1 to 8, wherein the first insulating layer and the second insulating layer are made of semiconductor material, the semiconductor material of the first insulating layer and the second insulating layer has a conduction band, and the energy level of the conduction band is at least 50 meV higher than the conduction band of the semiconductor material of the semiconductor layer.

[0117] Clause 10. The semiconductor superconductor hybrid device according to any one of Clauses 1 to 9, wherein the material of each of the first insulating layer and the second insulating layer is selected from the group consisting of: indium phosphide, gallium antimonide, indium gallium arsenide, and indium aluminum arsenide.

[0118] Clause 11. The semiconductor superconductor hybrid device according to any one of Clauses 1 to 10, further comprising a ferromagnetic insulator layer disposed between the superconductor layer and the semiconductor layer.

[0119] Clause 12. A quantum computer device comprising the semiconductor superconductor hybrid device according to any one of clauses 1 to 11.

[0120] Item 13. A method for manufacturing a semiconductor-superconductor hybrid device, the method comprising: forming a first insulating layer; forming a semiconductor layer on the first insulating layer; forming a second insulating layer on the semiconductor layer; and forming a superconductor layer on an edge of the semiconductor layer to achieve energy level hybridization between the semiconductor layer and the superconductor layer.

[0121] Item 14. The method of Item 13, further comprising forming a gate electrode for applying an electrostatic field to the semiconductor layer.

[0122] Clause 15. The method according to Clause 13 or Clause 14, wherein at least one of the first insulating layer, the second insulating layer, and the semiconductor layer is formed by selective area growth.

[0123] Clause 16. The method of any one of Clauses 13 to 15, wherein the semiconductor layer has a thickness in the range of 10 nm to 50 nm.

[0124] Clause 17. The method according to any one of clauses 13 to 16, wherein the semiconductor layer comprises a material having the following general formula:

[0125] InAs x Sb 1-x

[0126] Where X is in the range of 0 to 1.

[0127] Item 18. The method according to any one of Items 13 to 17, wherein the first insulating layer and the second insulating layer are each made of a material selected from the group consisting of: indium phosphide, indium gallium arsenide, and indium aluminum arsenide.

[0128] Clause 19. A method of inducing topological behavior in a semiconductor superconductor hybrid device according to any one of clauses 1 to 11, the method comprising: cooling the semiconductor superconductor hybrid device to a temperature at which the superconductor layer is superconducting; applying a magnetic field to the semiconductor layer and the superconductor layer; and applying an electrostatic field to the semiconductor layer.

[0129] Clause 20. The method of Clause 19, wherein the topological behavior comprises Majorana zero modes.

[0130] Other variations or use cases of the disclosed technology may become apparent to those skilled in the art once given the disclosure herein.The scope of the present disclosure is not limited by the described embodiments but only by the appended claims.

Claims

1. A semiconductor superconductor hybrid device, comprising: a semiconductor material layer; as well as a layer of superconductor material; wherein the superconductor material layer is arranged on a ferromagnetic insulator material layer arranged between the superconductor material layer and the semiconductor material layer, the ferromagnetic insulator material layer contacts an edge of the semiconductor material layer, and wherein the semiconductor material layer is arranged in a sandwich structure between a first insulating layer and a second insulating layer, each insulating layer is in contact with a corresponding opposite surface of the semiconductor material layer, and wherein the ferromagnetic insulator material layer and the superconductor material layer extend along the first insulating layer and the second insulating layer, and wherein one of the first insulating layer and the second insulating layer separates the semiconductor material layer from the surface of an underlying substrate, and the underlying substrate is associated with the semiconductor superconductor hybrid device. 2 . The semiconductor superconductor hybrid device according to claim 1 , wherein the first insulating layer extends from the surface of the underlying substrate. 3 . The semiconductor superconductor hybrid device according to claim 2 , wherein the first insulating layer is formed integrally with the surface of the underlying substrate. 4 . The semiconductor-superconductor hybrid device according to claim 1 , wherein the semiconductor material layer has a thickness in the range of 5 nm to 50 nm.

5. The semiconductor superconductor hybrid device according to claim 1, wherein the semiconductor material layer comprises a material of the following general formula: <h2 style=";text-align:left;direction:ltr">InAs<h2 style=";text-align:left;direction:ltr"> x <h2 style=";text-align:left;direction:ltr"> Sb<h2 style=";text-align:left;direction:ltr"> 1-x <h2 style=";text-align:left;direction:ltr"> , Where X is in the range of 0 to 1.

6. The semiconductor-superconductor hybrid device according to claim 1, wherein the first insulating layer and the second insulating layer are semiconductor materials that become insulating when cooled, and the semiconductor materials of the first insulating layer and the second insulating layer have a conduction band with an energy level at least 50 meV higher than the conduction band of the semiconductor material of the semiconductor material layer.

7. The semiconductor superconductor hybrid device according to claim 1, wherein the semiconductor material layer is InAs x Sb 1-x in, x is in the range of 0 to 1, the ferromagnetic insulator material layer is aluminum or InAs y Sb y , wherein y is in the range of 0 to 1, and the ferromagnetic insulator material layer includes EuS, GdN, Y3Fe5O 12 、Bi3Fe5O 12 , YFeO3, Fe2O3, Fe3O4, GdN, Sr2CrReO6, CrBr3 / CrI3 or YTiO3, and the first insulating layer and the second insulating layer are selected from indium phosphide, gallium antimonide, indium gallium arsenide and indium aluminum arsenide.

8. A semiconductor superconductor hybrid device, comprising: a semiconductor material layer; as well as a layer of superconductor material; wherein the superconductor material layer is arranged on a ferromagnetic insulator material layer arranged between the superconductor material layer and the semiconductor material layer, and the ferromagnetic insulator material layer contacts a side surface of the semiconductor material layer, so as to achieve energy level hybridization between the semiconductor material layer and the superconductor material layer when the superconductor material layer is cooled and becomes superconducting; and wherein the semiconductor material layer is arranged in a sandwich structure between a first insulating layer and a second insulating layer, each insulating layer is in contact with a corresponding opposite surface of the semiconductor material layer, and wherein the ferromagnetic insulator material layer and the superconductor material layer extend along the first insulating layer and the second insulating layer, and wherein one of the first insulating layer and the second insulating layer separates the semiconductor material layer from the surface of an underlying substrate, and the underlying substrate is associated with the semiconductor superconductor hybrid device.

9. The semiconductor superconductor hybrid device according to claim 8, wherein the first insulating layer extends from the surface of the underlying substrate. 10 . The semiconductor superconductor hybrid device according to claim 9 , wherein the first insulating layer is formed integrally with the surface of the underlying substrate.

11. The semiconductor-superconductor hybrid device according to claim 8, wherein the semiconductor material layer has a thickness in the range of 5 nm to 50 nm.

12. The semiconductor superconductor hybrid device according to claim 8, wherein the semiconductor material layer comprises a material of the following general formula: <h2 style=";text-align:left;direction:ltr">InAs<h2 style=";text-align:left;direction:ltr"> x <h2 style=";text-align:left;direction:ltr"> Sb<h2 style=";text-align:left;direction:ltr"> 1-x <h2 style=";text-align:left;direction:ltr"> , Where X is in the range of 0 to 1.

13. The semiconductor-superconductor hybrid device according to claim 8, wherein the first insulating layer and the second insulating layer are semiconductor materials that become insulating when cooled, and the semiconductor materials of the first insulating layer and the second insulating layer have a conduction band with an energy level at least 50 meV higher than the conduction band of the semiconductor material of the semiconductor material layer.

14. The semiconductor superconductor hybrid device according to claim 8, wherein the first insulating layer and the second insulating layer are each a material that becomes insulating when cooled, the material being selected from the group consisting of indium phosphide, gallium antimonide, indium gallium arsenide, and indium aluminum arsenide.

15. The semiconductor superconductor hybrid device according to claim 8, wherein the semiconductor material layer is InAs x Sb 1-x in, x is in the range of 0 to 1, the ferromagnetic insulator material layer is aluminum or InAs y Sb y , wherein y is in the range of 0 to 1, and the ferromagnetic insulator material layer includes EuS, GdN, Y3Fe5O 12 、Bi3Fe5O 12 , YFeO3, Fe2O3, Fe3O4, GdN, Sr2CrReO6, CrBr3 / CrI3 or YTiO3, and the first insulating layer and the second insulating layer are selected from indium phosphide, gallium antimonide, indium gallium arsenide and indium aluminum arsenide.

16. A quantum computer device, comprising the semiconductor superconductor hybrid device according to any one of claims 1 to 7 or any one of claims 8 to 15.

17. A method for manufacturing a semiconductor superconductor hybrid device, the method comprising: Arranging a semiconductor layer in a sandwich structure between a first insulating layer and a second insulating layer, each insulating layer being in contact with a corresponding opposite face of the semiconductor layer; as well as A ferromagnetic insulator material layer is formed between the superconductor material layer and the semiconductor layer, wherein the ferromagnetic insulator material layer contacts an edge of the semiconductor layer. Wherein the layer of ferromagnetic insulator material and the layer of superconductor material extend along the first insulating layer and the second insulating layer, and wherein one of the first insulating layer and the second insulating layer separates the semiconductor layer from a surface of an underlying substrate, and the underlying substrate is associated with the semiconductor-superconductor hybrid device.

18. The method of claim 17, wherein the first insulating layer extends from the surface of the underlying substrate.

19. The method of claim 17, wherein the first insulating layer is formed integrally with the surface of the underlying substrate.

20. The method of claim 17, wherein the semiconductor layer has a thickness in a range of 5 nm to 50 nm.

21. The method of claim 17, wherein the semiconductor layer comprises a material of the following general formula: <h2 style=";text-align:left;direction:ltr">InAs<h2 style=";text-align:left;direction:ltr"> x <h2 style=";text-align:left;direction:ltr"> Sb<h2 style=";text-align:left;direction:ltr"> 1-x <h2 style=";text-align:left;direction:ltr"> , Where X is in the range of 0 to 1.

22. The method of claim 17, wherein the first insulating layer and the second insulating layer are each a semiconductor material that becomes insulating when cooled, the semiconductor materials of the first insulating layer and the second insulating layer having a conduction band at an energy level at least 50 meV higher than a conduction band of the semiconductor material of the semiconductor layer.

23. A method for inducing topological behavior in a semiconductor superconductor hybrid device according to claim 1, the method comprising: Cooling the semiconductor superconductor hybrid structure to a temperature at which the superconductor material layer becomes superconducting; applying a magnetic field to the semiconductor material layer and the superconductor material layer; as well as An electrostatic field is applied to the layer of semiconductor material.

24. The method of claim 23, wherein the topological behavior comprises Majorana zero modes.

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