Transmitter, receiver and transmission system

Abstract

The sending device includes: a sending unit, which includes pixel data of a row constituting a frame of an image in a payload, and is capable of outputting multiple packets to a sending path, in which a header is added to the payload; and an insertion rate calculation unit, which can calculate the insertion rate of a filling code inserted into the payload so as to fill the difference between the sending rate of the pixel data input to the sending unit and the sending rate of the pixel data output from the sending unit to the sending path.

Description

Technical Field

[0001] The present disclosure relates to a transmitting device that transmits image data, a receiving device that receives image data, and a transmission system that transmits and receives image data. Background Art

[0002] Some transmission systems transmit and receive image data including pixel data corresponding to a plurality of lines and output from an imaging unit between a transmitting unit and a receiving unit. Patent document (PTL) 1 discloses a transmission system that generates a packet and transmits and receives image data by using the packet. The packet includes a header including control information and a payload including pixel data corresponding to a row. The technology disclosed in Patent document 1 enables a symbol group called a padding code to be inserted into the payload data to fill the transmission band difference between the transmission rate of the pixel data input to the transmitting unit (pixel data band) and the transmission rate of the pixel data sent from the transmitting unit to be input to the receiving unit (physical layer (PHY) transmission band).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2012-120158 Summary of the invention

[0006] In the technology disclosed in Patent Document 1, it is difficult to find the insertion rate of the above-mentioned stuffing code on the receiving unit side, making it difficult to perform optimal data processing.

[0007] It is desirable to provide a transmitting device, a receiving device, and a transmission system capable of performing optimal data processing.

[0008] According to one embodiment of the present disclosure, a sending device includes: a sending unit, configured to output a plurality of packets to a sending channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in a frame of an image; and an insertion rate calculator, configured to calculate an insertion rate of a filling code, which is inserted into the payload to fill a difference between a sending rate of pixel data input to the sending unit and a sending rate of pixel data output from the sending unit to the sending channel.

[0009] A receiving device according to an embodiment of the present disclosure includes a receiving unit, the receiving unit being configured to receive a plurality of packets from a sending unit of a sending device via a sending channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in a frame of an image. The receiving device is configured to receive data on an insertion rate of a stuffing code from the sending device, the stuffing code being inserted into the payload to fill a difference between a sending rate of pixel data input to the sending unit and a sending rate of pixel data output from the sending unit to the sending channel.

[0010] A transmission system according to an embodiment of the present disclosure includes: a transmitting device; and a receiving device. The transmitting device includes a transmitting unit configured to output a plurality of packets to a transmitting channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in a frame of an image, and an insertion rate calculator configured to calculate an insertion rate of a stuffing code, the stuffing code being inserted into the payload to fill the difference between the sending rate of the pixel data input to the transmitting unit and the sending rate of the pixel data output from the transmitting unit to the transmitting channel.

[0011] A transmitting device, a receiving device or a transmission system according to one embodiment of the present disclosure makes it possible to find an insertion rate of a stuffing code. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram showing a first configuration example of a transmission system according to one embodiment of the present disclosure.

[0013] Figure 2 is a block diagram showing a second configuration example of the transmission system according to one embodiment.

[0014] Figure 3 is an explanatory diagram showing an example of a frame format in a transmission system according to one embodiment.

[0015] Figure 4 It is shown Figure 3 An explanatory diagram of an example of a header structure of a packet in the frame format shown in FIG.

[0016] Figure 5 It is shown Figure 4 An explanatory diagram of an example of the contents of header information in the header structure shown in FIG.

[0017] Figure 6 is a block diagram showing a configuration example of a transmission unit in a transmission system according to one embodiment.

[0018] Figure 7 is a block diagram showing a configuration example of a receiving unit in a transmission system according to one embodiment.

[0019] Figure 8 : is an explanatory diagram showing an example of a control code added by a control code inserter of a transmitting unit in a transmission system according to an embodiment.

[0020] Fig. 9 : is an explanatory diagram showing an example of the value of the K character.

[0021] Fig.10 is an explanatory diagram showing an example of padding insertion.

[0022] Fig.11 is an explanatory diagram showing an example of packet data into which a control code is inserted.

[0023] Fig.12 is a block diagram showing a first example of a modified example of a transmission unit in a transmission system according to one embodiment.

[0024] Fig.13 is an explanatory diagram showing an example in which data indicating a stuffing code insertion rate is added to a header.

[0025] Fig.14 is a block diagram showing a second example of a modified example of the transmission unit in the transmission system according to one embodiment.

[0026] Fig.15 is a block diagram showing a third example of a modified example of the transmission unit in the transmission system according to one embodiment. DETAILED DESCRIPTION

[0027] The embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings. It should be noted that the description is given in the following order.

[0028] 1. An embodiment

[0029] 1.1 Configuration and Operation of a Transmission System According to an Embodiment Figures 1 to 11 )

[0030] 1.2 Improved Example of a Transmission System According to an Embodiment ( Figures 12 to 15 )

[0031] 1.3 Effect

[0032] 2. Other embodiments

[0033] <1. One embodiment>

[0034] [1.1 Configuration and Operation of a Transmission System According to One Embodiment]

[0035] [Configuration example of transmission system]

[0036] Figure 1A first configuration example of the transmission system 1 according to one embodiment of the present disclosure is shown.

[0037] Figure 1 The illustrated transmission system 1 includes a sensor module 11 and a digital signal processor (DSP) 12. The sensor module 11 and the digital signal processor 12 include, for example, large-scale integrated circuits (LSIs) different from each other, and are provided in the same imaging device (eg, a digital camera or a mobile phone) having an imaging function.

[0038] The sensor module 11 includes an imaging unit 21 and a transmitting unit 22. In addition, the sensor module 11 includes a system controller 51 and a register 53. In addition, the sensor module 11 includes a frame data input section 52 ( Figure 6 ). The system controller 51 and the register 53 are coupled to the imaging unit 21 and the transmitting unit 22.

[0039] The digital signal processor 12 includes a receiving unit 31 and an image processing unit 32. In addition, the digital signal processor 12 includes a register 142 and a system controller 143. In addition, the digital signal processor 12 includes a frame data output section 141 ( Figure 7 The register 142 and the system controller 143 are coupled to the receiving unit 31 and the image processing unit 32.

[0040] The system controller 51 and register 53 in the sensor module 11 and the register 142 and system controller 143 in the digital signal processor 12 are coupled to each other via the control line 13. This enables communication of control data and the like between the sensor module 11 and the digital signal processor 12.

[0041] The imaging unit 21 includes an image sensor such as a complementary metal oxide semiconductor (CMOS), and performs photoelectric conversion on light received via a lens. In addition, the imaging unit 21 performs analog-to-digital (A / D) conversion on a signal obtained by the photoelectric conversion, and outputs pixel data contained in one frame of an image to the sending unit 22 by sequentially outputting the data of each pixel.

[0042] The transmission unit 22 distributes the data of each pixel supplied from the imaging unit 21 to a plurality of transmission channels in the order in which the data is supplied from the imaging unit 21. The transmission unit 22 transmits the data of each pixel to the digital signal processor 12 in parallel via the plurality of transmission channels. Figure 1 In the example of FIG. 1 , eight transmission channels are used to perform the transmission of pixel data. The transmission channel between the sensor module 11 and the digital signal processor 12 may be a wired transmission channel or a wireless transmission channel. In the following, the transmission channel between the sensor module 11 and the digital signal processor 12 will be appropriately referred to as a lane.

[0043] The receiving unit 31 of the digital signal processor 12 receives the pixel data transmitted from the transmitting unit 22 via eight channels, and sequentially outputs the data of each pixel to the image processing unit 32 .

[0044] The image processing unit 32 generates a frame of image based on the pixel data supplied from the receiving unit 31, and performs various types of image processing by using the generated image. The image data sent from the sensor module 11 to the digital signal processor 12 is raw (RAW) data, and is subjected to various types of processing in the image processing unit 32, such as compression of image data, display of an image, and recording of image data on a recording medium.

[0045] Figure 2 A second configuration example of the transmission system 1 according to one embodiment is shown.

[0046] The imaging unit 21 may be configured to output a plurality of pixel data of different types for the same pixel. For example, as data of the same pixel, two pixel data of different types (first pixel data DATA1 and second pixel data DATA2) may be output, such as Figure 2 As shown. For example, for the same pixel, two pieces of pixel data with different gains can be output. In this case, for example, the two pieces of pixel data can be configured to be sent in parallel between the sending unit 22 and the receiving unit 31. For example, among channels 0 to 7, channels 0 to 3 can be configured as a first split transmission channel (LINK0) for sending the first pixel data DATA1, and channels 4 to 7 can be configured as a second split transmission channel (LINK1) for sending the second pixel data DATA2. In this way, for example, in order to send different types of pixel data in parallel between the sending unit 22 and the receiving unit 31, a configuration that splits a plurality of channels into a plurality of split transmission channels (LINK) for corresponding types of pixel data can be used.

[0047] It should be noted that the transmission system 1 may be provided with a plurality of transmission units 22 and a plurality of receiving units 31. In this case, for example, one or more frames of image data captured by one imaging unit 21 may be divided and input in parallel to a plurality of transmission units, and the one or more frames of image data input in parallel may be sent in parallel to a plurality of receiving units 31. Then, the one or more frames of image data received in parallel may be output in parallel from the plurality of receiving units 31 to the digital signal processor 12.

[0048] As described above, the sensor module 11 of the transmission system 1 may be provided with one or more sending units 22, and the one or more sending units 22 send one or more frames of captured image data. On the other hand, the digital signal processor 12 may be provided with one or more receiving units 31 corresponding to the sending units 22 of the sensor module 11, and the one or more receiving units 31 receive one or more frames of image data sent from the sensor module 11.

[0049] The following description is based on Figure 1 The data is sent in the transmission system 1. Figure 1 In the embodiment, the sensor module 11 has one transmitting unit 22, and the digital signal processor 12 has one receiving unit 31. Data transmission is similarly performed between each of the plurality of transmitting units 22 and each of the plurality of receiving units 31.

[0050] [Frame format]

[0051] Figure 3 An example of a frame format for transmitting one frame of image data between the sensor module 11 and the digital signal processor 12 is shown.

[0052] The effective pixel area A1 is an effective pixel area of ​​one frame of an image captured by the imaging unit 21. A margin area A2 is provided on the left side of the effective pixel area A1, in which the number of pixels in the vertical direction is the same as that in the effective pixel area A1.

[0053] A front dummy area A3 is provided on the upper side of the effective pixel area A1, and the number of pixels in the horizontal direction of the front dummy area A3 is the same as the total number of pixels in the horizontal direction of the effective pixel area A1 and the edge area A2. Figure 3 In the example of FIG. 1 , embedded data (Embedded Data) is inserted in the front virtual area A3. The embedded data includes information about setting values ​​related to imaging of the imaging unit 21, such as shutter speed, aperture, and gain. The embedded data can be inserted into a rear virtual area A4.

[0054] A rear dummy area A4 is provided below the effective pixel area A1 , and the number of pixels in the rear dummy area A4 in the horizontal direction is the same as the total number of pixels in the effective pixel area A1 and the edge area A2 in the horizontal direction.

[0055] The effective pixel area A1 , the edge area A2 , the front dummy area A3 , and the rear dummy area A4 are included in the image data area A11 .

[0056] A header is added before each line included in the image data area A11, and a start code is added before the header. In addition, a footer is optionally added after each line included in the image data area A11, and a control code described later, such as an end code (End Code), is added after the footer. In the case where a footer is not added, a control code such as an end code is added after each line included in the image data area A11.

[0057] Each time a frame of image captured by the imaging unit 21 is sent from the sensor module 11 to the digital signal processor 12, Figure 3 The entire data in the format shown in is sent as the transmission data.

[0058] Figure 3 The strip on the upper side shows the structure of the packet used for transmission of the transmission data shown on the lower side. Assuming that the pixels arranged in the horizontal direction are one row, the payload of the packet stores the data of the pixels included in one row of the image data area A11. The transmission of the entire image data of one frame is performed by using packets whose number is equal to or greater than the number of pixels in the vertical direction of the image data area A11.

[0059] A packet is configured by adding a header and a footer to a payload storing pixel data corresponding to a row. As will be described in detail later, the header includes additional information of the pixel data stored in the payload, such as frame start, frame end, valid row, row number, reserved, and error correction code (ECC). In addition, the header includes an embedded row and data identification (ID), as enclosed by a thick line L11. A start code and an end code as control codes are at least added to each packet.

[0060] In this way, a format is adopted in which pixel data contained in one frame of image is transmitted for each line. This makes it possible to transmit additional information, such as a header, and control codes such as a start code and an end code during the blanking period of each line.

[0061] Figure 4 Shows Figure 3 An example of the header structure of a packet in the frame format is shown in FIG. Figure 5 Shows Figure 4 An example of the contents of the header information in the header structure shown in FIG.

[0062] As described above, a packet includes a header and payload data, which is pixel data corresponding to a row. A footer can be added to the packet. The header includes header information and header ECC. A start code is added at the beginning of each packet, and an end code is added after each packet.

[0063] The header information includes frame start, frame end, valid line, line number and reserved. The header information also includes embedded line as line information and data ID as data identification. Figure 5 The information content and amount of each piece of information are shown.

[0064] The start of frame is a 1-bit information indicating the beginning of a frame. Figure 3 The frame start value of the header of the packet of the pixel data of the first row in the image data area A11 is set to 1, and the frame start value of the header of the packet for transmitting the pixel data of another row is set to 0.

[0065] The frame end is 1-bit information indicating the end of the frame. The frame end value of the header of the packet including the pixel data of the end row of the effective pixel area A1 in the payload is set to 1, and the frame end value of the header of the packet for sending the pixel data of another row is set to 0.

[0066] The frame start and the frame end are used as frame information of information related to the frame.

[0067] The valid row is 1-bit information indicating whether the row of pixel data stored in the payload is a row of valid pixels. The valid row value of the header of the packet for sending the pixel data of one row in the valid pixel area A1 is set to 1, and the valid row value of the header of the packet for sending the pixel data of another row is set to 0.

[0068] The row number is 13-bit information indicating the row number of the row including the pixel data stored in the payload.

[0069] The valid row and the row number are used as row information of the information related to the row.

[0070] The embedded row is 1-bit information indicating whether the packet is a packet for transmitting a row including embedded data inserted. For example, the embedded row value of the header for transmitting a packet including embedded data is set to 1, and the embedded row value of the header for transmitting another row is set to 0. As described above, information on setting values ​​related to imaging is inserted as embedded data in a predetermined row of the front virtual area A3 or the rear virtual area A4.

[0071] The data ID is P-bit information indicating the number of pixel data stored in the payload. The P bit represents a predetermined number of bits equal to or greater than 1 bit.

[0072] The reserved area is a 31-P bit area for extension. The data amount of the entire header information is 6 bytes.

[0073] like Figure 4As shown, the header ECC arranged after the header information includes a cyclic redundancy check (CRC) code, which is a 2-byte error detection code calculated based on the 6-byte header information. In addition, the header ECC includes two pieces of information identical to the 8-byte information after the cyclic redundancy check code, i.e., a set of header information and a cyclic redundancy check code.

[0074] That is to say, the header of a packet includes three sets of identical header information and cyclic redundancy check codes. The data volume of the entire header is 8 bytes of the first set of header information and cyclic redundancy check codes, 8 bytes of the second set of header information and cyclic redundancy check codes, and 8 bytes of the third set of header information and cyclic redundancy check codes, that is, a total of 24 bytes.

[0075] [Configuration of the Transmitting Unit 22 and the Receiving Unit 31]

[0076] Figure 6 A configuration example of the transmission unit 22 in the transmission system 1 is shown. Figure 7 A configuration example of the receiving unit 31 in the transmission system 1 is shown.

[0077] The sending unit 22 and the receiving unit 31 both include the configuration of the link layer and the configuration of the physical layer. Figure 6 and Figure 7 , the configuration shown above the solid line L2 is the configuration of the link layer, and the configuration shown below the solid line L2 is the configuration of the physical layer.

[0078] It should be noted that the configuration shown above the solid line L1 is a configuration of the application layer. The application layer includes a system controller 51, a frame data input section 52, and a register 53, and includes a frame data output section 141, a register 142, and a system controller 143. For example, the frame data input section 52 is provided in the imaging unit 21. For example, the frame data output section 141 is provided in the image processing unit 32.

[0079] The system controller 51 communicates with the LINK-TX protocol manager 61 of the transmission unit 22 and controls the transmission of the image data by, for example, providing information related to the frame format.

[0080] The frame data input section 52 performs imaging in response to a user's instruction or the like, and supplies data of each pixel included in an image obtained by performing the imaging to the pixel-to-byte converter 62 of the transmission unit 22 .

[0081] The register 53 stores information such as the number of bits and the number of channels for pixel-to-byte conversion. The image data transmission process is performed based on the information stored in the register 53.

[0082] The frame data output section 141 generates one frame of image based on the pixel data of each line supplied from the receiving unit 31, and outputs the image. Various types of processing are performed using the image output from the frame data output section 141.

[0083] The register 142 stores corresponding types of setting values ​​related to reception of image data, such as the number of bits and the number of channels for byte-to-pixel conversion. Image data reception processing is performed based on the information stored in the register 142.

[0084] The system controller 143 communicates with the LINK-RX protocol manager 121 and controls the order of mode changes and the like.

[0085] [Configuration of Link Layer of Transmitting Unit 22]

[0086] like Figure 6 As shown, as a configuration of the link layer, the transmission unit 22 is provided with a LINK-TX protocol manager 61, a pixel to byte converter 62, a payload ECC inserter 63, a packet generator 64, and a channel distributor 65. The LINK-TX protocol manager 61 includes a state controller 71, a header generator 72, a data inserter 73, and a footer generator 74.

[0087] The state controller 71 of the LINK-TX protocol manager 61 manages the state of the link layer of the transmission unit 22 .

[0088] The header generator 72 generates a header to be added to a payload storing pixel data corresponding to one line, and outputs the header to the packet generator 64 . Figure 4 An example of a header is shown in FIG.

[0089] The header generator 72 generates header information under the control of the system controller 51. For example, from the system controller 51, the header generator 72 is supplied with information indicating the row number of the pixel data output by the frame data input section 52 and information indicating the start and end of a frame.

[0090] In addition, the header generator 72 calculates a cyclic redundancy check code by applying the header information to a generating polynomial. The generating polynomial of the cyclic redundancy check code to be added to the header information is represented by the following expression (1), for example:

[0091] CRC16=X 16 +X 15 +X 2 +1……(1)

[0092] The header generator 72 generates a set of header information and a cyclic redundancy check code by adding the cyclic redundancy check code to the header information, and generates a header by repeatedly arranging three sets of the same header information and the cyclic redundancy check code. The header generator 72 outputs the generated header to the packet generator 64.

[0093] The data inserter 73 generates data for stuffing and outputs the data to the pixel-to-byte converter 62 and the channel distributor 65. The payload stuffing data, which is the stuffing data provided to the pixel-to-byte converter 62, is added to the pixel data after the pixel-to-byte conversion and is used to adjust the data amount of the pixel data to be stored in the payload. In addition, the channel stuffing data, which is the stuffing data provided to the channel distributor 65, is added to the data after the channel distribution and is used to adjust the data amount between the channels.

[0094] The footer generator 74 appropriately calculates a 32-bit cyclic redundancy check code by applying the payload data to a generating polynomial under the control of the system controller 51, and outputs the cyclic redundancy check code determined by the calculation to the packet generator 64 as a footer. The generating polynomial of the cyclic redundancy check code added as a footer is represented by, for example, the following expression (2):

[0095] CRC32=X 32 +X 31 +X 4 +X 3 +X+1……(2)

[0096] The pixel-to-byte converter 62 acquires the pixel data provided from the frame data input section 52, and performs pixel-to-byte conversion of converting the data of each pixel into data in units of 1 byte. For example, the pixel value (RGB) of each pixel of the image captured by the imaging unit 21 is represented by any number of bits among 8 bits, 10 bits, 12 bits, 14 bits, and 16 bits.

[0097] The pixel-to-byte converter 62 performs pixel-to-byte conversion on each pixel in order starting from the pixel at the left end of the row, for example. In addition, the pixel-to-byte converter 62 generates payload data by adding payload padding data provided from the data inserter 73 to the pixel data in bytes obtained by the pixel-to-byte conversion, and outputs the payload data to the payload ECC inserter 63.

[0098] According to the order of obtaining pixel data by conversion, the pixel data converted from pixel to byte are grouped into a predetermined number of groups. In the link layer of the transmitting unit 22, after grouping in this way, for each cycle defined by the clock signal, the pixel data at the same position in each group are processed in parallel. For example, when the pixel data is assigned to 16 groups, the processing of the pixel data is performed by processing 16 pixel data arranged in each row in the same cycle.

[0099] As mentioned above, the payload of a packet includes pixel data for one row. Figure 3 The processing of pixel data of the effective pixel area A1 in FIG. 1 is described here, and pixel data of another area, such as the edge area A2, is also processed together with the pixel data of the effective pixel area A1.

[0100] After grouping the pixel data corresponding to a row, add payload padding data so that each group has the same data length. The payload padding data is 1 byte data.

[0101] The payload data having such a configuration is supplied from the pixel-to-byte converter 62 to the payload ECC inserter 63 .

[0102] The payload ECC inserter 63 calculates an error correction code to be used for error correction of the payload data based on the payload data provided from the pixel to byte converter 62, and inserts a parity check code as the error correction code determined by the calculation into the payload data. For example, a Reed-Solomon code is used as the error correction code. It should be noted that the insertion of the error correction code is optional. For example, only one of the insertion of the parity check code of the payload ECC inserter 63 and the addition of the footnote of the footnote generator 74 may be performed.

[0103] In the payload ECC inserter 63, basically, a 2-byte parity code is generated based on, for example, 224 pieces of pixel data, and is inserted after the 224 pieces of pixel data.

[0104] The payload ECC inserter 63 outputs the payload data into which the parity code has been inserted to the packet generator 64. The payload data supplied from the pixel-to-byte converter 62 to the payload ECC inserter 63 is output to the packet generator 64 as it is without performing parity code insertion.

[0105] The packet generator 64 generates a packet by adding the header generated by the header generator 72 to the payload data supplied from the payload ECC inserter 63. In the case where a footer has been generated by the footer generator 74, the packet generator 64 also adds the footer to the payload data.

[0106] The packet generator 64 outputs packet data, which is data included in one generated packet, to the channel distributor 65. The channel distributor 65 is provided with: packet data including header data and payload data; packet data including header data, payload data and footer data; or packet data including header data and payload data into which a parity check code has been inserted. Figure 4 The packet structure in is a logical structure. At the link layer and physical layer, it has Figure 4 The data of the group in the structure is processed in bytes.

[0107] The channel distributor 65 distributes the packet data supplied from the packet generator 64 to each channel of channels 0 to 7 to be used for data transmission in order from the data at the beginning.

[0108] The channel distributor 65 outputs the packet data assigned to each channel to the physical layer. Although the following description is based on the case where data is transmitted using eight channels 0 to 7, the same processing is performed even when the number of channels used for data transmission is another number.

[0109] [Configuration of Physical Layer of Transmission Unit 22]

[0110] like Figure 6 As shown, the transmitting unit 22 is provided with a PHY-TX state controller 81, a clock generator 82, and signal processors 83-0 to 83-N as a configuration of the physical layer. The signal processor 83-0 includes a control code inserter 91, an 8B10B symbol encoder 92, a synchronizer 93, and a transmitter 94. Among the packet data output from the channel distributor 65, the packet data assigned to channel 0 is input to the signal processor 83-0, and the packet data assigned to channel 1 is input to the signal processor 83-1. In addition, the packet data assigned to channel N is input to the signal processor 83-N.

[0111] In this way, the physical layer of the transmission unit 22 is provided with the same number of signal processors 83-0 to 83-N as the number of channels, and processing of packet data to be transmitted using each channel is performed in parallel in each of the signal processors 83-0 to 83-N. Although the configuration of the signal processor 83-0 is described, the signal processors 83-1 to 83-N also have similar configurations.

[0112] The PHY-TX state controller 81 controls each unit of the signal processors 83 - 0 to 83 -N. For example, the timing of each process performed by the signal processors 83 - 0 to 83 -N is controlled by the PHY-TX state controller 81 .

[0113] The clock generator 82 generates a clock signal and outputs the clock signal to the synchronizer 93 of each of the signal processors 83 - 0 to 83 -N.

[0114] The control code inserter 91 of the signal processor 83-0 adds the control code to the packet data provided from the channel distributor 65. The control code is a code represented by one symbol selected from a plurality of types of symbols prepared in advance or by a combination of a plurality of types of symbols. Each symbol inserted by the control code inserter 91 is 8-bit data. By performing 8B10B conversion in the subsequent circuit, one symbol inserted by the control code inserter 91 becomes 10-bit data. On the other hand, as described later, the received data is 10B8B converted in the receiving unit 31; each symbol before the 10B8B conversion contained in the received data is 10-bit data, and each symbol after the 10B8B conversion becomes 8-bit data.

[0115] Control codes include Figure 4 The start code, end code, etc. shown in FIG. In addition, the control code includes an idle code, a fill code, a synchronization code, a correction code, and a standby code.

[0116] Figure 8 An example of the control code added by the control code inserter 91 is shown.

[0117] The idle code is a symbol group that is repeatedly transmitted in a period other than the packet data transmission period. The idle code is represented by the D character D00.0 (00000000), that is, the 8B10B code.

[0118] The start code is a symbol group indicating the start of a packet. As mentioned above, the start code is added before the packet. The start code is represented by four symbols K28.5, K27.7, K28.2, and K27.7, which is a combination of three K characters. Fig. 9 An example of the value of each K character is shown.

[0119] The end code is a symbol group indicating the end of the group. As mentioned above, the end code is added after the group. The end code is represented by four symbols K28.5, K29.7, K30.7, and K29.7, which is a combination of three K characters.

[0120] The padding code is a symbol group called a padding code, which is inserted into the payload data to fill the difference between the pixel data band and the physical layer (PHY) transmission band. The pixel data band is the transmission rate at which the pixel data output from the imaging unit 21 is input to the transmission unit 22, and the PHY transmission band is the transmission rate at which the pixel data transmitted from the transmission unit 22 is input to the receiving unit 31. The padding code is represented by four symbols K23.7, K28.4, K28.6, and K28.7, which is a combination of four K characters.

[0121] Fig.10 A fill code insertion example is shown.

[0122] Fig.10 The upper level shows the payload data assigned to each channel before the stuffing code is inserted, and the Fig.10 The lower level shows the payload data after the stuffing code is inserted. Fig.10 In the example of , the stuffing code is inserted between the third pixel data and the fourth pixel data, between the sixth pixel data and the seventh pixel data, and between the twelfth pixel data and the thirteenth pixel data. In this way, the stuffing code is inserted in the same position of the payload data on each channel of channels 0 to 7.

[0123] Insertion of the stuffing code into the payload data assigned to channel 0 is performed by the control code inserter 91 of the signal processor 83-0. Insertion of the stuffing code into the payload data assigned to other channels is also similarly performed at the same timing in each of the signal processors 83-1 to 83-N. The number of stuffing codes is determined based on the difference between the pixel data band and the physical layer transmission band, the frequency of the clock signal generated by the clock generator 82, etc.

[0124] In this way, when the pixel data band is narrower and the physical layer transmission band is wider, the padding code is inserted to adjust the difference between the two bands. For example, by inserting the padding code, the difference between the pixel data band and the physical layer transmission band is adjusted to a constant range.

[0125] The synchronization code is a symbol group for realizing bit synchronization and symbol synchronization between the transmitting unit 22 and the receiving unit 31. The synchronization code is represented by two symbols K28.5 and Any**. Any** indicates that any type of symbol can be used. For example, during the training mode before starting to send packet data between the transmitting unit 22 and the receiving unit 31, the synchronization code is repeatedly sent.

[0126] The deskew code is a symbol group for correcting data offset between channels, that is, the difference in reception timing of data received by each channel of the receiving unit 31. The deskew code is represented by two symbols K28.5 and any **. The use of the deskew code to correct data offset between channels will be described later.

[0127] The standby code is a symbol group used to notify the receiving unit 31 that the output of the transmitting unit 22 enters a state such as high impedance (High-Z) and no longer transmits data. That is, when the transmitting unit 22 ends the transmission of packet data and enters the standby state, the standby code is sent to the receiving unit 31. The standby code is represented by two symbols K28.5 and any **.

[0128] Fig.11An example of packet data with a control code inserted therein is shown.

[0129] like Fig.11 As shown, in each of the signal processors 83-0 to 83-N, a start code is added before the packet data, and a stuffing code is inserted into the payload data. An end code is added after the packet data, and a correction code is added after the end code. Fig.11 In the example, an idle code is added after the correction code.

[0130] The control code inserter 91 outputs the packet data to which the control code is added to the 8B10B symbol encoder 92 .

[0131] The 8B10B symbol encoder 92 performs 8B10B conversion on the packet data supplied from the control code inserter 91 (the packet data to which the control code has been added), and outputs the packet data converted into data of 10-bit units to the synchronizer 93 .

[0132] The synchronizer 93 outputs each bit of the packet data supplied from the 8B10B symbol encoder 92 to the transmitter 94 according to the clock signal generated by the clock generator 82 .

[0133] The transmitter 94 transmits the packet data supplied from the synchronizer 93 to the receiving unit 31 via the transmission channel included in lane 0. In the case where data transmission is performed by using eight lanes, the packet data is also transmitted to the receiving unit 31 using the transmission channels included in lanes 1 to 7.

[0134] [Configuration of Physical Layer of Receiving Unit 31]

[0135] like Figure 7 As shown, as a configuration of the physical layer, the receiving unit 31 is provided with a PHY-RX state controller 101 and signal processors 102-0 to 102-N. The signal processor 102-0 includes a receiver 111, a clock generator 112, a synchronizer 113, a symbol synchronizer 114, a 10B8B symbol decoder 115, an offset corrector 116, and a control code remover 117. Packet data transmitted via a transmission channel included in channel 0 is input to the signal processor 102-0, and packet data transmitted via a transmission channel included in channel 1 is input to the signal processor 102-1. In addition, packet data transmitted via a transmission channel included in channel N is input to the signal processor 102-N.

[0136] In this manner, the physical layer of the receiving unit 31 is provided with the same number of signal processors 102-0 to 102-N as the number of channels, and processing of packet data transmitted using each channel is performed in parallel in each of the signal processors 102-0 to 102-N. Although the configuration of the signal processor 102-0 is described, the signal processors 102-1 to 102-N also have similar configurations.

[0137] The receiver 111 receives a signal representing packet data transmitted from the transmission unit 22 via a transmission channel included in lane 0 , and outputs the signal to the clock generator 112 .

[0138] The clock generator 112 realizes bit synchronization by detecting the edge of the signal provided from the receiver 111 and generates a clock signal based on the edge detection cycle. The clock generator 112 outputs the signal provided from the receiver 111 to the synchronizer 113 together with the clock signal.

[0139] The synchronizer 113 samples the signal received by the receiver 111 according to the clock signal generated by the clock generator 112, and outputs the packet data obtained by the sampling to the symbol synchronizer 114. The clock generator 112 and the synchronizer 113 implement a clock data recovery (CDR) function.

[0140] The symbol synchronizer 114 realizes symbol synchronization by detecting the control code included in the packet data, or by detecting the partial symbol included in the control code. For example, the symbol synchronizer 114 detects the K28.5 symbol included in the start code, the end code and the correction code to realize symbol synchronization. The symbol synchronizer 114 outputs the packet data to the 10B8B symbol decoder 115 in 10-bit units representing each symbol.

[0141] Furthermore, the symbol synchronizer 114 realizes symbol synchronization by detecting a symbol boundary included in a synchronization code which is repeatedly transmitted from the transmission unit 22 during a training mode before starting transmission of packet data.

[0142] The 10B8B symbol decoder 115 performs 10B8B conversion on the packet data in 10-bit units supplied from the symbol synchronizer 114 , and outputs the packet data converted into data in 8-bit units to the offset corrector 116 .

[0143] The offset corrector 116 detects the correction code from the packet data supplied from the 10B8B symbol decoder 115. Information on the detection timing of the correction code supplied from the offset corrector 116 is supplied to the PHY-RX state controller 101.

[0144] Furthermore, the offset corrector 116 corrects the data offset between the lanes by matching the timing of the correction code with the timing indicated by the information provided from the PHY-RX state controller 101. The information provided from the PHY-RX state controller 101 indicates the latest timing of the timing of the correction code detected in each of the signal processors 102-0 to 102-N.

[0145] The offset corrector 116 outputs the packet data whose data offset has been corrected to the control code remover 117 .

[0146] The control code remover 117 removes the control code added to the packet data, and outputs the data from the start code to the end code as packet data to the link layer.

[0147] The PHY-RX state controller 101 controls each unit of the signal processors 102-0 to 102-N and causes each unit to perform correction of data offset between channels, etc. In addition, in the case where a transmission error occurs on a predetermined channel and a control code is lost, the PHY-RX state controller 101 performs error correction of the control code by adding a control code transmitted via another channel instead of the lost control code.

[0148] [Configuration of Link Layer of Receiving Unit 31]

[0149] like Figure 7 As shown, as a configuration of the link layer, the receiving unit 31 is provided with a link receiving (LINK-RX) protocol manager 121, a channel integrator 122, a packet separator 123, a payload error corrector 124, and a byte to pixel converter 125. The LINK-RX protocol manager 121 includes a state controller 131, a header error corrector 132, a data remover 133, and a footer error detector 134.

[0150] The channel integrator 122 integrates the packet data supplied from the signal processors 102 - 0 to 102 -N of the physical layer by rearranging the packet data in the reverse order of the order allocated to each channel by the channel distributor 65 of the transmission unit 22 .

[0151] When the packet data of each channel is integrated, the channel stuffing data is removed by the channel integrator 122 under the control of the data remover 133. The channel integrator 122 outputs the integrated packet data to the packet separator 123.

[0152] The packet separator 123 separates packet data corresponding to one packet integrated by the channel integrator 122 into packet data included in the header data and packet data included in the payload data. The packet separator 123 outputs the header data to the header error corrector 132 and outputs the payload data to the payload error corrector 124.

[0153] In addition, in the case where the packet includes a footer, the packet separator 123 separates data corresponding to one packet into packet data included in the header data, packet data included in the payload data, and packet data included in the footer data. The packet separator 123 outputs the header data to the header error corrector 132, and outputs the payload data to the payload error corrector 124. In addition, the packet separator 123 outputs the footer data to the footer error detector 134.

[0154] In the case where the parity code is inserted into the payload data supplied from the packet separator 123, the payload error corrector 124 detects an error in the payload data by performing error correction calculation based on the parity code, and performs correction of the detected error.

[0155] The payload error corrector 124 outputs pixel data subjected to error correction obtained by performing error correction on each of the basic block and the additional block to the byte-to-pixel converter 125. In the case where a parity check code is not inserted into the payload data supplied from the packet separator 123, the payload data supplied from the packet separator 123 is output to the byte-to-pixel converter 125 as it is.

[0156] The byte-to-pixel converter 125 removes payload padding data included in the payload data provided from the payload error corrector 124 under the control of the data remover 133 .

[0157] In addition, the byte-to-pixel converter 125 performs byte-to-pixel conversion, converting the data of each pixel in bytes obtained by removing the payload padding data into pixel data in units of, for example, 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits. The conversion performed in the byte-to-pixel converter 125 is opposite to the pixel-to-byte conversion performed by the pixel-to-byte converter 62 of the transmission unit 22.

[0158] The byte-to-pixel converter 125 outputs the pixel data obtained by the byte-to-pixel conversion in units of, for example, 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits to the frame data output section 141. In the frame data output section 141, for example, valid pixels per row identified by a valid row of header information are generated from the pixel data obtained by the byte-to-pixel converter 125, and one frame of image is generated by arranging each row according to the row number of the header information.

[0159] The state controller 131 of the LINK-RX protocol manager 121 manages the state of the link layer of the receiving unit 31 .

[0160] The header error corrector 132 acquires three sets of header information and cyclic redundancy check codes based on the header data supplied from the packet separator 123. The header error corrector 132 performs error detection calculation, which is calculation for detecting errors in the header information, for each set of header information and cyclic redundancy check code by using the cyclic redundancy check code of the same set as the header information.

[0161] In addition, the header error corrector 132 estimates the correct header information based on at least one of the error detection result of the header information of each group and the comparison result of the data determined by the error detection calculation, and outputs the estimated correct header information and the decoding result. The data determined by the error detection calculation is a value determined by applying the cyclic redundancy check generator polynomial to the header information. In addition, the decoding result is information indicating decoding success or decoding failure.

[0162] It is assumed that the three groups of header information and cyclic redundancy check codes are respectively group 1, group 2, and group 3. In this case, the header error corrector 132 obtains whether the header information of group 1 includes an error (error detection result) and data 1 as data determined by the error detection calculation through error detection calculation on group 1. In addition, the header error corrector 132 obtains whether the header information of group 2 includes an error and data 2 as data determined by the error detection calculation through error detection calculation on group 2. The header error corrector 132 obtains whether the header information of group 3 includes an error and data 3 as data determined by the error detection calculation through error detection calculation on group 3.

[0163] Furthermore, the header error corrector 132 determines each of whether Data 1 and Data 2 match, whether Data 2 and Data 3 match, and whether Data 3 and Data 1 match.

[0164] For example, when no error is detected in all error detection calculations for Group 1, Group 2, and Group 3, and the comparison results of the data determined by the error detection calculations all match, the header error corrector 132 selects information indicating successful decoding as the decoding result. In addition, the header error corrector 132 estimates that all header information is correct, and selects any one of the header information of Group 1, the header information of Group 2, and the header information of Group 3 as output information.

[0165] On the other hand, in the case where no error is detected by the error detection calculation only for group 1, the header error corrector 132 selects information indicating successful decoding as the decoding result. In addition, the header error corrector 132 estimates that the header information of group 1 is correct and selects the header information of group 1 as output information.

[0166] Furthermore, in the case where no error is detected by the error detection calculation only for group 2, the header error corrector 132 selects information indicating successful decoding as the decoding result. In addition, the header error corrector 132 estimates that the header information of group 2 is correct and selects the header information of group 2 as output information.

[0167] In the case where no error is detected by the error detection calculation only for group 3, the header error corrector 132 selects information indicating successful decoding as the decoding result. In addition, the header error corrector 132 estimates that the header information of group 3 is correct and selects the header information of group 3 as output information.

[0168] The header error corrector 132 outputs the decoding result and output information selected in the above manner to the register 142, and causes the register 142 to store the decoding result and output information. In this way, the header information error correction of the header error corrector 132 is performed by detecting the header information without error from the plurality of header information using the cyclic redundancy check code and outputting the detected header information.

[0169] The data remover 133 controls the channel integrator 122 to remove the channel stuffing data, and controls the byte-to-pixel converter 125 to remove the payload stuffing data.

[0170] Based on the footer data provided from the packet separator 123, the footer error detector 134 acquires the cyclic redundancy check code stored in the footer. The footer error detector 134 performs error detection calculation by using the acquired cyclic redundancy check code to detect an error in the payload data. The footer error detector 134 outputs an error detection result and causes the register 142 to store the error detection result.

[0171] [Overview of Operations of the Sensor Module 11 and the Digital Signal Processor 12]

[0172] Next, an overview of the operations of the sensor module 11 and the digital signal processor 12 is described. The operation of an imaging device including the transmission system 1 is described as an example.

[0173] The imaging unit 21 of the sensor module 11 performs imaging when an instruction to start imaging is given by, for example, pressing a shutter button provided in the imaging device. The frame data input section 52 ( Figure 6 ) By outputting the data of each pixel in sequence, the pixel data included in a frame of image obtained by imaging is output to the sending unit 22.

[0174] Through the data transmission process of the transmission unit 22 , a packet including a payload storing pixel data corresponding to one line is generated, and the packet data included in the packet is transmitted to the reception unit 31 .

[0175] The receiving unit 31 performs data receiving processing. Through the data receiving processing, the receiving unit 31 receives the packet data transmitted from the transmitting unit 22 and outputs the pixel data stored in the payload to the image processing unit 32.

[0176] The data transmission processing performed by the transmission unit 22 and the data reception processing performed by the reception unit 31 are alternately performed for the pixel data corresponding to one row. That is, if the pixel data of a given row is transmitted by the data transmission processing, the data reception processing is performed. If the pixel data of one row is received by the data reception processing, the data transmission processing is performed for the pixel data of the next row. The data transmission processing of the transmission unit 22 and the data reception processing of the reception unit 31 can be appropriately performed in parallel in time.

[0177] When transmission and reception of pixel data of all rows included in one frame image are completed, the frame data output section 141 of the image processing unit 32 generates one frame image based on the pixel data supplied from the receiving unit 31 .

[0178] [1.3 Modification Example of Transmission System 1 According to One Embodiment]

[0179] like Figures 8 to 11 As described, in the transmission system 1 according to an embodiment, a stuffing code may be inserted into the payload data to fill the difference between the transmission rate (pixel data band) of the pixel data input from the imaging unit 21 to the transmitting unit 22 and the transmission rate (physical layer transmission band) of the pixel data transmitted from the transmitting unit 22 to be input to the receiving unit 31. The stuffing code insertion rate is determined by the operation of the sensor module 11 as the transmitting side, but the digital signal processor 12 as the receiving side has no means of finding the stuffing code insertion rate and must be configured to be able to receive data including any type of stuffing code inserted.

[0180] Therefore, described below is a technique that enables finding a stuffing code insertion rate on the receiving side as an improved example of the transmission system 1 according to one embodiment.

[0181] It should be noted that, when the physical layer transmission band is larger than the pixel data band and a predetermined condition is satisfied, the stuffing code is inserted into the payload. For example, the stuffing code is inserted when the following conditional expression (A) is satisfied.

[0182] CIS_Bandwidth×(57 / 56)×(5 / 4) <PHY_Bandwidth……(A)

[0183] Here, in the conditional expression (A), CIS_Bandwidth corresponds to the pixel data band input from the imaging unit 21 to the transmission unit 22, and is represented by the following conditional expression (B).

[0184] CIS_Bandwidth = pixel_clock_rate * PIXEL_BIT... (B), where

[0185] pixel_clock_rate: pixel input rate [megapixels / second], and

[0186] PINXEL_BIT: The number of bits per pixel.

[0187] Furthermore, in the conditional expression (A), PHY_Bandwidth corresponds to the physical layer transmission band of the pixel data transmitted from the transmission unit 22 to be input to the reception unit 31 , and is represented by the following conditional expression (C).

[0188] PHY_Bandwidth=output_bit_rate*Lane_NUM……(C), where

[0189] Output_bit_rate: output bit rate [bits / second], and

[0190] Lane_NUM: The channel number of the output channel.

[0191] Furthermore, in conditional expression (A), (57 / 56) is the data transmission efficiency when 4 parity bits are added, and is calculated in the following manner.

[0192] (224+4) / 224=57 / 56

[0193] Furthermore, in the conditional expression (A), (5 / 4) is the transmission efficiency of the data subjected to 8B10B conversion, and is calculated in the following manner.

[0194] 10 / 8=5 / 4

[0195] Fig.12 A first example of a modified example of the transmission unit 22 in the transmission system 1 according to one embodiment is shown.

[0196] exist Fig.12 In the first example shown, Figure 6 The illustrated configuration further includes an insertion rate calculator 75 that calculates a stuffing code insertion rate in the LINK-TX protocol manager 61 of the transmission unit 22 .

[0197] It should be noted that the stuffing code insertion rate represents the ratio of the stuffing code length to the payload length. As described above, after the data is allocated to the channels, the stuffing code is inserted by the control code inserter 91.

[0198] Fig.13An example is shown in which data indicating a stuffing code insertion rate is added to a header.

[0199] For example, data indicating the stuffing code insertion rate calculated by the insertion rate calculator 75 may be added to a reserved area in the header, such as Fig.13 The header generator 72 generates a header that adds data indicating a stuffing code insertion rate to a reserved area, for example.

[0200] In this case, the receiving unit 31 can receive a packet including data indicating a stuffing code insertion rate in a header via a channel. Therefore, on the receiving side, for example, the frame data output section 141 and the system controller 143 can find the stuffing code insertion rate.

[0201] Fig.14 A second example of a modified example of the transmission unit 22 in the transmission system 1 according to one embodiment is shown.

[0202] For example, the register 53 on the transmission side may be made to store data indicating the stuffing code insertion rate calculated by the insertion rate calculator 75, such as Fig.14 The register 53 can output data indicating the stuffing code insertion rate to the receiving side via a path different from the channel as the packet transmission path. The path different from the channel can be, for example, Figure 1 and Figure 2 The control line 13 shown. On the receiving side, data indicating the stuffing code insertion rate can be received via a path different from the packet transmission path, and the register 142 on the receiving side can be made to store the data. Therefore, on the receiving side, for example, the frame data output section 141 and the system controller 143 can find the stuffing code insertion rate. It should be noted that a portion other than the register 142 can store the data indicating the stuffing code insertion rate. For example, the frame data output section 141 or the system controller 143 can store the data indicating the insertion rate.

[0203] Fig.15 A third example of a modified example of the transmission unit 22 in the transmission system 1 according to one embodiment is shown.

[0204] In addition, for example, data indicating the stuffing code insertion rate calculated by the insertion rate calculator 75 may be added to the embedded data area, such as Fig.15 It should be noted that although Fig.15 An example is shown in which the front virtual area A3 includes the embedded data area, but the embedded data area may be inserted in the rear virtual area A4. The packet generator 64 generates a packet that adds data indicating a stuffing code insertion rate to the embedded data area, for example.

[0205] In this case, the receiving unit 31 can receive a packet including data indicating the stuffing code insertion rate in the virtual area via the channel. Therefore, on the receiving side, for example, the frame data output section 141 and the system controller 143 can find the stuffing code insertion rate.

[0206] [1.3 Effect]

[0207] As described above, the improved example of the transmission system 1 according to one embodiment makes it possible to find the stuffing code insertion rate. This configuration makes it possible to perform optimal data processing. On the receiving side, for example, the frame data output section 141 and the system controller 143 can find the stuffing code insertion rate and the payload length.

[0208] It should be noted that the effects described in this specification are merely examples and not limiting, and other effects may be achieved. The same applies to the effects of the following other embodiments.

[0209] <2. Other embodiments>

[0210] The technology according to the present disclosure is not limited to the description of one embodiment described above, and various modifications may be made.

[0211] For example, the present technology may have the following configurations.

[0212] According to the present technology having the following configuration, a stuffing code insertion rate can be found. This configuration makes it possible to perform optimal data processing. (1)

[0214] A sending device, comprising:

[0215] a transmitting unit configured to output a plurality of packets to a transmitting channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in one frame of an image; and

[0216] An insertion rate calculator is configured to calculate an insertion rate of a stuffing code inserted into the payload to fill a difference between a transmission rate of pixel data input to the transmission unit and a transmission rate of pixel data output from the transmission unit to the transmission channel. (2)

[0218] The sending device according to (1), further comprising:

[0219] The header generator is configured to add data indicating the insertion rate of the stuffing code calculated by the insertion rate calculator to the header. (3)

[0221] The sending device according to (1), further comprising:

[0222] A register is configured to store data indicating the insertion rate of the stuffing code calculated by the insertion rate calculator. (4)

[0224] The transmission device according to (3), wherein the register is configured to output data indicating an insertion rate of the stuffing code to a reception device configured to receive the packet via the transmission channel via a path different from a transmission path of the packet. (5)

[0226] The sending device according to (1), further comprising:

[0227] The packet generator is configured to generate a packet including a dummy area in the payload including the substitute pixel data, and add data indicating an insertion rate of the stuffing code to the dummy area. (6)

[0229] A sending device according to any one of (1) to (5), wherein a padding code is inserted into a payload when a sending rate of pixel data output from a sending unit to a sending channel is greater than a sending rate of pixel data input to the sending unit and a predetermined condition is satisfied. (7)

[0231] A receiving device, comprising:

[0232] A receiving unit is configured to receive a plurality of packets from a transmitting unit of a transmitting device via a transmitting channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in a frame of an image, wherein

[0233] The receiving device is configured to receive data about the insertion rate of the stuffing code from the transmitting device, and the stuffing code is inserted into the payload to fill the difference between the transmission rate of the pixel data input to the transmitting unit and the transmission rate of the pixel data output from the transmitting unit to the transmitting channel. (8)

[0235] The reception device according to (7), wherein the reception unit is configured to receive a packet including data on an insertion rate of the stuffing code via the transmission channel. (9)

[0237] The receiving device according to (7), wherein the receiving device is configured to receive the data indicating the insertion rate of the stuffing code via a path different from a transmission path of the packet. (10)

[0239] A transmission system, comprising:

[0240] a transmitting device; and

[0241] A receiving device, wherein

[0242] The sending device comprises:

[0243] a transmitting unit configured to output a plurality of packets to a transmitting channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in one frame of an image, and

[0244] An insertion rate calculator is configured to calculate an insertion rate of a stuffing code inserted into the payload to fill a difference between a transmission rate of pixel data input to the transmission unit and a transmission rate of pixel data output from the transmission unit to the transmission channel. (11)

[0246] The transmission system according to (10), wherein the receiving device

[0247] The receiving unit is configured to receive a plurality of packets from a transmitting unit of a transmitting device via a transmitting channel, and

[0248] The method is configured to receive data on the insertion rate of the stuffing code from the transmitting device.

[0249] This application claims the benefit of Japanese Priority Patent Application No. 2019-209580 filed in the Japan Patent Office on November 20, 2019, the entire contents of which are incorporated herein by reference.

[0250] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors within the scope of the appended claims or the equivalents thereof.

Claims

1. A sending device, comprising: a transmitting unit configured to output a plurality of packets to a transmitting channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in one frame of an image; an insertion rate calculator configured to calculate an insertion rate of a stuffing code inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission channel, and a header generator configured to add data indicating the insertion rate of the stuffing code calculated by the insertion rate calculator to the header so that a receiving side can obtain the stuffing code insertion rate, Wherein, when the transmission rate of the pixel data output from the transmitting unit to the transmitting channel is greater than the transmission rate of the pixel data input to the transmitting unit and a predetermined condition is satisfied, the filling code is inserted into the payload, and the predetermined condition is CIS_Bandwidth×(57 / 56)×(5 / 4) < PHY_Bandwidth, wherein CIS_Bandwidth corresponds to the pixel data band input to the transmitting unit, and PHY_Bandwidth corresponds to the physical layer transmission band of the pixel data sent from the transmitting unit to be input to the receiving unit.

2. The sending device according to claim 1, further comprising: A register configured to store data indicating the insertion rate of the stuffing code calculated by the insertion rate calculator.

3. A receiving device, comprising: A receiving unit is configured to receive a plurality of packets from a transmitting unit of a transmitting device via a transmitting channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in a frame of an image, wherein The receiving device is configured to receive data related to an insertion rate of a stuffing code from the transmitting device, the stuffing code being inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmitting unit and a transmission rate of the pixel data output from the transmitting unit to the transmitting channel, the data indicating the insertion rate of the stuffing code being added to the header, Wherein, when the transmission rate of the pixel data output from the transmitting unit to the transmitting channel is greater than the transmission rate of the pixel data input to the transmitting unit and a predetermined condition is satisfied, the filling code is inserted into the payload, and the predetermined condition is CIS_Bandwidth×(57 / 56)×(5 / 4) < PHY_Bandwidth, wherein CIS_Bandwidth corresponds to the pixel data band input to the transmitting unit, and PHY_Bandwidth corresponds to the physical layer transmission band of the pixel data sent from the transmitting unit to be input to the receiving unit.

4. A transmission system comprising: Transmitting device; as well as A receiving device, wherein The sending device comprises: a transmitting unit configured to output a plurality of packets to a transmitting channel, each packet including a payload and a header added to the payload, the payload including pixel data corresponding to a row included in one frame of an image, an insertion rate calculator configured to calculate an insertion rate of a stuffing code inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission channel, and a header generator configured to add data indicating the insertion rate of the stuffing code calculated by the insertion rate calculator to the header so that a receiving side can obtain the stuffing code insertion rate, Wherein, when the transmission rate of the pixel data output from the transmitting unit to the transmitting channel is greater than the transmission rate of the pixel data input to the transmitting unit and a predetermined condition is satisfied, the filling code is inserted into the payload, and the predetermined condition is CIS_Bandwidth×(57 / 56)×(5 / 4) < PHY_Bandwidth, wherein CIS_Bandwidth corresponds to the pixel data band input to the transmitting unit, and PHY_Bandwidth corresponds to the physical layer transmission band of the pixel data sent from the transmitting unit to be input to the receiving unit.

5. The transmission system according to claim 4, wherein: The receiving device: comprising a receiving unit configured to receive a plurality of the packets from the sending unit of the sending device via the sending channel, and The receiving device is configured to receive data related to the insertion rate of the stuffing code from the sending device.

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