Memory control method, memory storage device, and memory control circuit unit

Abstract

The present invention provides a memory control method, a memory storage device, and a memory control circuit unit. The method includes: generating, by one of a plurality of processing circuits, a first operation instruction, where the first operation instruction indicates accessing a first memory group among a plurality of memory groups; and in response to first status information, sending a first instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation. The first status information reflects a first startup status of the first memory group, and the first instruction sequence does not include a control instruction sequence for starting up the first memory group. Thereby, the access efficiency of a multi-core memory control circuit unit for a rewritable non-volatile memory module can be improved.

Description

Technical Field

[0001] The present invention relates to a memory control technology, and more particularly to a memory control method, a memory storage device, and a memory control circuit unit. Background Art

[0002] The growth of smart phones, tablet computers, and notebook computers has been very rapid in recent years, resulting in a sharp increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (e.g., flash memories) have the characteristics of data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for being built into various portable multimedia devices exemplified above.

[0003] Generally, before a memory controller accesses a certain memory module, the memory controller needs to issue a specific operation instruction to activate this memory module. After activating this memory module, the memory controller can then issue an access instruction sequence to access this memory module. However, in the control mechanism of a multi-core memory controller, the multiple central processing units of the multi-core memory controller do not know which memory modules each other has accessed. Therefore, each central processing unit of the multi-core memory controller often sends the above specific operation instruction before each access to a memory module to attempt to activate the desired memory module. Such redundant behavior also causes the access performance of the multi-core memory controller to decline. Summary of the Invention

[0004] The present invention provides a memory control method, a memory storage device, and a memory control circuit unit, which can improve the access performance of a multi-core memory control circuit unit to a rewritable non-volatile memory module.

[0005] An exemplary embodiment of the present invention provides a memory control method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of memory groups. The memory control method includes: generating, by one of a plurality of processing circuits, a first operation instruction, where the first operation instruction indicates accessing a first memory group among the plurality of memory groups; and in response to first status information, sending a first instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation. The first status information reflects a first activation state of the first memory group, and the first instruction sequence does not include a control instruction sequence, and the control instruction sequence is used to activate the first memory group.

[0006] In an exemplary embodiment of the present invention, the first startup state includes a state in which the first memory group has been started.

[0007] In an exemplary embodiment of the present invention, the memory control method further includes: in response to second state information, sending a second instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform the access operation, where the second state information reflects a second startup state of the first memory group, and the second instruction sequence includes the control instruction sequence.

[0008] In an exemplary embodiment of the present invention, the second startup state includes a state in which the first memory group has not been started.

[0009] In an exemplary embodiment of the present invention, the second instruction sequence further includes an access instruction sequence, the access instruction sequence carries instruction information related to the access operation, and the control instruction sequence is transmitted to the first memory group before the access instruction sequence.

[0010] In an exemplary embodiment of the present invention, the control instruction sequence is used to adjust the on-chip termination circuit corresponding to the first memory group to a predetermined state.

[0011] In an exemplary embodiment of the present invention, the first operation instruction includes group identification information, the control instruction sequence, and the access instruction sequence, and the group identification information reflects that the memory group indicated by the first operation instruction for access is the first memory group.

[0012] In an exemplary embodiment of the present invention, the step of sending the first instruction sequence to the first memory group according to the first operation instruction in response to the first state information includes: ignoring the control instruction sequence according to the group identification information and the first state information; and sending the first instruction sequence to the first memory group according to the access instruction sequence.

[0013] In an exemplary embodiment of the present invention, the step of sending the first instruction sequence to the first memory group according to the first operation instruction in response to the first state information includes: updating an access flag corresponding to the first memory group according to the first operation instruction; comparing the access flag corresponding to the first memory group with a status flag corresponding to the first memory group; and sending the first instruction sequence to the first memory group according to the comparison result.

[0014] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of memory groups. The memory control circuit unit includes a plurality of processing circuits. One of the plurality of processing circuits is used to generate a first operation instruction. The first operation instruction instructs to access a first memory group among the plurality of memory groups. In response to first status information, the memory control circuit unit is used to send a first instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation, where the first status information reflects a first startup state of the first memory group, the first instruction sequence does not include a control instruction sequence, and the control instruction sequence is used to start the first memory group.

[0015] In an exemplary embodiment of the present invention, in response to second status information, the memory control circuit unit is further used to send a second instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform the access operation, where the second status information reflects a second startup state of the first memory group, and the second instruction sequence includes the control instruction sequence.

[0016] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit sending the first instruction sequence to the first memory group according to the first operation instruction in response to the first status information includes: ignoring the control instruction sequence according to the group identification information and the first status information; and sending the first instruction sequence to the first memory group according to the access instruction sequence.

[0017] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit sending the first instruction sequence to the first memory group according to the first operation instruction in response to the first status information includes: updating an access flag corresponding to the first memory group according to the first operation instruction; comparing the access flag corresponding to the first memory group with a status flag corresponding to the first memory group; and sending the first instruction sequence to the first memory group according to the comparison result.

[0018] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of memory groups, and the memory control circuit unit includes a plurality of processing circuits and an instruction sending circuit. The instruction sending circuit is connected to the plurality of processing circuits. One of the plurality of processing circuits is used to generate a first operation instruction. The first operation instruction instructs to access a first memory group among the plurality of memory groups. In response to first status information, the instruction sending circuit is used to send a first instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation, where the first status information reflects a first startup state of the first memory group, the first instruction sequence does not include a control instruction sequence, and the control instruction sequence is used to start the first memory group.

[0019] In an exemplary embodiment of the present invention, in response to second status information, the instruction sending circuit is further used to send a second instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform the access operation, where the second status information reflects a second startup state of the first memory group, and the second instruction sequence includes the control instruction sequence.

[0020] In an exemplary embodiment of the present invention, the operation of the instruction sending circuit to send the first instruction sequence to the first memory group according to the first operation instruction in response to the first status information includes: ignoring the control instruction sequence according to the group identification information and the first status information; and sending the first instruction sequence to the first memory group according to the access instruction sequence.

[0021] In an exemplary embodiment of the present invention, the operation of the instruction sending circuit to send the first instruction sequence to the first memory group according to the first operation instruction in response to the first status information includes: updating an access flag corresponding to the first memory group according to the first operation instruction; comparing the access flag corresponding to the first memory group with a status flag corresponding to the first memory group; and sending the first instruction sequence to the first memory group according to the comparison result.

[0022] Based on the above, after a first operation instruction indicating access to the first memory group is generated by one of the multiple processing circuits, in response to the first status information, the first instruction sequence can be sent to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation. In particular, the first instruction sequence does not include a control instruction sequence for starting the first memory group. Thereby, the access efficiency of the multi-core memory control circuit unit to the rewritable non-volatile memory module can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0027] Figure 5 is a schematic diagram of a memory control circuit unit and a rewritable non-volatile memory module shown according to an exemplary embodiment of the present invention;

[0028] Figure 6 is a schematic diagram of sending different types of instruction sequences according to an operation instruction in different states of a first memory group shown according to an exemplary embodiment of the present invention;

[0029] Figure 7 is a schematic diagram of sending different types of instruction sequences according to an operation instruction in different states of a first memory group shown according to an exemplary embodiment of the present invention;

[0030] Figure 8 is a flowchart of a memory control method shown according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0032] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0033] Figure 1 FIG. is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0034] Please refer to Figure 1 and Figure 2 As shown in FIG., the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus 110.

[0035] In an exemplary embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be connected to the I / O device 12 through the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0036] In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 in a wired or wireless manner.

[0037] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0038] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 a memory storage device 30 and a host system 31.

[0039] Figure 3 is a schematic diagram of a host system and a memory storage device shown in an exemplary embodiment of the present invention. Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be various non-volatile memory storage devices such as a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices such as an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342, etc., which directly connect the memory module to the substrate of the host system.

[0040] Figure 4 is a schematic diagram of a memory storage device shown in an exemplary embodiment of the present invention. Please refer toFigure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0041] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a single chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip containing the memory control circuit unit 42.

[0042] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware form and perform operations such as data writing, reading, and erasing in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0043] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which 1 bit can be stored in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which 2 bits can be stored in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which 3 bits can be stored in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which 4 bits can be stored in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0044] Each storage cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each storage cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the storage cell. This operation of changing the threshold voltage of the storage cell is also called "writing data to the storage cell" or "programming the storage cell". As the threshold voltage changes, each storage cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a storage cell belongs to, thereby obtaining the one or more bits stored in this storage cell.

[0045] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can form a plurality of physical programming units, and these physical programming units can form a plurality of physical erasure units. Specifically, the memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0046] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (such as management data like error correction codes). In an exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area can also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit for erasure. That is, each physical erasure unit contains the smallest number of memory cells to be erased together. For example, the physical erasure unit is a physical block.

[0047] Figure 5 It is a schematic diagram of a memory control circuit unit and a rewritable non-volatile memory module shown in an exemplary embodiment of the present invention. Please refer to Figure 5 , the memory control circuit unit 42 can include a processor core 51 and an instruction sending circuit 52. The processor core 51 is connected to the instruction sending circuit 52. The processor core 51 is used to control the overall operation of the memory control circuit unit 11 and / or the memory storage device 10. In particular, the processor core 51 is a multi-core architecture, and the memory control circuit unit 11 is a multi-core memory control circuit unit.

[0048] The processor core 51 may include processing circuits 511, 512, and a register 513. The register 513 is connected to the processing circuits 511, 512, and the instruction sending circuit 52. The processing circuits 511 and 512 may each include a processing circuit such as a Central Processing Unit (CPU) or a microprocessor. When accessing the rewritable non-volatile memory module 43, at least one of the processing circuits 511 and 512 may generate an operation instruction and store the operation instruction in the register 513. The instruction sending circuit 52 may send one or more instruction sequences to the rewritable non-volatile memory module 43 according to the operation instruction in the register 513 to instruct the rewritable non-volatile memory module 43 to perform a corresponding access operation. In addition, the total number of the processing circuits 511 and 512 may be more, and the present invention does not limit it.

[0049] In an exemplary embodiment, the instruction sending circuit 52 is a hardware circuit. In an exemplary embodiment, the instruction sending circuit 52 may also be implemented as a software or firmware module.

[0050] In an exemplary embodiment, the memory control circuit unit 42 may further include various circuit modules such as a host interface, a memory interface, an error checking and correcting circuit, a buffer memory, and a power management circuit. The host interface can be used to connect the memory control circuit unit 42 to Figure 1 the host system 11. The memory interface can be used to transfer data and / or signals between the memory control circuit unit 42 and the rewritable non-volatile memory module 43. The error checking and correcting circuit can be used to perform error detection and / or error correction on the data read from the rewritable non-volatile memory module 43. The buffer memory can be used to temporarily store data. The power management circuit can be used to manage the power supplied to the memory storage device 10.

[0051] The rewritable non-volatile memory module 43 includes a plurality of memory groups 53(0) to 53(m). Each of the memory groups 53(0) to 53(m) may include a plurality of memory cells. For example, each of the memory groups 53(0) to 53(m) may refer to a Chip Enabled (CE) area. The memory control circuit unit 11 may access any one of the memory groups 53(0) to 53(m) individually or in parallel via channels (also referred to as memory channels) 501(0) to 501(n). In addition, the present invention does not limit the total number of the channels 501(0) to 501(n) and the memory groups 53(0) to 53(m). n may be the same as or different from m.

[0052] In an exemplary embodiment, one of the processing circuits 511 and 512 may generate an operation instruction (also referred to as a first operation instruction). The first operation instruction may be used to indicate accessing a specific memory group (also referred to as a first memory group) among the memory groups 53(0) to 53(m). For example, the first operation instruction may be used to indicate reading data from a physical address in the first memory group or writing data to a physical address in the first memory group. The first operation instruction may be stored in the register 513.

[0053] In response to specific status information (also referred to as first status information), the instruction sending circuit 52 may send an instruction sequence (also referred to as a first instruction sequence) to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation corresponding to the first operation instruction. The first status information may reflect the status of the first memory group (also referred to as a first startup status). In particular, the first instruction sequence may not include a specific instruction sequence (also referred to as a control instruction sequence), and the control instruction sequence is used to start the first memory group.

[0054] In an exemplary embodiment, the operation of starting the first memory group includes adjusting the on-die termination (ODT) circuit corresponding to the first memory group to a predetermined state. That is, the control instruction sequence may be used to adjust the on-die termination circuit corresponding to the first memory group to the predetermined state. After adjusting the on-die termination circuit corresponding to the first memory group to the predetermined state, the on-die termination circuit may provide a termination impedance to the first memory group to reduce signal reflection or noise of the first memory group on the signal transmission path.

[0055] In an exemplary embodiment, the operation of adjusting the on-die termination circuit corresponding to the first memory group to a predetermined state may include adjusting the termination impedance provided by the on-die termination circuit. For example, adjusting the impedance value of the termination impedance to a predetermined value. For example, the termination impedance may be provided by an impedance element (such as a resistor) in the on-die termination circuit. Alternatively, in an exemplary embodiment, the operation of adjusting the on-die termination circuit corresponding to the first memory group to a predetermined state may also include turning on or activating the on-die termination circuit.

[0056] In an exemplary embodiment, the first startup state includes a state in which the first memory group has been started. In particular, in the state where the first memory group has been started, the on-chip termination circuit corresponding to the first memory group is already in the predetermined state. Therefore, when the first operation instruction needs to be executed, if the first memory group is in the started state, the instruction sending circuit 52 can send a first instruction sequence that does not include the control instruction sequence to the first memory group according to the first operation instruction. Thereby, in the state where the first memory group has been started, the first memory group can skip the program of adjusting the on-chip termination circuit and directly execute the access operation corresponding to the first operation instruction according to the first instruction sequence, thereby effectively improving the access efficiency of the first memory group.

[0057] In an exemplary embodiment, in response to another state information (also referred to as the second state information), the instruction sending circuit 52 can send another instruction sequence (also referred to as the second instruction sequence) to the first memory group according to the first operation instruction to instruct the first memory group to execute the access operation corresponding to the first operation instruction. Similar to the first state information, the second state information can also reflect the state of the first memory group (also referred to as the second startup state). However, the first startup state is different from the second startup state. In particular, the second instruction sequence can include the control instruction sequence for starting the first memory group.

[0058] In an exemplary embodiment, the second startup state includes a state in which the first memory group has not been started. In particular, in the state where the first memory group has not been started, the on-chip termination circuit corresponding to the first memory group is not in the predetermined state. Therefore, when the first operation instruction needs to be executed, if the first memory group is in the not-started state, the instruction sending circuit 52 can send a second instruction sequence that includes the control instruction sequence to the first memory group according to the first operation instruction. Thereby, in the state where the first memory group has not been started, according to the second instruction sequence, the on-chip termination circuit corresponding to the first memory group can be first adjusted to the predetermined state. After adjusting the on-chip termination circuit corresponding to the first memory group to the predetermined state, the first memory group can execute the access operation corresponding to the first operation instruction according to the remaining content in the second instruction sequence. Thereby, the signal transmission quality of the first memory group can also be ensured.

[0059] Figure 6 It is a schematic diagram showing different types of instruction sequences being sent according to operation instructions in different states of the first memory group as shown in the exemplary embodiment of the present invention. Please refer to Figure 6, assume that the operation instruction 61 in register 513 indicates accessing memory group 53(0) (i.e., the first memory group). According to the operation instruction 61, the instruction sending circuit 52 can obtain the status information corresponding to the memory group 53(0), which can reflect the current status of the memory group 53(0). For example, according to the operation instruction 61, the instruction sending circuit 52 can obtain one of the first status information and the second status information. The first status information reflects that the first memory group has been activated, while the second status information reflects that the first memory group has not been activated.

[0060] In an exemplary embodiment, if the obtained status information is the first status information (indicating that the memory group 53(0) has been activated), the instruction sending circuit 52 can send the first instruction sequence to the memory group 53(0) according to the operation instruction 61. For example, the first instruction sequence can include an instruction sequence (also referred to as an access instruction sequence) 601. The instruction sequence 601 is used to carry instruction information related to the access operation to be performed. In response to the instruction sequence 601, the memory group 53(0) can skip (i.e., not execute) the program for adjusting the on-chip termination circuit corresponding to the memory group 53(0), and directly execute the access operation corresponding to the operation instruction 61 (such as reading data from the memory group 53(0) or writing data into the memory group 53(0)).

[0061] In an exemplary embodiment, if the obtained status information is the second status information (indicating that the memory group 53(0) has not been activated), the instruction sending circuit 52 can send the second instruction sequence to the memory group 53(0) according to the operation instruction 61. For example, the second instruction sequence can include instruction sequences 601 and 602. The instruction sequence 601 is used to carry instruction information related to the access operation to be performed. The instruction sequence 602 is used to activate the memory group 53(0) (such as adjusting the on-chip termination circuit corresponding to the memory group 53(0) to a predetermined state). In particular, the instruction sequence 602 will be transmitted to the memory group 53(0) before the instruction sequence 601, to indicate that the memory group 53(0) adjusts the on-chip termination circuit corresponding to the memory group 53(0) before executing the access operation corresponding to the operation instruction 61.

[0062] That is to say, in the state where the memory group 53(0) has not been activated, the memory group 53(0) can first receive the instruction sequence 602, and then receive the instruction sequence 601. In response to the instruction sequence 602, the memory group 53(0) can adjust the on-chip termination circuit corresponding to the memory group 53(0). Then, in response to the instruction sequence 601, the memory group 53(0) can execute the access operation corresponding to the operation instruction 61 (such as reading data from the memory group 53(0) or writing data into the memory group 53(0)).

[0063] In other words, in Figure 6 in an exemplary embodiment, the instruction sending circuit 52 needs to send a second instruction sequence including the instruction sequence 602 to the memory group 53(0) only when the obtained status information is the second status information. If the obtained status information is the first status information, the instruction sequence sent by the instruction sending circuit 52 to the memory group 53(0) may not include the instruction sequence 602. Thereby, it is possible to avoid repeatedly adjusting the on-chip termination circuit corresponding to the memory group 53(0) when the memory group 53(0) has been activated, thereby accelerating the access performance of the memory group 53(0). For example, in an exemplary embodiment, by skipping (i.e., not executing) the procedure of adjusting the on-chip termination circuit corresponding to the memory group 53(0) and directly executing the access operation corresponding to the operation instruction 61, the access time can be saved by about 150 nanoseconds (ns), but the present invention is not limited thereto.

[0064] Figure 7 is a schematic diagram showing different types of instruction sequences being sent according to operation instructions in different states of a first memory group as shown in an exemplary embodiment of the present invention. Please refer to Figure 7 , in an exemplary embodiment, the operation instruction 61 may include group identification information 701, a control instruction sequence 702, and an access instruction sequence 703. The group identification information 701, the control instruction sequence 702, and the access instruction sequence 703 may be continuously stored in the register 513.

[0065] The group identification information 701 corresponds to the memory group 53(0). That is, the group identification information 701 can reflect that the memory group indicated by the operation instruction 61 for access is the memory group 53(0). The control instruction sequence 702 can carry control information for activating the memory group 53(0) (such as adjusting the on-chip termination circuit corresponding to the memory group 53(0)). The access instruction sequence 703 can be used to carry instruction information related to the access operation to be performed. For example, the instruction information can reflect that the access operation to be performed is a read, write, or erase operation and the physical address to be accessed, etc.

[0066] In an exemplary embodiment, the instruction sending circuit 52 may determine that the currently accessed memory group 53(0) has been activated according to the group identification information 702 and the obtained first status information. In the state where the memory group 53(0) has been activated, the instruction sending circuit 52 may ignore the control instruction sequence 702 and send a first instruction sequence according to the access instruction sequence 703. For example, the instruction sending circuit 52 may filter out the control instruction sequence 702 (i.e., not send the control instruction sequence 702) and reflect (such as add, transfer, or copy) the instruction information in the access instruction sequence 703 into the instruction sequence 601. Then, the instruction sending circuit 52 may send the instruction sequence 601 to the memory group 53(0) to instruct the memory group 53(0) to perform an access operation corresponding to the operation instruction 61.

[0067] In an exemplary embodiment, the instruction sending circuit 52 may determine that the currently accessed memory group 53(0) has not been activated according to the group identification information 702 and the obtained second status information. In the state where the memory group 53(0) has not been activated, the instruction sending circuit 52 may send a second instruction sequence according to the control instruction sequence 702 and the access instruction sequence 703. For example, the instruction sending circuit 52 may reflect (such as add, transfer, or copy) the instruction information in the access instruction sequence 703 into the instruction sequence 601 and reflect (such as add, transfer, or copy) the control information in the control instruction sequence 702 into the instruction sequence 602. Then, the instruction sending circuit 52 may sequentially send the instruction sequences 602 and 601 to the memory group 53(0) to instruct the memory group 53(0) to activate the on-chip termination circuit corresponding to the memory group 53(0) and then perform an access operation corresponding to the operation instruction 61.

[0068] In an exemplary embodiment, according to the group identification information 701, the instruction sending circuit 52 may obtain the status information corresponding to the memory group 53(0). The status information may include a status flag. The value of this status flag may reflect the status of the first memory group. For example, when the value of this status flag is "1" (i.e., the obtained status information is the first status information), it indicates that the first memory group is in an activated state, and when the value of this status flag is "0" (i.e., the obtained status information is the second status information), it indicates that the first memory group is in an unactivated state, and the present invention is not limited thereto. In an exemplary embodiment, the instruction sending circuit 52 may store this status flag in its internal storage space (such as an internal register) and may update this status flag according to the change in the status of the first memory group.

[0069] In an exemplary embodiment, according to the group identification information 701 (or the operation instruction 61), the instruction sending circuit 52 can update the access flag corresponding to the memory group 53(0). For example, according to the group identification information 701, the instruction sending circuit 52 can set the value of the access flag corresponding to the memory group 53(0) to "1". After reading the status information corresponding to the memory group 53(0), the instruction sending circuit 52 can compare the access flag corresponding to the memory group 53(0) with the status flag corresponding to the memory group 53(0). If the access flag corresponding to the memory group 53(0) is the same as the status flag corresponding to the memory group 53(0) (for example, both are the value "1"), it means that the memory group 53(0) indicated by the operation instruction 61 for access has been activated. Or, if the access flag corresponding to the memory group 53(0) is different from the status flag corresponding to the memory group 53(0) (for example, the value of the access flag is "1" and the value of the status flag is "0"), it means that the memory group 53(0) indicated by the operation instruction 61 for access has not been activated yet. The instruction sending circuit 52 can send the first instruction sequence or the second instruction sequence to the memory group 53(0) according to the comparison result.

[0070] In an exemplary embodiment, in response to a certain comparison result (also called the first comparison result) (that is, the access flag corresponding to the memory group 53(0) is the same as the status flag corresponding to the memory group 53(0)), the instruction sending circuit 52 can send the instruction sequence 601 to the memory group 53(0) according to the access instruction sequence 703. Or, in response to another comparison result (also called the second comparison result) (that is, the access flag corresponding to the memory group 53(0) is different from the status flag corresponding to the memory group 53(0) (for example, the value of the access flag is "1" and the value of the status flag is "0"), it means that the memory group 53(0) indicated by the operation instruction 61 for access has not been activated yet. At this time, the instruction sending circuit 52 can send the instruction sequences 601 and 602 to the memory group 53(0) according to the control instruction sequence 702 and the access instruction sequence 703.

[0071] Please go back to Figure 5, in an exemplary embodiment, the memory control circuit unit 11 may access memory banks 53(0) and 53(1) via channel 501(0). In particular, when memory bank 53(0) is activated (i.e., the on-chip termination circuit corresponding to memory bank 53(0) is adjusted to a predetermined state), memory bank 53(1) is switched to an unactivated state. Similarly, when memory bank 53(1) is activated (i.e., the on-chip termination circuit corresponding to memory bank 53(1) is adjusted to a predetermined state), memory bank 53(0) is switched to an unactivated state. The memory control circuit unit 11 (such as the instruction sending circuit 52) may update the status flags corresponding to memory banks 53(0) and 53(1) according to the current states (i.e., whether they are activated) of memory banks 53(0) and 53(1).

[0072] In an exemplary embodiment, the memory control circuit unit 11 may include more combinations of processor cores 51 and instruction sending circuits 52. Each combination of a processor core 51 and an instruction sending circuit 52 may control and access one of memory banks 53(i) (or 53(i) and 53(i + 1)) via one of channels 501(0) to 501(n). i is a positive integer between zero and m - 1.

[0073] Figure 8 is a flowchart of a memory control method shown in an exemplary embodiment of the present invention. Please refer to Figure 8 , in step S801, a first operation instruction is generated by one of a plurality of processing circuits, where the first operation instruction indicates accessing a first memory bank among the plurality of memory banks. After step S801, one of steps S802 and S803 may be executed.

[0074] In an exemplary embodiment, in response to first status information, in step S802, a first instruction sequence is sent to the first memory bank according to the first operation instruction to instruct the first memory bank to perform an access operation. In particular, the first status information reflects a first activation state of the first memory bank, the first instruction sequence does not include a control instruction sequence, and the control instruction sequence is used to activate the first memory bank.

[0075] Alternatively, in an exemplary embodiment, in response to second status information, in step S803, a second instruction sequence is sent to the first memory bank according to the first operation instruction to instruct the first memory bank to perform an access operation. In particular, the second status information reflects a second activation state of the first memory bank, and the second instruction sequence includes the control instruction sequence to activate the first memory bank.

[0076] However,Figure 8 Each step in the above has been described in detail, so it will not be elaborated here. It should be noted that Figure 8 each step in can be implemented as multiple pieces of code or circuits, and the present invention does not limit this. In addition, Figure 8 the method of can be used in combination with the above exemplary embodiments or used alone, and the present invention does not limit this.

[0077] In summary, the present invention's exemplary embodiments propose to send different types of instruction sequences according to the same operation instruction in different states of the memory group, which can effectively improve the access efficiency of the multi-core memory control circuit unit to the memory group without affecting the operation stability of the memory group.

[0078] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that, For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory groups, and the memory control method includes: Generating, by one of a plurality of processing circuits, a first operation instruction, wherein the first operation instruction instructs accessing a first memory group among the plurality of memory groups; and In response to first status information, sending a first instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation, wherein the first status information reflects a first startup state of the first memory group, the first instruction sequence does not include a control instruction sequence for starting the first memory group, and the control instruction sequence adjusts an on-chip termination circuit corresponding to the first memory group to a predetermined state to start the first memory group.

2. The memory control method according to claim 1, wherein the first startup state includes a state in which the first memory group has been started.

3. The memory control method according to claim 1, further comprising: In response to second status information, sending a second instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform the access operation, wherein the second status information reflects a second startup state of the first memory group, and the second instruction sequence includes the control instruction sequence.

4. The memory control method according to claim 3, wherein the second startup state includes a state in which the first memory group has not been started.

5. The memory control method according to claim 3, wherein the second instruction sequence further includes an access instruction sequence, the access instruction sequence carries instruction information related to the access operation, and the control instruction sequence is transmitted to the first memory group before the access instruction sequence.

6. The memory control method according to claim 1, wherein the first operation instruction includes group identification information, the control instruction sequence, and an access instruction sequence, and the group identification information reflects that the memory group indicated by the first operation instruction to be accessed is the first memory group.

7. The memory control method according to claim 6, wherein the step of sending the first instruction sequence to the first memory group according to the first operation instruction in response to the first status information includes: Ignoring the control instruction sequence according to the group identification information and the first status information; And Sending the first instruction sequence to the first memory group according to the access instruction sequence.

8. The memory control method according to claim 1, wherein the step of sending the first instruction sequence to the first memory group according to the first operation instruction in response to the first status information includes: Updating an access flag corresponding to the first memory group according to the first operation instruction; Comparing the access flag corresponding to the first memory group with a status flag corresponding to the first memory group; And Send the first instruction sequence to the first memory group according to the comparison result.

9. A memory storage device, characterized in that, Comprising: A connection interface unit for connecting to a host system; A rewritable non-volatile memory module; And A memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory groups, the memory control circuit unit includes a plurality of processing circuits, one of the plurality of processing circuits is used to generate a first operation instruction, and the first operation instruction instructs to access a first memory group among the plurality of memory groups, in response to first status information, the memory control circuit unit is used to send a first instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation, wherein the first status information reflects a first startup state of the first memory group, the first instruction sequence does not include a control instruction sequence for starting the first memory group, and the control instruction sequence adjusts an on-chip termination circuit corresponding to the first memory group to a predetermined state to start the first memory group.

10. The memory storage device according to claim 9, wherein the first startup state includes a state in which the first memory group has been started.

11. The memory storage device according to claim 9, wherein in response to second status information, the memory control circuit unit is further used to send a second instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform the access operation, wherein the second status information reflects a second startup state of the first memory group, and the second instruction sequence includes the control instruction sequence.

12. The memory storage device according to claim 11, wherein the second startup state includes a state in which the first memory group has not been started.

13. The memory storage device according to claim 11, wherein the second instruction sequence further includes an access instruction sequence, the access instruction sequence carries instruction information related to the access operation, and the control instruction sequence is transmitted to the first memory group before the access instruction sequence.

14. The memory storage device according to claim 9, wherein the first operation instruction includes group identification information, the control instruction sequence and the access instruction sequence, and the group identification information reflects that the memory group indicated by the first operation instruction to be accessed is the first memory group.

15. The memory storage device according to claim 14, wherein in response to the first status information, the operation of the memory control circuit unit sending the first instruction sequence to the first memory group according to the first operation instruction includes: Ignoring the control instruction sequence according to the group identification information and the first status information; And Sending the first instruction sequence to the first memory group according to the access instruction sequence.

16. The memory storage device according to claim 9, wherein in response to the first status information, the operation of the memory control circuit unit for sending the first instruction sequence to the first memory group according to the first operation instruction includes: Updating an access flag corresponding to the first memory group according to the first operation instruction; Comparing the access flag corresponding to the first memory group with a status flag corresponding to the first memory group; And Sending the first instruction sequence to the first memory group according to the comparison result.

17. A memory control circuit unit, characterized in that, For controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory groups, and the memory control circuit unit includes: A plurality of processing circuits; and An instruction sending circuit connected to the plurality of processing circuits, wherein one of the plurality of processing circuits is used to generate a first operation instruction, and the first operation instruction indicates accessing a first memory group among the plurality of memory groups, In response to the first status information, the instruction sending circuit is used to send a first instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform an access operation, wherein the first status information reflects a first startup state of the first memory group, the first instruction sequence does not include a control instruction sequence for starting the first memory group, and the control instruction sequence adjusts an on-chip termination circuit corresponding to the first memory group to a predetermined state to start the first memory group.

18. The memory control circuit unit according to claim 17, wherein the first startup state includes a state in which the first memory group has been started.

19. The memory control circuit unit according to claim 17, wherein in response to second status information, the instruction sending circuit is further used to send a second instruction sequence to the first memory group according to the first operation instruction to instruct the first memory group to perform the access operation, wherein the second status information reflects a second startup state of the first memory group, and the second instruction sequence includes the control instruction sequence.

20. The memory control circuit unit according to claim 19, wherein the second startup state includes a state in which the first memory group has not been started.

21. The memory control circuit unit according to claim 19, wherein the second instruction sequence further includes an access instruction sequence, the access instruction sequence carries instruction information related to the access operation, and the control instruction sequence is transmitted to the first memory group before the access instruction sequence.

22. The memory control circuit unit according to claim 17, wherein the first operation instruction includes group identification information, the control instruction sequence, and an access instruction sequence, and the group identification information reflects that the memory group indicated by the first operation instruction to be accessed is the first memory group.

23. The memory control circuit unit according to claim 22, wherein in response to the first status information, the operation of the instruction sending circuit sending the first instruction sequence to the first memory group according to the first operation instruction includes: Ignoring the control instruction sequence according to the group identification information and the first status information; And Sending the first instruction sequence to the first memory group according to the access instruction sequence.

24. The memory control circuit unit according to claim 17, wherein in response to the first status information, the operation of the instruction sending circuit sending the first instruction sequence to the first memory group according to the first operation instruction includes: Updating an access flag corresponding to the first memory group according to the first operation instruction; Comparing the access flag corresponding to the first memory group with a status flag corresponding to the first memory group; And Sending the first instruction sequence to the first memory group according to the comparison result.

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