Instruction jump method, processor and electronic device

Abstract

The embodiment of the present application provides a kind of instruction jump method, processor and electronic equipment, it is applied to binary translation system, and the binary translation system is used to translate source program in client into target program in host computer, and the method comprises: when the source program is translated into target program, obtain first jump instruction, the first jump instruction is the instruction of target program in the host computer, and the first jump instruction includes first operation code register identifier;The first jump instruction is executed, to record the running number and the number of times of missing of the first jump instruction in the table entry of corresponding jump refill table according to the first register identifier.The embodiment of the present application can provide jump tendency information about program running for binary translator, improve the running efficiency of binary translator, and additional hardware structure is not needed, which reduces the optimization cost and difficulty of binary translation.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an instruction jump method, a processor, and an electronic device. Background Technology

[0002] CPU (Central Processing Unit) instruction sets can be categorized by instruction complexity into Complex Instruction Set Computer (CISC) instructions and Reduced Instruction Set Computer (RISC) instructions. CISC instructions are numerous, applicable at widely varying frequencies, and have inconsistent instruction lengths; RISC instructions are fewer, applicable at similar frequencies, and have fixed instruction lengths. The simplified RISC instruction set makes designing multi-stage pipelines and multi-level processor caches easier, thereby improving microprocessor performance.

[0003] With the continuous development of microprocessor technology, the performance of microprocessors has become increasingly powerful. To enable computers to process different CPU instruction sets simultaneously and improve processing efficiency, binary translation technology has emerged. This technology allows source code for one CPU architecture to run on another CPU architecture; for example, it allows the rapid migration of software ecosystems from mature CPU architectures to emerging CPU architectures. However, this technology still suffers from technical problems such as low translation efficiency and excessive redundant operations. To address the inefficiency of binary translators, some microprocessors provide additional binary translators within the processor core to support code optimization. These additional binary translation auxiliary structures, like other structures in the microprocessor, need to provide interfaces to user mode or kernel mode so that the microprocessor can manage the code at runtime.

[0004] In existing technologies, microprocessors used in binary translation systems can simultaneously support two instruction sets: one is the microprocessor's native instruction set, and the other is the binary translation instruction set, i.e., the commonly used instruction set received by the target translator. For example, to translate instruction set A into instruction set B, instructions with the same functionality as commonly used instructions in A can be added to processor B to achieve binary translation optimization. In this approach, although the second instruction set can access all necessary hardware, the overall overhead is high, and its engineering implementation is very complex. The binary translator cannot effectively obtain information about the program's jump tendencies, thus affecting the translator's operating efficiency. Summary of the Invention

[0005] This invention provides an instruction jump method, processor, and electronic device that can provide a binary translator with jump tendency information about program execution, thereby improving the operating efficiency of the binary translator.

[0006] To address the aforementioned problems, this invention discloses an instruction jump method applied to a binary translation system. The binary translation system translates a source program in a client machine into a target program in a host machine. The method includes:

[0007] When the source program is translated into the target program, a first jump instruction is obtained. The first jump instruction is an instruction of the target program in the host machine. The first jump instruction includes a first opcode register identifier.

[0008] Execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in the corresponding jump refill table entry based on the first register identifier.

[0009] On the other hand, embodiments of the present invention disclose another instruction jump method applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client machine into a target program in a host machine, the method comprising:

[0010] When the source program is translated into the target program, a first jump instruction is obtained, wherein the first jump instruction is an instruction of the target program in the host machine; the first jump instruction includes a first register identifier;

[0011] Execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in a preset jump refill table according to the first register identifier;

[0012] Based on the number of times the first jump instruction was executed and the number of times it missed, the instructions stored in the predicted jump address of the first jump instruction were rearranged.

[0013] In another aspect, embodiments of the present invention disclose a processor applied to a binary translation system.

[0014] The binary translation system is used to translate a source program in the client machine into a target program in the host machine, and the processor includes:

[0015] The instruction fetch unit is used to fetch a first jump instruction when the source program is translated into a target program. The first jump instruction is an instruction of the target program in the host machine, and the first jump instruction includes a first opcode register identifier.

[0016] The processing unit is configured to execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in the corresponding jump refill table entry according to the first register identifier.

[0017] In another aspect, embodiments of the present invention disclose another processor applied to a binary translation system, the binary translation system being used to translate a source program in a client machine into a target program in a host machine, the processor comprising:

[0018] The instruction fetch unit is used to fetch a first jump instruction when the source program is translated into a target program. The first jump instruction is an instruction of the target program in the host machine. The first jump instruction includes a first register identifier.

[0019] The processing unit is configured to execute the first jump instruction, record the number of times the first jump instruction is executed and the number of times it misses in a preset jump refill table according to the first register identifier; and rearrange the instructions stored in the predicted jump address of the first jump instruction according to the number of times the first jump instruction is executed and the number of times it misses.

[0020] Furthermore, embodiments of the present invention also disclose an electronic device, the electronic device including a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors using the aforementioned instruction jump method.

[0021] This invention also discloses a readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to execute the aforementioned instruction jump method.

[0022] The embodiments of the present invention have the following advantages:

[0023] This invention provides an instruction jump method that records the execution count and miss count of the first jump instruction in the target program using a jump refill table. This provides the binary translation system with information about the tendency of the first jump instruction. The binary translation system can access the records of the first jump instruction in the jump refill table to obtain the overall execution tendency of the target program, and thus optimize the binary translation based on this tendency, improving the system's efficiency. Furthermore, the data processing method provided by this invention does not require additional hardware in the binary translator, saving costs and is easy to implement, reducing the optimization cost and difficulty of binary translation. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of the steps of an instruction jump method according to the present invention;

[0026] Figure 2 This is a control flowchart of a jump and refill form according to the present invention;

[0027] Figure 3 This is a control flowchart of a jump and refill table in the hardware of the present invention;

[0028] Figure 4 This is a flowchart of another instruction jump method of the present invention;

[0029] Figure 5 This is a schematic diagram of the execution flow of a target program according to the present invention;

[0030] Figure 6 This is a schematic diagram of the execution flow of another target program of the present invention;

[0031] Figure 7 This is a structural block diagram of a processor according to the present invention;

[0032] Figure 8 This is a structural block diagram of another processor of the present invention;

[0033] Figure 9 This is a structural block diagram of an electronic device for instruction switching according to the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Method Implementation Examples

[0036] Reference Figure 1 The diagram illustrates a flowchart of an instruction jump method provided by an embodiment of the present invention. The instruction jump method is applied to a binary translation system, which translates a source program in a client machine into a target program in a host machine. Figure 1As shown, the method may specifically include the following steps:

[0037] Step 101: When the source program is translated into the target program, obtain the first jump instruction. The first jump instruction is the instruction of the target program in the host machine. The first jump instruction includes the first opcode register identifier.

[0038] Step 102: Execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it missed in the corresponding jump refill table entry according to the first register identifier.

[0039] Wherein, the first jump instruction is the host machine corresponding instruction, the first jump instruction corresponds to the first jump address and the second jump address, the first jump address is the target jump address to which the first jump instruction is to jump under the jump condition, and the second jump address is the target jump address to which the first jump instruction is to jump under the jump condition.

[0040] It should be noted that the source program is in binary code. During the translation process, the binary translation system can only obtain the compiled binary code (i.e., the source program). After disassembling the binary code, it obtains the assembly-level code; at this point, it cannot segment the code based on functions within the source program. Typically, the binary translation system divides the obtained source program into translation units, with the last instruction of each translation unit usually being a jump instruction from the source program. The binary translation system operates on translation units as the basic unit.

[0041] Jump instructions are commonly used instructions in instruction sets. They are used to switch program execution from executing a first instruction sequence to executing a second instruction sequence. When the binary translation system retrieves a jump instruction from the instruction memory, it determines whether the jump instruction meets the jump condition. If the jump condition is met, the program jumps to the target jump address and begins executing the second instruction sequence; if the jump condition is not met, it continues executing the next instruction in the first instruction sequence. For the first jump instruction in this embodiment, if the first jump instruction meets the jump condition, it jumps to the first jump address, retrieves the target instruction from the instruction register based on the first jump address, and executes it; if the first jump instruction does not meet the jump condition, it jumps to the second jump address, retrieves the target instruction from the instruction register based on the second jump address, and executes it.

[0042] In this embodiment of the invention, the first jump instruction is an instruction of the target program in the host machine, and there exists a client jump instruction in the client's source program corresponding to the first jump instruction. In the source program, the jump instruction corresponds to two jump directions: one is the jump direction when the jump condition is met, and the other is the jump direction when the jump condition is not met. Each jump direction corresponds to a jump address. Assume that for jump instruction A1 in the source program, the offset address when the jump condition is met is offset0, and the offset address when the jump condition is not met is offset1. In the source program, after the processor judges the jump instruction, it can directly jump to the target jump address according to the jump condition, the offset address, and the address of the jump instruction. In other words, in the source program, the overhead of going to offset0 and offset1 is the same. However, after the binary translation system translates the source program, the original instruction order is scrambled. In the target program of the host machine, the next instruction after the currently executed jump instruction does not necessarily belong to the same instruction sequence as the jump instruction. Furthermore, a large number of B instructions will be inserted into the translated target program. When the target program in the host machine goes to the target jump address corresponding to offset1, it needs to execute one or more "b offset1" instructions first. B instructions are also a type of jump instruction. Therefore, when the target program goes to the target jump address corresponding to offset1, it often needs to perform continuous jumps. Continuous jumps will generate cavitation, which can easily cause errors in the host machine when prefetching instructions, affecting the running efficiency of the binary translation system.

[0043] Clearly, if the frequency of jump instructions failing to meet jump conditions is high within the preset time, the target program will need to execute the B instruction multiple times, severely impacting the efficiency of the binary translation system. Conversely, if the frequency of jump instructions failing to meet jump conditions is low within the preset time, the target program will execute the B instruction a limited number of times, resulting in a lower impact on the efficiency of the binary translation system. Therefore, to effectively optimize the binary translation system, it is necessary to determine the jump tendency of jump instructions during the execution of the target program. Based on this tendency, the binary translation system can be optimized in a targeted manner to improve its efficiency while reducing optimization costs.

[0044] To address this issue, embodiments of the present invention provide an instruction jump method. This method records the execution count and miss count of the first jump instruction in the target program using a jump refill table, providing the binary translation system with information about the tendency of the first jump instruction. The binary translation system can access the records of the first jump instruction in the jump refill table to obtain the overall execution tendency of the target program, thereby optimizing the binary translation based on this tendency and improving the system's efficiency. Furthermore, the data processing method provided by this invention does not require additional hardware in the binary translator, saving costs and is easy to implement, reducing the optimization cost and difficulty of binary translation.

[0045] It should be noted that, in this embodiment of the invention, before the source program is translated into the target program, a new jump instruction can be added to the instruction set corresponding to the host machine, namely, the first jump instruction in this embodiment of the invention. The first jump instruction includes an opcode, operands, a first register identifier, etc. The opcode is used to define the first jump instruction as a jump instruction, and when the first jump instruction is executed, the processor records the number of times the first jump instruction is executed and the number of misses (i.e., the number of times the first jump instruction does not meet the jump condition) in the jump refill table. The operands are used to indicate the jump target of the first jump instruction. The first register identifier is used to indicate the position of the entry in the jump refill table used to record the number of times the first jump instruction is executed and the number of misses.

[0046] A binary translation system translates the source program in the client machine into the target program in the host machine. Essentially, it translates the various instructions in the client's instruction set into the instructions in the host machine's instruction set. Therefore, after adding a first jump instruction to the host machine's instruction set, the binary translation system translates the source program in the client machine into the target program in the host machine, which contains the first jump instruction. By executing the first jump instruction, the number of executions and misses can be recorded without adding new hardware to the binary translation system, saving overhead and simplifying implementation, thus reducing the optimization cost and difficulty of binary translation.

[0047] In an optional embodiment of the present invention, the method further includes:

[0048] Step S11: Obtain the table entry control instruction, wherein the table entry control instruction is the instruction corresponding to the host machine;

[0049] Step S12: Execute the table entry control instruction to perform a control operation on the preset jump and refill table.

[0050] In this embodiment of the invention, a preset jump refill table is used to record the number of times the first jump instruction is executed and the number of times it misses. To ensure the normal use of the jump refill table, in this embodiment of the invention, an entry control instruction can be added to the instruction set corresponding to the host machine to maintain and manage the jump refill table.

[0051] It should be noted that the table entry control instruction includes an opcode, operands, etc. The opcode of the table entry control instruction defines its function; the processor can determine which specific control operation to perform when executing the table entry control instruction based on its opcode. The operands of the table entry control instruction specify the source of the data required for the control operation performed by the instruction. The operand field of the table entry control instruction can contain the operand itself, the operand address, or the method for calculating the operand address.

[0052] Optionally, the table entry control instruction includes a table entry setting instruction, and the control operation for the preset jump refill table includes: setting a first preset threshold and a second preset threshold for the preset jump refill table, wherein the first preset threshold is a threshold corresponding to the number of runs recorded in the jump refill table, and the second preset threshold is a threshold corresponding to the number of misses recorded in the jump refill table.

[0053] As an example, the table entry control instruction in this embodiment of the invention can be a table entry setting instruction. The table entry setting instruction is used to set a threshold for jump refilling of the table. Specifically, it can include a first preset threshold corresponding to the number of times the first jump instruction is run, and a second preset threshold corresponding to the number of times the first jump instruction is missed.

[0054] In practical applications, binary translation systems can determine the execution tendency of a first jump instruction by comparing the number of executions and misses of the first jump instruction recorded in the jump refill table with their respective thresholds. For example, suppose the offset address when the first jump instruction A1 meets the jump condition is offset0, and the offset address when it does not meet the jump condition is offset1; if the number of misses of the first jump instruction is less than a second preset threshold, it can be determined that the first jump instruction is more likely to go to the jump address corresponding to offset0 when it meets the jump condition and offset1 when it does not meet the jump condition. During the execution of the target program, the B instruction needs to be executed multiple times. After determining the jump tendency of the first jump instruction, the binary translation system can adopt corresponding optimization schemes. For example, if the number of misses of the first jump instruction is greater than the first preset threshold, the instructions stored in the first jump address and the second jump address can be rearranged to minimize the number of times the target program executes the B instruction, and so on.

[0055] It should be noted that for the table entry setting instruction, its operands can be the first preset threshold and the second preset threshold to be set. During the execution of the table entry setting instruction, the processor can set the first preset threshold and the second preset threshold for the jump refill table according to the operands set for the table entry.

[0056] Optionally, the table entry control instruction includes a table entry reading instruction, and the control operation on the preset jump refill table includes: reading the first preset threshold and the second preset threshold corresponding to the preset jump refill table.

[0057] As another example, the table entry control instruction in this embodiment of the invention can also be a table entry read instruction. This table entry read instruction is used to read the first preset threshold and the second preset threshold corresponding to the jump refill table. Furthermore, the processor can also write the read first preset threshold and the second preset threshold into the memory of the binary translation system, so that the binary translation system can read the stored first preset threshold and the second preset threshold each time a thread switch occurs, and perform context switching.

[0058] It should be noted that for the table entry read instruction, its operand can be the storage address of the first preset threshold and the second preset threshold to be read. When the processor executes the table entry control instruction, it can read the specific values ​​of the first preset threshold and the second preset threshold from the storage address of the first preset threshold and the second preset threshold.

[0059] Optionally, the table entry control instruction includes a table entry clearing instruction. Executing the table entry control instruction to perform control operations on the preset jump refill table includes: after each reset of the first preset threshold and the second preset threshold of the jump refill table, executing the table entry clearing instruction to clear the records of each table entry in the jump refill table.

[0060] As another example, the table entry control instructions in this embodiment of the invention can also be table entry clearing instructions, which are used to clear the content of the corresponding table entry in the jump and refill table, so as to maintain the timeliness of the data recorded in the table entry.

[0061] It should be noted that for the table entry clearing instruction, its operand can be the register identifier corresponding to the table entry to be cleared. When the processor executes the table entry clearing instruction, it can clear the record in the corresponding table entry according to the register identifier.

[0062] The data recorded in the jump refill table can be used for thread switching. To ensure the correctness of thread switching, this embodiment of the invention clears all entries in the jump refill table after each reset of the first and second preset thresholds, and recounts the number of times the first jump instruction was executed and the number of misses.

[0063] In an optional embodiment of the present invention, the table entry clearing instruction further includes a second register identifier, and the method further includes: if the number of runs recorded in the table entry corresponding to the second register identifier is greater than or equal to a first preset threshold, then the table entry clearing instruction is executed to clear the record of the table entry corresponding to the second register identifier by jumping and refilling the table.

[0064] The second register identifier is the operand of the entry clearing instruction, used to indicate the entry to be cleared. In this embodiment of the invention, if the number of times the first jump instruction is executed is greater than or equal to a first preset threshold, the number of times the first jump instruction is executed and the number of jumps in the jump refill table can be cleared to zero, so as to ensure the timeliness of the number of executions and jumps recorded in the jump refill table and avoid data redundancy.

[0065] In an optional embodiment of the present invention, after obtaining the first jump instruction and before executing the first jump instruction, the method further includes:

[0066] Step S21: Determine whether there are any unused entries in the preset jump refill table;

[0067] Step S22: If there are no unoccupied entries in the jump refill table, then determine the target entry based on the attribute information of each entry in the jump refill table;

[0068] Step S23: Determine the register identifier corresponding to the target entry as the first register identifier of the first jump instruction and the second register identifier of the entry clear instruction;

[0069] Step S24: Execute the entry clearing instruction to clear the record of the entry corresponding to the second register identifier in the table and jump to refill the table; the attribute information includes at least one of the initial recording time and the record update frequency.

[0070] In this embodiment of the invention, each first jump instruction corresponds to an entry for recording its execution count and miss count. If there are unoccupied entries in the current jump refill table, the execution count and miss count of the first jump instruction are directly recorded in the unoccupied entries. If there are no unoccupied entries in the current jump refill table, that is, the jump refill table is full, the target entry can be determined based on the attribute information of each entry, and the register identifier corresponding to the target entry is determined as the first register identifier of the first jump instruction conforming to the second register identifier of the entry clearing instruction. Then, the entry clearing instruction is executed, and the execution count and miss count of the first jump instruction recorded in the target entry are cleared according to the second register identifier. Since the entry clearing instruction is executed before the first jump instruction, the target entry is in an unoccupied state when the first jump instruction is executed, and the execution count and miss count of the first jump instruction can be recorded in the target entry.

[0071] The attribute information includes at least one of the following: initial recording time and recording update frequency.

[0072] As an example, the attribute information includes the initial record time, which can be used to determine the earliest recorded entry as the target entry. In other words, if the jump-to-refill table is full, the "first-in, first-out" principle is followed, overwriting the content of the earliest recorded entry.

[0073] As another example, the attribute information includes the record update frequency, and the table entry with the lowest record update frequency within a preset time period can be used as the target table entry.

[0074] The following describes the collaborative workflow of the first jump instruction, the entry setting instruction, the entry reading instruction, and the entry clearing instruction in the target program. (Refer to...) Figure 2 This illustrates a control flowchart for a jump-and-refill form according to an embodiment of the present invention. Figure 2As shown, the jump refill table (BRT) records the number of misses and execution counts for each first jump instruction based on its address (PC) in the target program. During the execution of the first jump instruction (BUBRT), the binary translation system determines whether the first jump instruction meets the jump condition. If the first jump instruction meets the jump condition (taken), the execution count of that first jump instruction in the jump refill table is incremented by 1; if the first jump instruction does not meet the jump condition (not taken), both the miss count and the execution count of that first jump instruction in the jump refill table are incremented by 1. Simultaneously, the execution threshold (i.e., the first preset threshold in this embodiment) and the miss threshold (i.e., the second preset threshold in this embodiment) can be set for the jump refill table using the entry setting instruction (SBRT). After setting the thresholds, the execution threshold and miss threshold of the jump refill table can be read using the entry reading instruction (LBRT). In addition, the records in the corresponding entries can be cleared by the Entry Clearing Command (CLBRT). For example, after each time the threshold for jumping and refilling the table is reset by the Entry Setting Command, the Entry Clearing Command can be executed to clear the records in each entry of the jumping and refilling table; or, if the number of runs recorded in a certain entry is greater than the running threshold, the records in that entry can be cleared by executing the Entry Clearing Command.

[0075] In this embodiment of the invention, the maintenance and management of the jump-and-refill table can be achieved through the first jump instruction, the table entry setting instruction, the table entry reading instruction, and the table entry clearing instruction.

[0076] Figure 2 The control flow shown for redirected form re-entry is a software-level control. At the hardware level, various components also need to work together to achieve the maintenance and management of the redirected form re-entry. (Refer to...) Figure 3 This illustrates a control flowchart for jump-and-refill table functionality in hardware provided by an embodiment of the present invention. Figure 3 As shown, the processor system includes components such as a processor core, bus interface unit, interrupt controller, and memory controller. In this embodiment of the invention, the maintenance and management of the jump refill table are mainly performed by the processor core. Specifically, the processor core may include an execution unit, which may further include a register file, extended registers, logical extended registers, and an arithmetic logic unit. The execution unit maintains and manages the jump refill table (BRT) by executing the first jump instruction (BUBRT), entry setting instruction (SBRT), entry reading instruction (LBRT), and entry clearing instruction (LBRT) in the target program. The specific execution flow is as follows: Figure 2 As shown.

[0077] In summary, this invention provides an instruction jump method that records the execution count and miss count of the first jump instruction in the target program through a jump refill table. This provides the binary translation system with information about the tendency of the first jump instruction. The binary translation system can access the records of the first jump instruction in the jump refill table to obtain the overall execution tendency of the target program, and thus optimize the binary translation based on this tendency, improving the operating efficiency of the binary translation system. Furthermore, the data processing method provided by this invention does not require additional hardware structures in the binary translator, saving costs and is easy to implement, reducing the optimization cost and difficulty of binary translation.

[0078] Reference Figure 4 This diagram illustrates a flowchart of another instruction jump method provided by an embodiment of the present invention. The instruction jump method is applied to a binary translation system, which translates a source program in a client machine into a target program in a host machine. Figure 4 As shown, the method may specifically include the following steps:

[0079] Step 201: When the source program is translated into the target program, a first jump instruction is obtained. The first jump instruction is an instruction of the target program in the host machine. The first jump instruction includes a first register identifier.

[0080] Step 202: Execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in a preset jump refill table according to the first register identifier.

[0081] Step 203: Based on the number of times the first jump instruction has been executed and the number of times it has missed, the instructions stored in the predicted jump address of the first jump instruction are rearranged.

[0082] The predicted jump address of the first jump instruction includes a first jump address and a second jump address. The first jump address is the target jump address when the first jump instruction hits the jump condition, and the second jump address is the target jump address when the first jump instruction fails to hit the jump condition.

[0083] The binary translation method provided in this invention can be applied to a binary translation system. The binary translation system is used to convert binary code executed on one architecture into binary code that can be executed by another architecture; wherein, the aforementioned architecture refers to a CPU architecture running an instruction set.

[0084] It should be noted that the source program is in binary code. The binary translation system translates the source program in the client machine to obtain the target program in the host machine. The first jump instruction is an instruction of the target program in the host machine.

[0085] Each instruction in the target program consists of five processing stages: Instruction Fetch (IF) stage, which reads the instruction from memory and stores it in a register; Instruction Decode (ID) stage, which breaks down and interprets the fetched instruction according to a predetermined instruction format; Execute (EX) stage, which performs the various operations specified by the instruction to implement the instruction's function; Memory Access (MEM) stage, which obtains the address of the operand in memory based on the instruction address code and reads the operand from memory for computation; and Writeback (WB) stage, which writes the execution result data from the execution stage back to the register so that it can be quickly accessed by subsequent instructions.

[0086] The instruction jump method provided in this embodiment of the invention adds a first jump instruction to the instruction set corresponding to the host machine. The newly added first jump instruction is the same as other instructions in the instruction set corresponding to the host machine and goes through the above five processing stages.

[0087] It should be noted that the first jump instruction includes an opcode, operands, a first register identifier, etc. The opcode is used to define the first jump instruction as a jump instruction, and when the first jump instruction is executed, the processor records the number of times the first jump instruction has been executed and the number of misses (i.e., the number of times the first jump instruction does not meet the jump condition) in the jump refill table. The operands are used to indicate the jump target of the first jump instruction. The first register identifier is used to indicate the position of the entry in the jump refill table used to record the number of times the first jump instruction has been executed and the number of misses. For example, the first register identifier can be used as the operand of the first jump instruction.

[0088] A binary translation system translates a source program in the client machine into a target program in the host machine. Essentially, it translates various instructions from the client machine's instruction set into instructions from the host machine's instruction set. Therefore, after adding a first jump instruction to the host machine's instruction set, the binary translation system translates the source program in the client machine into a target program in the host machine, which contains the first jump instruction.

[0089] In the target program, if the first jump instruction does not meet the jump condition, when going to the second jump address, it is often necessary to execute one or more additional B instructions generated by binary translation, resulting in continuous jumps and cavitation. This can easily cause errors in the host machine when prefetching instructions, affecting the operating efficiency of the binary translation system.

[0090] In this embodiment of the invention, when the source program is translated into the target program, a first jump instruction is obtained and executed. Based on the first register identifier contained in the first jump instruction, the execution count and miss count of the first jump instruction are recorded in the corresponding entry of the jump reloading table. Furthermore, based on the execution count and miss count of the first jump instruction, the instructions stored in the predicted jump address of the first jump instruction are rearranged to minimize the number of times the target program travels to the second jump address, thereby reducing the execution count of the B instruction in the target program, lowering the hardware overhead of the binary translation system, and improving the operating efficiency of the binary translation system.

[0091] In an optional embodiment of the present invention, the step of rearranging the instructions stored in the predicted jump address of the first jump instruction according to the number of times the first jump instruction is executed and the number of misses includes:

[0092] Step S31: Determine whether the number of times the first jump instruction is executed is greater than a first preset threshold.

[0093] Step S32: If the number of runs is less than the first preset threshold, update the number of runs of the first jump instruction in the jump refill table according to the first register identifier, and determine whether the number of misses of the first jump instruction is greater than the second preset threshold.

[0094] Step S33: If the number of misses is greater than the second preset threshold, adjust the jump direction of the first jump instruction and swap the instructions stored in the first jump address and the second jump address, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

[0095] In this embodiment of the invention, the number of executions and the number of misses recorded in the jump refill table can be determined. If, during the execution of the first jump instruction, the number of executions of the first jump instruction recorded in the jump refill table is less than a first preset threshold, then the entry corresponding to the first jump instruction in the jump refill table is updated according to the first register identifier, its execution count is incremented by 1, and it is further determined whether the number of misses of the first jump instruction is greater than a second preset threshold, so as to determine the jump tendency information of the first jump instruction.

[0096] If the number of misses of the first jump instruction is greater than the second preset threshold, it means that the first jump instruction is more likely to jump to the second jump address within a limited number of executions.

[0097] In this embodiment of the invention, the jump refill table records the execution count and miss count of the first jump instruction. If the miss count of the first jump instruction is greater than a second preset threshold, it indicates that the first jump instruction tends to jump to the second jump address. If execution continues in the current jump direction, the B instruction generated by binary translation will be executed multiple times, severely affecting the execution efficiency of the binary translation system. For example, assuming the jump condition of the first jump instruction A1 is a = b, the offset address corresponding to the first jump address is offset0, the offset address corresponding to the second jump address is offset1, the instruction stored in the first jump address is instruction A2, and the instruction stored in the second jump address is instruction A3. (Refer to...) Figure 5 This diagram illustrates the execution flow of a target program according to an embodiment of the present invention. Figure 5 As shown, when the processor executes the first jump instruction A1, it determines whether the first jump instruction A1 meets the jump condition. If the jump condition is met (a = b), it directly jumps to the first jump address, retrieves instruction A2 from the first jump address, and executes it. If the jump condition is not met (a ≠ b), before heading to the second jump address, it needs to execute one or more "b offset1" instructions first, and then retrieves instruction A3 from the second jump address and executes it. This increases the hardware overhead of the binary translation system and affects the operating efficiency of the binary translation system.

[0098] Therefore, in this embodiment of the invention, as long as the number of times the first jump instruction is executed is greater than a first preset threshold and the number of times the second jump instruction is executed is greater than a second preset threshold, the jump direction of the first jump instruction is adjusted, and the instructions stored in the first jump address and the second jump address are swapped, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met. (Refer to...) Figure 6 This illustrates a schematic diagram of the execution flow of another target program provided in an embodiment of the present invention. Figure 6As shown, when the processor determines that the first jump instruction satisfies the jump condition (a=b), it fetches instruction A2 from the second jump address and executes it; when it determines that the first jump instruction does not satisfy the jump condition (a≠b), it fetches instruction A3 from the first jump address and executes it. This invention, after adjusting the jump direction of the first jump instruction and swapping the instructions stored in the first and second jump addresses, ensures that the next instruction to be executed by the target program is still instruction A2 when a=b and instruction A3 when a≠b. It does not change the execution logic of the target program, but compared to… Figure 5 , Figure 6 In the execution flow shown, if the target program does not meet the jump condition of the first jump instruction, it does not need to go to the second jump address corresponding to offset1. It can directly obtain instruction A3 from the first jump address corresponding to offset0 and execute it. Although the target program still needs to execute the "b offset1" instruction when going to the second jump address if the first jump instruction meets the jump condition, since the number of misses of the first jump instruction is greater than the first preset threshold, it means that in the same amount of time, the number of times the first jump instruction meets the jump condition is less than the number of times the jump condition is not met. Compared to... Figure 5 The execution flow shown is as follows: Figure 6 The execution flow shown effectively reduces the number of times the "b offset1" instruction is executed, thereby reducing the hardware overhead of the binary translation system and improving its operating efficiency.

[0099] In an optional embodiment of the present invention, the method further includes:

[0100] If the number of runs is greater than or equal to the first preset threshold, then based on the table entry clearing instruction, the number of runs and the number of misses of the first jump instruction in the jump refill table are cleared to zero.

[0101] In this embodiment of the invention, to ensure the timeliness of the jump refill table, if the number of times the first jump instruction is executed is greater than or equal to the first preset threshold, a table entry clearing instruction can be executed to reset the number of times the first jump instruction is executed and the number of misses in the jump refill table to zero, and the next round of recording can begin. Both the first preset threshold and the second preset threshold can be set according to actual needs, and this embodiment of the invention does not impose specific limitations on them. Generally, the first preset threshold is less than the second preset threshold.

[0102] In an optional embodiment of the present invention, after reordering the instructions stored in the predicted jump address of the first jump instruction in step 203, the method further includes: converting the first jump instruction into a second jump instruction, wherein the binary translation system does not count the number of times the second jump instruction is executed or the number of times it misses.

[0103] It should be noted that, in this embodiment of the invention, only the execution count and jump count of the marked first jump instruction are counted and recorded in the jump refill table. The execution count and jump count of other jump instructions in the translated instruction set, namely the second jump instruction, are not counted. The second jump instruction is the first jump instruction after instruction rearrangement. Compared with the first jump instruction, when executing the second jump instruction, regardless of whether the second jump instruction meets the jump condition, the number of times the processor executes the B instruction has been effectively reduced. Therefore, there is no need to process the second jump instruction again, and there is no need to record the execution count and jump count of the second jump instruction in the jump refill table, so as to avoid excessive occupation of the table entries and improve the utilization rate of the jump refill table.

[0104] In an optional embodiment of the present invention, the method further includes:

[0105] Step S21: Receive the table entry setting instruction for the jump refill table;

[0106] Step S22: In response to the form setting instruction, set the first preset threshold and the second preset threshold for the jump and refill form.

[0107] In this embodiment of the invention, a first preset threshold and a second preset threshold can be set for the jump refill form using a form entry setting instruction. Specifically, the first and second preset thresholds can be configured in the form entry setting instruction. After receiving the threshold setting instruction, the binary translation system can set the jump refill form according to the first and second preset thresholds carried in the threshold setting instruction.

[0108] In an optional embodiment of the present invention, the method further includes:

[0109] After each time the first preset threshold and the second preset threshold of the jump refill table are set, an entry clearing command is executed to clear the records of each entry in the jump refill table.

[0110] It should be noted that the data recorded in the jump refill table can be used for thread switching. To ensure the correctness of thread switching, this embodiment of the invention executes a table entry clearing instruction after each reset of the first and second preset thresholds of the jump refill table, thereby clearing all entries in the jump refill table and recounting the number of times the first jump instruction was executed and the number of misses.

[0111] In an optional embodiment of the present invention, after obtaining the first jump instruction and before executing the first jump instruction, the method further includes:

[0112] Step S41: Determine whether there are any unused entries in the preset jump and refill table;

[0113] Step S42: If there are no unoccupied entries in the jump refill table, then determine the target entry based on the attribute information of each entry in the jump refill table;

[0114] Step S43: Determine the register identifier corresponding to the target entry as the first register identifier of the first jump instruction and the second register identifier of the entry clear instruction;

[0115] Step S44: Execute the table entry clearing instruction to clear the record of the table entry corresponding to the second register identifier in the table and jump to refill it.

[0116] In this embodiment of the invention, each first jump instruction corresponds to an entry for recording its execution count and miss count. If there are unoccupied entries in the current jump refill table, the execution count and miss count of the first jump instruction are directly recorded in the unoccupied entries. If there are no unoccupied entries in the current jump refill table, that is, the jump refill table is full, the target entry can be determined based on the attribute information of each entry, and the register identifier corresponding to the target entry is determined as the first register identifier of the first jump instruction conforming to the second register identifier of the entry clearing instruction. Then, the entry clearing instruction is executed, and the execution count and miss count of the first jump instruction recorded in the target entry are cleared according to the second register identifier. Since the entry clearing instruction is executed before the first jump instruction, the target entry is in an unoccupied state when the first jump instruction is executed, and the execution count and miss count of the first jump instruction can be recorded in the target entry.

[0117] The attribute information includes at least one of the following: initial recording time and recording update frequency.

[0118] As an example, the attribute information includes the initial record time, which can be used to determine the earliest recorded entry as the target entry. In other words, if the jump-to-refill table is full, the "first-in, first-out" principle is followed, overwriting the content of the earliest recorded entry.

[0119] As another example, the attribute information includes the record update frequency, and the table entry with the lowest record update frequency within a preset time period can be used as the target table entry.

[0120] In an optional embodiment of the present invention, the method further includes:

[0121] If a context switch occurs in the scheduling thread of the binary translation system, the data recorded in the jump refill table is read based on the table entry read instruction, and the read data is stored in the preset memory of the binary translation system.

[0122] In this embodiment of the invention, based on the table entry read instruction, the thresholds corresponding to the number of jump refill operations and the number of misses, namely the first preset threshold and the second preset threshold, can be read, and the read data can be stored in preset memory. It should be noted that this preset memory is the permanent memory of the binary translation system, which facilitates the binary translation system to read the stored data each time a thread switch occurs.

[0123] In an optional embodiment of the present invention, before obtaining the first jump instruction in step 201, the method further includes:

[0124] Step S51: Obtain the source program to be translated, wherein the source program includes at least one jump instruction;

[0125] Step S52: The source program is segmented based on the jump instruction to obtain at least one translation unit;

[0126] Step S53: Disassemble the at least one translation unit to obtain the assembler program corresponding to each translation unit;

[0127] Step S54: Call the translation function to translate the assembly program corresponding to each translation unit to obtain the target program corresponding to each translation unit.

[0128] In this embodiment of the invention, the target program is obtained by translating the source program using a binary translation system. Specifically, after acquiring the source program, the binary translation system first segments the source program based on jump instructions to obtain translation units, which are the basic working units of the binary translation system. Then, the binary translation system disassembles the translation units to obtain the assembly program corresponding to each translation unit. Each translation unit corresponds to one assembly program. Finally, the binary translation system calls the corresponding translation function to translate the obtained assembly program to obtain the target program corresponding to the translation unit. The translation function can be any function skilled in instruction translation from the art; this embodiment of the invention does not impose specific limitations on it.

[0129] It should be noted that the binary translation system processes the source program according to the segmented translation units and the order in which these units are processed. Specifically, after obtaining the translation instruction set corresponding to each translation unit, the binary translation system translates each unit sequentially according to the order of the translation units.

[0130] In summary, this invention provides an instruction jump method that records the execution count and miss count of the first jump instruction in the target program through a jump refill table, thereby providing the binary translation system with bias information about the first jump instruction. Furthermore, in this invention, based on the execution count and miss count of the first jump instruction, the instructions stored in the predicted jump address of the first jump instruction are rearranged to minimize the execution count of the B instruction in the target program, reducing the hardware overhead of the binary translation system and improving its operating efficiency.

[0131] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0132] Device Examples

[0133] Reference Figure 7 The diagram illustrates a block diagram of a processor according to the present invention, applied to a binary translation system for translating a source program in a client machine into a target program in a host machine. The processor 70 includes an instruction fetch unit 701 and a processing unit 702.

[0134] In one embodiment of the present invention Figure 7 The processor shown can be used to execute Figure 1 The instruction jump method shown is as follows:

[0135] The instruction fetch unit 701 is used to fetch a first jump instruction when the source program is translated into a target program. The first jump instruction is an instruction of the target program in the host machine, and the first jump instruction includes a first opcode register identifier.

[0136] Processing unit 702 is configured to execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in the corresponding jump refill table entry according to the first register identifier.

[0137] Optionally, the instruction fetching unit is further configured to:

[0138] Obtain the table entry control instruction, wherein the table entry control instruction is the corresponding instruction of the host machine;

[0139] The processing unit is also used for:

[0140] Execute the table entry control command to perform a control operation on the preset jump and refill table.

[0141] Optionally, the table entry control instructions include table entry setting instructions, and the processing unit is specifically used for:

[0142] A first preset threshold and a second preset threshold are set for the preset jump refill table. The first preset threshold is the threshold corresponding to the number of runs recorded in the jump refill table, and the second preset threshold is the threshold corresponding to the number of misses recorded in the jump refill table.

[0143] Optionally, the table entry control instruction includes a table entry read instruction, and the processing unit is specifically used for:

[0144] Read the first and second preset thresholds corresponding to the preset jump refill table.

[0145] Optionally, the table entry control instruction includes a table entry clearing instruction, and the processing unit is specifically used for:

[0146] After each time the first preset threshold and the second preset threshold of the jump refill table are reset, the table entry clearing command is executed to clear the records of each table entry in the jump refill table.

[0147] Optionally, the entry clearing instruction further includes a second register identifier, and the processing unit is further configured to:

[0148] If the number of runs recorded in the entry corresponding to the second register identifier is greater than or equal to the first preset threshold, then the entry clearing instruction is executed to clear the entry and refill the record in the entry corresponding to the second register identifier.

[0149] Optionally, the processing unit is further configured to:

[0150] Determine if there are any unused entries in the preset redirect and refill table;

[0151] If there are no unoccupied entries in the jump refill table, the target entry is determined based on the attribute information of each entry in the jump refill table.

[0152] The register identifier corresponding to the target entry is determined as the first register identifier of the first jump instruction and the second register identifier of the entry clear instruction;

[0153] Execute the entry clearing instruction to clear the record corresponding to the second register identifier in the table and jump to refill the record; the attribute information includes any one of the initial recording time and the record update frequency.

[0154] In another embodiment of the invention Figure 7 The processor shown can also be used to process Figure 4 The instruction jump method shown is as follows:

[0155] The instruction fetch unit 701 is used to fetch a first jump instruction when the source program is translated into a target program. The first jump instruction is an instruction of the target program in the host machine. The first jump instruction includes a first register identifier.

[0156] Processing unit 702 is configured to execute the first jump instruction to record the number of times the first jump instruction is executed and the number of times it misses in a preset jump refill table according to the first register identifier; and to perform instruction rearrangement on the instructions stored in the predicted jump address of the first jump instruction according to the number of times the first jump instruction is executed and the number of times it misses.

[0157] Optionally, the first jump instruction includes a first jump address and a second jump address, wherein the first jump address is the target jump address when the first jump instruction hits the jump condition, and the second jump address is the target jump address when the first jump instruction fails to hit the jump condition. The processing unit is specifically used for:

[0158] Determine whether the number of times the first jump instruction is executed is greater than a first preset threshold;

[0159] If the number of runs is less than the first preset threshold, the number of runs of the first jump instruction is updated in the jump refill table according to the first register identifier, and it is determined whether the number of misses of the first jump instruction is greater than the second preset threshold.

[0160] If the number of misses is greater than the second preset threshold, the jump direction of the first jump instruction is adjusted, and the instructions stored in the first jump address and the second jump address are swapped, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

[0161] Optionally, the processing unit is further configured to:

[0162] If the number of runs is greater than or equal to the first preset threshold, then based on the table entry clearing instruction, the number of runs and the number of misses of the first jump instruction in the jump refill table are cleared to zero.

[0163] Optionally, after adjusting the jump direction of the first jump instruction, the processing unit is further configured to:

[0164] The first jump instruction is converted into a second jump instruction, wherein the binary translation system does not count the number of times the second jump instruction is executed or the number of times it misses.

[0165] Optionally, the processing unit is further configured to:

[0166] Receive instructions for setting table entries for the jump and refill table;

[0167] In response to the table entry setting instruction, the first preset threshold and the second preset threshold for the jump refill table are set based on the table entry setting instruction.

[0168] Optionally, the processing unit is further configured to:

[0169] After each time the first preset threshold and the second preset threshold of the jump refill table are set, an entry clearing command is executed to clear the records of each entry in the jump refill table.

[0170] Optionally, after obtaining the first jump instruction and before executing the first jump instruction, the processing unit is further configured to:

[0171] Determine if there are any unused entries in the preset redirect and refill table;

[0172] If there are no unused entries in the jump refill table, the target entry is determined based on the attribute information of each entry in the jump refill table.

[0173] The register identifier corresponding to the target entry is determined to be the first register identifier of the first jump instruction and the second register identifier of the entry clear instruction;

[0174] Execute the table entry clear instruction to clear the record in the table corresponding to the second register identifier and jump to refill the table.

[0175] Optionally, the attribute information includes either the initial recording time or the recording update frequency.

[0176] Optionally, the processing unit is further configured to:

[0177] If a context switch occurs in the scheduling thread of the binary translation system, the data recorded in the jump refill table is read based on the table entry read instruction, and the read data is stored in the preset memory of the binary translation system.

[0178] Optionally, before fetching the first jump instruction, the instruction fetching unit is further configured to:

[0179] Obtain the source program to be translated, wherein the source program includes at least one jump instruction;

[0180] The processing unit is also used for:

[0181] The source program is segmented based on the jump instruction to obtain at least one translation unit;

[0182] Disassemble the at least one translation unit to obtain the assembler program corresponding to each translation unit;

[0183] The translation function is called to translate the assembly program corresponding to each translation unit, thereby obtaining the target program corresponding to each translation unit.

[0184] It should be noted that the processor 70 may also include a decoding unit 703. The decoding unit 703 is used to decode the instructions to be executed.

[0185] The processing unit 702 may include an execution unit 7021. The execution unit 7021 is used to perform arithmetic operations.

[0186] Optionally, the processing unit 702 may also include a physical register file 7022. During instruction execution, the instruction may include source operands that need to be read from the physical register file 7022. The physical register file may also store other data related to instruction execution. For example, the execution result of the execution unit 7021 may be written back to the physical register file 7022.

[0187] Optionally, the execution unit 7021 may include at least one arithmetic unit. The at least one arithmetic unit may be of different types, such as a fixed-point arithmetic unit, a floating-point arithmetic unit, etc.

[0188] Optionally, the processor provided in this embodiment of the invention can be a single-issue processor. A single-issue processor means that it fetches only one instruction from memory in one clock cycle, decodes only one instruction, executes only one instruction, and writes only one operation result.

[0189] It should be noted that the embodiments of the present invention do not limit the type and implementation of the processor. For example, the processor can be a microprocessor, a chip, etc.

[0190] Figure 8 Another structural block diagram of the processor provided in an embodiment of the present invention. Figure 8 The processor shown is compared to Figure 7 The processor shown can be a multi-issue processor. A multi-issue processor is one that can fetch multiple instructions from memory and decode them simultaneously within a single clock cycle. For example... Figure 8 As shown, the processor provided in this embodiment of the invention, in Figure 7 Based on the processor shown, it may also include a renaming unit 7023, an issuing unit 7024, and a reordering unit 7025.

[0191] The renaming unit 7023 is used to rename the address of the instruction written back to the physical register file 7022.

[0192] The sending unit 7024 is used to determine which unit to send the instruction to for execution, for example, to the execution unit, or to the fixed-point arithmetic unit in the execution unit, or to the floating-point arithmetic unit in the execution unit, and so on.

[0193] The reordering unit 7025 is used to mark the data at the write-back address of the instruction in the physical register file 7022 as committed, according to the order of the instructions.

[0194] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0195] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0196] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0197] This invention provides an electronic device for instruction jumps. The electronic device is applied to a binary translation system for translating a source program in a client machine into a target program in a host machine. The electronic device includes a memory and one or more programs, which are stored in the memory and configured to be executed by one or more processors. The one or more programs contain instructions for performing the following operations: when the source program is translated into the target program, obtaining a first jump instruction, which is an instruction of the target program in the host machine, and the first jump instruction includes a first opcode register identifier; executing the first jump instruction to record the number of times the first jump instruction is executed and the number of times it misses in the corresponding jump refill table entry according to the first register identifier.

[0198] In another embodiment of the present invention, the electronic device includes one or more programs, which are further configured to be executed by one or more processors. The one or more programs include instructions for performing the following operations: when the source program is translated into a target program, obtaining a first jump instruction, wherein the first jump instruction is an instruction of the target program in the host machine; the first jump instruction includes a first register identifier; executing the first jump instruction to record the number of times the first jump instruction is executed and the number of times it misses in a preset jump refill table according to the first register identifier; and rearranging the instructions stored in the predicted jump address of the first jump instruction according to the number of times the first jump instruction is executed and the number of times it misses.

[0199] Figure 9 This is a structural block diagram illustrating an electronic device 300 for instruction switching according to an exemplary embodiment. For example, the electronic device 300 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0200] Reference Figure 9 The electronic device 300 may include one or more of the following components: a processor 70, a memory 302, and a computer program 3021 stored in the memory 302 and executable on the processor. When the processor 70 executes the program, it implements the data processing method of the foregoing embodiments.

[0201] In an exemplary embodiment, the electronic device 300 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0202] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 304 including instructions, which can be executed by a processor 70 of an electronic device 300 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0203] A non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform... Figure 1 The instruction jump method is shown.

[0204] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0205] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0206] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0207] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0208] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0209] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0210] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0211] The foregoing has provided a detailed description of the instruction jump method, processor, and electronic device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for instruction jump, characterized in that, Applied to a binary translation system for translating a source program in a client machine into a target program in a host machine, the method includes: When the source program is translated into the target program, a first jump instruction is obtained. The first jump instruction is an instruction of the target program in the host machine. The first jump instruction includes a first register identifier. Execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in the corresponding jump refill table entry according to the first register identifier; The method further includes: Obtain the table entry control instruction, wherein the table entry control instruction is the corresponding instruction of the host machine; Execute the table entry control command to perform a control operation on the preset jump and refill table; The table entry control instructions include table entry setting instructions, and the control operation for performing a preset jump and refill table includes: A first preset threshold and a second preset threshold are set for the preset jump refill table. The first preset threshold is the threshold corresponding to the number of runs recorded in the jump refill table, and the second preset threshold is the threshold corresponding to the number of misses recorded in the jump refill table.

2. The method according to claim 1, characterized in that, The table entry control instructions include table entry reading instructions, and the control operation for performing a preset jump and refill table includes: Read the first and second preset thresholds corresponding to the preset jump refill table.

3. The method according to claim 1, characterized in that, The table entry control instructions include a table entry clearing instruction. Executing the table entry control instructions to perform a control operation on a preset jump and refill table operation includes: After each time the first preset threshold and the second preset threshold of the jump refill table are reset, the table entry clearing command is executed to clear the records of each table entry in the jump refill table.

4. The method according to claim 3, characterized in that, The table entry clearing instruction also includes a second register identifier, and the method further includes: If the number of runs recorded in the entry corresponding to the second register identifier is greater than or equal to the first preset threshold, then the entry clearing instruction is executed to clear the entry and refill the record in the entry corresponding to the second register identifier.

5. The method according to any one of claims 1 to 4, characterized in that, After obtaining the first jump instruction and before executing the first jump instruction, the method further includes: Determine if there are any unused entries in the preset redirect and refill table; If there are no unoccupied entries in the jump refill table, the target entry is determined based on the attribute information of each entry in the jump refill table. The register identifier corresponding to the target entry is determined as the first register identifier of the first jump instruction and the second register identifier of the entry clear instruction; Execute the entry clearing instruction to clear the record corresponding to the second register identifier in the table and jump to refill the record; the attribute information includes any one of the initial recording time and the record update frequency.

6. A method for instruction jump, characterized in that, Applied to a binary translation system for translating a source program in a client machine into a target program in a host machine, the method includes: When the source program is translated into the target program, a first jump instruction is obtained, wherein the first jump instruction is an instruction of the target program in the host machine; the first jump instruction includes a first register identifier; Execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in a preset jump refill table according to the first register identifier; Based on the number of times the first jump instruction is executed and the number of times it misses, the instructions stored in the predicted jump address of the first jump instruction are rearranged. The predicted jump address includes a first jump address and a second jump address. The first jump address is the target jump address when the first jump instruction hits the jump condition, and the second jump address is the target jump address when the first jump instruction misses the jump condition. Based on the number of times the first jump instruction has been executed and the number of times it has missed the jump condition, the instructions stored in the predicted jump address of the first jump instruction are rearranged, including: Determine whether the number of times the first jump instruction is executed is greater than a first preset threshold; If the number of runs is less than the first preset threshold, the number of runs of the first jump instruction is updated in the jump refill table according to the first register identifier, and it is determined whether the number of misses of the first jump instruction is greater than the second preset threshold. If the number of misses is greater than the second preset threshold, the jump direction of the first jump instruction is adjusted, and the instructions stored in the first jump address and the second jump address are swapped, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

7. The method according to claim 6, characterized in that, The method further includes: If the number of runs is greater than or equal to the first preset threshold, then based on the table entry clearing instruction, the number of runs and the number of misses of the first jump instruction in the jump refill table are cleared to zero.

8. The method according to claim 6, characterized in that, After reordering the instructions stored in the predicted jump address of the first jump instruction, the method further includes: The first jump instruction is converted into a second jump instruction, wherein the binary translation system does not count the number of times the second jump instruction is executed or the number of times it misses.

9. The method according to claim 6, characterized in that, The method further includes: Receive instructions for setting table entries for the jump and refill table; In response to the table entry setting instruction, the first preset threshold and the second preset threshold for the jump refill table are set based on the table entry setting instruction.

10. The method according to claim 9, characterized in that, The method further includes: After each time the first preset threshold and the second preset threshold of the jump refill table are set, a table entry clearing command is executed to clear the records of each table entry in the jump refill table.

11. The method according to any one of claims 6 to 10, characterized in that, After obtaining the first jump instruction and before executing the first jump instruction, the method further includes: Determine if there are any unused entries in the preset redirect and refill table; If there are no unused entries in the jump refill table, the target entry is determined based on the attribute information of each entry in the jump refill table. The register identifier corresponding to the target entry is determined to be the first register identifier of the first jump instruction and the second register identifier of the entry clear instruction; Execute the table entry clear instruction to clear the record in the table corresponding to the second register identifier and jump to refill the table.

12. The method according to claim 11, characterized in that, The attribute information includes at least one of the following: initial recording time and recording update frequency.

13. The method according to any one of claims 6 to 10, characterized in that, The method further includes: If a context switch occurs in the scheduling thread of the binary translation system, the data recorded in the jump refill table is read based on the table entry read instruction, and the read data is stored in the preset memory of the binary translation system.

14. The method according to any one of claims 6 to 10, 12, characterized in that, Before obtaining the first jump instruction, the method further includes: Obtain the source program to be translated, wherein the source program includes at least one jump instruction; The source program is segmented based on the jump instruction to obtain at least one translation unit; Disassemble the at least one translation unit to obtain the assembler program corresponding to each translation unit; The translation function is called to translate the assembly program corresponding to each translation unit, thereby obtaining the target program corresponding to each translation unit.

15. A processor, characterized in that, Applied to a binary translation system, the binary translation system is used to translate a source program in a client machine into a target program in a host machine, the processor comprising: The instruction fetch unit is used to fetch a first jump instruction when the source program is translated into a target program. The first jump instruction is an instruction of the target program in the host machine, and the first jump instruction includes a first register identifier. The processing unit is configured to execute the first jump instruction to record the number of times the first jump instruction was executed and the number of times it was missed in the corresponding jump refill table entry according to the first register identifier; The instruction fetching unit is also used for: Obtain the table entry control instruction, wherein the table entry control instruction is the corresponding instruction of the host machine; The processing unit is also used for: Execute the table entry control command to perform a control operation on the preset jump and refill table; The table entry control instructions include table entry setting instructions, and the processing unit is specifically used for: A first preset threshold and a second preset threshold are set for the preset jump refill table. The first preset threshold is the threshold corresponding to the number of runs recorded in the jump refill table, and the second preset threshold is the threshold corresponding to the number of misses recorded in the jump refill table.

16. The processor according to claim 15, characterized in that, The table entry control instructions include table entry read instructions, and the processing unit is specifically used for: Read the first and second preset thresholds corresponding to the preset jump refill table.

17. The processor according to claim 15, characterized in that, The table entry control instructions include table entry clearing instructions, and the processing unit is specifically used for: After each time the first preset threshold and the second preset threshold of the jump refill table are reset, the table entry clearing command is executed to clear the records of each table entry in the jump refill table.

18. The processor according to claim 17, characterized in that, The entry clearing instruction also includes a second register identifier, and the processing unit is further configured to: If the number of runs recorded in the entry corresponding to the second register identifier is greater than or equal to the first preset threshold, then the entry clearing instruction is executed to clear the entry and refill the record in the entry corresponding to the second register identifier.

19. The processor according to any one of claims 15 to 18, characterized in that, The processing unit is also used for: Determine if there are any unused entries in the preset redirect and refill table; If there are no unoccupied entries in the jump refill table, the target entry is determined based on the attribute information of each entry in the jump refill table. The register identifier corresponding to the target entry is determined as the first register identifier of the first jump instruction and the second register identifier of the entry clear instruction; Execute the entry clearing instruction to clear the record corresponding to the second register identifier in the table and jump to refill the record; the attribute information includes any one of the initial recording time and the record update frequency.

20. A processor, characterized in that, Applied to a binary translation system, the binary translation system is used to translate a source program in a client machine into a target program in a host machine, the processor comprising: The instruction fetch unit is used to fetch a first jump instruction when the source program is translated into a target program. The first jump instruction is an instruction of the target program in the host machine. The first jump instruction includes a first register identifier. The processing unit is configured to execute the first jump instruction, and record the number of times the first jump instruction is executed and the number of times it misses in a preset jump refill table according to the first register identifier; and rearrange the instructions stored in the predicted jump address of the first jump instruction according to the number of times the first jump instruction is executed and the number of times it misses. The predicted jump address includes a first jump address and a second jump address. The first jump address is the target jump address when the first jump instruction hits the jump condition, and the second jump address is the target jump address when the first jump instruction misses the jump condition. Based on the number of times the first jump instruction has been executed and the number of times it has missed the jump condition, the instructions stored in the predicted jump address of the first jump instruction are rearranged, including: Determine whether the number of times the first jump instruction is executed is greater than a first preset threshold; If the number of runs is less than the first preset threshold, the number of runs of the first jump instruction is updated in the jump refill table according to the first register identifier, and it is determined whether the number of misses of the first jump instruction is greater than the second preset threshold. If the number of misses is greater than the second preset threshold, the jump direction of the first jump instruction is adjusted, and the instructions stored in the first jump address and the second jump address are swapped, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

21. An electronic device, characterized in that, The electronic device includes a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors using the instruction jump method as described in any one of claims 1 to 5 or 6 to 14.

Images