Data processing system and method for reading instruction data of instruction from memory

Abstract

The present invention provides a data processing system and a method for reading instruction data from a memory. The data processing system includes a microprocessor and a memory, and is capable of checking the integrity of data read from the memory by the microprocessor. When an instruction address is transmitted from the microprocessor to the memory for reading instruction data corresponding to the instruction address, predetermined dummy data is read from the memory simultaneously with the instruction data. The integrity of the instruction data can be checked by comparing the predetermined dummy data with hardwired data not stored in the memory. If the dummy data matches the hardwired data, the instruction data read from the memory is determined to be correct.

Description

Technical Field

[0001] The present application relates to a data processing system, and more particularly, to a data processing system and a method thereof for loading instruction data of an instruction from a memory. Background Art

[0002] In a data processing system, a microprocessor can access memory (e.g., read-only memory (ROM), random access memory (RAM), or any other non-volatile memory) using an instruction address to load instruction data. However, in many cases, the output of the memory can be affected by various factors, such as temperature and power supply voltage fluctuations (e.g., voltage drops, surges, or rising / falling conditions). For example, under low-voltage operation, voltage fluctuations can cause errors in instruction data read from the memory, causing the microprocessor to execute incorrect instructions. In some cases, due to the execution of the incorrect instruction, critical data may be deleted from the memory, causing serious failure of the memory. Summary of the Invention

[0003] In the present application, a data processing system and method thereof are provided to prevent erroneous instruction data from being read from a memory.

[0004] In one embodiment of the present application, a data processing system includes a memory, a read data check circuit, and a microprocessor. The memory includes a first area and a second area, wherein the first area stores a plurality of instruction data and the second area stores dummy data. The read data check circuit is coupled to the second area of ​​the memory to receive the dummy data and compare the dummy data with hardwired data. The microprocessor is coupled to the memory and the read data check circuit and is configured to: access the memory using an instruction address to retrieve the instruction data; receive the instruction data from the first area and a comparison result from the read data check circuit in response to the instruction address; and determine, based on the comparison result, that the instruction data corresponds to the instruction address.

[0005] In one embodiment of the present application, a method for reading instruction data of an instruction from a memory is provided, comprising: receiving a first instruction address corresponding to a first instruction; obtaining the first instruction data and first dummy data from the memory based on the first instruction address; comparing the first dummy data with hardwired data; and then providing the first instruction data to a microprocessor when it is determined that the dummy data matches the hardwired data.

[0006] In the present invention, a comparison stage is added to the instruction pipeline of the instruction. Therefore, the application cross-checks the integrity of the instruction data by using dummy data that is read at the same time (or under the same conditions) as the instruction data, thereby reducing the chance of executing an erroneous or undesirable instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a data processing system according to an embodiment of the present application;

[0008] Figure 2 is a schematic diagram of an instruction pipeline architecture of a microprocessor in a data processor system according to an embodiment of the present application;

[0009] Figure 3 is a schematic diagram of an instruction pipeline of a microprocessor for processing multiple instructions according to an embodiment of the present application;

[0010] Figure 4 FIG. 4 is a flowchart of reading data from a memory according to an embodiment of the present application.

[0011] Description of the accompanying drawings

[0012] 10: instruction; 212: instruction decoding unit;

[0013] 100: data processing system; 213: instruction issuing unit;

[0014] 110: microprocessor; 214: functional unit;

[0015] 120: memory; 216: register file;

[0016] 121: first zone; 217: control and interface circuit;

[0017] 122: Second area; 218: Address generation circuit;

[0018] 130: sense amplifier circuit; 260: read data check circuit;

[0019] 131: first sense amplifier; CP1, CP2, CP3: comparison stage;

[0020] 133: Second sense amplifier; EXEC1, EXEC2, EXEC3: Execution

[0021] 140: comparator; stage;

[0022] 141: Read failure counter; ID1, ID2, ID3: instruction decoding stage;

[0023] 150: Multiplexer; IF1, IF2, IF3: Extraction stage;

[0024] 200: data processor system; NOP: transfer character;

[0025] 201: system bus; OP1: first instruction;

[0026] 210: microprocessor; OP2: second instruction;

[0027] 211: instruction fetch unit; OP3: third instruction;

[0028] S401, S403, S405, S407, S409, S411, S413, S415, S417, S419, S421: steps. DETAILED DESCRIPTION

[0029] The following provides a plurality of embodiments for implementing the present application. In the following description, the coupling of a first feature and a second feature may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which the first feature and the second feature are connected by an additional feature so that the first feature and the second feature may not be in direct contact. In addition, the present application may repeat reference numerals and / or letters in various examples, and this repetition is for the purpose of simplicity and clarity.

[0030] In a data processing system, a microprocessor accesses a memory according to an instruction address to obtain instruction data. Typically, the microprocessor will not find or verify whether the instruction data received from the memory is correct, and therefore may execute an erroneous or unexpected instruction. In the present application, a comparison stage is added to the instruction pipeline of the instruction. In detail, using an instruction to access the memory will output at least two pieces of data from the memory. In response to the instruction address, the memory will output the instruction data and dummy data specified by the instruction address. The correctness of the instruction address (that is, whether the instruction data corresponds to the instruction address) can be checked by using dummy data that is also read from the memory at the same time as the instruction data. Therefore, the present application cross-checks the integrity of the instruction data by using dummy data that is read at the same time as the instruction data (or under the same conditions), thereby reducing the chance of executing erroneous or unexpected instructions.

[0031] like Figure 1As shown, a data processing system 100 according to an embodiment of the present application includes a microprocessor 110, a memory 120, a sense amplifier circuit 130, a comparator 140, and a multiplexer 150. The microprocessor 110 is coupled to the memory 120 and the comparator 140. In addition, the microprocessor 110 may be coupled to input / output devices (not shown) via a bus (not shown). The memory 120 may include a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an electrically programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a NAND flash memory, or a NOR flash memory, or a combination thereof. In addition, the present application may also include a flash memory having a serial peripheral interface (SPI) interface, such as an SPI NAND. In this embodiment, the memory 120 may be a ROM. The memory 120 is coupled to the sense amplifier circuit 130 for data reading. In an embodiment, memory 120 includes a first area 121 and a second area 122. First area 121 is configured to store program codes of instructions and data required to execute instructions (eg, instruction data corresponding to instruction addresses), while second area 122 is configured to store predetermined virtual data.

[0032] In an embodiment, the dummy data may be predetermined data having a number of bits, such as 2, 4, 8, 16, or 32 bits. The dummy data represents expected data used to check the integrity of instruction data read from the memory 120. The sense amplifier circuit 130 includes at least a first sense amplifier (SA) 131 and a second sense amplifier 133. The first sense amplifier 131 is coupled between the first region 121 of the memory 120 and the microprocessor 110 to provide the data stored in the first region 121 to the microprocessor 110. The second sense amplifier 133 is coupled between the second region 122 of the memory 120 and the comparator 140 to provide the dummy data stored in the second region 122 to the comparator 140.

[0033] Comparator 140 is configured to receive dummy data and hardwired data, and to compare the dummy data with the hardwired data to determine whether any data read from first region 121 of memory 120 during a particular access is correct based on the dummy data obtained from second region 122 of memory 120. That is, for each access to memory 120, data from first region 121 and dummy data from second region 122 of memory 120 are obtained via first sense amplifier 131 and second sense amplifier 133, respectively. In one embodiment, comparator 140 further includes a read fail counter 141 that tracks the number of failed reads of an instruction address. When the number of read failures reaches a predetermined number, read fail counter 141 may output a read fail signal to terminate the read attempt. The present application is not limited to the location of read fail counter 141. In alternative embodiments, the read fail counter may be located external to comparator 140 and coupled between comparator 140 and multiplexer 150.

[0034] In an embodiment, the hardwired data may be implemented by a logic circuit having a plurality of logic gates or switches programmed to represent a predetermined number of bits having a specific pattern (i.e., a series of 1s and 0s). In one embodiment, the hardwired data may have a bit pattern that is instruction data (e.g., a refresh command, a reset command, an erase command, or other command that resets or erases the instruction pipeline of the microprocessor). In other embodiments, the hardwired data may be part of the microprocessor 110 that is specifically programmed to have the bit pattern described above.

[0035] Multiplexer 150 is coupled between sense amplifier 130 and microprocessor 110. Multiplexer 150 is configured to select data obtained from first region 121 of memory 120 or hardwired data as output to microprocessor 110 based on a read fail signal. The read fail signal may be obtained from read fail counter 141 based on the number of read attempts. In one embodiment, unless the read fail signal is set (i.e., logic 1), multiplexer 150 may be configured to output data obtained from first region 121 of memory 120. However, the present application does not limit the parity of the read fail signal used to select data obtained from first region 121 of memory 120 or hardwired data. In another embodiment, the read fail signal used to select data obtained from first region 121 of memory 120 may have a logic value of 1, while the read fail signal used to select hardwired data may have a logic value of 0. The read fail signal may be output by microprocessor 110 or comparator 140, and the present application does not limit the source or generation method of the read fail signal.

[0036] In operation of the data processing system 100, the microprocessor 110 is configured to execute instructions using an instruction pipeline, wherein the execution of instructions can be broken down into several stages, such as an instruction fetch stage, an instruction decode stage, an instruction execute stage, a compare stage, and a write-back stage. The microprocessor 110 may include: a cache memory having a relatively high access rate; and a translation table (e.g., a translation lookaside table) that records the location of instruction data corresponding to the instruction (i.e., the instruction address). When the microprocessor 110 receives an instruction, the microprocessor 110 may access the translation table and obtain the instruction address corresponding to the address in the specified memory 120. Therefore, the microprocessor 110 accesses the memory 120 using the instruction address to obtain the instruction data. In response to the instruction address received from the microprocessor 110, the memory 120 outputs the instruction data from the first area 121 of the memory 120 and the dummy data from the second area 122 of the memory 120 through the sense amplifier circuit 130. First area 121 of memory 120 is addressable by instruction addresses from microprocessor 110, while second area 122 of memory 120 is not addressable. The same dummy data stored in second area 122 of memory 120 should be obtained along with the instruction data from first area 121 of memory 120 upon each access by microprocessor 110 in response to the instruction address. However, due to conditions such as voltage fluctuations that cause read errors as described above, the data read from memory 120 may be incorrect. In such cases, the dummy data read from second area 122 of memory 120 can be used to check the integrity of instruction data read from first area 121 of memory 120 simultaneously or in response to the same access to memory 120. Because the dummy data is predetermined, expected data, data processing system 100 can compare the read dummy data with predetermined, hardwired data not stored in memory 120.

[0037] If the dummy data matches the hardwired data, data processing system 100 determines that the instruction data read from first area 121 of memory 120 is correct. That is, the instruction data corresponds to the instruction address used to access memory 120. If the dummy data does not match the hardwired data, data processing system 100 determines that the instruction data read from first area 121 of memory 120 is incorrect (i.e., a read error). The dummy data obtained through this first access to memory 120 will be referred to as first dummy data. The microprocessor's instruction pipeline will be paused, and microprocessor 110 will access memory 120 again using the same instruction address to retrieve the instruction data. It should be noted that the above process is referred to as a second access to memory 120 by using the same instruction address as the first access to memory 120. The instruction data obtained from memory 120 during the second access to memory 120 will be referred to as second instruction data, while the instruction data obtained during the first access to memory 120 will be referred to as first instruction data. Similarly, dummy data obtained during the first access period will be referred to as first dummy data, and dummy data obtained during the second access period will be referred to as second dummy data.

[0038] The second access to memory 120 may include multiple second accesses to memory 120. Each of the second accesses to memory 120 uses the instruction address to obtain the second instruction data and the second dummy data. The second access to memory 120 is repeatedly performed until the second dummy data read from the second area 122 of memory 120 matches the hardwired data or a maximum number of attempts is reached. The maximum number of attempts is a predetermined number of times the microprocessor 110 attempts to access memory 120 using the same instruction address. When the maximum number of attempts is reached, the hardwired data is transmitted to the microprocessor 110 instead of the (second) instruction data, thereby concluding the process of reading the instruction data from memory 120. The hardwired data may have a bit pattern representing a refresh command, a reset command, an erase command, or other command that resets, erases, or terminates the microprocessor's instruction pipeline. Specifically, a read fail signal is transmitted to multiplexer 150 (e.g., a select input terminal of the multiplexer), which is configured to select the hardwired data as an output to the microprocessor 110. According to the hard-wired data, the microprocessor 110 will then refresh, reset, erase or terminate the current instruction pipeline. Therefore, the execution of instruction data erroneously read from the memory 120 can be prevented.

[0039] exist Figure 2In the data processor system 200, the microprocessor 210 is coupled to the memory 120 via the system bus 201, wherein instruction addresses, instruction data, and other data / control signals are transmitted between the microprocessor 210 and the memory 120 via the system bus 201. In this embodiment, the data processor system 200 includes a read data check circuit 260 coupled between the microprocessor 210 and the memory 120. The read data check circuit 260 may include the following: Figure 1 The comparator 140 and the multiplexer 150 shown in FIG are used to check the integrity of the instruction data read from the memory 120. The read data check circuit 260 receives the hard-wired data (e.g., from a hard-wired logic circuit), however, the present application is not limited thereto. In some other embodiments, the hard-wired data may be embedded in the read data check circuit 260. It should be noted that, as Figure 1 The sense amplifier circuit 130 shown in FIG. 1 is also included in Figure 2 In the embodiment shown in , the sense amplifier circuit 130 may be disposed between the microprocessor 210 and the memory 120 or at the front end of the memory 120 for reading data from the memory 120 .

[0040] In an embodiment, microprocessor 210 may include an instruction fetch unit 211, an instruction decode unit 212, an instruction issue unit 213, functional units 214, a register file 216, and control and interface circuitry 217 having an address generation circuit 218. The instruction fetch unit 211 is coupled to the instruction decode unit 212. The instruction decode unit 212 is coupled to the register file 216. The instruction issue unit 213 is coupled to the instruction decode unit 212 and the functional units 214. In some embodiments, the instruction issue unit 213 may also be coupled to the register file 216. The functional units 214 are coupled to the instruction issue unit 213 and the register file 216. The control and interface circuitry 217 is coupled to the instruction fetch unit 211, the instruction decode unit 212, the instruction issue unit 213, and the functional units 214. The control and interface circuitry 217 is configured as a communication interface that provides a method for communication between the microprocessor 210 and other hardware devices (e.g., memory 120) via the system bus 201. In some embodiments, control and interface circuitry 217 may also be coupled to register file 216 (not shown).

[0041] When instruction 10 is received by microprocessor 210, instruction fetch unit 211 extracts instruction data (e.g., instruction opcode, assembly code) of instruction 10 from memory 120 via control and interface circuit 217. This may be referred to as the instruction fetch (IF) stage. In one embodiment, address generation circuit 218 generates an instruction address corresponding to the received instruction 10 and transmits the instruction address to memory 120 via system bus 201. Memory 120 transmits the instruction data corresponding to the instruction address back to microprocessor 210 via system bus 201. Next, instruction decode unit 212 may access register file 216 or memory 120 to obtain operand data specified by instruction 10. This may be referred to as the instruction decode (ID) stage. Once the operand data is decoded, the instruction data and corresponding operand data are transmitted to instruction issue unit 213. In an embodiment, the instruction issue unit 213 is configured to check the comparison result between the virtual data read from the second area 122 of the memory 120 and the hardwired data. This may be referred to as the compare (CP) stage or the instruction issue stage. The comparison result may be presented by one or more bits obtained from the read data check circuit 260, and the comparison result may be transmitted to the microprocessor 210 as one of the control signals. It should be noted that the comparison result may be a signal indicating that the currently fetched instruction data is correct or a signal indicating that a subsequent instruction can be processed. This application does not limit the implementation of the comparison result. If the comparison result indicates that the instruction data is correct (or that the subsequent instruction is allowed), the instruction data and corresponding operand data are transmitted to the functional unit 214 for execution. This may be referred to as the execute (Exec) stage. If the comparison result indicates that the instruction data is incorrect, the instruction pipeline will be paused and the instruction data for the current instruction will be fetched again.

[0042] Figure 3A timing diagram of microprocessor 110 and microprocessor 210 is shown for processing a first instruction (OP1), a second instruction (OP2), and a third instruction (OP3). In one embodiment, the forward character NOP indicates a pause in which no instructions (operations) are being executed during these clock cycles. As described above, each instruction is processed sequentially in stages, including an instruction fetch stage (IF), an instruction decode stage (ID), a compare stage (CP), and an execute stage (EXEC). In one embodiment, the first instruction (OP1) is successfully processed through the IF stage (IF1) in the first clock cycle, the ID stage (ID1) in the second clock cycle, the CP stage (CP1) in the third clock cycle, and then the EXEC stage (EXEC1) in the fourth clock cycle. The second instruction (OP2) is first fetched in the second clock cycle (i.e., the IF stage, IF2) and decoded in the third clock cycle (i.e., the ID stage, ID2). The integrity of the (second) instruction data can be checked in the compare stage (CP2) in the fourth clock cycle. However, the comparison result of the second instruction indicating instruction data read from memory 120 may be incorrect. In other words, the dummy data read from the second area 122 of the memory 120 simultaneously with the instruction data read from the first area 121 does not match the hardwired data. The microprocessor will halt the pipeline in the fourth clock cycle and will fetch (IF2) the second instruction (OP2) again in the fifth clock cycle. Meanwhile, the instruction fetch (IF3) of the third instruction will be postponed until the sixth clock cycle.

[0043] In an embodiment, the instruction data fetch (IF2) of the second instruction fails again at the second comparison stage (CP2) of the second instruction in the seventh clock cycle. As a result, the instruction pipeline will be paused again in the seventh clock cycle, wherein the second instruction fetch (IF3) of the third instruction after the second instruction will be postponed to the ninth clock cycle again. In an embodiment, the instruction data of the second instruction will be continuously read from the memory when trying for the second time, wherein the instruction data fetched (IF2) in the eighth clock cycle will be determined to be correct (i.e., the virtual data matches the hardwired data) and executed (Exec2) in the eleventh clock cycle. Because the comparison stage (CP2) of the second instruction in the tenth clock cycle will indicate that the instruction data read from the memory is correct, the instruction data of the third instruction fetched (IF3) in the ninth clock cycle will continue the instruction decoding stage (ID3) in the tenth clock cycle, the comparison stage (CP3) in the eleventh clock cycle, and the execution stage (EXEC3) in the final twelfth clock cycle.

[0044] It should be noted that the microprocessor of the present application will continue to re-fetch the second instruction, halt the pipeline, and postpone the instruction fetch (IF3) of the third instruction until a predetermined number of attempts (i.e., a maximum number of attempts) for reading the instruction data of the instruction from the memory is reached. The read data check circuit 260 may include a counter that tracks the number of times the instruction data fetched using the same instruction address is determined to have failed to read or is incorrect. When the counter reaches the predetermined number of attempts, the read data check circuit 260 (e.g., multiplexer 150) transmits hardwired data as the fetched instruction data to the microprocessor instead of re-accessing the memory, where the hardwired data may be a command to terminate, erase, reset, or refresh the instruction pipeline of the microprocessor.

[0045] exist Figure 4 In an embodiment of the present invention, the microprocessor may receive one or more instructions for execution and will therefore access the memory to obtain instruction data corresponding to the received instructions. Figure 4 As shown, in step S401, an instruction address corresponding to an instruction may be received from a memory by a microprocessor. In step S403, instruction data specified by the instruction address is obtained from a first area of ​​the memory, and dummy data is obtained from a second area of ​​the memory. For example, the microprocessor retrieves the instruction data by transmitting the instruction address to the memory. In response to the instruction address, the memory is accessed to obtain both the instruction data from the first area and the dummy data from the second area.

[0046] In step S405, the virtual data obtained from the second area of ​​the memory is compared with the hardwired data. In an embodiment, the hardwired data is predetermined and not stored in the memory. If the virtual data matches the hardwired data (i.e., the "yes" path of step S405), the process proceeds to step S407. In step S407, the instruction data corresponding to the instruction address is provided to the microprocessor. If the virtual data does not match the hardwired data (i.e., the "no" path of step S405), the process proceeds to step S413, which will be described later.

[0047] In step S409, it is determined whether the current instruction is the last instruction. In other words, step S409 determines whether there are other instruction addresses to be processed. If so, the process proceeds to step S421 to set an incomplete instruction status bit for indicating that all instruction data have been extracted. Then, the process ends. On the other hand, if step S409 determines that the current instruction is not the last instruction, the process proceeds to step S411. In step S411, a ready signal (also referred to as a second signal) is provided to indicate that the memory is ready to receive the next address. In an embodiment, the ready signal can be provided to the microprocessor from a comparator (or a data read check circuit).

[0048] Referring back to step S405, if the virtual data does not match the hardwired data (i.e., the "No" path), the process proceeds to step S413. In step S413, a Not Ready signal (also referred to as a first signal) is provided to indicate that the memory is not ready to receive the next instruction address. In an embodiment, the Not Ready signal can be provided to the microprocessor from a comparator (or a data read check circuit). In one embodiment, the Ready signal and the Not Ready signal can be a single bit, in which a logic "1" and a logic "0" can represent Ready and Not Ready, respectively. In other words, the process can set and reset a bit of one of the control signals to inform the microprocessor whether the memory is ready to receive the next instruction address.

[0049] In step S415, a read fail counter is incremented to track the number of read fails caused by one instruction address. In some embodiments, the read fail counter may be reset after determining that the dummy data matches the hardwired data (step S405) because the microprocessor will be provided with instruction data corresponding to the instruction address and will process instruction data corresponding to the next instruction.

[0050] At step S417, the process determines whether the read fail counter has reached the maximum read attempts. If so, the process proceeds to step S419, in which hard-wired data is provided to the microprocessor (via a multiplexer) to reset, erase, or refresh the microprocessor's instruction pipeline. The process then proceeds to S421 to end the process by setting the incomplete instruction status bit, because the instruction pipeline will be erased, reset, or refreshed in response to the hard-wired data. On the other hand, when the process determines that the read fail counter has not reached the maximum read attempts (the "No" path), the process returns to step S403, where the same instruction address is used to obtain another instruction data from the first area of ​​the memory and another dummy data from the second area of ​​the memory. In other words, if the attempt to read the instruction data corresponding to the instruction address does not reach the maximum read attempts, the memory will be accessed again by using the same instruction address.

[0051] In one embodiment, step S409 and step S421 are optional. That is, step S407 directly transfers to step S411, and step S419 directly transfers to the end of the process.

[0052] The features of several embodiments have been summarized above so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art will appreciate that they may readily use this application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this application, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of this application.

Claims

1. A data processing system comprising: A memory comprising a first area and a second area; a read data check circuit coupled to the second region of the memory to receive dummy data and compare the dummy data to hardwired data; as well as a microprocessor, coupled to the memory and the read data check circuit, configured to: access the memory using an instruction address to retrieve instruction data; receiving the instruction data from the first region and a comparison result from the read data check circuit in response to the instruction address; Determining, based on the comparison result, that the instruction data corresponds to the instruction address, wherein the read data checking circuit comprises: a comparator coupled between the second region of the memory and the microprocessor, and a multiplexer coupled between the first region of the memory and the microprocessor and configured to: receive the instruction data and the hardwired data from the first region of the memory; and selecting the hard-wired data or the instruction data received from the memory as output to the microprocessor according to a read failure signal.

2. The data processing system of claim 1 , wherein when the comparison result indicates that the virtual data matches the hardwired data, the microprocessor determines that the instruction data received from the first region of the memory corresponds to the instruction address and fetches another instruction address of a subsequent instruction from the memory. 3 . The data processing system of claim 1 , wherein the microprocessor accesses the memory again using the instruction address when the comparison result indicates that the virtual data does not match the hardwired data.

4. The data processing system of claim 1 , wherein the microprocessor includes an instruction pipeline that processes a plurality of instructions in a received order, wherein the microprocessor is configured to stall the instruction pipeline when the comparison result indicates that the virtual data does not match the hardwired data.

5. The data processing system of claim 1, wherein the read fail signal is set according to a predetermined number of maximum attempts to read the memory, and the hardwired data is selected as the output to the microprocessor to terminate execution of the instruction address. 6 . The data processing system according to claim 1 , wherein the hard-wired data is a refresh instruction to refresh an instruction pipeline of the microprocessor.

7. The data processing system according to claim 1, further comprising: A sense amplifier circuit is coupled to the memory and reads the instruction data from the first region of the memory and the dummy data from the second region of the memory, wherein the instruction data is output to the microprocessor and the dummy data is output to the read data check circuit.

8. The data processing system of claim 1 , wherein the microprocessor is configured to process a first instruction and a second instruction in an instruction pipeline, wherein the instruction pipeline comprises an instruction fetch stage, an instruction decode stage, a compare stage, and an execute stage, wherein the compare stage pauses the instruction pipeline and restarts from the instruction fetch stage of the first instruction when the comparison result indicates that the virtual data does not match the hardwired data.

9. The data processing system of claim 8, wherein the microprocessor continues processing the second instruction upon determining that the dummy data matches the hardwired data in the comparison stage of the first instruction.

10. The data processing system according to claim 1, wherein the hard-wired data is predetermined and stored in a storage circuit other than the memory, and the memory is a non-volatile memory.

11. A method for reading instruction data of an instruction from a memory, comprising: receiving a first instruction address corresponding to a first instruction; obtaining first instruction data and first dummy data from the memory based on the first instruction address; comparing the first virtual data with hardwired data; selecting the first instruction data or the hard-wired data received from the memory as output to the microprocessor according to a read failure signal; as well as Upon determining that the first virtual data matches the hardwired data, the first instruction data is provided to the microprocessor.

12. The method according to claim 11, further comprising: When it is determined that the first virtual data matches the hardwired data, the first instruction data corresponding to the first instruction address is provided to the microprocessor.

13. The method according to claim 11, further comprising: After determining that the first dummy data matches the hardwired data, a second instruction address of a second instruction following the first instruction is received.

14. The method according to claim 11, further comprising: Upon determining that the first dummy data does not match the hardwired data, a first signal is provided to the microprocessor to indicate that the memory is not ready for a second instruction following the first instruction.

15. The method according to claim 11, further comprising: A read fail counter is incremented upon determining that the first dummy data does not match the hardwired data.

16. The method according to claim 15, further comprising: A determination is made as to whether the read failure counter has reached a predetermined number of read attempts.

17. The method according to claim 16, further comprising: The first instruction data and the first dummy data are repeatedly obtained from the memory based on the first instruction address until the read fail counter reaches the predetermined number of read attempts.

18. The method according to claim 16, further comprising: The hardwired data is provided to the microprocessor upon determining that the read fail counter has reached the predetermined number of read attempts.

19. The method of claim 11, wherein the hardwired data is predetermined and stored in a storage circuit other than the memory.

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