A solid-state storage device and a method for writing data thereto

Abstract

The present application provides a solid-state storage device and a method for writing data thereto, wherein the method comprises the following steps: in response to receiving a write command, identifying whether the write command hits a cache unit; if the write command hits the cache unit, determining whether the hit cache unit is affected by a flush command; if the hit cache unit is affected by the flush command, temporarily caching the write command to wait until the flush command is processed before processing the write command or allocating a new cache unit that is not affected by the flush command to the write command.

Description

Technical Field

[0001] The present application relates to a storage device, and more particularly to a solid-state storage device and a method for writing data thereto. Background Art

[0002] Figure 1 The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The solid-state storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control the data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used to store and manage the mapping of the host logical address to the flash memory physical address, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] In existing solid-state storage devices, FTL (Flash Translation Layer) is used to maintain mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of solid-state storage devices perceived by upper-layer software such as operating systems. Physical addresses are addresses used to access physical storage units of solid-state storage devices. In related technologies, address mapping can also be implemented using intermediate address forms. For example, logical addresses are mapped to intermediate addresses, and then the intermediate addresses are further mapped to physical addresses.

[0008] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is an important metadata in a solid-state storage device. Usually, the data items of the FTL table record the address mapping relationship in units of data pages in the solid-state storage device.

[0009] The NVMe protocol also defines a flush command, which instructs the storage device to save all data (and its metadata) to be written by all commands received before the flush command to the non-volatile storage medium.

[0010] Solid-state storage devices use cache to improve performance. For a write command, after the data indicated by the write command is written to the cache, it indicates that the write command processing is complete. Due to the existence of the cache, when processing the Flush command, the data in the cache must be written to the non-volatile storage medium, and this process takes too long. It is necessary to reduce or avoid the performance jitter caused by the process of writing the data in the cache to the non-volatile storage medium experienced by the host due to the Flush command. Summary of the invention

[0011] The solid-state storage device and the method for writing data thereto of the present application solve the problem of performance jitter caused by a Flush command when the solid-state storage device writes data.

[0012] According to the first aspect of the present application, the present application provides a method for writing data to a solid-state storage device, which includes the following steps: in response to receiving a flush command, obtaining the current time to generate a timestamp associated with the flush command; accessing a cache descriptor; obtaining timestamp data in the cache descriptor; and writing data of a cache unit indicated by a cache descriptor whose timestamp is earlier than the timestamp of the flush command into a non-volatile memory.

[0013] According to the first aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein the flush command processing is indicated to be completed when the data of the cache units indicated by all cache descriptors whose timestamps are earlier than the timestamp of the flush command are written into the non-volatile memory.

[0014] According to the first aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein the cache descriptor includes an index of an allocated cache unit, a timestamp indicating a write time of the allocated cache unit, and an address of data in the allocated cache unit.

[0015] According to a first aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein an address of the data is a logical address or a physical address of a non-volatile memory.

[0016] According to a first aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein when a write command is received, a cache unit and a cache descriptor of a dynamic random access memory are allocated to the write command.

[0017] According to a first aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, after receiving a flush command, a mark is set to indicate that there is a flush command to be processed; after the flush command processing is completed, the set mark is cleared.

[0018] According to the second aspect of the present application, the present application also provides a method for writing data to a solid-state storage device, which includes the following steps: in response to data being written to a cache unit of a dynamic random access memory, polling a cache descriptor; and writing the data in the cache unit to a non-volatile memory according to the cache descriptor.

[0019] According to a second aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, in response to data in a cache unit being written into a non-volatile memory, the cache unit is released.

[0020] According to the third aspect of the present application, the present application also provides a method for writing data to a solid-state storage device, which includes the following steps: in response to receiving a write command, identifying whether the write command hits a cache unit; if the write command hits the cache unit, determining whether the hit cache unit is affected by the flush command; if the hit cache unit is affected by the flush command, temporarily caching the write command to wait until the flush command is processed before processing the write command or allocating a new cache unit that is not affected by the flush command to the write command.

[0021] According to a third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, if the write command does not hit a cache unit, an idle cache unit is allocated for the write command, and data corresponding to the write command is stored in the cache unit.

[0022] According to the third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein whether the write command hits the cache unit is identified by determining whether the logical address to be accessed by the write command is consistent with the logical address recorded by the cache descriptor.

[0023] According to the third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, if the hit cache unit is not affected by the flush command, the write command to be written is stored in the hit cache unit, and an indication is given that the write command processing is completed.

[0024] According to the third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, when there is no flush command to be executed or there is a flush command to be executed but the timestamp of the flush command to be executed is less than the timestamp of the hit cache unit, it is determined that the hit cache unit is not affected by the flush command.

[0025] According to the third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, when there is a flush command to be executed and the timestamp of the flush command to be executed is not less than the timestamp of the hit cache unit, it is determined that the hit cache unit is affected by the flush command.

[0026] According to a third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, while temporarily caching the write command, the command continues to be received and processed.

[0027] A method for writing data to a solid-state storage device according to the third aspect of the present application, wherein a new cache unit not affected by a flush command is allocated to a write command, which is any unoccupied cache unit when there is no flush command to be executed, or an unoccupied cache unit where there is a flush command to be executed but the timestamp of the flush command to be executed is less than the timestamp of the cache unit.

[0028] According to the third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein, after allocating a new cache unit that is not affected by a flush write command to a write command, a cache descriptor is also allocated to the new cache unit that is not affected by a flush write command.

[0029] According to the third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein the cache descriptor includes an index of an allocated cache unit, a timestamp indicating a write time of the allocated cache unit, and an address of data in the allocated cache unit.

[0030] According to a method for writing data to a solid-state storage device according to the third aspect of the present application, after the data corresponding to the write command is stored in a cache unit, the completion of the write command is indicated.

[0031] According to a fourth aspect of the present application, the present application also provides a solid-state storage device, comprising a dynamic random access memory, a controller and a non-volatile memory, wherein the controller executes one of the methods described above.

[0032] According to a fourth aspect of the present application, the present application also provides a program comprising program code, which, when loaded into a CPU and executed in the CPU, causes the CPU to execute one of the methods described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0034] Figure 1 A schematic diagram of the structure of a solid-state storage device in the prior art;

[0035] Figure 2 is a schematic diagram of the structure of a solid-state storage device according to an embodiment of the present application;

[0036] Figure 3 is a cache descriptor according to an embodiment of the present application;

[0037] Figures 4A-4C A schematic diagram of processing a Flush command according to an embodiment of the present application;

[0038] Figures 5A-5D Schematic diagram of processing a Flush command according to another embodiment of the present application;

[0039] Figure 6 A flowchart of using cache to process a Flush command according to an embodiment of the present application;

[0040] Figure 7 A flowchart of using cache to process Flush commands according to another embodiment of the present application DETAILED DESCRIPTION

[0041] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0042] Figure 2 The block diagram of a solid-state storage device according to an embodiment of the present application is shown. The control component of the solid-state storage device includes a host interface 210, a CPU 220, an address translation unit 230, and a media interface 240 for accessing the NVM chip 105. The control component is also coupled to an external memory (eg, DRAM) 260.

[0043] The memory of the control unit stores cache descriptors, one or more of which record the address of the corresponding cache unit 265 in DRAM 260 and the storage device address of the data occupying the cache unit (eg, the logical address or physical address of the storage device accessible by the host).

[0044] The host interface 210 is used to exchange commands and data with the host. For example, the host and the storage device communicate via the NVMe / PCIe protocol, the host interface 210 processes the PCIe protocol data packet, extracts the NVMe protocol command, and returns the processing result of the NVMe protocol command to the host.

[0045] The CPU 220 is coupled to the host interface 210, and is used to receive IO commands sent by the host to the storage device, and use one or more cache units 265 to service the received IO commands. If the host uses a logical address to access the storage device, the CPU 220 also accesses the address conversion unit 230 to convert the logical address into a physical address. The CPU 220 also sends the received IO command (the form of the IO command may change during the processing process, and is collectively referred to as an IO command here for simplicity) to the media interface 240, and the media interface 240 accesses one or more NVM chips according to the IO command.

[0046] Figure 3 A cache descriptor according to an embodiment of the present application is shown.

[0047] Each cache descriptor is used to describe a corresponding cache unit. The cache descriptor records the index of the corresponding cache unit ( Figure 3 The cache unit index, timestamp and logical address (LBA) of the cache unit descriptor. The cache unit index indicates the location of the cache unit in DRAM 260. The timestamp records the time when the cache unit is allocated, and the logical address (LBA) records the logical address accessed by the IO command to which the cache unit is allocated. It can be understood that when the host uses the physical address to access the storage device, the logical address field of the cache unit descriptor is replaced to record the physical address.

[0048] Figures 4A-4C A schematic diagram of processing a Flush command according to an embodiment of the present application is shown.

[0049] Figure 4A The IO commands received in the command queue are shown in chronological order. The earliest write command (IOW1) is received at time T1, followed by a write command (IO W2) at time T2, and then a flush command, followed by a write command (IO W3) and a write command (IO W4) at time T3 and time T4, respectively. Figure 4A In FIG. 1 , the arrow indicates the direction of time flow. The time when the Flush command is received is between time T3 and time T4.

[0050] Figure 4BThe state of the cache unit before the Flush command is processed is shown. According to the storage device of the embodiment of the present application, after receiving the Flush command, it does not stop receiving and processing other IO commands. Therefore, although the Flush command is received before the write command (IO W3), the write command (IO W3) and the write command (IO W4) have been processed, the cache unit (indicated by ID3) is allocated to the write command (IO W3), and the data to be written by the write command (IO W3) has been stored in the cache unit, and the cache unit (indicated by ID4) is allocated to the write command (IO W4), but the data to be written by the write command (IO W4) has not yet been written into the cache unit.

[0051] Figure 4C 1 shows the state of the cache unit after processing the Flush command. In response to receiving the Flush command, all IO commands received before receiving the Flush command (see Figure 4A , write command (IO W1) and write command (IO W2)) to write the data to be written into the non-volatile storage medium (eg, NVM chip 105, see also Figure 2 ). Next, the host can be informed that the Flush command has been processed. At this time, whether the data to be written by the write command (IO W3) and the write command (IO W4) is written into the non-volatile storage medium is not subject to the semantic constraints of the Flush command.

[0052] Figures 5A-5D A schematic diagram of processing a Flush command according to another embodiment of the present application is shown.

[0053] Figure 5A and Figure 4A Similarly, the IO commands received in the command queue are shown in chronological order. The earliest write command (IO W1) is received at time T1, followed by a write command (IO W2) at time T2, and then a flush command, followed by a write command (IO W3) and a write command (IO W4) at time T3 and time T4, respectively. Figure 5A In FIG. 1 , the arrow indicates the direction of time flow. The time when the Flush command is received is between time T3 and time T4.

[0054] Figure 5BThe state of the cache unit before the Flush command is processed is shown. According to the storage device of the embodiment of the present application, after receiving the Flush command, it does not stop receiving and processing other IO commands. Therefore, although the Flush command is received before the write command (IO W3), the write command (IO W3) and the write command (IO W4) have already been processed, and a cache unit (indicated by ID3) is allocated to the write command (IO W3), and the data to be written by the write command (IO W3) has not yet been stored in the cache unit. And before the Flush command starts to be processed, the write command (IO W4) has not yet been allocated a cache unit.

[0055] Figure 5C The state of the cache unit at a certain moment in the process of processing the Flush command is shown. In response to receiving the Flush command, all IO commands received before receiving the Flush command (see Figure 5A , write command (IO W1) and write command (IO W2)) to write the data to be written into the non-volatile storage medium (eg, NVM chip 105, see also Figure 2 ).exist Figure 5C At the moment of the display, the data to be written by the write command (IO W1) has been written into the non-volatile storage medium, while the data to be written by the write command (IO W2) has not been written into the non-volatile storage medium. The data to be written by the write command (IO W3) has not yet been written into the cache unit. And the cache unit has not yet been allocated to the write command (IO W4).

[0056] Figure 5D Shows the state of the cache unit after processing the Flush command. All IO commands received before receiving the Flush command (see Figure 5A , the data to be written by the write command (IO W1) and the write command (IO W2)) has been written to the non-volatile storage medium (eg, NVM chip 105, see also Figure 2 ). Since the write command (IO W1) is processed, the cache unit occupied by it is released, and the cache unit can be allocated to other write commands. The cache unit occupied by the write command (IO W2) has not been released yet.

[0057] Next, the host can be informed that the Flush command has been processed. At this time, whether the data to be written by the write command (IO W3) and the write command (IO W4) is written to the non-volatile storage medium is not subject to the semantic constraints of the Flush command. For example, see Figure 5D , the data to be written by the write command (IO W3) has not yet been written into the cache unit. And the cache unit (ID 4) is allocated to the write command (IO W4).

[0058] Figure 6This is a flowchart of using cache to process Flush commands according to an embodiment of the present application.

[0059] according to Figure 6 The processing flow shown in the embodiment of Figure 2 The CPU 220 controls and coordinates with other parts of the control component 104 to complete the task.

[0060] In response to an IO command (610) obtained from the host interface, the type of the IO command is identified to distinguish whether the IO command is a write command (620) or a flush command (670). For a write command, a cache is allocated for the write command, for example, an unused cache unit and a cache descriptor are allocated. The address of the allocated cache unit, a timestamp indicating the current time, and the data to be written by the write command are recorded in the cache descriptor, and the data to be written is obtained from the host, and the data to be written is stored in the allocated cache unit (630). Although the data corresponding to the write command has not been written to the NVM chip, the host can be indicated that the write command processing is completed (640).

[0061] Another task executed in the CPU is used to move the data written into the cache unit to the NVM chip (650). For example, in response to data being written into the cache unit, the process of moving the data into the NVM chip is started. As another example, each cache descriptor is polled to move the data of the cache unit into which the data is written to the NVM chip in turn. Optionally, in response to the data in the cache unit being moved to the NVM chip, the cache unit is released, so that the timestamp in the cache unit is updated (or cleared), and the cache unit can be allocated to other write commands.

[0062] For an IO command obtained from the host interface, such as a Flush command, the current time is obtained to generate a timestamp associated with the Flush command (680). By accessing each cache descriptor, it is identified whether the data of the cache units indicated by each cache descriptor with a timestamp earlier than the timestamp of the Flush command have all been moved to the NVM chip (660). If the data of the cache units indicated by each cache descriptor with a timestamp earlier than the timestamp of the Flush command have all been moved to the NVM chip, the host is indicated that the Flush command processing is completed (690).

[0063] If the data of the cache units indicated by the cache descriptors with timestamps earlier than the timestamp of the Flush command have not been moved to the NVM chip, for the Flush command, after the data of the cache units indicated by the cache descriptors with timestamps earlier than the timestamp of the Flush command have been moved to the NVM chip (660), the host is informed that the Flush command processing is complete (690). It can be understood that while waiting for the data of the cache units indicated by the cache descriptors with timestamps earlier than the timestamp of the Flush command to be moved to the NVM chip, the execution can continue. Figure 6 The process shown in FIG. 1 obtains IO commands from the host interface and processes them.

[0064] For example, if a Flush command is received, a flag is set to indicate that a Flush command is pending. And after each IO command is obtained from the host interface, if a flag indicating that a Flush command is pending is found, each cache descriptor is accessed to identify whether the data of the cache units indicated by each cache descriptor whose timestamp is earlier than the timestamp of the Flush command has been moved to the NVM chip. If it is identified that the Flush command has been processed, the set flag is also cleared.

[0065] See also Figure 6 As an example, the task of moving the data written to the cache unit to the NVM chip is continuously executed, rather than being executed in response to identifying that the data of the cache units indicated by the cache descriptors with a timestamp earlier than the timestamp of the Flush command have not all been moved to the NVM chip. However, the processing of the Flush command depends on moving the data of the cache units associated with the Flush command in the cache unit to the NVM chip. Optionally, in response to processing the Flush command, the task of moving the data of the cache units associated with the Flush command to the NVM chip is prioritized so that the data written to these cache units can be moved to the NVM chip as soon as possible.

[0066] Figure 7 This is a flowchart of using cache to process Flush commands according to another embodiment of the present application.

[0067] exist Figure 6 Based on the flowchart shown, according to Figure 7 The flowchart of the embodiment further handles the situation where the IO write command hits the cache unit.

[0068] In response to receiving a write command (720), it is determined whether the write command hits the cache unit by determining whether the logical address to be accessed by the write command is consistent with the logical address recorded in the cache descriptor (730).

[0069] If the write command does not hit the cache unit, an idle cache unit is allocated for the write command, a timestamp indicating the current time is recorded in the cache entry corresponding to the cache unit, and the data corresponding to the write command is stored in the cache unit (740). And the completion of the write command processing is indicated to the host (770).

[0070] If the write command hits the cache unit, it is further identified whether the hit cache unit is a cache unit affected by the Flush command and its data needs to be written into the NVM chip (750). If the hit cache unit is not affected by the Flush command (there is no Flush command to be executed, or there is a Flush command to be executed, but the timestamp of the Flush command to be executed is less than the timestamp of the hit cache unit), the data to be written by the write command is stored in the hit cache unit (760), and the host is indicated that the write command processing is completed (770). If the hit cache unit is affected by the Flush command (there is a Flush command to be executed, and the timestamp of the Flush command to be executed is not less than the timestamp of the hit cache unit) (750), the write command is temporarily cached (780) to wait until the Flush command is processed before processing the write command. During the temporary caching of the write command, other IO commands are also obtained from the host interface for processing to avoid performance jitter of the storage device caused by executing the Flush command.

[0071] Optionally, if the hit cache unit is affected by the Flush command, a new cache unit and cache descriptor are allocated for the write command, the address of the allocated cache unit, a timestamp indicating the current time, and the data to be written by the write command are recorded in the cache descriptor, the data to be written is obtained from the host, the data to be written is stored in the allocated cache unit, and then the host is indicated that the write command processing is completed.

[0072] The embodiment of the present application also provides a program including program code. When the program is loaded into a host and executed on the host, the program enables the processor of the host to execute one of the methods according to the embodiment of the present application provided above.

[0073] It should be understood that each block of the block diagram and the flow chart and the combination of blocks of the block diagram and the flow chart can be implemented by various means including computer program instructions, respectively. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer or other programmable data control device to produce a machine, so that the instructions executed on the computer or other programmable data control device create a device for implementing the functions specified in one or more flow chart blocks.

[0074] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data control device to function in a particular manner, so that the instructions stored in the computer readable memory can be used to manufacture an article of manufacture including computer readable instructions for implementing the functions specified in one or more flowchart blocks. The computer program instructions may also be loaded onto a computer or other programmable data control device to cause a series of operations to be performed on the computer or other programmable data control device, thereby producing a computer-implemented process, and the instructions executed on the computer or other programmable data control device provide operations for implementing the functions specified in one or more flowchart blocks.

[0075] Thus, the blocks of the block diagrams and flow charts support a combination of means for performing a specified function, a combination of operations for performing a specified function, and a combination of program instruction means for performing a specified function. It should also be understood that each block of the block diagrams and flow charts and the combination of blocks of the block diagrams and flow charts can be implemented by a hardware-based special-purpose computer system that performs the specified function or operation, or by a combination of special-purpose hardware and computer instructions.

[0076] Although the present invention has been described with reference to examples, this is for illustrative purposes only and is not intended to limit the present application, and changes, additions and / or deletions to the embodiments may be made without departing from the scope of the present application.

[0077] Those skilled in the art to which these embodiments relate and who benefit from the teachings presented in the above description and associated drawings will recognize many modifications and other embodiments of the present application described herein. Therefore, it should be understood that the present application is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used only in a general and descriptive sense and are not used for the purpose of limitation.

Claims

1. A method for writing data to a solid-state storage device, characterized in that: The steps include: In response to receiving a write command, identifying whether the write command hits a cache unit; If the write command hits the cache unit, determining whether the hit cache unit is affected by the flush command; If the hit cache unit is affected by the flush command, temporarily cache the write command to wait until the flush command is processed before processing the write command or allocate a new cache unit that is not affected by the flush command for the write command; When there is a flush command to be executed and the timestamp of the flush command to be executed is not less than the timestamp of the hit cache unit, it is determined that the hit cache unit is affected by the flush command.

2. The method for writing data to a solid-state storage device according to claim 1, wherein: If the write command does not hit the cache unit, an idle cache unit is allocated for the write command, and the data corresponding to the write command is stored in the cache unit.

3. The method for writing data to a solid-state storage device according to claim 1, wherein: If the hit cache unit is not affected by the flush command, the write command to be written is stored in the hit cache unit, and the write command processing is indicated to be completed.

4. The method for writing data to a solid-state storage device according to claim 3, characterized in that: When there is no flush command to be executed or there is a flush command to be executed but the timestamp of the flush command to be executed is smaller than the timestamp of the hit cache unit, it is determined that the hit cache unit is not affected by the flush command.

5. The method for writing data to a solid-state storage device according to claim 1, wherein: in, While the write command is temporarily buffered, commands continue to be received and processed.

6. The method for writing data to a solid-state storage device according to claim 1, wherein: in, The new cache unit not affected by the flush command allocated to the write command is any unoccupied cache unit when there is no flush command to be executed, or an unoccupied cache unit where there is a flush command to be executed but the timestamp of the flush command to be executed is less than the timestamp of the cache unit.

7. The method for writing data to a solid-state storage device according to claim 6, wherein: in, After allocating a new cache unit that is not affected by the flush command to the write command, a cache descriptor is also allocated to the new cache unit that is not affected by the flush command.

8. The method for writing data to a solid-state storage device according to any one of claims 2 to 7, characterized in that: After the data corresponding to the write command is stored in the cache unit, the write command is indicated to be completed.

9. A solid-state storage device comprising a dynamic random access memory, a controller and a non-volatile memory, wherein: The controller executes the method according to any one of claims 1-8.

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