Chip verification method, device, electronic device and storage medium

Abstract

The embodiments of the present application provide a chip verification method, device, electronic device and storage medium, the method comprising: constructing a simulation linked list in a reference model based on a linked list to be tested in the chip to be tested; when the chip to be tested performs a first read operation on the linked list to be tested and obtains a first read result, reading the simulation linked list based on the reference model according to the first read operation to obtain a second read result; determining whether the linked list logic verification of the linked list to be tested passes based on the first read result and the second read result; when the linked list logic verification of the linked list to be tested passes, verifying the first chip logic and the second chip logic in the chip to be tested based on the reference model. It is possible to separately verify the linked list logic of the linked list to be tested in the chip to be tested and the chip logic in the chip to be tested, thereby improving the accuracy of the verification of the chip to be tested.

Description

Technical Field

[0001] The present application relates to the field of chip verification, and more specifically, to a chip verification method, device, electronic device and storage medium. Background Art

[0002] In the prior art, when a reference model constructs a simulation linked list based on the chip to be tested to store data, the constructed simulation linked list is consistent with the linked list to be tested in the chip to be tested, and the chip to be tested generates a request to read the linked list to be tested from the first internal logic, obtains the data in the linked list to be tested, and then executes the second internal logic of the chip to be tested to generate a simulation result. After the reference model waits for the read request of the linked list to be tested of the chip to be tested, it reads data from the simulation linked list, one data slice at a time, and then executes the second internal logic in the reference model to generate a simulation result, which is sent to the comparator to compare the simulation result of the chip to be tested with the simulation result of the reference model, thereby realizing the verification of the chip to be tested.

[0003] However, the above chip verification method has the following defects: the reference model needs to be completely aligned with the chip to be tested, including the read and write timing of the linked list, in order to verify the chip to be tested, which results in a long verification time for the chip to be tested. In addition, the linked list logic of the linked list to be tested of the chip to be tested and the chip logic of the chip to be tested are verified at the same time during the verification, resulting in poor verification accuracy. Summary of the invention

[0004] The purpose of the present application is to provide a chip verification method, device, electronic device and storage medium, which can shorten the chip verification time and improve the accuracy of chip verification.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a chip verification method, the method comprising:

[0007] Based on the linked list to be tested in the chip to be tested, a simulation linked list is constructed in the reference model;

[0008] When the chip under test performs a first read operation on the linked list under test to obtain a first read result, the simulation linked list is read according to the first read operation based on the reference model to obtain a second read result;

[0009] Based on the first reading result and the second reading result, determining whether the linked list logic verification of the linked list to be tested passes;

[0010] When the linked list logic of the linked list to be tested is verified, the first chip logic and the second chip logic in the chip to be tested are verified based on the reference model, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the read linked list data in the linked list to be tested.

[0011] In an optional implementation, when there are multiple first reading results and multiple second reading results, the step of determining whether the linked list logic verification of the linked list to be tested passes based on the first reading result and the second reading result includes:

[0012] Determining whether each of the first reading results is consistent with the corresponding second reading result;

[0013] When each of the first reading results is consistent with each of the corresponding second reading results, it is determined that the linked list logic verification of the linked list to be tested passes.

[0014] In an optional embodiment, the method further comprises:

[0015] When there is inconsistency between each of the first reading results and each of the corresponding second reading results, determining that the linked list logic verification of the linked list to be tested fails;

[0016] The linked list logic of the linked list to be tested is corrected based on the linked list logic of the simulated linked list of the reference model.

[0017] In an optional implementation, the reference model constructs a first standard logic based on the first chip logic of the chip to be tested, and constructs a second standard logic based on the second chip logic, and the step of verifying the first chip logic and the second chip logic in the chip to be tested based on the reference model when the linked list logic of the linked list to be tested passes the verification includes:

[0018] When the linked list logic verification of the linked list to be tested passes, obtaining a target data packet, wherein the target data packet carries a target channel address;

[0019] Slicing the target data packet and storing it in the to-be-tested linked list according to the linked list logic;

[0020] Storing the target data packet in the data storage queue of the reference model;

[0021] The chip under test executes the first chip logic and reads a plurality of first data of the linked list under test;

[0022] After the chip under test processes the plurality of the first data based on the logic of the second chip, a plurality of first processing results are obtained, wherein each of the first processing results carries a channel address;

[0023] Based on the target channel address, determining a plurality of target processing results in each of the first processing results;

[0024] Execute the first standard logic based on the reference model to read the target data packet stored in the data storage queue;

[0025] After slicing the target data packet based on the reference model, a plurality of second processing results are obtained based on the second standard logic in the reference model;

[0026] Based on each of the target processing results and each of the second processing results, the first chip logic and the second chip logic in the chip under test are verified.

[0027] In an optional implementation, the step of verifying the first chip logic and the second chip logic in the chip under test based on each of the target processing results and each of the second processing results includes:

[0028] When each of the target processing results is consistent with each of the second processing results, determining that the first chip logic and the second chip logic in the chip to be tested are correct;

[0029] When there is inconsistency between each of the target processing results and each of the second processing results, it is determined that the first chip logic and the second chip logic in the chip to be tested are wrong.

[0030] In a second aspect, an embodiment of the present application provides a chip verification device, the device comprising:

[0031] A construction module, used for constructing a simulation linked list in a reference model based on the linked list to be tested in the chip to be tested;

[0032] A determination module, configured to read the simulation linked list based on the reference model according to the first reading operation to obtain a second reading result when the chip under test performs a first reading operation on the linked list under test to obtain a first reading result;

[0033] A determination module, configured to determine whether the linked list logic verification of the linked list to be tested passes based on the first reading result and the second reading result;

[0034] A verification module is used to verify the first chip logic and the second chip logic in the chip to be tested based on the reference model when the linked list logic of the linked list to be tested is verified, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the read linked list data in the linked list to be tested.

[0035] In a third aspect, an embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the chip verification method when executing the computer program.

[0036] In a fourth aspect, an embodiment of the present application provides a storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the chip verification method are implemented.

[0037] This application has the following beneficial effects:

[0038] The present application constructs a simulated linked list in a reference model based on a linked list to be tested in a chip to be tested; when the chip to be tested performs a first read operation on the linked list to be tested and obtains a first read result, the simulated linked list is read based on the reference model according to the first read operation to obtain a second read result, and based on the first read result and the second read result, it is determined whether the linked list logic verification of the linked list to be tested passes, and when the linked list logic verification of the linked list to be tested passes, the first chip logic and the second chip logic in the chip to be tested are verified based on the reference model, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the linked list data in the linked list to be tested read. It is possible to separately verify the linked list logic of the linked list to be tested in the chip to be tested and the chip logic in the chip to be tested, thereby improving the accuracy of the verification of the chip to be tested. In addition, when the reference model verifies the linked list logic of the linked list to be tested in the chip to be tested, it does not need to rely on the timing of the chip to be tested, thereby shortening the time for verifying the chip to be tested and improving the efficiency of the verification of the chip to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A block diagram of an electronic device provided in an embodiment of the present application;

[0041] Figure 2One of the flowcharts of a chip verification method provided in an embodiment of the present application;

[0042] Figure 3 A second flow chart of a chip verification method provided in an embodiment of the present application;

[0043] Figure 4 A third flowchart of a chip verification method provided in an embodiment of the present application;

[0044] Figure 5 A structural block diagram of a chip verification device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0048] In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, it is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the invention is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0049] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0050] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0051] After extensive research, the inventors found that in the prior art, during the verification process of the chip to be tested, the reference model needs to be completely aligned with the timing of the chip to be tested, including the read and write timing of the linked list, in order to realize the verification of the chip to be tested. In addition, the construction of the reference model depends on the timing of the chip to be tested, which is unstable. The data channel of the message in each request for scheduling the linked list is out of order. The scheduling processes one data slice at a time and sends out a comparison result. Therefore, the reference model needs to wait for the scheduling result of the chip to be tested, resulting in a slow verification process. In addition, during the verification, the reference model is too dependent on the timing of the chip to be tested, that is, the reference model is often consistent with the practice of the chip to be tested, which will cause problems with the accuracy of the verification of the chip to be tested.

[0052] In view of the discovery of the above problems, the present embodiment provides a chip verification method, device, electronic device and storage medium, which can realize the separate verification of the linked list logic of the linked list to be tested in the chip to be tested and the chip logic in the chip to be tested, thereby improving the accuracy of the verification of the chip to be tested. In addition, when the reference model verifies the linked list logic of the linked list to be tested of the chip to be tested, it does not need to rely on the timing of the chip to be tested, thereby shortening the verification time of the chip to be tested and improving the efficiency of the verification of the chip to be tested. The solution provided by this embodiment is described in detail below.

[0053] This embodiment provides an electronic device that can verify a chip. In a possible implementation, the electronic device can be a user terminal, for example, the electronic device can be, but is not limited to, a server, a smart phone, a personal computer (PC), a tablet computer, a personal digital assistant (PDA), a mobile Internet device (MID), an emulator, etc.

[0054] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of the structure of the electronic device 100 provided in the embodiment of the present application. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0055] The electronic device 100 includes a chip authentication device 110 , a memory 120 , and a processor 130 .

[0056] The memory 120 and the processor 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. The chip verification device 110 includes at least one software function module that can be stored in the memory 120 in the form of software or firmware or solidified in the operating system (OS) of the electronic device 100. The processor 130 is used to execute the executable modules stored in the memory 120, such as the software function modules and computer programs included in the chip verification device 110.

[0057] The memory 120 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc. The memory 120 is used to store a program, and the processor 130 executes the program after receiving an execution instruction.

[0058] Please refer to Figure 2 , Figure 2 For application Figure 1 The flowchart of a chip verification method of the electronic device 100 is shown in FIG. 1 , and each step of the method is described in detail below.

[0059] Step 201: construct a simulation linked list in a reference model based on the linked list to be tested in the chip to be tested.

[0060] Step 202: When the chip under test performs a first read operation on the linked list under test and obtains a first read result, the simulated linked list is read based on the reference model according to the first read operation to obtain a second read result.

[0061] Step 203: Based on the first reading result and the second reading result, determine whether the linked list logic verification of the linked list to be tested passes.

[0062] Step 204: when the linked list logic of the linked list to be tested is verified, the first chip logic and the second chip logic in the chip to be tested are verified based on the reference model.

[0063] The first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the linked list data in the read linked list to be tested.

[0064] The linked list to be tested in the chip to be tested is a storage structure in which the reference of the previous storage unit points to the next storage unit. The linked list connects the storage units through pointers. A linked list is a type of linear list. The so-called linear list includes sequential linear lists and linked lists. Linked lists are not implemented in sequence, but are implemented with pointers or node addresses, and are not continuous in memory.

[0065] The data path layer in the current chip is responsible for receiving, reporting, and forwarding data from the receiving end, as well as allocating and scheduling data to be sent from the sending end. Often in the data path layer, it is necessary to temporarily store the received message or the message data to be sent in the data storage device, and because of time division multiplexing, it is not necessary to wait until all the current messages are received before starting to receive the next message. Often, messages from different data paths are uploaded to the data path layer in segments and interleaved. The linked list can link discontinuous memories.

[0066] The reference model constructs a simulated linked list based on the linked list to be tested in the chip to be tested. Compared with the linked list to be tested, the simulated linked list ensures the accuracy of the linked list logic in the linked list.

[0067] It can be said that the simulated linked list is a standard linked list of the chip to be tested, and the accuracy of the linked list logic of the linked list to be tested of the chip to be tested is verified based on the simulated linked list in the reference model.

[0068] When the list logics of the linked list to be tested and the simulated linked list are completely consistent, it indicates that the list logic of the linked list to be tested in the chip to be tested is accurate. When there is any inconsistency between the list logics of the linked list to be tested and the simulated linked list, it indicates that the list logic of the linked list to be tested in the chip to be tested is inaccurate.

[0069] Exemplarily, when the simulated linked list in the reference model is A chain, B chain, and C, and the linked list to be tested in the chip to be tested is A chain, B chain, and D, when the chip to be tested searches and reads the linked list to be tested with B as the address, D will be read, and when the reference model searches and reads with B as the address, C will be read. The first reading result of the linked list to be tested by the chip to be tested is inconsistent with the second reading result of the simulated linked list by the reference model, so the linked list logic verification of the linked list to be tested in the chip to be tested fails. When the first reading result of the linked list to be tested by the chip to be tested is consistent with the second reading result of the simulated linked list by the reference model, the linked list logic verification of the linked list to be tested in the chip to be tested passes.

[0070] When the linked list logic of the linked list to be tested is verified to be successful, the accuracy of the first chip logic and the second chip logic in the chip to be tested is verified.

[0071] The first chip logic and the second chip logic in the chip to be tested are mainly the logic for realizing the functions of the chip. When the first chip logic and the second chip logic of the chip to be tested are correct, the chip to be tested can realize the functions of the chip. When the first chip logic and the second chip logic of the chip to be tested are wrong, the functions of the chip cannot be realized. Therefore, it is necessary to verify the first chip logic and the second chip logic of the chip to be tested.

[0072] Regarding the verification method of verifying the first chip logic and the second chip logic of the chip to be tested, the first chip logic and the second chip logic of the chip to be tested may be verified based on a reference model.

[0073] In the reference model, the first standard logic and the second standard logic are constructed based on the first chip logic and the second chip logic of the chip to be tested. It should be noted that the first standard logic and the second standard logic in the reference model are the correct logics to realize the functions of the chip to be tested, so that the first chip logic and the second chip logic that may have errors are verified based on the completely correct logic.

[0074] Since the aforementioned part verifies the linked list logic of the linked list to be tested in the chip to be tested, and the linked list logic in the linked list to be tested passes the verification, it can be ensured that when the data in the linked list to be tested is read based on the linked list logic, when the reading operations of the reference model and the chip to be tested are consistent, the data obtained by the chip to be tested and the reference model are consistent, thereby avoiding the influence of the linked list logic and realizing separate verification of the first chip logic and the second chip logic of the chip to be tested.

[0075] Exemplarily, when the linked list logic of the linked list to be tested of the chip to be tested is verified to be passed, a read request for the data in the linked list to be tested is generated based on the first chip logic of the linked list to be tested, and the target data in the linked list to be tested is obtained based on the read request. After the target data is processed by the second chip logic, a target value is obtained. At the same time, when the first standard logic of the reference model is consistent with the first chip logic, the reference model will inevitably generate a request to obtain the target data in the simulation linked list. When the first standard logic of the reference model is consistent with the second chip logic of the chip to be tested, the reference model obtains a data value after processing the target data based on the second standard logic. The data value is inevitably consistent with the target value. Therefore, whether the first chip logic and the second chip logic of the chip to be tested have passed the verification can be judged based on whether the data value is consistent with the target value.

[0076] The present application constructs a simulated linked list in a reference model based on a linked list to be tested in a chip to be tested; when the chip to be tested performs a first read operation on the linked list to be tested and obtains a first read result, the simulated linked list is read based on the reference model according to the first read operation to obtain a second read result, and based on the first read result and the second read result, it is determined whether the linked list logic verification of the linked list to be tested passes, and when the linked list logic verification of the linked list to be tested passes, the first chip logic and the second chip logic in the chip to be tested are verified based on the reference model, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the linked list data in the linked list to be tested read. It is possible to separately verify the linked list logic of the linked list to be tested in the chip to be tested and the chip logic in the chip to be tested, thereby improving the accuracy of the verification of the chip to be tested. In addition, when the reference model verifies the linked list logic of the linked list to be tested in the chip to be tested, it does not need to rely on the timing of the chip to be tested, thereby shortening the time for verifying the chip to be tested and improving the efficiency of the verification of the chip to be tested.

[0077] How to determine whether the linked list logic of the linked list to be tested of the chip to be tested has passed the verification based on the first reading result and the second reading result, with respect to the above step 203, in another embodiment of the embodiment of the present application, as Figure 3 As shown, a chip verification method is provided, which specifically includes the following steps:

[0078] This embodiment is explained in the case where there are a plurality of first reading results and a plurality of second reading results.

[0079] Step 203 - 1 : Determine whether each first reading result is consistent with the corresponding second reading result.

[0080] Step 203 - 2 : when each first reading result is consistent with each corresponding second reading result, it is determined that the linked list logic verification of the linked list to be tested passes.

[0081] Since a linked list is a storage structure in which a reference from a previous storage unit points to a next storage unit, each time data in the linked list to be tested is read, only one slice of data in the linked list to be tested can be read. When multiple data are stored in the linked list to be tested, the chip to be tested will generate multiple first read operations to obtain the data in the linked list to be tested. Each time each first read operation is executed, one piece of data will be obtained, thereby obtaining multiple first read results.

[0082] The reference model is based on a plurality of first read operations of the chip to be tested, and the reference model obtains a plurality of second read results of the simulation linked list.

[0083] Exemplarily, when the simulated linked list in the reference model is A chain, B chain, and C chain, and the linked list to be tested in the chip to be tested is A chain, B chain, and D, when the chip to be tested reads the linked list to be tested, multiple first read operations will be generated to read all the data in the linked list to be tested. When the chip to be tested uses B as the address to search and read the linked list to be tested, the operation of using B as the address to search and read is the first read operation, and what is read at this time is D, that is, the first read result. When the chip to be tested uses A as the address to search and read the linked list to be tested, the operation of using A as the address to search and read is another first read operation, and what is read at this time is B, that is, another first read result. The reference model is based on the first read operation of using B as the address to search and read, and the result of the read is C, that is, the second read result. The reference model uses A as the address to search and read the first read operation, and the result of the read is B, that is, another second read result.

[0084] In the first read operation with B as the address, the first read result of the chip under test is inconsistent with the second read result of the reference model, and in the first read operation with A as the address, the first read result of the chip under test is consistent with the second read result of the reference model. At this time, it is determined that the linked list logic verification of the linked list under test of the chip under test fails.

[0085] In the case where each first reading result is inconsistent with each corresponding second reading result, it is determined that the linked list logic verification of the linked list to be tested has failed, and the linked list logic of the linked list to be tested is corrected based on the linked list logic of the simulated linked list of the reference model. That is, in the above-mentioned first reading operation with B as the address search and reading, when the first reading result of the chip to be tested is inconsistent with the second reading result of the reference model, the linked list logic of the linked list to be tested of the chip to be tested is corrected based on the linked list logic of the simulated linked list of the reference model, thereby ensuring that the linked list logic of the linked list to be tested in the chip to be tested is consistent with the linked list logic of the simulated linked list in the reference model.

[0086] When each first reading result is consistent with each corresponding second reading result, it is determined that the linked list logic verification of the linked list to be tested passes.

[0087] How to verify the first chip logic and the second chip logic of the chip to be tested based on the reference model, with respect to the above step 204, in another embodiment of the embodiment of the present application, as Figure 4 As shown, a chip verification method is provided, which specifically includes the following steps:

[0088] Before the reference model verifies the first chip logic and the second chip logic of the chip to be tested, the reference model constructs a first standard logic based on the first chip logic of the chip to be tested, and constructs a second standard logic based on the second chip logic.

[0089] It should be noted that the first standard logic and the second standard logic are both logics for realizing the functions of the chip under test, and the first chip logic and the second chip logic of the chip under test may have errors, so the first chip logic and the second chip logic of the chip under test need to be verified.

[0090] Step 204 - 1 : when the linked list logic verification of the linked list to be tested passes, the target data packet is obtained.

[0091] The target data packet carries the target channel address.

[0092] Step 204-2: Slice the target data packet and store it in the to-be-tested linked list according to the linked list logic.

[0093] Step 204 - 3 : Store the target data packet into the data storage queue of the reference model.

[0094] Step 204 - 4 : The chip under test executes the first chip logic and reads a plurality of first data in the linked list under test.

[0095] Step 204 - 5 : The chip under test processes the plurality of first data based on the logic of the second chip to obtain a plurality of first processing results.

[0096] Each first processing result carries a channel address.

[0097] Step 204 - 6 : Based on the target channel address, determine a plurality of target processing results in each first processing result.

[0098] Step 204 - 7 : Execute the first standard logic based on the reference model to read the target data packet stored in the data storage queue.

[0099] Step 204 - 8 : After slicing the target data packet based on the reference model, a plurality of second processing results are obtained based on the second standard logic in the reference model.

[0100] Step 204 - 9 : Based on each target processing result and each second processing result, verify the first chip logic and the second chip logic in the chip under test.

[0101] It should be noted that multiple whole packets will be transmitted in sequence in the same channel, and each data packet in the channel carries the channel address of the channel. At this time, the target data packet can be one of the multiple whole packets of the channel. For example, whole packet A, whole packet B and whole packet C will be transmitted in sequence in channel 1. At this time, whole packet A, whole packet B and whole packet C all carry channel address 1, among which whole packet A can be used as the target data packet, and the target channel address of the target data packet is channel 1, whole packet B can be used as the target data packet, and the target channel address of the target data packet is channel 1, and whole packet C can be used as the target data packet, and the target channel address of the target data packet is channel 1.

[0102] The target data packet carrying the target channel address is stored in the chip to be tested and the reference model respectively.

[0103] The target data packet is stored in the reference model and the chip to be tested in different ways. For the chip to be tested, since the data in the linked list to be tested of the chip to be tested is stored as sliced ​​data, when the target data packet is stored in the chip to be tested, the target data packet needs to be sliced ​​and the sliced ​​data is stored according to the linked list logic of the linked list to be tested of the chip to be tested.

[0104] When storing the target data packet into the reference model, the target data packet can be stored in the data storage queue of the reference model, wherein the target data packet is stored in the corresponding channel address in the data storage list according to the target channel address, and at least one data packet is stored in the target channel address.

[0105] The chip under test generates multiple read operations based on the first chip logic in the chip under test, and obtains multiple first data in the linked list under test based on the multiple read operations. After each first data is processed based on the second chip logic of the chip under test, multiple first processing results are obtained. At this time, each first processing result carries a corresponding channel address.

[0106] It should be noted that, since the chip under test reads data in the linked list under test out of order, the multiple first data obtained by the chip under test include not only the slice data of the target data packet but also data other than the slice data of the target data packet.

[0107] Therefore, in order to verify whether the execution logic of the same data in the chip under test is consistent with the execution logic in the reference model, it is necessary to obtain multiple target processing results from multiple first processing results based on the target channel address. The channel address carried by each target processing result is the target channel address, and the target processing result must be the result after processing the target data packet.

[0108] Exemplarily, when the first processing results are: A1-1, B1-1, C1-1, A2-1, D1-2, C2-2, D-3, where A1, B1, C1, D1 are data types, 1, 2 and 3 are channel addresses, when the target data packet is A and the target channel address is 1, the multiple target processing results obtained from the multiple first processing results are A1-1 and A2-1.

[0109] The reference model reads a target data packet in a data storage queue based on a first standard logic.

[0110] It should be noted that, in the reference model, based on the first standard logic, each whole packet of data in the channel corresponding to the target channel address in the data storage queue is read, and each whole packet of data is read in the order of each whole packet of data. A plurality of second reading results are generated, and based on the data type of the target data packet, the reading result of the target data packet is obtained from the plurality of second reading results. The reference model processes the reading result of the target data packet based on the second standard logic to obtain a second processing result.

[0111] The first chip logic and the second chip logic of the chip under test are verified through the multiple target processing results and the second processing results.

[0112] It should be noted that when comparing multiple target processing results and a second processing result, the multiple target processing results can be converted into one target processing result based on a preset algorithm, so as to determine whether the first chip logic and the second chip logic of the chip to be tested are correct by judging whether the converted target processing result and the second processing result are consistent.

[0113] In another example, after slicing the target data packet based on the reference model, multiple second processing results are obtained based on the second standard logic in the reference model. Then, based on each target processing result and each second processing result, that is, each target processing result is compared with each corresponding second processing result, and the first chip logic and the second chip logic of the chip to be tested are verified based on the comparison results.

[0114] When each target processing result is consistent with each second processing result, determining that the first chip logic and the second chip logic in the chip to be tested are correct;

[0115] When there is inconsistency between each target processing result and each second processing result, it is determined that the first chip logic and the second chip logic in the chip to be tested are wrong.

[0116] Please refer to Figure 5 The present application embodiment also provides a method for applying Figure 1 The chip verification device 110 of the electronic device 100 includes:

[0117] A construction module 111 is used to construct a simulation linked list in a reference model based on the linked list to be tested in the chip to be tested;

[0118] A determination module 112 is configured to read the simulation linked list based on the reference model according to the first reading operation to obtain a second reading result when the chip under test performs a first reading operation on the linked list under test to obtain a first reading result;

[0119] A determination module 113, configured to determine whether the linked list logic verification of the linked list to be tested passes based on the first reading result and the second reading result;

[0120] The verification module 114 is used to verify the first chip logic and the second chip logic in the chip to be tested based on the reference model when the linked list logic of the linked list to be tested is verified, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the read linked list data in the linked list to be tested.

[0121] The present application constructs a simulated linked list in a reference model based on a linked list to be tested in a chip to be tested; when the chip to be tested performs a first read operation on the linked list to be tested and obtains a first read result, the simulated linked list is read based on the reference model according to the first read operation to obtain a second read result, and based on the first read result and the second read result, it is determined whether the linked list logic verification of the linked list to be tested passes, and when the linked list logic verification of the linked list to be tested passes, the first chip logic and the second chip logic in the chip to be tested are verified based on the reference model, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the linked list data in the linked list to be tested read. It is possible to separately verify the linked list logic of the linked list to be tested in the chip to be tested and the chip logic in the chip to be tested, thereby improving the accuracy of the verification of the chip to be tested. In addition, when the reference model verifies the linked list logic of the linked list to be tested in the chip to be tested, it does not need to rely on the timing of the chip to be tested, thereby shortening the time for verifying the chip to be tested and improving the efficiency of the verification of the chip to be tested.

[0122] The present application also provides an electronic device 100, which includes a processor 130 and a memory 120. The memory 120 stores computer executable instructions, and when the computer executable instructions are executed by the processor 130, the chip verification method is implemented.

[0123] The embodiment of the present application further provides a storage medium, which stores a computer program. When the computer program is executed by the processor 130, the chip verification method is implemented.

[0124] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0125] In addition, each functional module in each embodiment of the present application can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part. If the function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk.

[0126] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0127] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip verification method, characterized in that: The method comprises: Based on the linked list to be tested in the chip to be tested, a simulation linked list is constructed in the reference model; When the chip under test performs a first read operation on the linked list under test to obtain a first read result, the simulation linked list is read according to the first read operation based on the reference model to obtain a second read result; Based on the first reading result and the second reading result, determining whether the linked list logic verification of the linked list to be tested passes; In the case where the linked list logic of the linked list to be tested is verified, the first chip logic and the second chip logic in the chip to be tested are verified based on the reference model, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the read linked list data in the linked list to be tested; The reference model constructs a first standard logic based on the first chip logic of the chip to be tested, and constructs a second standard logic based on the second chip logic. When the linked list logic of the linked list to be tested passes the verification, the step of verifying the first chip logic and the second chip logic in the chip to be tested based on the reference model includes: When the linked list logic verification of the linked list to be tested passes, obtaining a target data packet, wherein the target data packet carries a target channel address; Slicing the target data packet and storing it in the to-be-tested linked list according to the linked list logic; Storing the target data packet in the data storage queue of the reference model; The chip under test executes the first chip logic and reads a plurality of first data of the linked list under test; After the chip under test processes the plurality of the first data based on the logic of the second chip, a plurality of first processing results are obtained, wherein each of the first processing results carries a channel address; Based on the target channel address, determining a plurality of target processing results in each of the first processing results; Execute the first standard logic based on the reference model to read the target data packet stored in the data storage queue; After slicing the target data packet based on the reference model, a plurality of second processing results are obtained based on the second standard logic in the reference model; Based on each of the target processing results and each of the second processing results, the first chip logic and the second chip logic in the chip under test are verified.

2. The method according to claim 1, characterized in that In the case that there are multiple first reading results and multiple second reading results, the step of determining whether the linked list logic verification of the linked list to be tested passes based on the first reading result and the second reading result includes: Determining whether each of the first reading results is consistent with the corresponding second reading result; When each of the first reading results is consistent with each of the corresponding second reading results, it is determined that the linked list logic verification of the linked list to be tested passes.

3. The method according to claim 2, characterized in that The method further comprises: When there is inconsistency between each of the first reading results and each of the corresponding second reading results, determining that the linked list logic verification of the linked list to be tested fails; The linked list logic of the linked list to be tested is corrected based on the linked list logic of the simulated linked list of the reference model.

4. The method according to claim 1, characterized in that: The step of verifying the first chip logic and the second chip logic in the chip under test based on each of the target processing results and each of the second processing results includes: When each of the target processing results is consistent with each of the second processing results, determining that the first chip logic and the second chip logic in the chip to be tested are correct; When there is inconsistency between each of the target processing results and each of the second processing results, it is determined that the first chip logic and the second chip logic in the chip to be tested are wrong.

5. A chip verification device, characterized in that: The device comprises: A construction module, used for constructing a simulation linked list in a reference model based on the linked list to be tested in the chip to be tested; A determination module, configured to read the simulation linked list based on the reference model according to the first reading operation to obtain a second reading result when the chip under test performs a first reading operation on the linked list under test to obtain a first reading result; A determination module, configured to determine whether the linked list logic verification of the linked list to be tested passes based on the first reading result and the second reading result; A verification module, configured to verify the first chip logic and the second chip logic in the chip to be tested based on the reference model when the linked list logic of the linked list to be tested is verified, wherein the first chip logic is used to generate a read request for the linked list to be tested, and the second chip logic is used to process the read linked list data in the linked list to be tested; The reference model constructs a first standard logic based on the first chip logic of the chip to be tested, and constructs a second standard logic based on the second chip logic, and the verification module is specifically used to: When the linked list logic verification of the linked list to be tested passes, obtaining a target data packet, wherein the target data packet carries a target channel address; Slicing the target data packet and storing it in the to-be-tested linked list according to the linked list logic; Storing the target data packet in the data storage queue of the reference model; The chip under test executes the first chip logic and reads a plurality of first data of the linked list under test; After the chip under test processes the plurality of the first data based on the logic of the second chip, a plurality of first processing results are obtained, wherein each of the first processing results carries a channel address; Based on the target channel address, determining a plurality of target processing results in each of the first processing results; Execute the first standard logic based on the reference model to read the target data packet stored in the data storage queue; After slicing the target data packet based on the reference model, a plurality of second processing results are obtained based on the second standard logic in the reference model; Based on each of the target processing results and each of the second processing results, the first chip logic and the second chip logic in the chip under test are verified.

6. The device according to claim 5, characterized in that In the case where there are multiple first reading results and multiple second reading results, the determination module is further configured to: Determining whether each of the first reading results is consistent with the corresponding second reading result; When each of the first reading results is consistent with each of the corresponding second reading results, it is determined that the linked list logic verification of the linked list to be tested passes.

7. The device according to claim 5, characterized in that The determination module is also used for: When there is inconsistency between each of the first reading results and each of the corresponding second reading results, determining that the linked list logic verification of the linked list to be tested fails; The linked list logic of the linked list to be tested is corrected based on the linked list logic of the simulated linked list of the reference model.

8. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method according to any one of claims 1 to 4 when executing the computer program.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

Images