OTP unit and memory

Abstract

The present application provides an OTP cell and a memory. The OTP cell includes a hard breakdown component, a data reading unit, and a switching unit. Among them, the hard breakdown component includes at least two hard breakdown devices. The output voltage of the hard breakdown component in the short-circuit state is different from the output voltage of the hard breakdown component in the non-short-circuit state. The short-circuit state is the state where all hard breakdown devices are short-circuited, and the non-short-circuit state is other states except the short-circuit state. The hard breakdown device is a device with hard breakdown characteristics; the data reading unit is electrically connected to the hard breakdown component, and the data reading unit is used to convert the output voltage of the hard breakdown component into a digital signal and output it; the switching unit includes at least two switching devices, the switching unit is electrically connected to the hard breakdown component and the data reading unit respectively, and the number of switching devices is the same as the number of hard breakdown devices and they are electrically connected in one-to-one correspondence. This OTP cell ensures better reliable performance.

Description

Technical Field

[0001] The present application relates to the field of memories, and more particularly, to an OTP cell and a memory. Background Art

[0002] OTP (One Time Programable) devices, as a kind of one-time programmable devices, are usually used to store configuration information when the chip is powered on, such as trim information, failure addresses, device IDs, and manufacturing IDs. Due to process difficulties, it is difficult to avoid a small amount of random short circuits (generally in the order of 10 - 100 ppm) during the preparation of MTJ. An ECC module is adopted in the MRAM array to repair random Shorts. If there is a short circuit in the OTP for storing chip configuration information, it will cause incorrect configuration information. Problematic chips can be screened out during the CP test, but the chip yield will be damaged to a certain extent. Taking a 100 ppm short probability and a chip containing 100 bit MTJ OTP information as an example, the yield loss due to MTJ random short circuits is 100 ppm * 100 = 1%; when the chip yield reaches over 90%, a 1% yield loss is quite significant. Therefore, there is an urgent need for a device structure to solve the influence of MTJ short circuits introduced during the existing process manufacturing on the reliability of OTP.

[0003] The above information disclosed in the background art section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that is not prior art known to those skilled in the art in their own country. Summary of the Invention

[0004] The main purpose of the present application is to provide an OTP cell and a memory to solve the problem that the MTJ short circuits introduced during the process manufacturing of the existing technology affect the reliability of OTP.

[0005] To achieve the above object, according to one aspect of the present application, an OTP unit is provided, which includes a hard breakdown component, a data reading unit, and a switching unit. Among them, the hard breakdown component includes at least two hard breakdown devices. The output voltage of the hard breakdown component in the short-circuit state is different from the output voltage of the hard breakdown component in the non-short-circuit state. The short-circuit state is the state where all the hard breakdown devices are short-circuited, and the non-short-circuit state is other states except the short-circuit state. The hard breakdown device is a device with hard breakdown characteristics; the data reading unit is electrically connected to the hard breakdown component, and the data reading unit is used to convert the output voltage of the hard breakdown component into a digital signal and output it; the switching unit includes at least two switching devices, the switching unit is electrically connected to the hard breakdown component and the data reading unit respectively, and the number of the switching devices is the same as the number of the hard breakdown devices and is electrically connected in one-to-one correspondence.

[0006] Optionally, the hard breakdown component further includes an AND gate, the hard breakdown device is a memory bit, the first end of the memory bit is electrically connected to the first end of the switching device in one-to-one correspondence, the second end of the memory bit is electrically connected to the bit line, the second end of the switching device is electrically connected to the word line, the third end of the switching device is grounded, the first end of the memory bit is electrically connected to an input end of the AND gate in one-to-one correspondence, and the output end of the AND gate is electrically connected to the data reading unit.

[0007] Optionally, the hard breakdown component further includes a NAND gate, the hard breakdown device is a memory bit, the first end of the memory bit is electrically connected to the first end of the switching device through a source line in one-to-one correspondence, the second end of the memory bit is electrically connected to the bit line, the second end of the switching device is electrically connected to the word line, the third end of the switching device is grounded, the first end of the memory bit is electrically connected to an input end of the NAND gate in one-to-one correspondence, and the output end of the NAND gate is electrically connected to the data reading unit.

[0008] Optionally, the hard breakdown device is a memory bit, the hard breakdown component includes a first memory bit and a second memory bit, there are two switching devices, namely a first switching device and a second switching device, a first end of the first memory bit is electrically connected to a bit line, a second end of the first memory bit is electrically connected to a first end of the second memory bit, a second end of the second memory bit is electrically connected to a first end of the second switching device through a source line, the second end of the second memory bit is also electrically connected to the data reading unit, a first end and a third end of the first switching device are respectively electrically connected to the first end and the second end of the first memory bit, a second end of the first switching device is electrically connected to a write operation enable switch, a second end of the second switching device is electrically connected to a word line, a third end of the second switching device is grounded, and the second end of the second memory bit is also electrically connected to the data reading unit.

[0009] Optionally, the memory bit is an MTJ.

[0010] Optionally, the first switching device is a PMOS transistor and the second switching device is an NMOS transistor.

[0011] Optionally, the data reading unit includes a sense amplifier and a resistor. The sense amplifier includes a first input terminal, a second input terminal and a first output terminal. The first input terminal is electrically connected to the hard breakdown component, the second input terminal is electrically connected to the resistor, and the first output terminal is the output terminal of the data reading unit.

[0012] Optionally, the hard breakdown device is an RRAM, a PCRAM or a diode.

[0013] Optionally, the switching device is an NMOS transistor. A first end of the switching device is a drain of the NMOS transistor, a second end of the switching device is a gate of the NMOS transistor, and a third end of the switching device is a source of the NMOS transistor.

[0014] Optionally, the NMOS transistor is a thick gate transistor.

[0015] To achieve the above object, according to one aspect of the present application, there is also provided a memory, the memory includes a plurality of OTP units, and the OTP unit is any one of the above-mentioned OTP units.

[0016] The present application provides an OTP unit. The OTP unit includes a hard breakdown component, a data reading unit, and a switching unit. The hard breakdown component includes at least two hard breakdown devices. The output voltage of the hard breakdown component in the short - circuit state is different from the output voltage of the hard breakdown component in the non - short - circuit state. Among them, the short - circuit state is the state where all the hard breakdown devices are short - circuited, and the non - short - circuit state is other states except the short - circuit state. That is, the non - short - circuit state includes the situation where all the hard breakdown devices are operating normally and the situation where some of the hard breakdown devices are short - circuited. The data reading unit is electrically connected to the hard breakdown component and is used to convert the output voltage of the hard breakdown component into a digital signal and output it. The switching unit includes at least two switching devices. The switching unit is electrically connected to the hard breakdown component and the data reading unit respectively. The number of the switching devices is the same as the number of the hard breakdown devices and they are electrically connected in one - to - one correspondence. The output voltage of the OTP unit in the short - circuit state of the hard breakdown component is different from its output voltage in the non - short - circuit state, that is, the output voltage when all the hard breakdown devices are short - circuited is different from the output voltage in other cases. Different voltages are converted into different digital signals and output via the data reading unit, ensuring that when all the hard breakdown devices are short - circuited, it can be detected in time, avoiding the problem of incorrect configuration information when all the hard breakdown devices are short - circuited caused by the process manufacturing in the prior art, and ensuring better reliable performance of the OTP. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The schematic diagrams of the specification drawings forming a part of the present application are used to provide a further understanding of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0018] Figure 1 shows a schematic diagram of an OTP unit according to an embodiment of the present application;

[0019] Figures 2 to 5 respectively show schematic diagrams of OTP units according to four specific embodiments of the present application;

[0020] Figure 6 shows according to Figure 5 the embodiment of the OTP unit timing schematic diagram;

[0021] Figure 7 is a schematic diagram showing a memory according to an embodiment of the present application.

[0022] Among them, the above - mentioned drawings include the following reference numerals:

[0023] 10. OTP unit; 20. Hard breakdown component; 30. Data reading unit; 40. Switching unit; 200. Hard breakdown device; 201. First storage bit; 202. Second storage bit; 203. AND gate; 204. NAND gate; 400. Switching device; 401. First switching device; 402. Second switching device. Detailed implementation manners

[0024] It should be noted that the following detailed description is exemplary and is intended to provide further description of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs.

[0025] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there can also be an intermediate element. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0027] As introduced in the background art, the MTJ short circuit introduced in the prior art process manufacturing has an impact on the OTP reliability. To solve the above problems, the present application proposes an OTP unit and a memory.

[0028] According to a typical embodiment of the present application, as Figure 1As shown, an OTP unit 10 is provided, which includes a hard breakdown component 20, a data reading unit 30, and a switching unit 40. Among them, the above-mentioned hard breakdown component 20 includes at least two hard breakdown devices 200. The output voltage of the above-mentioned hard breakdown component 20 in the short-circuit state is different from the output voltage of the above-mentioned hard breakdown component 20 in the non-short-circuit state. The above-mentioned short-circuit state is a state in which all of the above-mentioned hard breakdown devices 200 are short-circuited, and the above-mentioned non-short-circuit state is other states except the above-mentioned short-circuit state. The above-mentioned hard breakdown device 200 is a device with hard breakdown characteristics; the above-mentioned data reading unit 30 is electrically connected to the above-mentioned hard breakdown component 20, and the above-mentioned data reading unit 30 is used to convert the output voltage of the above-mentioned hard breakdown component 20 into a digital signal and output it; the above-mentioned switching unit 40 includes at least two switching devices 400, and the above-mentioned switching unit 40 is electrically connected to the above-mentioned hard breakdown component 20 and the above-mentioned data reading unit 30 respectively. The number of the above-mentioned switching devices 400 is the same as the number of the above-mentioned hard breakdown devices 200 and they are electrically connected in one-to-one correspondence.

[0029] The above-mentioned OTP unit includes a hard breakdown component, a data reading unit, and a switching unit. The above-mentioned hard breakdown component includes at least two hard breakdown devices. The output voltage of the above-mentioned hard breakdown component in the short-circuit state is different from the output voltage of the above-mentioned hard breakdown component in the non-short-circuit state. Among them, the above-mentioned short-circuit state is a state in which all of the above-mentioned hard breakdown devices are short-circuited, and the above-mentioned non-short-circuit state is other states except the above-mentioned short-circuit state, that is, the non-short-circuit state includes the situation where all of the above-mentioned hard breakdown devices are operating normally and some of the above-mentioned hard breakdown devices are short-circuited. The above-mentioned data reading unit is electrically connected to the above-mentioned hard breakdown component and is used to convert the output voltage of the above-mentioned hard breakdown component into a digital signal and output it. The above-mentioned switching unit includes at least two switching devices. The above-mentioned switching unit is electrically connected to the above-mentioned hard breakdown component and the above-mentioned data reading unit respectively. The number of the above-mentioned switching devices is the same as the number of the above-mentioned hard breakdown devices and they are electrically connected in one-to-one correspondence. For the above-mentioned OTP unit, the output voltage in the short-circuit state of the above-mentioned hard breakdown component is different from its output voltage in the non-short-circuit state, that is, the output voltage when all of the above-mentioned hard breakdown devices are short-circuited is different from the output voltage in other cases. Different voltages are converted into different digital signals and output through the above-mentioned data reading unit, ensuring that when all of the above-mentioned hard breakdown devices are short-circuited, it can be detected in time, avoiding the problem of incorrect configuration information when all hard breakdown devices are short-circuited in the prior art during the process of process manufacturing, and ensuring better reliable performance of the OTP.

[0030] According to a specific embodiment of the present application, the above-mentioned hard breakdown component further includes an AND gate, the above-mentioned hard breakdown device is a memory bit, the first end of the above-mentioned memory bit is electrically connected to the first end of the above-mentioned switching device in one-to-one correspondence, the second end of the above-mentioned memory bit is electrically connected to the bit line, the second end of the above-mentioned switching device is electrically connected to the word line, the third end of the above-mentioned switching device is grounded, the first end of the above-mentioned memory bit is electrically connected to an input end of the above-mentioned AND gate in one-to-one correspondence, and the output end of the above-mentioned AND gate is electrically connected to the above-mentioned data reading unit. The above-mentioned OTP storage unit, through the first end of the above-mentioned memory bit being electrically connected to an input end of the above-mentioned AND gate in one-to-one correspondence, and the output end of the above-mentioned AND gate being electrically connected to the above-mentioned data reading unit, further ensures that when all the above-mentioned memory bits are short-circuited, the output value of the above-mentioned data reading unit is different from the output value in other cases, further ensures that the short-circuit state of the above-mentioned hard breakdown device can be recognized in time, and further avoids the problem of incorrect configuration information caused by the short-circuit state of the hard breakdown device in the OTP unit.

[0031] It should be noted that the output voltage of the above-mentioned hard breakdown component in the short-circuit state is converted by the above-mentioned data reading unit and output as 1. In a specific embodiment, when the above-mentioned hard breakdown component further includes an AND gate, when the above-mentioned hard breakdown component is in the short-circuit state, that is, when all the above-mentioned memory bits are short-circuited, the above-mentioned data reading unit outputs 1; when the above-mentioned hard breakdown component is in the non-short-circuit state, that is, when all the above-mentioned memory bits are working normally or some of the above-mentioned memory bits are short-circuited, the above-mentioned data reading unit outputs 0.

[0032] According to another specific embodiment of the present application, the above-mentioned hard breakdown component further includes a NAND gate, the above-mentioned hard breakdown device is a memory bit, the first end of the above-mentioned memory bit is electrically connected to the first end of the above-mentioned switching device in one-to-one correspondence through the source line, the second end of the above-mentioned memory bit is electrically connected to the bit line, the second end of the above-mentioned switching device is electrically connected to the word line, the third end of the above-mentioned switching device is grounded, the first end of the above-mentioned memory bit is electrically connected to an input end of the above-mentioned NAND gate in one-to-one correspondence, and the output end of the above-mentioned NAND gate is electrically connected to the above-mentioned data reading unit. The above-mentioned OTP storage unit, the first end of the above-mentioned memory bit is electrically connected to an input end of the above-mentioned NAND gate in one-to-one correspondence, and the output end of the above-mentioned NAND gate is electrically connected to the above-mentioned data reading unit, which further ensures that when all the above-mentioned memory bits are short-circuited, the output value of the above-mentioned data reading unit is different from the output value in other cases, further ensures that it can be detected in time when all the above-mentioned memory bits are short-circuited, and further avoids the problem of incorrect configuration information.

[0033] In another specific embodiment, when the above-mentioned hard breakdown component further includes a NAND gate, when the above-mentioned hard breakdown component is in a short-circuit state, that is, when all the above-mentioned memory bits are short-circuited, the output of the above-mentioned data reading unit is 0; when the above-mentioned hard breakdown component is in a non-short-circuit state, that is, when all the above-mentioned memory bits are operating normally or some of the above-mentioned memory bits are short-circuited, the output of the above-mentioned data reading unit is 1.

[0034] In order to further ensure that when all the above-mentioned memory bits are short-circuited, the output value of the above-mentioned data reading unit is different from the output values in other cases, further ensure that the short-circuit state of the above-mentioned hard breakdown device can be recognized in a timely manner, and further avoid the problem that the configuration information of the OTP unit is incorrect due to the short-circuit state of the hard breakdown device. According to another specific embodiment of the present application, the above-mentioned hard breakdown device is a memory bit, the above-mentioned hard breakdown component includes a first memory bit and a second memory bit, there are two above-mentioned switching devices, namely a first switching device and a second switching device, the first end of the above-mentioned first memory bit is electrically connected to the bit line, the second end of the above-mentioned first memory bit is electrically connected to the first end of the above-mentioned second memory bit, the second end of the above-mentioned second memory bit is electrically connected to the first end of the above-mentioned second switching device through the source line, the second end of the above-mentioned second memory bit is also electrically connected to the above-mentioned data reading unit, the first end and the third end of the above-mentioned first switching device are respectively electrically connected to the first end and the second end of the above-mentioned first memory bit, the second end of the above-mentioned first switching device is electrically connected to the write operation enable switch, the second end of the above-mentioned second switching device is electrically connected to the word line, the third end of the above-mentioned second switching device is grounded, and the second end of the above-mentioned second memory bit is also electrically connected to the above-mentioned data reading unit.

[0035] In the actual application process, when the above-mentioned OTP unit writes data, the above-mentioned second switching device is in an open state. First, the above-mentioned first switching device is turned on, so that the write voltage passes through the above-mentioned second memory bit, causing the above-mentioned second memory bit to be short-circuited. Then, the above-mentioned first switching device is turned off, so that the write voltage passes through the above-mentioned first memory bit, causing the above-mentioned first memory bit to be short-circuited. At this time, the above-mentioned first switching device and the above-mentioned second switching device are both short-circuited, and the output of the above-mentioned data reading unit is 1.

[0036] In the actual application process, the above-mentioned memory bit can include any one or several devices with hard breakdown characteristics. In a specific embodiment, the above-mentioned memory bit is an MTJ.

[0037] The above-mentioned first switching device and the above-mentioned second switching device in the present application can be any switching devices in the prior art. In another specific embodiment of the present application, the above-mentioned first switching device is a PMOS transistor, and the above-mentioned second switching device is an NMOS transistor.

[0038] In another specific embodiment of the present application, the above data reading unit includes a sense amplifier and a resistor. The above sense amplifier includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is electrically connected to the hard breakdown component, the second input terminal is electrically connected to the resistor, and the first output terminal is the output terminal of the data reading unit. The data reading unit including the sense amplifier and the resistor can ensure that the output result is relatively accurate after being processed by the data reading unit.

[0039] In the actual application process, the above hard breakdown device is an RRAM, a PCRAM, or a diode. Both the RRAM, the PCRAM, and the diode have the hard breakdown characteristic, and both can achieve that the output voltage in the short - circuit state is different from the output voltage in the non - short - circuit state. This can further avoid the problem of incorrect configuration information when all hard breakdown devices are short - circuited during the process manufacturing in the prior art, and ensure that the OTP has better reliable performance. Of course, the above hard breakdown device can also be other devices with the hard breakdown characteristic.

[0040] According to another specific embodiment of the present application, the above switching device is an NMOS transistor. The first end of the switching device is the drain of the NMOS transistor, the second end of the switching device is the gate of the NMOS transistor, and the third end of the switching device is the source of the NMOS transistor.

[0041] In order to ensure better reliability of the above NMPS transistor, in the actual application process, the above NMOS transistor is a thick - gate transistor.

[0042] According to another typical embodiment of the present application, a memory is further provided. The above memory includes a plurality of OTP units, and the OTP units are any of the above - mentioned OTP units.

[0043] The above - mentioned memory, including a plurality of OTP units, ensures that the output voltage when all the above - mentioned hard breakdown devices are short - circuited is different from the output voltage in other cases. The different voltages are converted into different digital signals and output via the above data reading unit, ensuring that when all the above - mentioned hard breakdown devices are short - circuited, it can be discovered in time, avoiding the problem of incorrect configuration information when all hard breakdown devices are short - circuited during the process manufacturing in the prior art, and ensuring that the reliable performance of the above - mentioned memory is better.

[0044] In order to enable those skilled in the art to more clearly and intuitively understand the technical solution of the present application, the following will be described in conjunction with specific embodiments.

[0045] Embodiment 1

[0046] Get as Figure 2The OTP cell shown, wherein there are two of the above-mentioned memory bits, namely the first memory bit 201 and the second memory bit 202. Both the first memory bit 201 and the second memory bit 202 are MTJs. There are two of the above-mentioned switching devices, namely the first switching device 401 and the second switching device 402. Both the first switching device 401 and the second switching device 402 are NMOS transistors. The above-mentioned hard breakdown component further includes an AND gate 203.

[0047] During the programming operation, a voltage VPE is applied to the word line WL and the bit line BL. The current flowing through both ends of the first memory bit 201 and the second memory bit 202 is IPE, and both the first memory bit 201 and the second memory bit 202 are broken down, causing both the first memory bit 201 and the second memory bit 202 to be short-circuited.

[0048] During the read operation, a voltage VR is applied to the word line WL and the bit line BL. The current flowing through both ends of the first memory bit 201 and the second memory bit 202 is IRD. When any one of the first memory bit 201 and the second memory bit 202 is in the Rp state or the Rap state, or when both the first memory bit 201 and the second memory bit 202 are in the Rp state or the Rap state, the voltage VR is mainly divided by the first memory bit 201 and / or the second memory bit 202, and the source line SL is at a low voltage. After passing through the AND gate 203 and the data reading unit 30, the output is "0"; when both the first memory bit 201 and the second memory bit 202 are in the short-circuit state, since the resistance values of the first memory bit 201 and the second memory bit 202 are very small, the voltage VR is mainly divided by the first switching device 401 and the second switching device 402. At this time, the source line SL is at a high level, and after passing through the AND gate 203 and the data reading unit 30, the output is "0".

[0049] Of course, the above-mentioned hard breakdown component may not include the above-mentioned AND gate. For example, Figure 3 As shown, when any one of the first memory bit 201 and the second memory bit 202 is in the Rp state or the Rap state, or when both the first memory bit 201 and the second memory bit 202 are in the Rp state or the Rap state, the output after passing through the data reading unit 30 is "0"; when both the first memory bit 201 and the second memory bit 202 are in the short-circuit state, the output after passing through the data reading unit 30 is "0".

[0050] Embodiment 2

[0051] Obtain as Figure 4The OTP cell shown, wherein there are two of the above-mentioned memory bits, namely a first memory bit 201 and a second memory bit 202. Both the first memory bit 201 and the second memory bit 202 are MTJs. There are two of the above-mentioned switching devices, namely a first switching device 401 and a second switching device 402. Both the first switching device 401 and the second switching device 402 are NMOS transistors. The above-mentioned hard breakdown component further includes a NAND gate 204.

[0052] During the programming operation, a voltage VPE is applied to the word line WL and the bit line BL. The current flowing through both ends of the first memory bit 201 and the second memory bit 202 is IPE, and both the first memory bit 201 and the second memory bit 202 are broken down, so that both the first memory bit 201 and the second memory bit 202 are short-circuited.

[0053] During the read operation, a voltage VR is applied to the word line WL and the bit line BL. The current flowing through both ends of the first memory bit 201 and the second memory bit 202 is IRD. When any one of the first memory bit 201 and the second memory bit 202 is in the Rp state or the Rap state, or when both the first memory bit 201 and the second memory bit 202 are in the Rp state or the Rap state, the voltage VR is mainly divided by the first memory bit 201 and / or the second memory bit 202, and the source line SL is at a low voltage. After passing through the NAND gate 204 and the data reading unit 30, the output is "1"; when both the first memory bit 201 and the second memory bit 202 are in the short-circuit state, since the resistance values of the first memory bit 201 and the second memory bit 202 are very small, the voltage VR is mainly divided by the first switching device 401 and the second switching device 402. At this time, the source line SL is at a high level, and after passing through the NAND gate 204 and the data reading unit 30, the output is "0".

[0054] Embodiment 3

[0055] Get as Figure 5 The OTP cell shown, wherein there are two of the above-mentioned memory bits, namely a first memory bit 201 and a second memory bit 202. Both the first memory bit 201 and the second memory bit 202 are MTJs. There are two of the above-mentioned switching devices, namely a first switching device 401 and a second switching device 402. The first switching device 401 is a PMOS transistor, and the second switching device 402 is an NMOS transistor. Figure 6 For Figure 5 The timing schematic diagram corresponding to the OTP cell.

[0056] During the programming operation, a voltage VPE is applied to the word line WL and the bit line BL, the write operation enable switch WE is turned on, so that the first switching device 401 is turned on, so that the second memory cell 202 is broken down; then the write operation enable switch WE is turned off, so that the first switching device 401 is turned off, so that the first memory cell 201 is broken down. At this time, the source line SL is at a high level, and after passing through the data reading unit 30, the output is "1".

[0057] Embodiment 4

[0058] Figure 7 The structure diagram of a memory according to a specific embodiment of the present application is shown. The above memory includes two OTP units. The above OTP unit includes a data reading unit 30. There are multiple memory cells in the above OTP unit. There are multiple switching devices. The above switching devices are all NMOS transistors. The above hard breakdown component further includes an AND gate 203.

[0059] Of course, the above memory may further include multiple OTP units, and the above switching devices may also be other switching devices.

[0060] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0061] 1). The OTP unit of the present application includes a hard breakdown component, a data reading unit and a switching unit. The above hard breakdown component includes at least two hard breakdown devices. The output voltage of the above hard breakdown component in the short-circuit state is different from the output voltage of the above hard breakdown component in the non-short-circuit state. Wherein, the above short-circuit state is the state where all the above hard breakdown devices are short-circuited, and the above non-short-circuit state is other states except the above short-circuit state, that is, the non-short-circuit state includes the situation where all the above hard breakdown devices are working normally and some of the above hard breakdown devices are short-circuited. The above data reading unit is electrically connected to the above hard breakdown component, and is used to convert the output voltage of the above hard breakdown component into a digital signal and output it. The above switching unit includes at least two switching devices. The above switching unit is electrically connected to the above hard breakdown component and the above data reading unit respectively. The number of the above switching devices is the same as the number of the above hard breakdown devices and is electrically connected in one-to-one correspondence. The above OTP unit has different output voltages in the short-circuit state and the non-short-circuit state of the above hard breakdown component, that is, the output voltage when all the above hard breakdown devices are short-circuited is different from the output voltage in other cases. Different voltages are converted into different digital signals and output through the above data reading unit, ensuring that when all the above hard breakdown devices are short-circuited, it can be detected in time, avoiding the problem of incorrect configuration information when all the hard breakdown devices are short-circuited during the process of process manufacturing in the prior art, and ensuring better reliable performance of the OTP.

[0062] 2) The memory of the present application includes multiple OTP units, which ensures that the output voltage when all the above-mentioned hard breakdown devices in the above-mentioned memory are short-circuited is different from the output voltage in other cases. Different voltages are converted into different digital signals and output via the above-mentioned data reading unit, ensuring that when all the above-mentioned hard breakdown devices are short-circuited, it can be detected in time, avoiding the problem of incorrect configuration information when all the hard breakdown devices are short-circuited during the process of process manufacturing in the prior art, and ensuring that the reliability performance of the above-mentioned memory is relatively good.

[0063] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. An OTP unit, characterized in that, Comprising: A hard breakdown component, including at least two hard breakdown devices. The output voltage of the hard breakdown component in the short-circuit state is different from the output voltage of the hard breakdown component in the non-short-circuit state. The short-circuit state is the state where all the hard breakdown devices are short-circuited, and the non-short-circuit state is other states except the short-circuit state. The hard breakdown device is a device with hard breakdown characteristics. A data reading unit, electrically connected to the hard breakdown component. The data reading unit is used to convert the output voltage of the hard breakdown component into a digital signal and output it. A switch unit, including at least two switch devices. The switch unit is electrically connected to the hard breakdown component and the data reading unit respectively. The number of switch devices is the same as the number of hard breakdown devices and they are electrically connected in one-to-one correspondence. The hard breakdown component further includes an AND gate. The hard breakdown device is a memory bit. The first end of the memory bit is electrically connected to the first end of the switch device in one-to-one correspondence. The second end of the memory bit is electrically connected to the bit line. The second end of the switch device is electrically connected to the word line. The third end of the switch device is grounded. The first end of the memory bit is electrically connected to an input end of the AND gate in one-to-one correspondence. The output end of the AND gate is electrically connected to the data reading unit.

2. The OTP unit according to claim 1, characterized in that The hard breakdown component further includes a NAND gate. The hard breakdown device is a memory bit. The first end of the memory bit is electrically connected to the first end of the switch device in one-to-one correspondence through a source line. The second end of the memory bit is electrically connected to the bit line. The second end of the switch device is electrically connected to the word line. The third end of the switch device is grounded. The first end of the memory bit is electrically connected to an input end of the NAND gate in one-to-one correspondence. The output end of the NAND gate is electrically connected to the data reading unit.

3. The OTP unit according to claim 1, characterized in that, The hard breakdown device is a memory bit. The hard breakdown component includes a first memory bit and a second memory bit. There are two switch devices, namely a first switch device and a second switch device. The first end of the first memory bit is electrically connected to the bit line. The second end of the first memory bit is electrically connected to the first end of the second memory bit. The second end of the second memory bit is electrically connected to the first end of the second switch device through a source line. The second end of the second memory bit is also electrically connected to the data reading unit. The first end and the third end of the first switch device are electrically connected to the first end and the second end of the first memory bit respectively. The second end of the first switch device is electrically connected to a write operation enable switch. The second end of the second switch device is electrically connected to the word line. The third end of the second switch device is grounded. The second end of the second memory bit is also electrically connected to the data reading unit.

4. The OTP unit according to any one of claims 1 to 3, characterized in that, The memory bit is an MTJ.

5. The OTP unit according to claim 3, characterized in that, The first switch device is a PMOS transistor, and the second switch device is an NMOS transistor.

6. The OTP unit according to claim 1, characterized in that, The data reading unit includes a sense amplifier and a resistor. The sense amplifier includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is electrically connected to the hard breakdown component, the second input terminal is electrically connected to the resistor, and the first output terminal is the output terminal of the data reading unit.

7. The OTP unit according to claim 1, characterized in that, The hard breakdown device is an RRAM, a PCRAM, or a diode.

8. The OTP unit according to claim 1 or 2, characterized in that, The switching device is an NMOS transistor. The first end of the switching device is the drain of the NMOS transistor, the second end of the switching device is the gate of the NMOS transistor, and the third end of the switching device is the source of the NMOS transistor.

9. The OTP unit according to claim 8, wherein, The NMOS transistor is a thick-gate transistor.

10. A memory, characterized in that, The memory includes a plurality of OTP units, and the OTP units are the OTP units described in any one of claims 1 to 9.

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