Preparation Method of Memory Based on One-Dimensional Nanostructures of II-VI Semiconductors

Abstract

The present invention provides a method for preparing a memory based on one-dimensional nanostructures of II-VI group semiconductors. The preparation method includes the following steps: providing a substrate; forming one-dimensional nanostructures based on II-VI group semiconductors on the substrate; forming a first metal electrode layer and a second metal electrode layer at both ends of the one-dimensional nanostructures to obtain a memory blank; and performing electron irradiation treatment on the memory blank to obtain a memory. The solution of the present invention obtains a memory based on one-dimensional nanostructures of II-VI group semiconductors with characteristics such as a large storage window and a high switching ratio, and the preparation method omits the processes of preparing a floating gate layer, an oxide barrier layer, and a tunneling layer, and the preparation method has a simple process.

Description

Technical Field

[0001] The present invention relates to the field of one-dimensional nanostructure memories, and particularly to a method for preparing a memory based on a II-VI semiconductor one-dimensional nanostructure and a memory obtained by using the preparation method. Background Art

[0002] Semiconductor memory devices are widely used in fields such as personal computers, mass storage servers, medical instruments, and portable electronic devices. Among various memory types, the floating-gate memory based on field-effect transistors has advantages such as a large storage window, fast write / erase speed, and stable storage performance. In addition, field-effect transistors are the main electronic device units in modern silicon electronics industry. Therefore, the floating-gate memory based on field-effect transistors can be perfectly compatible with modern electronic devices, facilitating device integration.

[0003] One-dimensional semiconductor nanostructures have excellent electronic properties and are ideal candidates for constructing floating-gate memories based on field-effect transistors. For example, silicon nanowires, carbon nanotubes, and zinc oxide nanowires have all been used to construct floating-gate memories. Generally, the floating-gate memory based on one-dimensional semiconductor nanostructures consists of five parts: a semiconductor channel (one-dimensional semiconductor nanostructure), a three-terminal electrode layer, a blocking layer, a floating-gate layer (storage medium), and a tunneling layer. Among them, the semiconductor channel, the three-terminal electrode layer, and the blocking layer are components of the field-effect transistor, while the floating-gate layer and the tunneling layer are used to achieve the storage function. Therefore, the preparation process of the floating-gate memory based on one-dimensional semiconductor nanostructures usually includes three steps: (1) preparation of the field-effect transistor; (2) deposition of a dielectric material on the semiconductor channel to prepare the tunneling layer; (3) deposition or internal injection of a storage medium on the upper part of the tunneling layer to prepare the floating-gate layer. In order to reduce costs and improve device reliability, it is necessary to further simplify the preparation process and optimize the preparation strategy. Summary of the Invention

[0004] The inventors of the present invention have found that the field-effect transistors based on II-VI semiconductor one-dimensional nanostructures exhibit weak storage performance. The surface states introduced by vacancy defects in the II-VI semiconductor one-dimensional nanostructures are the main reasons for the formation of the storage effect. In order to improve the storage capacity, further introducing a floating-gate storage layer and a tunneling layer is a feasible strategy. However, this strategy undoubtedly increases two preparation processes, and the improvement effect on the storage capacity is also limited. For the memory based on II-VI semiconductor one-dimensional nanostructures, there has not been a strategy reported that can both simplify the preparation process and greatly increase the storage capacity.

[0005] An object of the present invention is to provide a method for a memory based on II-VI semiconductor one-dimensional nanostructures with a large storage window and high on / off ratio characteristics.

[0006] A further object of the present invention is to further improve the storage window and the high switching ratio characteristics of the memory.

[0007] In particular, the present invention provides a method for preparing a memory based on a one-dimensional nanostructure of a II-VI group semiconductor, comprising the following steps:

[0008] Providing a substrate;

[0009] Forming a one-dimensional nanostructure based on a II-VI group semiconductor on the substrate;

[0010] Forming a first metal electrode layer and a second metal electrode layer at both ends of the one-dimensional nanostructure to obtain a memory blank;

[0011] Performing electron irradiation treatment on the memory blank to obtain a memory.

[0012] Optionally, the electron irradiation treatment is performed by bombarding the memory blank with a high-energy electron beam generated by an electron gun.

[0013] Optionally, the working environment of the electron gun is a vacuum environment, and the pressure is any value in the range of 10 -2 -10 -6 Pa;

[0014] The working voltage of the electron gun is any value in the range of 0.5-30 kV, the current of the high-energy electron beam is any value in the range of 50-300 pA, and the irradiation time is any value in the range of 1-3600 s.

[0015] Optionally, the II-VI group semiconductor is selected from cadmium selenide, cadmium sulfide, zinc selenide, zinc sulfide or zinc oxide.

[0016] Optionally, the structural form of the one-dimensional nanostructure is one or a combination of more of nanowires, nanobelts, nanorods and nanotubes.

[0017] Optionally, the first metal electrode layer and the second metal electrode layer are selected from the same material;

[0018] Optionally, the materials of the first metal electrode layer and the second metal electrode layer are both selected from low work function metals;

[0019] Optionally, the thicknesses of the first metal electrode layer and the second metal electrode layer are both any value in the range of 50-200 nm.

[0020] Optionally, the first metal electrode layer and the second metal electrode layer are selected from different materials.

[0021] Optionally, the material of the first metal electrode layer is selected from one of the low work function metals;

[0022] The material of the second metal electrode layer is selected from one of the noble metals.

[0023] Optionally, the thickness of the first metal electrode layer is any value in the range of 10 - 30 nm;

[0024] The thickness of the second metal electrode layer is any value in the range of 20 - 200 nm.

[0025] In particular, the present invention provides a memory based on II-VI group semiconductor one-dimensional nanostructures, which is obtained by using the foregoing preparation method.

[0026] According to the solution of the present invention, by forming II-VI group semiconductor one-dimensional nanostructures on a substrate, and forming a first metal electrode layer and a second metal electrode layer at both ends of the one-dimensional nanostructures, and performing electron irradiation treatment for a preset time, a memory based on II-VI group semiconductor one-dimensional nanostructures with characteristics such as a large storage window and a high switching ratio is obtained. Before this application, those skilled in the art did not propose or realize that electron irradiation can greatly improve the storage window and switching ratio and other characteristics of the II-VI group semiconductor one-dimensional nanostructure memory, and this preparation method omits the processes of preparing a floating gate layer, an oxide barrier layer, and a tunneling layer, and the preparation method has a simple process.

[0027] Furthermore, by limiting various parameters such as electron irradiation, the working conditions of the electron gun, the II-VI group semiconductor, the first metal electrode layer, and the second metal electrode layer within the scope of this application, the storage window and switching ratio and other characteristics of the II-VI group semiconductor one-dimensional nanostructure memory can be further improved, and at the same time, the reliability of this preparation method is also improved.

[0028] According to the following detailed description of specific embodiments of the present invention in conjunction with the drawings, those skilled in the art will become more clear about the above and other objects, advantages, and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Hereinafter, some specific embodiments of the present invention will be described in detail with reference to the drawings in an exemplary but non-limiting manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0030] Figure 1 Shows a schematic flow chart of a preparation method of a memory based on II-VI group semiconductor one-dimensional nanostructures according to an embodiment of the present invention;

[0031] Figure 2Schematic flowchart showing a method for preparing a memory based on a one-dimensional nanostructure of a II-VI semiconductor according to Embodiment 1 of the present invention;

[0032] Figure 3 Scanning electron micrograph showing a CdS nanowire memory according to an embodiment of the present invention;

[0033] Figure 4 I-V curve graph showing a large window memory according to an embodiment of the present invention;

[0034] Figure 5 Schematic flowchart showing a method for preparing a memory based on a one-dimensional nanostructure of a II-VI semiconductor according to Embodiment 2 of the present invention;

[0035] Figure 6 Schematic flowchart showing a method for preparing a memory based on a one-dimensional nanostructure of a II-VI semiconductor according to Embodiment 3 of the present invention. Detailed implementation manners

[0036] Figure 1 Schematic flowchart showing a method for preparing a memory based on a one-dimensional nanostructure of a II-VI semiconductor according to an embodiment of the present invention. As shown in the figure, the preparation method includes:

[0037] Step S110: Provide a substrate;

[0038] Step S120: Form a one-dimensional nanostructure based on a II-VI semiconductor on the substrate;

[0039] Step S130: Form a first metal electrode layer and a second metal electrode layer at both ends of the one-dimensional nanostructure to obtain a memory blank;

[0040] Step S140: Perform electron irradiation treatment on the memory blank to obtain a memory.

[0041] In step S110, the substrate may be, for example, a silicon oxide substrate, and the silicon oxide substrate serves as a barrier layer.

[0042] In step S120, it may be to transfer a one-dimensional nanostructure of a II-VI semiconductor prepared by using the prior art to the substrate. Among them, the II-VI semiconductor may be cadmium sulfide, cadmium selenide, zinc selenide, zinc sulfide or zinc oxide. Among them, there are various transfer methods, such as the contact printing method, the solution dispersion method or transfer using a displacement stage.

[0043] In step S130, the materials of the first metal electrode layer and the second metal electrode layer may be selected to be the same material or different materials.

[0044] In one embodiment, when the materials of the first metal electrode layer and the second metal electrode layer are selected to be the same material, the material is selected as a metal that matches the energy level of the II-VI group semiconductor one-dimensional nanostructure. For n-type II-VI group semiconductors, low work function metals such as indium, chromium, or titanium are used. For example, for n-type cadmium sulfide and cadmium selenide, metal indium is preferably used; for n-type zinc sulfide and zinc selenide, metal chromium is preferably used; for n-type zinc oxide, metal titanium is preferably used. The thickness of the metal material can be, for example, 50 nm, 80 nm, 100 nm, 150 nm, 180 nm, or 200 nm, or any other value within 50 - 200 nm.

[0045] When the materials of the first metal electrode layer and the second metal electrode layer are selected to be the same material, the preparation methods of the first metal electrode layer and the second metal electrode layer include the following steps:

[0046] 1) Define the corresponding electrode patterns at both ends of the II-VI group semiconductor one-dimensional nanostructure through one-time photolithography;

[0047] 2) Prepare the first metal electrode layer and the second metal electrode layer at the electrode patterns at both ends of the II-VI group semiconductor one-dimensional nanostructure by physical deposition.

[0048] When the materials of the first metal electrode layer and the second metal electrode layer are selected to be different materials, the material of the first metal electrode layer is selected as a metal that matches the energy level of the II-VI group semiconductor one-dimensional nanostructure, and the material of the first metal electrode layer is selected as a noble metal with good stability. For example, the material of the first metal electrode layer is selected as a low work function metal that has an ohmic contact with the n-type semiconductor, such as indium, chromium, or titanium. For example, for n-type cadmium sulfide and cadmium selenide, metal indium is preferably used; for n-type zinc sulfide and zinc selenide, metal chromium is preferably used; for n-type zinc oxide, metal titanium is preferably used. The thickness of the material of the first metal electrode layer can be, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, or any other value within 10 - 30 nm. The material of the second metal electrode layer is selected as noble metals such as gold and platinum, and the thickness of the material of the second metal electrode layer can be, for example, 20 nm, 50 nm, 80 nm, 100 nm, 150 nm, or 200 nm, or any other value within 20 - 200 nm.

[0049] When the materials of the first metal electrode layer and the second metal electrode layer are selected to be different materials, the preparation methods of the first metal electrode layer and the second metal electrode layer include the following steps:

[0050] 1’) Define the corresponding electrode patterns at both ends of the II-VI group semiconductor one-dimensional nanostructure through one-time photolithography;

[0051] 2’) Subsequently, by means of physical deposition, the materials of the first metal electrode layer and the second metal electrode layer are respectively evaporated at the electrode patterns at both ends of the II-VI group semiconductor one-dimensional nanostructure, and the first metal electrode layer and the second metal electrode layer are respectively obtained.

[0052] Among them, the photolithography methods in steps 1) and 1’) can use the methods in the prior art, as long as the corresponding electrode patterns can be prepared. The physical deposition methods in steps 2) and 2’) can be, for example, evaporation methods. The evaporation method can be thin film evaporation by using thermal evaporation, electron beam evaporation or magnetron sputtering evaporation.

[0053] In step S140, the electron irradiation method can use the methods in the prior art, as long as high-energy electrons can irradiate the memory blank. The working voltage of the electron gun is 0.5 kV, 1 kV, 2 kV, 5 kV, 10 kV, 20 kV or 30 kV, and can also be any other value in the range of 0.5 - 30 kV. The beam current of the electron gun is 50 pA, 100 pA, 200 pA, 300 pA, and can also be any other value in the range of 50 - 300 pA. The working environment of the electron gun is a vacuum environment, and the pressure range is 10 -2 Pa, 10 -3 Pa, 10 - 4 Pa, 10 -5 Pa or 10 -6 Pa, and can also be any other value in the range of 10 -2 -10 -6 Pa. The preset electron irradiation time is 1 s, 5 s, 10 s, 30 s, 60 s, 360 s, 1200 s, 2400 s or 3600 s, and can also be any other value in the range of 1 - 3600 s.

[0054] According to the solution of the present invention, by forming a II-VI group semiconductor one-dimensional nanostructure on a substrate, forming a first metal electrode layer and a second metal electrode layer at both ends of the one-dimensional nanostructure, and performing electron irradiation treatment for a preset time, a memory based on the II-VI group semiconductor one-dimensional nanostructure with characteristics such as a large storage window and a high switching ratio is obtained. Before this application, those skilled in the art did not propose or realize that electron irradiation can greatly improve the storage window and switching ratio and other characteristics of the II-VI group semiconductor one-dimensional nanostructure memory, and this preparation method omits the processes of preparing a floating gate layer, an oxide barrier layer and a tunneling layer, and the preparation method has a simple process.

[0055] By limiting various parameters such as electron irradiation, the working conditions of the electron gun, II-VI semiconductors, the first metal electrode layer, and the second metal electrode layer within the scope of this application, the storage window and switching ratio of the II-VI semiconductor one-dimensional nanostructure memory can be further improved, and at the same time, the reliability of the preparation method is also enhanced.

[0056] The following is an illustration with specific embodiments:

[0057] Embodiment 1:

[0058] The preparation method of this memory is as Figure 2 shown, including:

[0059] Step S111: Transfer CdS nanowires onto a silicon oxide substrate using the rubbing method;

[0060] Step S112: Define electrode patterns at both ends of the nanowires through photolithography, and successively evaporate 200 nm indium electrodes to obtain a memory blank;

[0061] Step S113: Bombard the memory blank under electron irradiation, where the acceleration voltage of the electron gun is 20 kV, the current magnitude of the high-energy electron beam is 200 pA, the working environment pressure is 10 -3 Pa, and the irradiation time is 60 s. Among them, the irradiation time can be any value within 1 - 3600 s.

[0062] Figure 3 shows a scanning electron microscope image of a CdS nanowire-based memory according to an embodiment of the present invention. Figure 4 shows an I-V curve graph of a large-window memory according to an embodiment of the present invention. During the test, a voltage linear sweep mode is adopted. The scanning range of the gate voltage is from -60 V to 60 V and then to -60 V, the scanning speed is 1 V / step, and the source-drain voltage is fixed at 1 V. Among them, the I-V curve graphs of the memory tested after irradiation times of 0, 30 s, and 60 s are shown. It can be Figure 4 seen that the storage window of the non-irradiated CdS device is less than 10 V. After irradiation treatment, the storage window increases. After the device is irradiated with electrons for 30 seconds and 60 seconds, the storage windows increase to 40 V and 80 V respectively. After irradiation, although the switching ratio of the memory slightly decreases, it is still as high as 10 5 . In the prior art, the way to increase the switching ratio is to introduce a floating gate storage medium in the device. In the preparation process, two additional processes of evaporating the floating gate layer and the oxide barrier layer are required. In addition, introducing the floating gate storage medium can increase the storage window to 40 - 60 V. In this application, the electron irradiation treatment not only omits the processes of evaporating the floating gate layer and the oxide barrier layer, simplifies the preparation process, but also greatly improves the storage window and improves the storage capacity of the memory.

[0063] Example 2:

[0064] The method for fabricating the memory is as follows Figure 5 shown, including:

[0065] Step S211: Transfer zinc oxide nanobelts onto a silicon oxide substrate using a rubbing method;

[0066] Step S212: Define electrode patterns at both ends of the nanobelts by photolithography, and successively deposit a 10-nm titanium electrode and a 40-nm gold electrode to obtain a memory blank;

[0067] Step S213: Bombard the memory blank under electron irradiation, where the acceleration voltage of the electron gun is 30 kV, the beam current is 230 pA, the working ambient pressure is 10 -3 Pa, and the irradiation time is 360 s.

[0068] Example 3:

[0069] The method for fabricating the large-window memory is as follows Figure 6 shown, including:

[0070] Step S311: Transfer zinc selenide nanobelts onto a silicon oxide substrate using a rubbing method;

[0071] Step S312: Define electrode patterns at both ends of the nanobelts by photolithography, and successively deposit a 20-nm chromium electrode and an 80-nm gold electrode to obtain a memory blank;

[0072] Step S313: Bombard the memory blank under electron irradiation, where the acceleration voltage of the electron gun is 10 kV, the beam current is 50 pA, the working ambient pressure is 10 -3 Pa, and the irradiation time is 2400 s.

[0073] In the above examples, the values are not limited to those defined in Examples 1 to 3. For example, II-VI group semiconductors also include materials such as cadmium selenide and zinc sulfide, and the one-dimensional nanostructures can be nanowires, nanobelts or nanotubes. The method for transferring one-dimensional nanostructures can be a rubbing method, a solution dispersion method or transfer using a displacement stage. The thickness of the single-layer and double-layer electrodes deposited can be any value within the range of 50 - 200 nm. The deposition method of the electrode material can be thermal evaporation, electron beam evaporation or magnetron sputtering evaporation. The working voltage of the electron gun can be any value within the range of 0.5 - 30 kV, the current of the high-energy electron beam can be any value within the range of 50 - 300 pA, the vacuum pressure can be any value within the range of 10 -2 -10 -6 Pa, and the preset irradiation time can be any value within the range of 1 - 3600 s.

[0074] At this point, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present invention can still be directly determined or derived from the disclosed content of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and construed to cover all such other variations or modifications.

Claims

1. Preparation method of a memory based on one-dimensional nanostructures of II-VI group semiconductors, characterized in that, it includes the following steps: Provide a substrate; Form one-dimensional nanostructures based on II-VI group semiconductors on the substrate; Form a first metal electrode layer and a second metal electrode layer at both ends of the one-dimensional nanostructures to obtain a memory blank; Perform electron irradiation treatment on the memory blank to obtain a memory.

2. The preparation method of the memory according to claim 1, characterized in that, The way of the electron irradiation treatment is to bombard the memory blank with high-energy electron beams generated by an electron gun.

3. The preparation method of the memory according to claim 2, characterized in that, The working environment of the electron gun is a vacuum environment, and the pressure is any value within the range of 10 -2 -10 -6 Pa; The working voltage of the electron gun is any value in the range of 0.5 - 30 kV, the current of the high-energy electron beam is any value in the range of 50 - 300 pA, and the irradiation time is any value in the range of 1 - 3600 s.

4. The preparation method of the memory according to any one of claims 1 - 3, characterized in that, The II-VI group semiconductors are selected as cadmium selenide, cadmium sulfide, zinc selenide, zinc sulfide or zinc oxide.

5. The preparation method of the memory according to claim 4, characterized in that, The structural form of the one-dimensional nanostructures is one or a combination of more of nanowires, nanobelts, nanorods and nanotubes.

6. The preparation method of the memory according to any one of claims 1 - 3, characterized in that, The first metal electrode layer and the second metal electrode layer are selected from the same material; Optionally, the materials of the first metal electrode layer and the second metal electrode layer are both selected from low work function metals; Optionally, the thicknesses of the first metal electrode layer and the second metal electrode layer are both any value in the range of 50 - 200 nm.

7. The preparation method of the memory according to any one of claims 1 - 3, characterized in that, The first metal electrode layer and the second metal electrode layer are selected from different materials.

8. The preparation method of the memory according to claim 7, characterized in that, The material of the first metal electrode layer is selected from one of the low work function metals; The material of the second metal electrode layer is selected from one of the noble metals.

9. The preparation method of the memory according to claim 8, characterized in that, The thickness of the first metal electrode layer is any value in the range of 10 - 30 nm; The thickness of the second metal electrode layer is any value in the range of 20 - 200 nm.

10. A memory based on one-dimensional nanostructures of II-VI group semiconductors, characterized in that, It is prepared by using the preparation method according to any one of claims 1 - 9.

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