A method of manufacturing a semiconductor structure and a method of forming a DRAM

Abstract

The application relates to a semiconductor structure manufacturing method and a DRAM forming method, and belongs to the technical field of semiconductors. The method solves the active area etching damage problem caused by the existing storage unit area polycrystalline silicon photoetching overlay deviation and polycrystalline silicon layer protrusion. The method comprises the following steps: providing a semiconductor substrate; forming an isolation layer in a storage unit area and part of a transition area; sequentially forming a polycrystalline silicon layer and a stop layer; removing the stop layer located in the storage unit area and at least part of the transition area; removing all of the polycrystalline silicon layer located in the storage unit area and at least part of the transition area and removing the remaining part of the stop layer by CMP; sequentially forming a metal material layer and an insulating material layer; and removing the multilayer above the semiconductor substrate in the transition area by an etching process. The polycrystalline silicon layer height difference in the transition area and the peripheral circuit area is eliminated by stripping the stop layer, so as to avoid the active area etching damage problem caused by the photoetching overlay deviation and the polycrystalline silicon layer protrusion.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a method for forming DRAM. Background Technology

[0002] When forming the gates of the memory cell area and the peripheral circuit area in DRAM, the peripheral circuit area requires a polysilicon layer, which removes the polysilicon from the memory cell area. During the photolithography and polysilicon etching process, there is a photolithography alignment error in the memory cell area. This error, together with the formation of the protruding polysilicon layer, causes etching damage to the active area of ​​the memory cell area or the peripheral circuit area, resulting in device defects.

[0003] refer to Figure 1 Polysilicon 112 is deposited over oxides 108, nitrides 110, and a semiconductor substrate in the memory cell region 102, the peripheral circuit region 106, and the partial transition region 104 between the memory cell region and the peripheral circuit region 106. (Reference) Figure 2 The polycrystalline layer of the memory cell region is photolithographically etched and etched. Due to the height difference after the polycrystalline layer is deposited, overlay misalignment is prone to occur during photolithography of the memory cell region. Figure 3 This illustrates how a misalignment in photolithography can cause a pattern to shift 114 cm to the left. Figure 4 and Figure 5 The diagram shows that when photolithographic overlay misalignment occurs, the pattern shifts to the right by 116 and 118 degrees; both further exacerbate the polysilicon layer protrusion problem. During subsequent polysilicon layer patterning in the peripheral circuit region, etching damage can occur to the active region of the substrate in the memory cell region or peripheral circuit region, such as… Figure 5 As shown. Summary of the Invention

[0004] The present invention aims to provide a method for manufacturing a semiconductor structure and a method for forming DRAM, in order to solve the problems of active area etching damage caused by polysilicon photolithography overlay deviation in existing memory cell areas and polysilicon layer protrusion.

[0005] On one hand, embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes a memory cell region, a peripheral circuit region, and a transition region between the memory cell region and the peripheral circuit region; forming an isolation layer in the memory cell region and a portion of the transition region; sequentially forming a polysilicon layer and a stop layer in the memory cell region, the transition region, and the peripheral circuit region; removing the stop layer located in the memory cell region and at least a portion of the transition region; removing all of the polysilicon layer located in the memory cell region and at least a portion of the transition region by a chemical mechanical planarization (CMP) process, and removing the remaining portion of the stop layer; sequentially forming a metal material layer and an insulating material layer in the memory cell region, the transition region, and the peripheral circuit region; and removing the multilayer located above the semiconductor substrate in the transition region by an etching process.

[0006] The beneficial effects of the above technical solution are as follows: With the stop layer protecting the transition region and peripheral circuit region, CMP processing is performed on the polysilicon layers in the memory cell region and transition region, followed by the removal of the stop layer. This eliminates the polysilicon layer protrusion problem caused by the height difference between the polysilicon layers in the transition region and peripheral circuit region. Because this process reduces the photolithography overlay accuracy requirements and eliminates the polysilicon layer height difference between the transition region and peripheral circuit region, it effectively avoids subsequent etching damage to the active region caused by the aforementioned reasons.

[0007] A further improvement to the above method, forming an isolation layer in the memory cell region and the partial transition region further includes: sequentially depositing an oxide layer and a nitride layer over the semiconductor substrate in the memory cell region, the transition region, and the peripheral circuit region; and removing the oxide layer and the nitride layer in the peripheral circuit region, while removing a portion of the oxide layer and a portion of the nitride layer in the transition region to expose a portion of the top surface of the semiconductor substrate, wherein the remaining oxide and remaining nitride in the transition region have sloping sidewalls, and the isolation layer includes the oxide layer and the nitride layer.

[0008] Based on further improvements to the above method, the thickness of the nitride layer is 50 angstroms or more.

[0009] Further improvements to the above method, sequentially forming a polysilicon layer and a stop layer in the memory cell region, the transition region, and the peripheral circuit region further include: depositing the polysilicon layer over the nitride layer in the memory cell region, over the nitride layer in the transition region, over the inclined sidewalls and the semiconductor substrate, and over the semiconductor substrate in the peripheral circuit region; and depositing the stop layer over the polysilicon layer in the memory cell region, the transition region, and the peripheral circuit region, wherein the polysilicon layer includes a first portion located in the memory cell region, a second portion located in the transition region, and a third portion located in the peripheral circuit region.

[0010] Based on a further improvement of the above method, the second part includes a first top surface, a second top surface, and an inclined top surface between the first top surface and the second top surface, wherein the first top surface is higher than the second top surface, the top surface of the first part is flush with the first top surface, and the top surface of the third part is flush with the second top surface.

[0011] Based on a further improvement of the above method, removing the stop layer located in the memory cell region and at least part of the transition region further includes: removing the portion of the stop layer located above the top surface of the first portion in the memory cell region and the portion located above the first top surface and the inclined side surface in at least part of the transition region by photolithography and etching processes, while retaining the portion of the stop layer located above the top surface of the second top surface and the third portion.

[0012] A further improvement to the above method, removing all of the polysilicon layer in the memory cell region and at least a portion of the transition region by CMP process, and removing the remaining portion of the stop layer, further includes: removing all polysilicon layers in the memory cell region and removing a portion of the polysilicon layer in the transition region by CMP process, such that the top surface of the portion of the polysilicon layer in the transition region is lower than the second top surface, to eliminate the height difference of the polysilicon layer between the transition region and the peripheral circuit region; and removing the remaining portion of the stop layer above the second top surface in the transition region and above the top surface of the third portion in the peripheral circuit region.

[0013] Based on a further improvement of the above method, the ratio of the first rate of removing the polysilicon layer to the second rate of removing the silicon nitride layer in the CMP process is greater than 20:1.

[0014] Further improvements to the above method, sequentially forming a metal material layer and an insulating material layer in the memory cell region, the transition region, and the peripheral circuit region, further include: depositing the metal material layer above the top surface of the isolation layer in the memory cell region, above the top surface of the isolation layer and the polysilicon layer in the transition region, and above the top surface of the polysilicon layer in the peripheral circuit region; and depositing the insulating material layer above the metal material layer in the memory cell region, the transition region, and the peripheral circuit region.

[0015] Based on further improvements to the above method, the height difference between the top surface of the insulating material layer and the memory cell area, the transition area, and the peripheral circuit area has no impact on the accuracy of subsequent multilayer etching and photolithography processes.

[0016] Further improvements to the above method include removing the multiple layers located above the semiconductor substrate in the transition region by etching process, which further includes: sequentially removing the insulating material layer, the metal material layer, the polysilicon layer, the nitride layer and the oxide layer above the semiconductor substrate in the transition region by photolithography and etching processes to form a stacked structure in the memory cell region.

[0017] Based on a further improvement of the above method, the materials of the insulating material layer, the stop layer and the nitride layer are Si3N4; the material of the metal material layer is W; and the material of the oxide layer is SiO2.

[0018] Based on further improvements to the above method, the thickness of the stop layer is in the range of 30 angstroms to 300 angstroms.

[0019] On the other hand, embodiments of the present invention provide a method for forming DRAM, including the semiconductor structure manufacturing method described above.

[0020] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0021] 1. When performing photolithography and etching on the stop layer of the memory cell area, since the polysilicon is not further etched, even if an overlay deviation occurs, it will not affect the subsequent active area patterning due to the correction of the subsequent CMP process.

[0022] 2. With the stop layer protecting the transition region and peripheral circuit region, CMP process is performed on the polysilicon layer in the memory cell region and transition region, and then the stop layer is stripped off. This basically eliminates the height difference of the polysilicon layer in the transition region and peripheral circuit region, providing a larger process window for subsequent photolithography overlay, effectively improving the subsequent gate (or bit line) photolithography accuracy, and avoiding etching damage to the active region.

[0023] 3. During the CMP process, the material removal rate of polycrystalline silicon layers is more than 20 times that of Si3N4 layers. The high selectivity of this material makes it easier to obtain wafer surfaces with high flatness.

[0024] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0025] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0026] Figure 1 This is a cross-sectional view of an intermediate process in the manufacturing method of an existing semiconductor structure.

[0027] Figure 2 This is a cross-sectional view of an intermediate process in the manufacturing method of an existing semiconductor structure.

[0028] Figure 3 The diagram shows a cross-sectional view of the device formed by offsetting the photolithography process of the existing memory cell area opening to the left.

[0029] Figure 4 The diagram shows a cross-sectional view of the device formed by offsetting the photolithography process of the existing memory cell area opening to the right.

[0030] Figure 5 A cross-sectional view of the etching damage to the active region after the photolithography process offset of the existing memory cell area opening is shown.

[0031] Figure 6 This is a cross-sectional view of an intermediate process in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0032] Figure 7 This is a cross-sectional view of an intermediate process in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0033] Figure 8 This is a cross-sectional view of an intermediate process in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0034] Figure 9 This is a cross-sectional view of an intermediate process in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0035] Figure 10 This is a cross-sectional view of an intermediate process in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0036] Figure 11 This is a cross-sectional view of an intermediate process in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0037] Figure 12 This is a cross-sectional view of an intermediate process in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0038] Figure label:

[0039] 200 - Semiconductor substrate; 202 - Memory cell region; 204 - Transition region; 206 - Peripheral circuit region; 208 - Oxide layer; 210 - Nitride layer; 212 - First portion; 214 - Second portion; 216 - Third portion; 218 - Stop layer; 220 - Part of the stop layer (remaining portion); 222 - Polysilicon layer; 224 - Metal material layer; 226 - Insulating material layer; Detailed Implementation

[0040] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0041] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0043] One specific embodiment of the present invention discloses a method for manufacturing a semiconductor structure. Hereinafter, reference will be made to... Figures 6 to 12 The process of manufacturing semiconductor structures is described in detail.

[0044] refer to Figure 6A semiconductor substrate 200 is provided. The semiconductor substrate 200 includes a memory cell region 202, a peripheral circuit region 206, and a transition region 204 between the memory cell region 202 and the peripheral circuit region 206.

[0045] refer to Figure 6 An isolation layer is formed in the memory cell region 202 and a portion of the transition region 204. The isolation layer includes an oxide layer 208 and a nitride layer 210. Specifically, the process further includes: sequentially depositing the oxide layer 208 and the nitride layer 210 over the semiconductor substrate 200 in the memory cell region 202, the transition region 204, and the peripheral circuit region 206; and removing the oxide layer and the nitride layer in the peripheral circuit region 206, while removing a portion of the oxide layer and a portion of the nitride layer in the transition region 204 to expose a portion of the top surface of the semiconductor substrate 200, wherein the remaining oxide and remaining nitride in the transition region 204 have sloping sidewalls. For example, the thickness of the nitride layer is 50 angstroms or more. The material of the nitride layer is Si3N4 and the material of the oxide layer is SiO2.

[0046] refer to Figure 6 A polysilicon layer and a stop layer 218 are sequentially formed in the memory cell region 202, the transition region 204, and the peripheral circuit region 206. Specifically, this further includes depositing a polysilicon layer over the nitride layer 210 in the memory cell region 202, over the nitride layer 210 in the transition region 204, over the inclined sidewalls and the semiconductor substrate, and over the semiconductor substrate in the peripheral circuit region 206. Specifically, the polysilicon layer includes a first portion 212 in the memory cell region 202, a second portion 214 in the transition region 204, and a third portion 216 in the peripheral circuit region 206. The second portion 214 includes a first top surface, a second top surface, and an inclined top surface between the first and second top surfaces, wherein the first top surface is higher than the second top surface, the top surface of the first portion 212 is flush with the first top surface, and the top surface of the third portion 216 is flush with the second top surface. Then, a stop layer 218 is deposited over the polysilicon layer in the memory cell region 202, the transition region 204, and the peripheral circuit region 206. For example, the thickness of the stop layer 218 is between 30 and 300 angstroms. For example, the material of the stop layer 218 is Si3N4.

[0047] refer to Figure 7 The stop layer located in the memory cell region and at least part of the transition region is removed. Specifically, this further includes removing the portion of the stop layer 218 located above the top surface of the first portion 212 in the memory cell region 202 and the portion located above the first top surface and the inclined side surface in at least part of the transition region 204 by photolithography and etching processes, while retaining the portion 220 of the stop layer 218 located above the top surface of the second top surface and the top surface of the third portion 216.

[0048] refer to Figure 8 and Figure 9 The polysilicon layer located in the memory cell region and at least a portion of the transition region is removed using a CMP process, and the remaining portion 220 of the stop layer is removed. Specifically, this further includes: referencing Figure 8 All polysilicon layers in memory cell region 202 and a portion of polysilicon layers in transition region 204 are removed using a CMP process, such that the top surface of the portion of polysilicon layers in transition region 204 is lower than the second top surface, to eliminate the height difference of the polysilicon layers between transition region 204 and peripheral circuit region 206. The remaining polysilicon layers include the polysilicon layer located in peripheral circuit region 206 (i.e., the third portion 216) and the polysilicon layer 222 located in transition region 204. The ratio of the first rate of polysilicon layer removal to the second rate of silicon nitride layer removal in the CMP process is greater than 20:1. Then, refer to... Figure 9 The remaining portion 220 of the stop layer, located above the second top surface in the transition region 204 and above the top surface of the third portion 216 in the peripheral circuit region 206, is removed by photolithography and etching processes.

[0049] In this embodiment, the CMP process for the polysilicon layer has a removal rate more than 20 times that of the CMP process for the Si3N4 layer, enabling rapid removal of the polysilicon layer relative to the Si3N4 layer below it. Furthermore, by eliminating the height difference between the polysilicon layer in the transition region and the peripheral circuit region, the overlay error is minimized, thereby improving the photolithography / etching accuracy of subsequent gate (or bit line) etching processes.

[0050] refer to Figure 10 and Figure 11 A metal material layer 224 and an insulating material layer 226 are sequentially formed in the storage cell area 202, the transition area 204, and the peripheral circuit area 206. Specifically, it further includes: a reference... Figure 10 A metal material layer 224 is deposited above the top surface of the isolation layer in memory cell region 202, above the top surface of the isolation layer and polysilicon layer 222 in transition region 204, and above the top surface of the polysilicon layer (third part 216) in peripheral circuit region 206. This metal material layer 224 can be a gate metal layer or a bit line metal layer. For example, the material of the metal material layer is W. Then, refer to... Figure 11An insulating material layer 226 is deposited over the metal material layer 224 in the memory cell region 202, transition region 204, and peripheral circuit region 206. Accordingly, this insulating material layer 226 can be a bit line capping layer or a gate insulating layer. For example, the material of the insulating material layer is Si3N4. The height difference of the top surface of the insulating material layer in the memory cell region 202, transition region 204, and peripheral circuit region 206 has no impact on the accuracy of subsequent multilayer photolithography and etching processes. In other words, the height difference of the top surface of the insulating material layer in the memory cell region 202, transition region 204, and peripheral circuit region 206 is within the allowable range of subsequent process errors.

[0051] Compared with the prior art, the semiconductor structure manufacturing method provided in this embodiment eliminates the height difference of the polysilicon layer in the transition region and the peripheral circuit region, so that the height difference of the subsequently formed metal material layer 224 and insulating material layer 226 in the transition region and the peripheral circuit region is minimized, thereby improving the photolithography / etching accuracy of the subsequent gate (or bit line) etching process.

[0052] refer to Figure 12 The process further includes removing multiple layers located above the semiconductor substrate 200 in the transition region 204 by etching. Specifically, this further includes sequentially removing the insulating material layer, metal material layer, polysilicon layer 222, nitride layer, and oxide layer above the semiconductor substrate 200 in the transition region 204 by photolithography and etching processes. Figure 12 The dashed portion (as shown in the image) forms a stacked structure in the memory cell area. The stacked structure includes: an isolation layer, a metal material layer above the isolation layer, and an insulating material layer above the metal material layer. Accordingly, this stacked structure can be used as a gate stacked structure. In an alternative embodiment, this stacked structure can also be used as a bit line stacked structure.

[0053] Compared with the prior art, the semiconductor structure manufacturing method provided in this embodiment performs CMP process on the polysilicon layer in the memory cell region and the transition region while protecting the transition region and the peripheral circuit region with a stop layer, and then peels off the stop layer, thereby eliminating the height difference of the polysilicon layer in the transition region and the peripheral circuit region to avoid the polysilicon layer protrusion problem.

[0054] The following section provides a detailed description of the manufacturing method of semiconductor structures using specific examples.

[0055] This application describes a method for removing polysilicon from memory cell regions using CMP (Chemical Metal Processing).

[0056] refer to Figure 6After depositing a polysilicon layer on the oxide and nitride layers 210 in the memory cell region, a Si3N4 layer is deposited. The Si3N4 serves as the stop layer for the CMP process, and the nitride layer 210 must be a Si3N4 film. The thickness of the stop layer (Si3N4) deposited on the polysilicon layer is... The thickness of the Si3N4 layer beneath the polycrystalline silicon layer is above.

[0057] refer to Figure 7 The Si3N4 layer in the area where the polysilicon layer is to be removed is removed by photolithography (i.e., cell aperture photolithography) and etching (Si3N4 etching).

[0058] refer to Figure 8 and Figure 9 The CMP process removes the polysilicon layer in the memory cell region and part of the polysilicon layer in the transition region. After CMP, the remaining Si3N4 layer is stripped. The CMP process has a removal rate difference of more than 20 times between polysilicon and Si3N4 (selectivity ratio higher than 20:1), completely removing the polysilicon layer in the memory cell region. The CMP process stops at the Si3N4 layer.

[0059] refer to Figure 10 and Figure 11 The deposition of metal layers and insulating material layers is unlimited in terms of type and number.

[0060] refer to Figure 12 Gate (or bit line) etching is performed to form a stacked structure in the memory cell area.

[0061] Another specific embodiment of the present invention discloses a method for forming DRAM, including the method for manufacturing the semiconductor structure of any of the above embodiments.

[0062] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0063] 1. When performing photolithography and etching on the stop layer of the memory cell area, since the polysilicon is not further etched, even if an overlay deviation occurs, it will not affect the subsequent active area patterning due to the correction of the subsequent CMP process.

[0064] 2. With the stop layer protecting the transition region and peripheral circuit region, CMP process is performed on the polysilicon layer in the memory cell region and transition region, and then the stop layer is stripped off. This basically eliminates the height difference of the polysilicon layer in the transition region and peripheral circuit region, providing a larger process window for subsequent photolithography overlay, effectively improving the subsequent gate (or bit line) photolithography accuracy, and avoiding etching damage to the active region.

[0065] 3. During the CMP process, the material removal rate of polycrystalline silicon layers is more than 20 times that of Si3N4 layers. The high selectivity of this material makes it easier to obtain wafer surfaces with high flatness.

[0066] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0067] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein the semiconductor substrate includes a memory cell region, a peripheral circuit region, and a transition region between the memory cell region and the peripheral circuit region; An isolation layer is formed in the storage cell area and part of the transition area; A polysilicon layer and a stop layer are sequentially formed in the memory cell region, the transition region, and the peripheral circuit region; Remove the stop layer located in the storage cell area and at least part of the transition area; The polysilicon layer located in the memory cell region and at least a portion of the transition region is removed by a CMP process, and the remaining portion of the stop layer is also removed. A metal material layer and an insulating material layer are sequentially formed in the storage cell area, the transition area, and the peripheral circuit area; and The multilayer layer located above the semiconductor substrate in the transition region is removed by an etching process.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Forming an isolation layer in the storage cell area and the partial transition area further includes: An oxide layer and a nitride layer are sequentially deposited over the semiconductor substrate in the memory cell region, the transition region, and the peripheral circuit region; and The oxide and nitride layers in the peripheral circuit region are removed, and a portion of the oxide and nitride layers in the transition region are also removed to expose a portion of the top surface of the semiconductor substrate. The remaining oxide and nitride layers in the transition region have sloping sidewalls, and the isolation layer includes the oxide and nitride layers.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The thickness of the nitride layer is 50 angstroms or more.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The sequential formation of a polysilicon layer and a stop layer in the memory cell region, the transition region, and the peripheral circuit region further includes: The polysilicon layer is deposited over the nitride layer in the memory cell region, the nitride layer in the transition region, the inclined sidewalls and the semiconductor substrate, and the semiconductor substrate in the peripheral circuit region; and The stop layer is deposited over the polysilicon layer in the memory cell region, the transition region, and the peripheral circuit region, wherein the polysilicon layer includes a first portion located in the memory cell region, a second portion located in the transition region, and a third portion located in the peripheral circuit region.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The second part includes a first top surface, a second top surface, and an inclined top surface between the first top surface and the second top surface, wherein the first top surface is higher than the second top surface, the top surface of the first part is flush with the first top surface, and the top surface of the third part is flush with the second top surface.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, Removing the stop layer located in the storage cell area and at least a portion of the transition area further includes: The portion of the stop layer located above the top surface of the first portion in the memory cell area and the portion located above the first top surface and the inclined sidewall in at least part of the transition area are removed by photolithography and etching processes, while the portion of the stop layer located above the top surface of the second top surface and the third portion is retained.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, Removing all of the polysilicon layer located in the memory cell region and at least a portion of the transition region, and removing the remaining portion of the stop layer, via a CMP process, further includes: The CMP process removes all polysilicon layers in the memory cell region and a portion of the polysilicon layers in the transition region, such that the top surface of the portion of the polysilicon layers in the transition region is lower than the second top surface, thereby eliminating the height difference of the polysilicon layers between the transition region and the peripheral circuit region; and Remove the remaining portion of the stop layer located above the second top surface in the transition region and above the top surface of the third portion in the peripheral circuit region.

8. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The ratio of the first rate at which the polysilicon layer is removed by the CMP process to the second rate at which the stop layer is removed is greater than 20:1, wherein the material of the stop layer is Si3N4.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The sequential formation of a metal material layer and an insulating material layer in the memory cell region, the transition region, and the peripheral circuit region further includes: The metal material layer is deposited above the top surface of the isolation layer in the memory cell region, above the top surface of the isolation layer and the polysilicon layer in the transition region, and above the top surface of the polysilicon layer in the peripheral circuit region; and The insulating material layer is deposited over the metal material layer in the storage cell area, the transition area, and the peripheral circuit area.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The height difference between the top surface of the insulating material layer and the storage cell area, the transition area, and the peripheral circuit area has no impact on the accuracy of subsequent multilayer photolithography and etching processes.

11. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Removing the multiple layers located above the semiconductor substrate in the transition region by an etching process further includes: The insulating material layer, the metal material layer, the polysilicon layer, the nitride layer, and the oxide layer above the semiconductor substrate in the transition region are sequentially removed by photolithography and etching processes to form a stacked structure in the memory cell region.

12. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The insulating material layer and the nitride layer are made of Si3N4. The material of the metallic layer is W; and The oxide layer is made of SiO2.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, The thickness of the stop layer is in the range of 30 angstroms to 300 angstroms.

14. A method for forming DRAM, characterized in that, The method of manufacturing the semiconductor structure described in any one of claims 1 to 13 above.

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