Three-dimensional memory and methods of making the same, memory systems

Abstract

The present disclosure provides a three-dimensional memory, a method for manufacturing the same, and a storage system. The three-dimensional memory includes a stack structure and a gate line gap structure. The gate line gap structure penetrates the stack structure along a stacking direction and extends in a first direction perpendicular to the stacking direction, wherein at least one of the gate line gap structures includes a reinforcement structure that divides the gate line gap structure in which the reinforcement structure is located into multiple segments in the first direction; and the reinforcement structure includes a semiconductor filling layer and a barrier layer that separates the stack structure from the semiconductor filling layer and separates the gate line gap structure from the semiconductor filling layer. In the three-dimensional memory provided by the present disclosure, the reinforcement structure is arranged in at least one of the gate line gap structures, the reinforcement structure includes the barrier layer and the semiconductor filling layer, and the reinforcement structure can provide structural support for the operation of removing the gate sacrificial layer in the process of forming the gate layer, thereby improving and releasing the local stress of the three-dimensional memory structure and increasing the stability of the three-dimensional memory structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor design and manufacturing, and more particularly, to a three-dimensional memory, a three-dimensional memory preparation method, and a storage system. BACKGROUND

[0002] The storage array of the three-dimensional memory includes a storage array region and a staircase region, wherein the storage array region and the staircase region can also be divided into a plurality of storage blocks by a plurality of gate line gaps.

[0003] In a conventional three-dimensional memory, the stack structure of the storage array is built on a substrate (e.g., a silicon wafer), and as the number of stacked layers increases, the media thin film layers included in the three-dimensional memory become more and more complex. Thus, when multiple layers are stacked, stress can accumulate in the wafer, and processes such as annealing in the manufacturing process of the three-dimensional memory can easily cause the above-mentioned media thin film layers to deform, which can eventually cause the wafer to bend or at least some processes to be difficult to perform.

[0004] In addition, due to the limitations of the preparation process of the existing three-dimensional memory, when the conduction of the channel layer of the storage array is realized, the gate sacrificial layer in the stack structure needs to be removed through the gate line gap, which further aggravates the instability of the three-dimensional memory structure.

[0005] Thus, how to improve the structural stability of the three-dimensional memory without affecting its performance is a problem to be solved at present. SUMMARY

[0006] Embodiments of the present disclosure provide a three-dimensional memory and a preparation method thereof, and a storage system, which can at least partially solve the above-mentioned problems in the related art.

[0007] In one aspect, the present disclosure provides a three-dimensional memory, comprising: a stack structure comprising a plurality of gate layers and a plurality of insulating layers alternately stacked along a stacking direction; and a gate line gap structure extending through the stack structure along the stacking direction and extending in a first direction perpendicular to the stacking direction, wherein at least one of the gate line gap structures comprises a reinforcing structure, the reinforcing structure divides the gate line gap structure in which the reinforcing structure is located into multiple segments in the first direction; and the reinforcing structure comprises a semiconductor filling layer and a barrier layer, the barrier layer separates the stack structure and the semiconductor filling layer, and separates the gate line gap structure and the semiconductor filling layer.

[0008] In one embodiment, the reinforcing structure extends through the stack structure along the stacking direction.

[0009] In one embodiment, the barrier layer is an oxide layer.

[0010] In one embodiment, the gate line gap structure comprises a first gate line gap structure, a plurality of the first gate line gap structures are spaced apart in a second direction and divide the stack structure into a plurality of memory blocks, the second direction is perpendicular to the stacking direction and perpendicular to the first direction, each of the first gate line gap structures comprises a plurality of the reinforcement structures, in adjacent first gate line gap structures, the reinforcement structures are arranged in alignment with each other or staggered with each other in the second direction.

[0011] In one embodiment, the stack structure comprises a plurality of memory blocks; the gate line gap structure comprises a plurality of second gate line gap structures, a plurality of the second gate line gap structures are located in the memory blocks and are spaced apart in a second direction, dividing the memory blocks into a plurality of finger memory areas, the second direction is perpendicular to the stacking direction and perpendicular to the first direction, each of the second gate line gap structures comprises a plurality of the reinforcement structures, in adjacent second gate line gap structures, the reinforcement structures are arranged in alignment with each other or staggered with each other in the second direction.

[0012] In one embodiment, the gate line gap structure comprises a plurality of first gate line gap structures and a plurality of second gate line gap structures, a plurality of the first gate line gap structures are spaced apart in a second direction and divide the stack structure into a plurality of memory blocks; a plurality of the second gate line gap structures are spaced apart in the second direction in each of the memory blocks and divide each of the memory blocks into a plurality of finger memory areas, the second direction is perpendicular to the stacking direction and perpendicular to the first direction, each of the first gate line gap structures comprises a plurality of the reinforcement structures, each of the second gate line gap structures comprises a plurality of the reinforcement structures, in adjacent first gate line gap structures and second gate line gap structures, the reinforcement structures are arranged in alignment with each other or staggered with each other in the second direction.

[0013] In one embodiment, each of the gate line gap structures comprises a plurality of the reinforcement structures, a plurality of the reinforcement structures in the same gate line gap structure have the same length in the first direction.

[0014] In one embodiment, each of the gate line gap structures comprises a plurality of the reinforcement structures, a plurality of the reinforcement structures in the same gate line gap structure have a spacing distance in the first direction greater than the length of the reinforcement structure in the first direction.

[0015] In one embodiment, a plurality of the gate line gap structures are spaced apart in a second direction, wherein the second direction is perpendicular to the stacking direction and perpendicular to the first direction; and the length of the reinforcement structure in the first direction is less than the spacing distance of adjacent gate line gap structures in the second direction.

[0016] In one embodiment, the gate line gap structures include first gate line gap structures, a plurality of the first gate line gap structures are spaced apart in a second direction, and divide the stack structure into a plurality of memory blocks, the second direction is perpendicular to the stacking direction and perpendicular to the first direction, and a plurality of the reinforcement structures of a same memory block have a same length in the second direction.

[0017] Another aspect of the present disclosure provides a method of fabricating a three-dimensional memory, the method includes: forming a dielectric stack structure at a side of a substrate, the dielectric stack structure includes alternatingly stacked insulating layers and gate sacrificial layers; forming gate line gaps extending through the dielectric stack structure and to the substrate, wherein the gate line gaps extend in a first direction perpendicular to a stacking direction, forming a reinforcement structure in at least one of the gate line gaps, the reinforcement structure divides the gate line gap into a plurality of segments in the first direction, wherein the reinforcement structure includes a semiconductor fill layer and a barrier layer separating the dielectric stack structure from the semiconductor fill layer and separating the gate line gap structure from the semiconductor fill layer.

[0018] In one embodiment, forming the reinforcement structure in the at least one of the gate line gaps includes: disposing the reinforcement structure to extend through the dielectric stack structure along the stacking direction.

[0019] In one embodiment, forming the reinforcement structure in the at least one of the gate line gaps includes: forming an initial first barrier layer on inner walls of the gate line gap; filling an initial semiconductor fill layer in a remaining space of the gate line gap, removing a portion of the initial semiconductor fill layer to form the semiconductor fill layer, wherein the semiconductor fill layer includes first and second surfaces opposite in the stacking direction and third and fourth surfaces opposite in the first direction, the first surface facing a bottom of the gate line gap; removing a portion of the initial first barrier layer to form a first barrier layer on the first, fifth, and sixth surfaces of the semiconductor fill layer; and forming a second barrier layer on the second, third, and fourth surfaces of the semiconductor fill layer.

[0020] In one embodiment, after forming the second barrier layer, the method further includes forming a gate layer, forming the gate layer includes: removing the gate sacrificial layers via portions of the gate line gaps other than the reinforcement structure to form sacrificial gaps; and filling a conductive material in the sacrificial gaps to form the gate layer.

[0021] In one embodiment, the method further includes: forming the barrier layer using an oxidation process.

[0022] In one embodiment, after the gate layer is formed, the dielectric stack structure is formed as a stack structure including the insulating layers and the gate layers alternately stacked, and the method further includes filling the gate line gap except for the reinforcement structure with a dielectric fill material.

[0023] Yet another aspect of the present disclosure provides a storage system including a controller and a memory provided by an aspect of the present disclosure, the controller coupled to the memory and configured to control the memory to store data.

[0024] In one embodiment, the memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0025] The three-dimensional memory and the method of fabricating the same, and the storage system according to at least one embodiment of the present disclosure provide the reinforcement structure including the barrier layer and the semiconductor fill layer in at least one gate line gap structure, in which the barrier layer separates the stack structure from the semiconductor fill layer and separates the gate line gap structure from the semiconductor fill layer, so that the reinforcement structure is not removed during a process of removing the gate sacrificial layer to form the gate layer, and the stack structure is provided with structural support, the local stress of the three-dimensional memory structure is improved and released, and the deformation and collapse of the stack structure during the above process are prevented, so that the stability of the three-dimensional memory structure is increased and the overall performance of the three-dimensional memory is improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments, read in conjunction with the accompanying drawings. In the drawings:

[0027] Figure 1 is a schematic top view of a three-dimensional memory according to one embodiment of the present disclosure;

[0028] Figures 2A to 2D are partial schematic cross-sectional views taken along AA' line, BB' line, CC' line and DD' line in Figure 1 , respectively;

[0029] Figures 3A to 3F are schematic top views of a three-dimensional memory according to one embodiment of the present disclosure, respectively;

[0030] Figure 4A is a flowchart of a method of fabricating a three-dimensional memory according to one embodiment of the present disclosure;

[0031] Figures 4B to 14D is a process schematic of a method of fabricating a three-dimensional memory according to one embodiment of the present disclosure; and

[0032] Figure 15 is a schematic diagram of a storage system structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The present disclosure will be described in detail by referring to the attached drawings to which there is no intention to limit the present disclosure, and the exemplary embodiments mentioned herein are only for explaining the present disclosure, not for limiting the scope of the present disclosure. Throughout the specification, like reference numerals refer to like elements.

[0034] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of explanation. The drawings are merely examples and are not strictly drawn to scale. As used in this document, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring device or measuring methodology which would be recognized by those of ordinary skill in the art.

[0035] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "include", "comprise", "have", "contain", and / or "contain", etc. are open-ended expressions, not closed expressions, in the present specification, which means that the presence of the stated features, elements, and / or components is indicated, but the presence or addition of one or more other features, elements, components, and / or combinations thereof is not excluded. In addition, when an expression such as "at least one of" appears after a list of listed features, it modifies the entire list of features, not just the individual elements of the list. When describing embodiments of the present disclosure, the use of "may" indicates "one or more embodiments of the present disclosure". And, the term "exemplary" is intended to mean example or illustrative.

[0036] In addition, in the present disclosure, when expressions such as "connected", "covered", and / or "formed on" are used, it can mean direct contact or indirect contact between the respective components, unless there is an explicit other limitation or it can be inferred from the context.

[0037] Unless otherwise defined, all words and phrases used in this document, including technical terms and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, unless explicitly stated otherwise in the present disclosure, words defined in a common dictionary should be interpreted to have meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0038] Note that the embodiments and features of the present disclosure can be combined with one another as long as there is no contradiction. In addition, the specific steps included in the method described in the present disclosure are not necessarily limited to the order described as long as there is no contradiction with the context, and can be performed in any order or in parallel. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0039] Figure 1 is a schematic top view of a three-dimensional memory according to one embodiment of the present disclosure. Figures 2A to 2D are schematic cross-sectional views taken along lines AA', BB', CC', and DD' in Figure 1

[0040] As shown in Figure 1 , Figures 2A to 2D , the three-dimensional memory 10 can include a stack structure 110 and a plurality of gate line gap structures 120. The gate line gap structures 120 penetrate the stack structure 110 along a stacking direction (z direction) and extend in a first direction (x direction) perpendicular to the stacking direction. At least one gate line gap structure 120 can include a reinforcement structure 130 that divides the gate line gap structure 120 in which the plurality of reinforcement structures 130 are located into multiple segments in the first direction. The reinforcement structure 130 can include a semiconductor fill layer 131 and a barrier layer 132 that separates the stack structure 110 from the semiconductor fill layer 131 and separates the gate line gap structure 120 from the semiconductor fill layer 131.

[0041] The three-dimensional memory provided according to at least one embodiment of the present disclosure, by providing a reinforcement structure including a barrier layer and a semiconductor fill layer in at least one gate line gap structure, where the barrier layer can separate the stack structure from the semiconductor fill layer and separate the gate line gap structure from the semiconductor fill layer, thus the reinforcement structure will not be removed in the process of removing the gate sacrificial layer to form the gate layer, can provide structural support for the stack structure, improve and release the local stress of the three-dimensional memory structure, prevent the stack structure from deforming and collapsing and the like in the above process, thereby increasing the stability of the three-dimensional memory structure and improving the overall performance of the three-dimensional memory.

[0042] Specifically, in a plane perpendicular to the stacking direction, the stack structure 110 can be defined to include a storage array region (not shown) and a staircase region (not shown). According to some embodiments, the storage array region can be provided at the center of the stack structure 110 and include a plurality of staircase regions at the edges of the stack structure 110. According to some embodiments, the staircase region can be provided at the center of the stack structure 110 and a plurality of storage array regions can be provided at the edges of the stack structure 110.

[0043] ​The gate line gap structures 120 run through the stack structure 110 in the stacking direction. In addition, the plurality of gate line gap structures 120 can also be spaced apart in a second direction (y direction) which is perpendicular to the stacking direction and perpendicular to the first direction, so that the stack structure 110 can be divided into a plurality of memory blocks M by the gate line gap structures 120 (as shown in FIG. 1). Figure 1 A memory block M is shown. Further, one or more additional gate line gap structures 120 can also be formed in each memory block M, so that each memory block M is further divided into a plurality of finger memory areas F. Each memory block M and each finger memory area F includes a memory array of a plurality of channel structures 140.

[0044] As shown in FIGS. 1 and 2, the gate line gap structures 120 can be formed by removing the semiconductor material of the semiconductor base 100’ in the gate line gap structures 120. In addition, the gate line gap structures 120 can also be formed by removing the semiconductor material of the semiconductor base 100’ in the gate line gap structures 120 and by removing the semiconductor material of the semiconductor base 100’ in the memory blocks M. Figure 2C And 2D As shown in FIG. 1, in one embodiment of the present disclosure, the semiconductor fill layer 131 of the reinforcement structure 130 can include a first surface (not shown) and a second surface (not shown) opposite to each other in the stacking direction, wherein the first surface is located at the bottom of the gate line gap structure 120 (which can be understood as the side of the gate line gap structure 120 close to the substrate / semiconductor base 100’); a third surface (not shown) and a fourth surface (not shown) opposite to each other in the first direction; and a fifth surface (not shown) and a sixth surface (not shown) opposite to each other in the second direction. The barrier layer 132 of the reinforcement structure 130 can include a first barrier layer 132-1 and a second barrier layer 132-2, wherein the first barrier layer 132-1 is located at the first surface, the fifth surface and the sixth surface of the semiconductor fill layer 131, and the second barrier layer 132-2 is located at the second surface, the third surface and the fourth surface of the semiconductor fill layer 131. In other words, the reinforcement structure 130 can include the semiconductor fill layer 131 and the barrier layer 132 wrapping the semiconductor fill layer 131.

[0045] Specifically, as an option, the barrier layer can be an oxide layer, for example, the first barrier layer 132-1 and the second barrier layer 132-2 can be oxide layers. Alternatively, the semiconductor fill layer 131 can be a polysilicon layer, and at least one of the first barrier layer 132-1 and the second barrier layer 132-2 can be a silicon oxide layer.

[0046] As described above, the gate sacrificial layer can generally be a silicon nitride layer. As an option, in the case where the barrier layer is an oxide layer, for example, the first barrier layer and the second barrier layer are silicon oxide layers, the barrier layer including the first barrier layer and the second barrier layer can have a high etching selectivity with the gate sacrificial layer, so that the barrier layer can not be removed when the gate sacrificial layer is removed, and thus the reinforcement structure can not be removed in the above operation due to the presence of the barrier layer, and the semiconductor fill layer in the reinforcement structure can provide effective structural support for the above operation, improving and releasing the local stress of the three-dimensional memory structure.

[0047] AsFigures 2A to 2D As shown, the stack structure 110 includes a plurality of gate layers 111 and a plurality of insulating layers 112 alternately stacked, wherein the gate layers 111 include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide, etc. The insulating layers 112 include, but are not limited to, a silicon oxide (SiO X ) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, etc. The number of layers of the stack structure 110 is not limited to the number of layers shown in the figure, and can be additionally provided as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0048] The gate line gap structure 120 can include an isolation layer 121 and a dielectric filling layer 122. The isolation layer 121 can isolate the stack structure 110 from the dielectric filling layer 122, and includes, but is not limited to, a dielectric material layer such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. Alternatively, the isolation layer 121 can also be formed of the same material as the insulating layer 112, such as silicon oxide. The dielectric filling layer 122 includes, but is not limited to, a dielectric filling material layer or a semiconductor material layer, such as a polysilicon layer. Using a polysilicon layer as the dielectric filling layer 122 can effectively reduce the warping of the wafer in the extension direction (x direction) of the gate line gap structure 120.

[0049] Figures 3A to 3F are schematic top views of a three-dimensional memory according to one embodiment of the present disclosure, respectively.

[0050] Referring again to Figure 1 , the plurality of gate line gap structures 120 can be spaced apart at a predetermined interval d along the second direction, wherein at least one gate line gap structure 120 can include a reinforcement structure 130. The reinforcement structure 130 can include various arrangements in the gate line gap structure 120.

[0051] In particular, as shown in Figure 3A , the gate line gap structure 120 can include a first gate line gap structure 101 and a second gate line gap structure 102. The plurality of first gate line gap structures 120 are spaced apart in the second direction, dividing the stack structure 110 (as shown in Figure 2A ) into a plurality of memory blocks M. In addition, each memory block M can further include a plurality of second gate line gap structures 102 spaced apart in the second direction, which can further divide each memory block M into a plurality of finger memory areas F.

[0052] Alternatively, in some embodiments of the present disclosure, the first gate line gap structures 101 and the second gate line gap structures 102 can have the same width in the second direction. As another alternative, in some embodiments of the present disclosure, the first gate line gap structures 101 and the second gate line gap structures 102 can have different widths in the second direction, for example, the width of the first gate line gap structures 101 in the second direction is greater than the width of the second gate line gap structures 102 in the second direction, thereby facilitating achieving higher storage density in the three-dimensional memory.

[0053] As shown in FIG. 1A, in one embodiment of the present disclosure, the reinforcement structures 130 in the adjacent first gate line gap structures 101 are staggered with each other in the second direction. Figure 3C As shown in FIG. 1A, in one embodiment of the present disclosure, the reinforcement structures 130 in the adjacent first gate line gap structures 101 are aligned with each other in the second direction.

[0054] Figure 3F As shown in FIG. 1A, in one embodiment of the present disclosure, each memory block M includes a plurality of second gate line gap structures 102, and the reinforcement structures 130 in the adjacent second gate line gap structures 102 in each memory block M are staggered with each other in the second direction.

[0055] As shown in FIG. 1A, in one embodiment of the present disclosure, each memory block M includes a plurality of second gate line gap structures 102, and the reinforcement structures 130 in the adjacent second gate line gap structures 102 in each memory block M are aligned with each other in the second direction. Figure 3B As shown in FIG. 1A, in one embodiment of the present disclosure, each memory block M includes at least one second gate line gap structure 102, and the reinforcement structures 130 in the adjacent first gate line gap structures 101 and the second gate line gap structures 102 are staggered with each other in the second direction, the adjacent two first gate line gap structures 101 are aligned with each other in the second direction, and the reinforcement structures 130 in the adjacent two second gate line gap structures 102 are aligned with each other in the second direction.

[0056] Figure 3E As shown in FIG. 1A, in one embodiment of the present disclosure, each memory block M includes at least one second gate line gap structure 102, and the reinforcement structures 130 in the adjacent first gate line gap structures 101 and the second gate line gap structures 102 are staggered with each other in the second direction, the adjacent two first gate line gap structures 101 are staggered with each other in the second direction, and the reinforcement structures 130 in the adjacent two second gate line gap structures 102 are staggered with each other in the second direction.

[0057] As shown in FIG. 1A, in one embodiment of the present disclosure, each memory block M includes at least one second gate line gap structure 102, and the reinforcement structures 130 in the adjacent first gate line gap structures 101 and the second gate line gap structures 102 are staggered with each other in the second direction, the adjacent two first gate line gap structures 101 are staggered with each other in the second direction, and the reinforcement structures 130 in the adjacent two second gate line gap structures 102 are staggered with each other in the second direction. Figure 3A As shown in FIG. 1A, in one embodiment of the present disclosure, each memory block M includes at least one second gate line gap structure 102, and the reinforcement structures 130 in the adjacent first gate line gap structures 101 and the second gate line gap structures 102 are staggered with each other in the second direction, the adjacent two first gate line gap structures 101 are staggered with each other in the second direction, and the reinforcement structures 130 in the adjacent two second gate line gap structures 102 are staggered with each other in the second direction.

[0058] Figure 3D As shown in FIG. 1A, in one embodiment of the present disclosure, each memory block M includes at least one second gate line gap structure 102, and the reinforcement structures 130 in the adjacent first gate line gap structures 101 and the second gate line gap structures 102 are staggered with each other in the second direction, the adjacent two first gate line gap structures 101 are staggered with each other in the second direction, and the reinforcement structures 130 in the adjacent two second gate line gap structures 102 are staggered with each other in the second direction. ​​​

[0059] Figures 3A to 3F The arrangement of the reinforcing structures can enable, when fabricating the gate layers of the three-dimensional memory, the removal step of removing the gate sacrificial layers via the gate line gap structures to have an optimized process window, while obtaining the stable and uniform support provided by the reinforcing structures, by reducing the number of the reinforcing structures and reducing the footprint of the reinforcing structures in the plane perpendicular to the stacking direction.

[0060] Specifically, in the process of removing the entire gate sacrificial layers by using a process such as wet etching, the portions of the gate line gaps other than the reinforcing structures can serve as the passages for the etchant and the chemical precursor. In other words, the etchant and the chemical precursor need to contact each of the gate sacrificial layers via the gate line gaps formed when the gate line gap structures are formed, and then remove the entire gate sacrificial layers. However, the reinforcing structures arranged in the gate line gaps occupy the space in the gate line gaps that is originally used to accommodate the etchant and the chemical precursor, and block the flow passage of the etchant and the chemical precursor, so that the footprint of the reinforcing structures in the plane perpendicular to the stacking direction determines the size of the process window of the removal step to some extent.

[0061] In addition, since the reinforcing structures are not removed in the process of removing the gate sacrificial layers to form the gate layers, the reinforcing structures can provide structural support for the stack structure in the above process, improve and release the local stress of the three-dimensional memory structure, and prevent the stack structure from deforming and collapsing in the above process.

[0062] Therefore, in at least one embodiment of the present disclosure, the reinforcing structures in the partially adjacent line gap structures can be staggered with each other in the second direction, and the reinforcing structures in the partially adjacent line gap structures can be aligned with each other in the second direction, according to different arrangements of the three-dimensional memory architecture, so that the number of the reinforcing structures is reduced and the footprint of the reinforcing structures in the plane perpendicular to the stacking direction is reduced while obtaining the stable and uniform support, and the process window of the removal step is optimized.

[0063] It should be understood that, Figures 3A to 3F The arrangement of the reinforcing structures 130 is only exemplarily listed, and the arrangement of the reinforcing structures 130 includes but is not limited to Figures 3A to 3F The arrangements shown in the above are not listed one by one here.

[0064] Again referring to Figure 1As an option, in one embodiment of the disclosure, the plurality of reinforcement structures 130 in the same gate line gap structure 120 can have the same length L1 in the first direction. Further, as another option, the plurality of reinforcement structures 130 in the same memory block M can also have the same length L1 in the first direction. Thus, in the three-dimensional memory provided in at least one embodiment of the disclosure, the plurality of reinforcement structures have the same size, which is advantageous for reducing the difficulty and cost of forming the reinforcement structures.

[0065] Further, in one embodiment of the disclosure, the plurality of reinforcement structures 130 in the same gate line gap structure 120 can have a spacing distance L2 in the first direction that is greater than the length L1 of the reinforcement structures 130 in the first direction. As described above, in the process of removing the gate sacrificial layers to form the gate layers, the spacing distance between adjacent reinforcement structures in the first direction being greater than the length of the reinforcement structures in the first direction can make the space in the gate line gap that serves as a passage for providing the etchant and the chemical precursor larger, thus increasing the process window of the removing step, which is advantageous for completely removing the gate sacrificial layers in the removing process and avoiding the occurrence of process results that are not good due to the residual gate sacrificial layers.

[0066] Further, in one embodiment of the disclosure, the length L1 of the reinforcement structures 130 in the first direction can be less than the spacing d of the adjacent gate line gap structures 120 in the second direction. As described above, in the process of removing the gate sacrificial layers to form the gate layers, the gate line gap generated when the gate line gap structure is formed can serve as a passage for providing the etchant and the chemical precursor. Setting the length of the reinforcement structures in the first direction to be less than the spacing of the adjacent gate line gap structures in the second direction can reduce the coverage of the reinforcement structures in the plane perpendicular to the stacking direction, increase the process window of the removing step, which is advantageous for completely removing the gate sacrificial layers in the removing process and avoiding the occurrence of process results that are not good due to the residual gate sacrificial layers.

[0067] Figure 4A is a flowchart of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the disclosure. As shown in Figure 4A the manufacturing method 1000 includes the following steps:

[0068] S1, forming a dielectric stack structure on one side of a substrate, the dielectric stack structure including alternatingly stacked insulating layers and gate sacrificial layers.

[0069] S2, forming a gate line gap extending through the dielectric stack structure and extending to the substrate, wherein the gate line gap extends in a first direction perpendicular to the stacking direction.

[0070] S3, forming a reinforcement structure in the at least one gate line gap, the reinforcement structure dividing the gate line gap into multiple segments in the first direction, wherein the reinforcement structure includes a semiconductor fill layer and a barrier layer, the barrier layer separating the dielectric stack from the semiconductor fill layer and separating the gate line gap structure from the semiconductor fill layer.

[0071] The following will be described in detail Figures 4B to 14D Detailed description of the specific process of each step of the above preparation method 1000.

[0072] Step S1

[0073] Figure 4B is a schematic top view of a three-dimensional memory intermediate after formation of the gate line gap 180 according to one embodiment of the present disclosure. Figure 5A is a partial cross-sectional schematic view of the intermediate along the AA' line in Figure 4B . Figure 5B is a partial cross-sectional schematic view of the intermediate along the BB' line in Figure 4B . Figure 5C is a partial cross-sectional schematic view of the intermediate along the CC' line in Figure 4B . Figure 5D is a partial cross-sectional schematic view of the intermediate along the DD' line in Figure 4B .

[0074] As shown in Figures 4B to 5D , step S1 forms a dielectric stack structure on one side of a substrate, the dielectric stack structure including alternatingly stacked insulating layers and gate sacrificial layers, which may, for example, include: preparing a substrate 100; forming a dielectric stack structure 110' on the substrate 100; and forming a channel structure 140 in the dielectric stack structure 110'.

[0075] Specifically, in one embodiment of the present disclosure, the preparation material of the substrate 100 can be selected from any suitable semiconductor material, for example, can be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or group III-V compound such as gallium arsenide, etc. Further, the substrate 100 can be selected from monocrystalline silicon.

[0076] In one embodiment of the present disclosure, the substrate 100 can be, for example, a composite substrate for supporting a device structure thereon. A plurality of layers made of different materials can be sequentially disposed by a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form the substrate 100.

[0077] The substrate 100 can include a substrate sacrificial layer, which can include a single layer, multiple layers, or a suitable combination of layers. For example, the substrate sacrificial layer can include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer can be a high dielectric constant dielectric layer, and as another option, the substrate sacrificial layer can include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed, where the dielectric layer can be a silicon nitride layer and the sacrificial layer can be a silicon oxide layer. As another option, the substrate sacrificial layer can include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer can be a single-crystal silicon or a polycrystalline silicon, and specifically, in one embodiment of the present disclosure, an exemplary material forming the sacrificial layer can be a polycrystalline silicon.

[0078] A portion of the substrate 100 can also form a well region doped by N-type or P-type dopants via an ion implantation or diffusion process. The dopants can include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present disclosure, the well regions can be made of the same dopants, or can be made of different dopants, and further, the doping concentrations of the well regions can be the same or different, which are not limited in the present disclosure.

[0079] The substrate 100 has opposite first and second sides. After forming the substrate 100, a dielectric stack structure 110’ can be formed on the first side of the substrate 100 by one or more thin film deposition processes, which can include, but are not limited to, CVD, PVD, ALD, or any combination thereof, which are not limited in the present disclosure. The dielectric stack structure 110’ can include a plurality of pairs of insulating layers 112 and gate sacrificial layers 113 stacked alternately with each other. For example, the dielectric stack structure 110’ can include 64 pairs, 128 pairs, or more than 128 pairs of the insulating layers 112 and the gate sacrificial layers 113. In some embodiments, the insulating layers 112 and the gate sacrificial layers 113 can include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the insulating layers 112 and the gate sacrificial layers 113 can include silicon oxide and silicon nitride, respectively. The silicon oxide layer can be used as an isolation stack layer, and the silicon nitride layer can be used as a sacrificial stack layer. Subsequently, the sacrificial stack layer can be etched away and replaced with a conductor layer including a conductive material.

[0080] The above describes the preparation method of a single dielectric stack structure. In fact, as the demand for three-dimensional memory storage capacity continues to increase, the storage stack gradually increases. To break through the limitations of traditional processes, a double stack technology or a multi-stack technology can also be used to form a dielectric stack structure by sequentially stacking a plurality of sub-dielectric stack structures in the stacking direction of the dielectric stack structure, wherein each sub-dielectric stack structure can include a plurality of insulating layers and gate sacrificial layers alternately stacked. The number of layers of each sub-dielectric stack structure can be the same or different. Since the content and structure involved in the preparation process of the single dielectric stack structure described above can be fully or partially applicable to the dielectric stack structure formed by the plurality of sub-dielectric stack structures described herein, the related or similar content is not described again. However, those skilled in the art can understand that the subsequent preparation process can be based on the multi-dielectric stack structure or the single-dielectric stack structure.

[0081] The channel structure 140 can include a functional layer (not shown) filled in a channel hole (not shown) and a channel layer 141. The functional layer and the channel layer 141 can be formed on the inner wall of the channel hole by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The channel hole can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. The channel hole can have a cylindrical or columnar shape extending through the dielectric stack structure 110' and to the substrate 100.

[0082] The functional layer can include a blocking layer (not shown) formed on the inner wall of the channel hole to block the outflow of charges, a charge trapping layer (not shown) formed on the surface of the blocking layer to store charges during the operation of the three-dimensional memory, and a tunneling layer (not shown) formed on the surface of the charge trapping layer.

[0083] In some embodiments, the functional layer can include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer can have a structure different from the ONO configuration.

[0084] The channel layer 141 can be used to transport the required charges (electrons or holes). According to one exemplary embodiment of the present disclosure, the channel layer 141 can be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0085] In some embodiments, the channel layer 141 can comprise silicon, such as amorphous silicon, polysilicon, or single crystal silicon. The material of the channel layer 141 includes, but is not limited to, P-doped polysilicon. Similar to the channel hole, the channel layer 141 also extends through the dielectric stack structure 110’ and into the substrate 100.

[0086] In addition, the channel structure 140 also includes a channel plug formed at the top of the channel hole away from the substrate 100. The material of the channel plug can be made of the same material as the channel layer, such as P-doped polysilicon, etc.

[0087] Step S2

[0088] Referring again to Figures 4B to 5D , the step S2 of forming the gate line gap extending through the dielectric stack structure and into the substrate, wherein the gate line gap extending in a first direction perpendicular to the stacking direction can comprise, for example: forming a gate line gap 180 in the dielectric stack structure 110’ having a spacing from the channel structure 140 in a second direction, wherein the gate line gap 180 extends in the first direction.

[0089] In particular, the dielectric stack structure 110’ can include a memory array region (not shown) and a staircase region (not shown). According to some embodiments, the memory array region can be disposed in the center of the dielectric stack structure 110’ and include two staircase regions at the edges of the dielectric stack structure 110’. According to some embodiments, the staircase region can be disposed in the center of the dielectric stack structure 110’ and the two memory array regions are disposed at the edges of the dielectric stack structure 110’. The memory array region of the dielectric stack structure 110’ can be partitioned by the gate line gap 180 to form a plurality of memory blocks.

[0090] Referring to Figure 4B , a pair of gate line gaps 180, such as a first gate line gap, can define a memory block M therebetween. One or more additional gate line gaps 180, such as a second gate line gap, can be formed in a memory block M to further partition the memory block M into a plurality of finger memory regions F. Each memory block M and each finger memory region F includes a plurality of memory arrays composed of channel structures 140.

[0091] In conventional three-dimensional memory fabrication processes, all of the gate line spaces have the same critical dimension, such as width in the second direction. In contrast, in one embodiment of the present disclosure, the width in the second direction of the first gate line spaces can be set to be greater than the width in the second direction of the second gate line spaces. Alternatively, in one embodiment of the present disclosure, after a reinforcement structure is formed in at least one of the gate line spaces, the width in the second direction of the gate line space including the reinforcement structure can be set to be less than the width in the second direction of the gate line space not including the reinforcement structure. By the above definition, the effective memory cell array area can be effectively increased.

[0092] The gate line spaces 180 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Alternatively, the gate line spaces 180 can extend through the dielectric stack structure 110' and into the substrate 100 in a direction approximately perpendicular to the substrate 100. Further, the gate line spaces 180 can also be selected to extend into different layer structures included in the substrate 100, or the gate line spaces 180 can also extend only through the dielectric stack structure 110', depending on the different settings of the three-dimensional memory architecture.

[0093] Step S3

[0094] Figures 6A to 6D are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figure 4B are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figures 7A to 7D are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figure 4B are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figures 8A to 8D are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figure 4B are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figures 9A to 9D are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figure 4B are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figures 10A to 10D are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figure 4B are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figures 11A to 11D are cross-sectional views of a partial profile taken along the AA' line, the BB' line, the CC' line, and the DD' line in FIG. 1 1 1, respectively, of an intermediate body after forming the initial first barrier layer 132-1'according to one embodiment of the present disclosure. Figure 4BA schematic diagram of a partial cross-section taken from lines AA', BB', CC', and DD'. Figures 12A to 12D According to one embodiment of this disclosure, the intermediate body after forming the sacrificial gap 114 is respectively along... Figure 4B A schematic diagram of a partial cross-section taken from lines AA', BB', CC', and DD'. Figures 13A to 13D According to one embodiment of this disclosure, the intermediate bodies after forming the gate layer 111 are respectively along... Figure 4B A schematic diagram of a partial cross-section taken from lines AA', BB', CC', and DD'.

[0095] like Figures 6A to 13D ,as well as Figures 2A to 2D As shown, step S3 forms a reinforcement structure in at least one gate line gap. The reinforcement structure divides the gate line gap into multiple segments in a first direction. The reinforcement structure includes a semiconductor filling layer and a barrier layer. The barrier layer separates the dielectric stack structure from the semiconductor filling layer and the gate line gap structure from the semiconductor filling layer. This separation may include, for example, forming an initial first barrier layer 132-1'; forming an initial semiconductor filling layer 131'; forming a semiconductor filling layer 131; forming a partial gate line gap 181 and forming a first barrier layer 132-1; forming a second barrier layer 132-2; forming a sacrificial gap 114; and forming a gate layer 111.

[0096] After forming the gate line gap 180, a reinforcement structure 130 can be formed in at least one gate line gap 180. This reinforcement structure includes a barrier layer and a semiconductor filling layer, which are not removed during the process of removing the gate sacrificial layer to form the gate layer. Therefore, it can provide structural support for the intermediate of the three-dimensional memory, improve and release the local stress of the three-dimensional memory structure, prevent the intermediate from deforming and collapsing during the above process, thereby increasing the stability of the three-dimensional memory structure and improving the overall performance of the three-dimensional memory.

[0097] In some embodiments of this disclosure, forming a plurality of reinforcement structures 130 in at least one gate line gap 180 may include: forming an initial first barrier layer 132-1' on the inner wall of the gate line gap 180; filling the remaining space of the gate line gap 180 with an initial semiconductor filling layer 131'; removing a portion of the initial semiconductor filling layer 131' to form a semiconductor filling layer 131, wherein the semiconductor filling layer 131 includes a first surface and a second surface opposite in the stacking direction, and a third surface and a fourth surface opposite in the first direction, the first surface being directly opposite the bottom of the gate line gap 180 (which can be understood as the portion of the gate line gap 180 near the substrate 100); forming the first barrier layer 132-1 on the first surface, the fifth surface, and the sixth surface of the semiconductor filling layer 131; and forming a second barrier layer 132-2 on the second surface, the third surface, and the fourth surface of the semiconductor filling layer 131. After forming the second barrier layer 132-2, it can be understood that a plurality of reinforcement structures 130 have been formed in at least one gate line gap 180. In other words, the reinforcement structure 130 includes a semiconductor filling layer 131 and a barrier layer 132 that encloses the semiconductor filling layer 131. The barrier layer 132 may include a first barrier layer 132-1 and a second barrier layer 132-2.

[0098] In some embodiments of this disclosure, after forming the second barrier layer 132-2, a gate layer 111 may also be formed. Forming the gate layer 111 may include: removing the gate sacrificial layer 113 through the portion of the gate line gap 180 other than the reinforcing structure 130 to form a sacrificial gap 114; and filling the sacrificial gap 114 with a conductive material to form the gate layer 111.

[0099] Specifically, such as Figures 6A to 6D As shown, in one embodiment of this disclosure, an initial first barrier layer 132-1' may be formed on the inner wall of the gate line gap 180. The initial first barrier layer 132-1' may include a first portion 133 formed on the side wall of the gate line gap 180 and a second portion 134 formed at the bottom of the gate line gap 180 (which can be understood as the portion of the gate line gap 180 near the substrate 100).

[0100] Alternatively, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to form the first portion 133 and the second portion 134 on the inner wall of the gate line gap 180; or, as another option, a thermal oxidation process can be used to form an oxide layer on the inner wall of the gate line gap 180 as the first portion 133 and the second portion 134. During the formation of the initial first barrier layer 132-1' by the thermal oxidation process, since the dielectric stack structure 110' includes a sacrificial stack layer formed by stacking a gate sacrificial layer 113 such as silicon nitride, and an isolation stack layer formed by stacking an insulating layer 112 such as silicon oxide, if the isolation stack layer itself is an oxide stack layer, the first portion 133 may include: an oxide layer 133' formed on the surface of the sacrificial stack layer exposed in the gate line gap 180 by the above-described thermal oxidation process; and a portion 112' of the oxide stack layer exposed in the gate line gap 180.

[0101] like Figures 6A to 8D As shown, after forming the initial first barrier layer 132-1', the gate gap 180 can be filled using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to form the initial semiconductor filling layer 131'. The initial semiconductor filling layer 131' is formed in the gate gap 180 and on the top surface of the dielectric stack structure 110' (which can be understood as the surface of the dielectric stack structure 110' away from the substrate 100).

[0102] Furthermore, such as Figures 7A to 8D As shown, the portion of the initial semiconductor filling layer 131' formed on the top surface of the dielectric stack structure 110' can also be removed by, for example, a dry etching process or a combination of dry and wet etching processes; or other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning and / or chemical mechanical polishing (CMP), etc., leaving only the portion of the initial semiconductor filling layer 131' located at the gate line gap 180.

[0103] As described above, the method for fabricating a three-dimensional memory according to an exemplary embodiment of this disclosure further includes a method for forming a gate layer, in which all the gate sacrificial layer needs to be removed during the formation of the gate layer. During the removal of all the gate sacrificial layer using processes such as wet etching, the gate line gaps can serve as pathways for providing etchant and chemical precursors.

[0104] Therefore, such as Figures 8A to 9DAs shown, after filling the gate line gaps 180 with the initial semiconductor fill layer 131', a portion of the initial semiconductor fill layer 131' is also removed to expose a portion of the gate line gaps 180 again as a path for providing etchant and chemical precursors. The exposed portion of the gate line gaps 180 forms a plurality of local gate line gaps 181. After removing the portion of the initial semiconductor fill layer 131', the remaining initial semiconductor fill layer 131' forms the semiconductor fill layer 131.

[0105] In particular, the etching mask layer 11 having patterns 01 and 02 can be formed on the top surface of the dielectric stack structure 110', the pattern 01 can expose a portion of the initial semiconductor fill layer 131' and a portion of the initial first barrier layer 132-1' thereunder. Thereby, in a subsequent etching process, the portion of the initial semiconductor fill layer 131' opposite to the pattern 01 in the gate line gaps 180 can be removed, and a portion of the initial first barrier layer 132-1' opposite to the removed portion of the initial semiconductor fill layer 131' can be exposed. The etching process can employ, for example, a dry etching process or a combination of dry and wet etching processes; or other fabrication processes can be performed, which are not limited in the present disclosure.

[0106] While the portion of the initial semiconductor fill layer 131' opposite to the pattern 01 in the gate line gaps 180 is removed, the portion of the initial semiconductor fill layer 131' opposite to the pattern 02 is retained and forms the semiconductor fill layer 131 as described above. The semiconductor fill layer 131 can provide structural support for the operation of removing the gate sacrificial layer in the process of forming the gate layer.

[0107] In combination Figure 9A and Figure 10D After exposing the portion of the initial first barrier layer 132-1' opposite to the removed portion of the initial semiconductor fill layer 131', the exposed portion of the initial first barrier layer 132-1' can be further removed until the gate sacrificial layer 113 is exposed, by continuing to employ, for example, a dry etching process or a combination of dry and wet etching processes; or other fabrication processes can be performed, such as patterning processes including photolithography, cleaning, and / or chemical mechanical polishing, etc. After removing the exposed portion of the initial first barrier layer 132-1', the remaining initial first barrier layer 132-1' forms the first barrier layer 132-1. The first barrier layer 132-1 is located on the first surface of the semiconductor fill layer 131, the fifth surface, and the sixth surface of the semiconductor fill layer 131, where the first surface is adjacent to the substrate 100, and the fifth surface and the sixth surface are two opposite surfaces of the semiconductor fill layer 131 in the second direction.

[0108] To prevent the semiconductor fill layer from being removed in the subsequent process of removing the gate sacrificial layer to form the gate layer, a second barrier layer is also formed on the remaining surfaces of the semiconductor fill layer. The barrier layer composed of the first barrier layer and the second barrier layer is not removed in the above process, so that the semiconductor fill layer in the reinforcement structure can provide structural support for the operation of removing the gate sacrificial layer, improve and release the local stress of the three-dimensional memory structure, and increase the stability of the three-dimensional memory structure.

[0109] In combination Figure 10A and Figure 11D , a thermal oxidation process can be used to form an oxide layer on the bottom surface of the partial gate line gap 181 as the fourth barrier layer 135; alternatively, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form the fourth barrier layer 135 on the bottom surface of the partial gate line gap 181. At the same time, the above process can also form a second barrier layer 132-2 on the semiconductor fill layer 131 to form a reinforcement structure 130. The second barrier layer 132-2 is located on the second surface, the third surface and the fourth surface of the semiconductor fill layer 131, wherein the second surface is opposite to the first surface in the stacking direction and away from the substrate 100, and the third surface and the fourth surface are two surfaces of the semiconductor fill layer 131 opposite in the first direction.

[0110] As shown in Figures 11A to 14D , and Figures 2A to 2D , according to one embodiment of the present disclosure, the preparation method 1000 of the three-dimensional memory of the present disclosure further comprises: removing the gate sacrificial layer 113 through the part of the gate line gap 180 other than the reinforcement structure 130 (which can be understood as the partial gate line gap 181) to form a sacrificial gap 114; forming an initial fifth barrier layer 136'; removing part of the initial fifth barrier layer 136' to form a fifth barrier layer 136 on the inner wall of the sacrificial gap 114 and the inner wall of the partial gate line gap 181; filling a conductive material in the remaining space of the sacrificial gap 114 to form a gate layer 111; and arranging an isolation layer 121 and a dielectric fill layer 122 in the partial gate line gap 181.

[0111] Specifically, as shown in Figures 11A to 12D , the partial gate line gap 181 can be used as a passage to provide etchant and chemical precursors, and a process such as wet etching is used to remove all the sacrificial layers 113 in the stack structure 110' to form a sacrificial gap 114. At the same time, in the step of forming the sacrificial gap 114, the reinforcement structure 130 will not be removed in the process of removing the gate sacrificial layer 113, so as to provide structural support, improve and release the local stress of the dielectric stack structure 110', prevent the dielectric stack structure 110' from deforming and collapsing in the above process, and thus increase the stability of the three-dimensional memory structure and improve the overall performance of the three-dimensional memory.

[0112] As shown in Figures 12A to 13D , a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be employed to form an initial fifth barrier layer 136’ on the inner walls of the sacrificial gaps 114 and the inner walls of the gate line gaps 180. The initial fifth barrier layer 136’ can be a high-k dielectric layer. The initial fifth barrier layer 136’ is formed on the inner walls of the sacrificial gaps 114, the inner walls of the partial gate line gaps 181, and the surface of the second barrier layer 132-2 of the reinforcement structure 130.

[0113] As shown in Figures 13A to 14D , a portion of the initial fifth barrier layer 136’ can be removed to form the fifth barrier layer 136 using, for example, a dry etching process or a combination of dry and wet etching processes, or other fabrication processes such as patterning processes including photolithography, cleaning, and / or chemical mechanical polishing, etc. The fifth barrier layer 136 is located on the inner walls of the sacrificial gaps 114, the inner walls of the partial gate line gaps 181, and the surface of the portion of the second barrier layer 132-2 in the first direction.

[0114] Referring to Figures 14A to 14D , and Figures 2A to 2D , after the formation of the fifth barrier layer 136, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be employed to fill the remaining space of the sacrificial gaps 114 (as shown in Figure 12A ) with a conductive material to form the gate electrode layer 111. The conductive material can be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. After the formation of the gate electrode layer 111, the alternating stack of the gate electrode layer 111 and the insulating layer 112 is formed as the stack structure 110.

[0115] Further, the method 1000 of fabricating a three-dimensional memory further includes forming an adhesion layer (not shown) between the gate electrode layer 111 and the fifth barrier layer 136. The adhesion layer is formed on the portion of the fifth barrier layer 136 on the inner walls of the sacrificial gaps 114 via the partial gate line gaps 181 using a deposition process such as CVD, PVD, ALD, or any combination thereof, and after the formation of the adhesion layer, the remaining space of the sacrificial gaps 114 (as shown in Figure 12A ) is filled with a conductive material to form the gate electrode layer 111. The adhesion layer can be made of a material that is capable of blocking the diffusion of metal ions and has electrical conductivity, such as titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, etc.

[0116] After the formation of the gate electrode layer 111, the partial gate line gaps 181 or the gate line gaps 180 can be filled with a dielectric filling material, thereby forming the gate line gap structure 120.

[0117] Specifically, the deposition process such as CVD, PVD, ALD or any combination thereof can be used to fill the isolation layer 121 and the dielectric filling layer 122 in the local gate line gap 181 (understood as the part of the gate line gap 180 with the reinforcement structure 130 except the reinforcement structure 130) in sequence; or the deposition process such as CVD, PVD, ALD or any combination thereof can be used to fill the isolation layer 121 and the dielectric filling layer 122 in the gate line gap 180 without the reinforcement structure 130 in sequence.

[0118] The isolation layer 121 includes but is not limited to a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and the like dielectric material layer. As an option, the same material as the insulating layer 112, such as silicon oxide, can also be selected to form the isolation layer 121. The dielectric filling layer 122 includes but is not limited to a dielectric filling material layer or a semiconductor material layer, for example, the dielectric filling layer 122 can be a polysilicon layer. Using a polysilicon layer as the dielectric filling layer 122 can effectively reduce the bending of the wafer in the extension direction (x direction) of the gate line gap structure 120.

[0119] In addition, as an option, a chemical mechanical polishing process or the like can also be used to thin the part of the second barrier layer 132-2 on the second surface, so that the surface of the second barrier layer 132-2 is flush with the surface of the stack structure 110 away from the substrate 100.

[0120] The preparation method of the three-dimensional memory provided by the embodiment of the present disclosure sets the reinforcement structure including the barrier layer and the semiconductor filling layer in at least one gate line gap structure, wherein the barrier layer can separate the stack structure from the semiconductor filling layer and separate the gate line gap structure from the semiconductor filling layer, so that the reinforcement structure will not be removed in the process of removing the gate sacrificial layer to form the gate layer, which can provide structural support for the stack structure, improve and release the local stress of the three-dimensional memory structure, prevent the stack structure from deforming and collapsing and the like in the above process, thereby increasing the stability of the three-dimensional memory structure and improving the overall performance of the three-dimensional memory.

[0121] In addition, the preparation method of the three-dimensional memory provided by the embodiment of the present disclosure further includes forming a semiconductor connecting layer (not shown) in the substrate 100, which can connect the local part of the plurality of channel layers 141 in the storage array, such as at least one of the side surface part and the bottom surface part of the channel layer 141, for realizing the conduction of the channel layer in the storage array. After forming the semiconductor connecting layer, the substrate 100 is formed into a substrate / semiconductor base 100'. The process of forming the semiconductor connecting layer can use the existing conventional process and be prepared according to actual needs, which is not described here.

[0122] Figure 15 is a structural schematic diagram of a storage system 30000 according to an embodiment of the present disclosure.

[0123] As Figure 15 illustrated, at least one embodiment of yet another aspect of the present disclosure further provides a storage system 30000. The storage system 30000 can include a memory 20000 and a controller 32000. The memory 20000 can be the same as the memory described in any of the embodiments above, and the present disclosure will not repeat it. The storage system 30000 can be a two-dimensional storage system or a three-dimensional storage system, and the following will be described taking the three-dimensional storage system as an example.

[0124] As an option, the three-dimensional memory can include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0125] Specifically, the three-dimensional storage system 30000 can include a three-dimensional memory 20000 and a controller 32000. The three-dimensional memory 20000 can be the same as the three-dimensional memory described in any of the embodiments above, and the present disclosure will not repeat it. The controller 32000 can control the three-dimensional memory 20000 through a channel CH, and the three-dimensional memory 20000 can perform an operation based on the control of the controller 32000 in response to a request from a host 31000. The three-dimensional memory 20000 can receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the three-dimensional memory 20000 can perform an internal operation corresponding to the command on the region selected by the address.

[0126] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of an RS-MMC and a micro-SD, a secure digital card in the form of an SD, a mini-SD and a micro-SD, a storage device of a personal computer memory card international association (PCMCIA) card type, a storage device of a peripheral component interconnect (PCI) type, a storage device of a high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The present disclosure provides a peripheral circuit, a memory and a storage system, and has the same beneficial effects as the three-dimensional memory provided by the present disclosure due to the provision of the three-dimensional memory, which will not be repeated here.

[0127] The above description is merely preferred embodiments of the present disclosure and a description of principles of technology employed. It will be understood by those skilled in the art that the scope of protection of the present disclosure is not limited to the technical solutions formed by the specific combinations of the above technical features, and also covers other technical solutions formed by any combinations of the above technical features or equivalent features without departing from the technical concept. For example, technical solutions formed by mutual replacement of the above features and technical features disclosed in the present disclosure (but not limited to) having similar functions.

Claims

1. A three-dimensional memory, comprising: Comprising: a stack structure including a plurality of gate layers and a plurality of insulating layers alternately stacked along a stacking direction; and a gate line gap structure penetrating through the stack structure along the stacking direction and extending in a first direction perpendicular to the stacking direction, wherein at least one of the gate line gap structures includes a reinforcement structure that divides the gate line gap structure in which the reinforcement structure is located into a plurality of segments in the first direction; and the reinforcement structure includes a semiconductor filling layer and a barrier layer, the barrier layer including a first barrier layer separating the stack structure from the semiconductor filling layer and a second barrier layer separating the gate line gap structure from the semiconductor filling layer. The reinforcement structure penetrates through the stack structure along the stacking direction.

2. The three-dimensional memory of Claim 1 wherein, 3. The three-dimensional memory according to claim 1, wherein the barrier layer is an oxide layer. The gate line gap structure includes a plurality of first gate line gap structures spaced apart in a second direction perpendicular to the stacking direction and perpendicular to the first direction and dividing the stack structure into a plurality of memory blocks, 4. The three-dimensional memory of any one of claims 1 to 3, wherein, each of the first gate line gap structures includes a plurality of the reinforcement structures, and the reinforcement structures in adjacent first gate line gap structures are arranged in alignment with each other or staggered with each other in the second direction. The stack structure includes a plurality of memory blocks, and the gate line gap structure includes a plurality of second gate line gap structures spaced apart in a second direction perpendicular to the stacking direction and perpendicular to the first direction and dividing the memory blocks into a plurality of finger memory regions, 5. The three-dimensional memory of any one of claims 1 to 3, wherein, each of the second gate line gap structures includes a plurality of the reinforcement structures, and the reinforcement structures in adjacent second gate line gap structures are arranged in alignment with each other or staggered with each other in the second direction. The gate line gap structure includes a plurality of first gate line gap structures spaced apart in a second direction and dividing the stack structure into a plurality of memory blocks, and a plurality of second gate line gap structures spaced apart in the second direction in each of the memory blocks and dividing each of the memory blocks into a plurality of finger memory regions, the second direction being perpendicular to the stacking direction and perpendicular to the first direction, 6. The three-dimensional memory of any one of claims 1-3, wherein, each of the first gate line gap structures includes a plurality of the reinforcement structures, and each of the second gate line gap structures includes a plurality of the reinforcement structures, and the reinforcement structures in adjacent first gate line gap structures and second gate line gap structures are arranged in alignment with each other or staggered with each other in the second direction.

7. The three-dimensional memory according to any one of claims 1 to 3, wherein each of the gate line gap structures includes a plurality of the reinforcement structures, and the plurality of the reinforcement structures in the same gate line gap structure have the same length in the first direction.

8. The three-dimensional memory according to any one of claims 1 to 3, wherein ​ ​ Each of the gate line gap structures includes a plurality of the reinforcement structures, and the plurality of the reinforcement structures in a same one of the gate line gap structures have a length in the first direction that is greater than a spacing distance of the plurality of the reinforcement structures in the same one of the gate line gap structures in the first direction.

9. The three-dimensional memory of any one of claims 1-3, wherein, the plurality of the gate line gap structures are spaced apart in a second direction that is perpendicular to the stacking direction and that is perpendicular to the first direction; and the length of the reinforcement structure in the first direction is less than a spacing distance of adjacent ones of the gate line gap structures in the second direction.

10. The three-dimensional memory of any one of claims 1-3, wherein, the gate line gap structures include first gate line gap structures, and a plurality of the first gate line gap structures are spaced apart in a second direction that is perpendicular to the stacking direction and that is perpendicular to the first direction, and divide the stack structure into a plurality of memory blocks, the plurality of the reinforcement structures in a same one of the memory blocks have a same length in the second direction.

11. A method of fabricating a three-dimensional memory, comprising: comprising: forming a dielectric stack structure on a side of a substrate, the dielectric stack structure including alternating insulating layers and gate sacrificial layers; forming gate line gaps extending through the dielectric stack structure and into the substrate, wherein the gate line gaps extend in a first direction that is perpendicular to a stacking direction, forming a reinforcement structure in at least one of the gate line gaps, the reinforcement structure dividing the gate line gap into a plurality of segments in the first direction, wherein the reinforcement structure includes a semiconductor fill layer and a barrier layer, the barrier layer including a first barrier layer separating the dielectric stack structure from the semiconductor fill layer and a second barrier layer separating the gate line gap structure from the semiconductor fill layer.

12. The method of claim 11, wherein, forming a reinforcement structure in at least one of the gate line gaps includes: disposing the reinforcement structure to extend through the dielectric stack structure in the stacking direction.

13. The method of claim 11, wherein, forming a reinforcement structure in at least one of the gate line gaps includes: forming an initial first barrier layer on an inner wall of the gate line gap; filling an initial semiconductor fill layer in a remaining space of the gate line gap, and removing a portion of the initial semiconductor fill layer to form the semiconductor fill layer, wherein the semiconductor fill layer includes first and second surfaces opposite in the stacking direction, third and fourth surfaces opposite in the first direction, and fifth and sixth surfaces opposite in a second direction, the first surface facing a bottom of the gate line gap; the second direction being perpendicular to the stacking direction and to the first direction; removing a portion of the initial first barrier layer to form the first barrier layer on the first, fifth, and sixth surfaces of the semiconductor fill layer; and forming the second barrier layer on the second, third, and fourth surfaces of the semiconductor fill layer.

14. The method of claim 13, wherein, after forming the second barrier layer, the method further includes forming a gate layer, forming the gate layer includes: removing the gate sacrificial layers via portions of the gate line gaps other than the reinforcement structure to form sacrificial gaps; and filling a conductive material in the sacrificial gap to form the gate layer.

15. The method of claim 11, wherein, The method further includes: forming the blocking layer using an oxidation process.

16. The method of claim 14, wherein, After forming the gate layer, the dielectric stack structure is formed as a stack structure including the insulating layers and the gate layers alternately stacked, and the method further includes: filling the gate line gap with a dielectric fill material except for the reinforcement structure.

17. A storage system, characterized by The storage system includes a controller coupled to the memory and configured to control the memory to store data.

18. The storage system of claim 17, wherein, The memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory. The memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

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