A display panel

Abstract

The present application discloses a display panel; the array layer of the display panel includes a plurality of first thin film transistors having a first active layer and a plurality of second thin film transistors having a second active layer, the materials of the first active layer and the second active layer are different, and the material of the second active layer includes a metal oxide; at the same time, the second thin film transistor also includes a first isolation layer arranged on a side of the second active layer close to a substrate, the first isolation layer is in contact with the second active layer, and the atomic percentage of hydrogen in the first isolation layer is less than a first threshold value; the present application reduces the proportion of hydrogen in the first isolation layer penetrating into the second active layer by arranging the first isolation layer on a side of the second active layer close to the substrate, and making the atomic percentage of hydrogen in the first isolation layer less than the first threshold value, thereby improving the electrical properties of the metal oxide in the second active layer, thereby improving the stability of the second thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology has attracted people's attention for its advantages such as high response speed, high contrast, and high brightness. In the context of no significant breakthroughs in battery technology, people have increasingly higher requirements for low power consumption of display devices. Therefore, LTPO (Low Temperature Polycrystalline-Si Oxide) technology came into being. LTPO technology combines the advantages of LTPS (Low Temperature Polycrystalline-Si) and oxide to achieve lower power consumption.

[0003] LTPO uses two active layers, LTPS and metal oxide. In the manufacturing process of LTPS, hydrogen needs to be introduced, and metal oxide is very sensitive to hydrogen. When the hydrogen content is too high, it will affect the electrical properties of the metal oxide thin film transistor. Therefore, it is necessary to provide a new display panel that can avoid the impact of hydrogen on the metal oxide thin film transistor. Summary of the invention

[0004] The present application provides a display panel to solve the problem of hydrogen affecting metal oxide thin film transistors in the LTPO manufacturing process and improve the stability of metal oxide thin film transistors.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a display panel, the display panel comprising a substrate and an array layer disposed on the substrate; wherein the array layer comprises:

[0007] A plurality of first thin film transistors, at least one of the first thin film transistors comprises a first active layer;

[0008] a plurality of second thin film transistors, at least one of the second thin film transistors comprises a second active layer, the first active layer and the second active layer are made of different materials, and the second active layer comprises a metal oxide;

[0009] The second thin film transistor further includes a first isolation layer, which is disposed on a side of the second active layer close to the substrate, the first isolation layer is in contact with the second active layer, and the atomic percentage of hydrogen in the first isolation layer is less than a first threshold.

[0010] In the display panel of the present application, the first isolation layer covers the first active layer and extends toward the second active layer;

[0011] The thickness of the first isolation layer corresponding to the first thin film transistor is greater than the thickness of the first isolation layer corresponding to the second thin film transistor.

[0012] In the display panel of the present application, the array layer includes:

[0013] A first gate layer, disposed on the first isolation layer;

[0014] A first insulating layer is disposed on the first gate layer;

[0015] The array layer further includes a plurality of grooves, at least one of the second thin film transistors is disposed in the groove, and the groove at least penetrates the first inter-insulating layer and a portion of the first isolation layer.

[0016] In the display panel of the present application, the atomic percentage of hydrogen in the first inter-insulating layer is greater than the atomic percentage of hydrogen in the first isolation layer.

[0017] In the display panel of the present application, the second thin film transistor includes:

[0018] a second isolation layer, disposed on the second active layer;

[0019] A second gate layer is disposed on the second isolation layer; and

[0020] a second interlayer insulating layer, disposed on the second gate layer, wherein the second interlayer insulating layer covers the second gate layer and the second active layer;

[0021] The second insulating layer extends from the second thin film transistor to the first thin film transistor, and the second insulating layer contacts the surface of the first insulating layer away from the first active layer, and the atomic percentage of hydrogen in the first insulating layer is greater than the atomic percentage of hydrogen in the second insulating layer.

[0022] In the display panel of the present application, the first gate layer includes a first sub-gate layer and a second sub-gate layer, the first isolation layer includes a first sub-isolation layer and a second sub-isolation layer, the first sub-isolation layer covers the first active layer, the first sub-gate layer is arranged on the first sub-isolation layer, the second sub-isolation layer covers the first sub-gate layer, and the second sub-gate layer is arranged on the second sub-isolation layer;

[0023] The atomic percentage of hydrogen in the first sub-isolation layer is less than the atomic percentage of hydrogen in the second sub-isolation layer.

[0024] In the display panel of the present application, the second active layer includes:

[0025] a channel portion corresponding to the second isolation layer and the second gate layer;

[0026] doping parts, arranged on both sides of the channel part;

[0027] The second inter-insulating layer is in contact with the channel material in the peripheral area of ​​the channel portion.

[0028] In the display panel of the present application, the second thin film transistor further includes:

[0029] a second source and drain electrode, wherein the second source and drain electrode is electrically connected to the second active layer;

[0030] An adjusting layer, disposed on the second insulating layer;

[0031] The orthographic projection of the adjustment layer on the second active layer at least partially overlaps with the second active layer, and the adjustment layer contains hydrogen elements.

[0032] In the display panel of the present application, the array layer includes a gate driving circuit area and a pixel circuit area, a plurality of the first thin film transistors are located in the gate driving circuit area, and a plurality of the second thin film transistors are located in the pixel circuit area.

[0033] In the display panel of the present application, the first thin film transistor also includes a first source and drain electrode electrically connected to the first active layer, the first source and drain electrode includes a first connecting segment and a second connecting segment that are continuously arranged, and the materials of the first connecting segment and the second connecting segment are different.

[0034] Beneficial effects: The present application discloses a display panel, which includes a substrate and an array layer arranged on the substrate; wherein the array layer includes: a plurality of first thin film transistors, at least one of the first thin film transistors includes a first active layer; a plurality of second thin film transistors, at least one of the second thin film transistors includes a second active layer, the materials of the first active layer and the second active layer are different, and the material of the second active layer includes a metal oxide; at the same time, the second thin film transistor also includes a first isolation layer, the first isolation layer is arranged on a side of the second active layer close to the substrate, the first isolation layer is in contact with the second active layer, and the atomic percentage of hydrogen in the first isolation layer is less than a first threshold; the present application reduces the proportion of hydrogen in the first isolation layer penetrating into the second active layer by arranging the first isolation layer on a side of the second active layer close to the substrate, and the atomic percentage of hydrogen in the first isolation layer is less than the first threshold, thereby improving the electrical properties of the metal oxide in the second active layer, thereby improving the stability of the second thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0036] Figure 1 is a top view of the display panel;

[0037] Figure 2 A first cross-sectional view of the display panel of the present application;

[0038] Figure 3 A partially enlarged view of a first cross-sectional view of the display panel of the present application;

[0039] Figure 4 A second cross-sectional view of the display panel of the present application;

[0040] Figure 5 This is a partially enlarged view of the second cross-sectional view of the display panel of the present application.

[0041] Description of reference numerals:

[0042] Display panel 10, substrate 310, first base 301, barrier layer 302, second base 303, buffer layer 304, third layer 305, first isolation layer 410, first sub-isolation layer 401, second sub-isolation layer 402, first inter-insulating layer 403, second inter-insulating layer 404, first planarizing layer 405, second planarizing layer 406, pixel definition layer 407, anode 408, first thin film transistor 100, first active layer 101, first gate layer 120, first Sub-gate layer 121, second sub-gate layer 122, first source and drain 110, first connecting segment 103, second connecting segment 104, first channel portion 1011, first doped portion 1012, second thin film transistor 200, second active layer 201, second gate layer 220, second isolation layer 420, second source and drain 210, adjustment layer 205, second channel portion 2011, second doped portion 2012, gate drive circuit area AA, pixel circuit area BB, bending area CC. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0044] See also Figure 1 to Figure 2 The display panel area can be divided into a pixel circuit area BB for displaying images and a gate drive circuit area AA for circuit routing located on both sides of the pixel circuit area BB. The gate drive circuit area AA provides signals for the pixel circuit area BB. Both the pixel circuit area BB and the gate drive circuit area AA have a large number of thin film transistors.

[0045] In the manufacturing process of LTPO, hydrogen needs to be introduced during the manufacturing process of LTPS, and metal oxide thin film transistors are very sensitive to hydrogen. When the hydrogen content is too high, it will affect the electrical properties of the metal oxide thin film transistors manufactured subsequently. Therefore, this application proposes the following solution based on the above technical problems.

[0046] See also Figures 1 to 3The present application provides a display panel 10, characterized in that the display panel 10 includes a substrate 310 and an array layer arranged on the substrate 310; wherein the array layer includes: a plurality of first thin film transistors 100, at least one of the first thin film transistors 100 includes a first active layer 101; a plurality of second thin film transistors 200, at least one of the second thin film transistors 200 includes a second active layer 201, the materials of the first active layer 101 and the second active layer 201 are different, and the material of the second active layer 201 includes a metal oxide; wherein the second thin film transistor 200 also includes a first isolation layer 410, the first isolation layer 410 is arranged on a side of the second active layer 201 close to the substrate 310, the first isolation layer 410 is in contact with the second active layer 201, and the atomic percentage of hydrogen element in the first isolation layer 410 is less than a first threshold value.

[0047] In this embodiment, the display panel may be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0048] In this example, see Figure 2 When the display panel is an OLED panel, the array layer further includes a first planar layer 405 , a second planar layer 406 , a pixel definition layer 407 , and an anode 408 .

[0049] In this embodiment, when the display panel is a flexible display panel, the display panel further includes a bending region CC.

[0050] In this embodiment, the first thin film transistor 100 may be a low temperature polysilicon thin film transistor.

[0051] In this embodiment, the material of the first active layer 101 may be LTPS.

[0052] In this embodiment, the second thin film transistor 200 may be a metal oxide thin film transistor, such as an IGZO thin film transistor.

[0053] In this embodiment, the first threshold is 2%.

[0054] In this embodiment, the material of the second active layer 201 may be metal oxide, such as IGZO.

[0055] In this embodiment, the material of the second active layer 201 may be IGZO, wherein the atomic percentage of metal indium is greater than or equal to 33%, and the device mobility may reach 20 square centimeters / volt·second.

[0056] In this embodiment, the first thin film transistor 100 may be located in the gate driving circuit area AA or in the pixel circuit area BB.

[0057] In this embodiment, the second thin film transistor 200 may be located in the gate driving circuit area AA or in the pixel circuit area BB.

[0058] In this embodiment, the hydrogen in the first isolation layer 410 may come from a hydrogen replenishing process.

[0059] In this embodiment, the substrate 310 may be a glass substrate or a polyimide substrate. When the substrate 310 is a flexible substrate, the display panel is a flexible display panel that can be folded, rolled, or the like.

[0060] In this embodiment, the substrate 310 may be formed by stacking multiple layers of materials. For example, the substrate 310 may be a first substrate 301, a barrier layer 302, a second substrate 303, a buffer layer 304, and a third layer 305 stacked in sequence. The materials of the first substrate 301 and the second substrate 303 may be polyimide, cycloolefin copolymer, or polyterephthalate materials. The material of the barrier layer 302 may be silicon nitride, silicon oxynitride, polyimide, or amorphous silicon. The material of the buffer layer 304 may be silicon nitride, silicon oxynitride, polyimide, or amorphous silicon. The material of the third layer 305 may be silicon nitride, silicon oxide, or the like.

[0061] In the present embodiment, the first isolation layer 410 is made of a material having an atomic percentage of hydrogen less than a first threshold, such as silicon oxide (SiOx).

[0062] In this embodiment, a bottom surface of the first active layer 101 may be in contact with the substrate 310 .

[0063] In this embodiment, a bottom surface of the second active layer 201 may be in contact with the first isolation layer 410 .

[0064] The present application sets the first isolation layer 410 on the side of the second active layer 201 close to the substrate 310, and the atomic percentage of hydrogen elements in the first isolation layer 410 is less than a first threshold value, thereby reducing the proportion of hydrogen elements in the first isolation layer 410 penetrating into the second active layer 201, thereby improving the electrical properties of the metal oxide in the second active layer 201, thereby enhancing the stability of the second thin film transistor 200.

[0065] The technical solution of the present application is now described in conjunction with specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0066] Embodiment 1

[0067] Hydrogen needs to be introduced during the process of manufacturing LTPS, and metal oxide thin film transistors are very sensitive to hydrogen. When the hydrogen content is too high, hydrogen will diffuse into the second active layer 201 in the metal oxide thin film transistor, affecting the electrical properties of the metal oxide thin film transistor.

[0068] See also Figures 2 to 3 In the display panel of the present application, the first isolation layer 410 covers the first active layer 101 and extends toward the second active layer 201; wherein the thickness of the first isolation layer 410 corresponding to the first thin film transistor 100 is greater than the thickness of the first isolation layer 410 corresponding to the second thin film transistor 200.

[0069] In this embodiment, the first isolation layer 410 covers the first active layer 101 , and the first isolation layer 410 extends to the bottom of the second active layer 201 of the metal oxide thin film transistor.

[0070] In the present embodiment, the first isolation layer 410 is made of a material having an atomic percentage of hydrogen less than a first threshold, such as silicon oxide (SiOx).

[0071] In this embodiment, the thickness of the first isolation layer 410 corresponding to the first active layer 101 is greater than the thickness of the first isolation layer 410 corresponding to the second active layer 201 .

[0072] In this embodiment, the thickness of the first isolation layer 410 at the location corresponding to the second active layer 201 ranges from 50 angstroms to 1300 angstroms.

[0073] In this embodiment, the thickness of the first isolation layer 410 at the second active layer 201 may be a thickness thinned by etching. In the art, etching is a conventional process and is not limited here.

[0074] In this embodiment, the first isolation layer 410 at the second active layer 201 is thinned so that the thickness of the first isolation layer 410 corresponding to the first active layer 101 is greater than the thickness of the first isolation layer 410 corresponding to the second active layer 201, thereby ensuring that the first isolation layer 410 in contact with the second active layer 201 is the middle part of the film layer, and the hydrogen content in the material of the middle part is less affected by the adjacent film layers, thereby ensuring that the hydrogen content in the material there is low, reducing the proportion of hydrogen elements in the first isolation layer 410 penetrating into the second active layer 201, thereby improving the electrical properties of the metal oxide in the second active layer 201, thereby enhancing the stability of the second thin film transistor 200.

[0075] In this embodiment, hydrogen needs to be introduced in the manufacturing process of the first interinsulating layer 403 of the first active layer 101, which results in a higher hydrogen content in the first interinsulating layer 403. By forming a groove running through the first interinsulating layer 403 and a portion of the first isolation layer 410, the first interinsulating layer 403 with a higher hydrogen content can be removed to prevent the hydrogen in the first interinsulating layer 403 from affecting the electrical properties of the subsequent second active layer 201.

[0076] See also Figures 2 to 3 In the display panel of the present application, the array layer includes: a first gate layer 120, arranged on the first isolation layer 410; a first inter-insulating layer 403, arranged on the first gate layer 120; wherein the array layer also includes a plurality of grooves, at least one of the second thin film transistors 200 is arranged in the groove, and the groove at least passes through the first inter-insulating layer 403 and a portion of the first isolation layer 410.

[0077] In this embodiment, the first interlayer insulating layer 403 is made of a material having an atomic percentage of hydrogen greater than a first threshold, such as silicon nitride (SiNx).

[0078] In the present embodiment, the first isolation layer 410 is made of a material having an atomic percentage of hydrogen less than a first threshold, such as silicon oxide (SiOx).

[0079] In this embodiment, the groove may be formed by an etching process, which is a conventional process in the art and is not limited here.

[0080] In this embodiment, the second thin film transistor 200 may be a metal oxide thin film transistor, such as an IGZO thin film transistor.

[0081] In this embodiment, the first thin film transistor 100 may be manufactured first, and after forming the first interlayer insulating layer 403, a groove may be dug by etching, and then the second thin film transistor 200 may be manufactured in the groove.

[0082] In this embodiment, the groove passes through the first inter-insulating layer 403 and a portion of the first isolation layer 410 , that is, the first inter-insulating layer 403 at the groove is completely removed, and the first isolation layer 410 is partially removed.

[0083] In this embodiment, a groove is formed that penetrates the first interlayer insulating layer 403 and a portion of the first isolation layer 410 to remove the first interlayer insulating layer 403 with a high hydrogen content, thereby preventing hydrogen in the first interlayer insulating layer 403 from penetrating into the second active layer 201, thereby improving the electrical properties of the metal oxide in the second active layer 201, thereby enhancing the stability of the second thin film transistor 200.

[0084] In this embodiment, hydrogen needs to be introduced in the manufacturing process of the first inter-insulating layer 403. The material used in the first inter-insulating layer 403 is conducive to the diffusion of hydrogen therein, so the hydrogen content in the first inter-insulating layer 403 is relatively high. In the process of hydrogen diffusing to the film layer adjacent to the first inter-insulating layer 403, hydrogen is not easy to diffuse in the first isolation layer 410 due to the material properties of the first isolation layer 410. Therefore, the hydrogen in the first isolation layer 410 is relatively small, thereby reducing the influence of the hydrogen in the first isolation layer 410 on the second active layer 201, and improving the stability of the second thin film transistor 200.

[0085] In the display panel of the present application, the atomic percentage of hydrogen in the first inter-insulating layer 403 is greater than the atomic percentage of hydrogen in the first isolation layer 410 .

[0086] In this embodiment, the material of the first interlayer insulating layer 403 is a material whose atomic percentage of hydrogen is greater than a first threshold, such as silicon nitride (SiNx). The material of the first isolation layer 410 is a material whose atomic percentage of hydrogen is less than a first threshold, such as silicon oxide (SiOx).

[0087] In this embodiment, the hydrogen in the first isolation layer 410 may come from a hydrogen replenishing process.

[0088] In this embodiment, the hydrogen in the first interlayer insulating layer 403 may come from a hydrogen replenishing process.

[0089] In this embodiment, by setting the atomic percentage of hydrogen elements in the first inter-insulating layer 403 to be greater than the atomic percentage of hydrogen elements in the first isolation, the atomic percentage of hydrogen elements in the first isolation layer 410 can be made as low as possible to reduce the impact of hydrogen on the second active layer 201 and improve the stability of the second thin film transistor 200.

[0090] In the display panel of the present application, the second thin film transistor 200 includes: a second isolation layer 420, which is arranged on the second active layer 201; a second gate layer 220, which is arranged on the second isolation layer 420; and a second interlayer insulating layer 404, which is arranged on the second gate layer 220, and the second interlayer insulating layer 404 covers the second gate layer 220 and the second active layer 201; wherein the second interlayer insulating layer 404 extends from the second thin film transistor 200 to the first thin film transistor 100, and the second interlayer insulating layer 404 contacts the surface of the first interlayer insulating layer 403 away from the first active layer 101, and the atomic percentage of hydrogen element in the first interlayer insulating layer 403 is greater than the atomic percentage of hydrogen element in the second interlayer insulating layer 404.

[0091] In this example, see Figure 3 to Figure 4 , the second isolation layer 420 is located between the second gate layer 220 and the second active layer 201 .

[0092] In this embodiment, the second interlayer insulating layer 404 covers the first interlayer insulating layer 403 and covers the second thin film transistor 200 located in the groove, and the second interlayer insulating layer 404 contacts the second gate layer 220 and the second active layer 201 that are not covered by the second isolation layer 420 .

[0093] In this embodiment, the material of the second inter-insulating layer 404 may be a material whose atomic percentage of hydrogen is less than a first threshold, such as silicon oxide (SiOx).

[0094] In this embodiment, the material of the first inter-insulating layer 403 may be a material whose atomic percentage of hydrogen is greater than a first threshold, such as silicon nitride (SiNx).

[0095] In this embodiment, the atomic percentage of hydrogen in the first interlayer insulating layer 403 is greater than the atomic percentage of hydrogen in the second interlayer insulating layer 404 .

[0096] In this embodiment, by covering the second thin film transistor 200 with the second interlayer insulating layer 404 and making the atomic percentage of hydrogen in the second interlayer insulating layer 404 smaller than the atomic percentage of hydrogen in the first interlayer insulating layer 403, the hydrogen content in the film layer contacted by the second active layer 201 can be reduced, and the penetration ratio of hydrogen in the second interlayer insulating layer 404 into the second active layer 201 can be reduced, thereby improving the electrical properties of the metal oxide in the second active layer 201, thereby enhancing the stability of the second thin film transistor 200.

[0097] In this example, see Figures 2 to 3 In the first thin film transistor 100, by setting the second sub-gate layer 122 on the first sub-gate layer 121, the second sub-gate layer 122 and the first sub-gate layer 121 can form a capacitor, which can save circuit area and increase the aperture ratio of the display panel. By setting the atomic percentage of hydrogen in the first sub-isolation layer 401 to be less than the atomic percentage of hydrogen in the second sub-isolation layer 402, and removing the second sub-isolation layer 402 at the groove, it is possible to avoid the hydrogen in the second sub-isolation layer 402 from affecting the first sub-isolation layer 401, thereby avoiding the excessive hydrogen content in the first sub-isolation layer 401 from affecting the second active layer 201, and improving the stability of the second thin film transistor 200.

[0098] In the display panel of the present application, the first gate layer 120 includes a first sub-gate layer 121 and a second sub-gate layer 122, the first isolation layer 410 includes a first sub-isolation layer 401 and a second sub-isolation layer 402, the first sub-isolation layer 401 covers the first active layer 101, the first sub-gate layer 121 is arranged on the first sub-isolation layer 401, the second sub-isolation layer 402 covers the first sub-gate layer 121, and the second sub-gate layer 122 is arranged on the second sub-isolation layer 402; wherein the atomic percentage of hydrogen element in the first sub-isolation layer 401 is less than the atomic percentage of hydrogen element in the second sub-isolation layer 402.

[0099] In this example, see Figure 2 and Figure 3 The first source and drain 110 can be a connecting segment formed at one time, which sequentially passes through the second inter-insulating layer 404, the first inter-insulating layer 403, and the first isolation layer 410, and is further electrically connected to the first doped portion 1012 of the first active layer 101.

[0100] In this embodiment, the first gate layer 120 may include a first sub-gate layer 121 and a second sub-gate layer 122. By disposing the second sub-gate layer 122 on the first sub-gate layer 121, a capacitor can be formed between the first sub-gate layer 121 and the second sub-gate layer 122, thereby saving circuit area and increasing the aperture ratio of the display panel.

[0101] In this embodiment, the first gate layer 120 may be a single gate.

[0102] In this embodiment, the materials of the first sub-isolation layer 401 and the second sub-isolation layer 402 are different, wherein the first sub-isolation layer 401 is a material whose atomic percentage of hydrogen element is less than a first threshold, such as silicon oxide (SiOx); and the second sub-isolation layer 402 is a material whose atomic percentage of hydrogen element is greater than the first threshold, such as silicon nitride (SiNx).

[0103] In this embodiment, the groove passes through the first inter-insulating layer 403 , the second sub-isolation layer 402 and a portion of the first sub-isolation layer 401 , that is, the bottom surface of the second active layer 201 is in contact with the first sub-isolation layer 401 .

[0104] In this embodiment, by providing the first sub-gate layer 121 and the second sub-gate layer 122, a capacitor can be formed between the first sub-gate layer 121 and the second sub-gate layer 122, thereby saving circuit area and increasing the aperture ratio of the display panel. At the same time, by setting the atomic percentage of hydrogen in the first sub-isolating layer 401 to be less than the atomic percentage of hydrogen in the second sub-isolating layer 402, and removing the second sub-isolating layer 402 at the groove, the hydrogen in the second sub-isolating layer 402 is prevented from subsequently diffusing into the first sub-isolating layer 401, thereby avoiding increasing the hydrogen content in the first sub-isolating layer 401, reducing the influence of hydrogen on the second active layer 201, and improving the stability of the second thin film transistor 200.

[0105] See also Figures 2 to 3 In the display panel of the present application, the second active layer 201 includes: a second channel portion 2011, corresponding to the second isolation layer 420 and the second gate layer 220; a second doped portion 2012, arranged on both sides of the second channel portion 2011; wherein the second inter-insulating layer 404 is in contact with the channel material in the peripheral area of ​​the second channel portion 2011.

[0106] In this embodiment, the second active layer 201 includes a second channel portion 2011, which is covered by the second gate layer 220 and is slightly larger than the second gate layer 220. The second doped portion 2012 is a portion of the second active layer 201 located on both sides of the second channel portion 2011.

[0107] In this embodiment, the second inter-insulating layer 404 covers the second doped portion 2012 and a portion of the second channel portion 2011 at a junction with the second doped portion 2012 .

[0108] In this embodiment, the second inter-insulating layer 404 covers the upper surface of the second gate layer 220 .

[0109] In this embodiment, by setting the second interlayer insulating layer 404 in contact with the channel material in the peripheral area of ​​the second channel portion 2011, it is possible to block the hydrogen in the first interlayer insulating layer 403 from diffusing into the second active layer 201, reduce the hydrogen content in the film layer in contact with the second active layer 201, and further reduce the impact on the second active layer 201, thereby improving the stability of the second thin film transistor 200.

[0110] In this embodiment, in order to further reduce the impact of hydrogen on the second active layer 201, the adjustment layer 205 can be set above the second thin film transistor 200. The adjustment layer 205 can be made of materials with different hydrogen contents according to the actual detected characteristics of the second active layer 201. The difference in hydrogen content in the material can be used to adjust the hydrogen content in the second active layer 201, thereby adjusting the electrical properties of the second thin film transistor 200 and improving the stability of the second thin film transistor 200.

[0111] See also Figures 2 to 3 In the display panel of the present application, the second thin film transistor 200 also includes: a second source and drain electrode 210, which is electrically connected to the second active layer 201; an adjustment layer 205, which is arranged on the second inter-insulating layer 404; wherein the orthographic projection of the adjustment layer 205 on the second active layer 201 at least partially overlaps with the second active layer 201, and the adjustment layer 205 contains hydrogen elements.

[0112] In this embodiment, the second source and drain 210 is electrically connected to the second doped portion 2012 of the second active layer 201 .

[0113] In this embodiment, an adjustment layer 205 is disposed on the upper surface of the second inter-insulating layer 404 at the groove, and the adjustment layer 205 can be used to adjust the hydrogen content in the second active layer 201 .

[0114] In this embodiment, the material of the adjustment layer 205 can be a material whose atomic percentage of hydrogen element is less than the first threshold value, such as silicon oxide (SiOx), or a material whose atomic percentage of hydrogen element is greater than the first threshold value, such as silicon nitride (SiNx), or SiON (silicon oxynitride), and the corresponding material can be selected according to the actual process requirements. For example, by measuring the electrical properties of the second thin film transistor 200, any one or more materials of SiOx, SiNx, and SiON can be selected as the material of the adjustment layer 205.

[0115] In this embodiment, by providing the adjustment layer 205 , the hydrogen content in the second active layer 201 of the second thin film transistor 200 can be adjusted, thereby adjusting the electrical properties of the second thin film transistor 200 and improving the stability of the second thin film transistor 200 .

[0116] See also Figure 1 to Figure 2 In the display panel of the present application, the array layer includes a gate driving circuit area AA and a pixel circuit area BB, a plurality of the first thin film transistors 100 are located in the gate driving circuit area AA, and a plurality of the second thin film transistors 200 are located in the pixel circuit area BB.

[0117] In this embodiment, the array layer includes the gate driver circuit area AA and the pixel circuit area BB, the gate driver circuit area AA is used to arrange the GOA (Gate Driver on Array, array substrate row drive) circuit, and the pixel circuit area BB is used to display the picture.

[0118] In this embodiment, a plurality of the first thin film transistors 100 are located in the gate driving circuit area AA, and a plurality of the second thin film transistors 200 are located in the pixel circuit area BB.

[0119] In this embodiment, a plurality of the second thin film transistors 200 are located in the gate driving circuit area AA, and a plurality of the first thin film transistors 100 are located in the pixel circuit area BB.

[0120] In this embodiment, the gate driving circuit area AA includes the first thin film transistor 100 and the second thin film transistor 200 , and the pixel circuit area BB includes the first thin film transistor 100 and the second thin film transistor 200 .

[0121] By disposing the first thin film transistor 100 and the second thin film transistor 200 in the gate driving circuit area AA and the pixel circuit area BB, the characteristics of both structures can be combined to achieve a display with higher quality and lower power consumption.

[0122] Embodiment 2

[0123] This embodiment is the same or similar to the first embodiment, except that: in the first embodiment, refer to Figure 2 , the first source and drain 110 may be a connecting segment formed at one time, and the connecting segment sequentially penetrates the second inter-insulating layer 404, the first inter-insulating layer 403, and the first isolation layer 410, and is further electrically connected to the first doped portion 1012 of the first active layer 101. In this embodiment, please refer to Figure 4 The first source and drain electrode 110 of the first thin film transistor 100 may include a first connecting segment 103 and a second connecting segment 104 that are continuously arranged, and the first source and drain electrode 110 is electrically connected to the first doped portion 1012 through the two connecting segments.

[0124] See also Figures 4 to 5 In the display panel of the present application, the first thin film transistor 100 also includes a first source-drain electrode 110 electrically connected to the first active layer 101, and the first source-drain electrode 110 includes a first connecting segment 103 and a second connecting segment 104 that are continuously arranged, and the materials of the first connecting segment 103 and the second connecting segment 104 are different.

[0125] In this embodiment, the first active layer 101 includes a first channel portion 1011 corresponding to the first gate layer 120 and the first doped portions 1012 located at two sides of the first channel portion 1011 .

[0126] In this embodiment, the first thin film transistor 100 includes a first source and drain electrode 110 , and the first source and drain electrode 110 is electrically connected to the first doped portion 1012 of the first active layer 101 .

[0127] In this example, see Figures 4 to 5 The first source and drain electrode 110 may include the first connecting segment 103 and the second connecting segment 104 which are continuously arranged. By configuring the first source and drain electrode 110 to be the first connecting segment 103 and the second connecting segment 104, the height of each connecting segment can be reduced, the process difficulty can be reduced, and the quality of the connecting segment can be improved.

[0128] In this embodiment, the materials of the first connecting section 103 and the second connecting section 104 can be set to different materials or the same material.

[0129] In this embodiment, the material of the first connecting segment 103 may be metal oxide, such as IGZO.

[0130] In this embodiment, the material of the second connecting section 104 may be metal, such as one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).

[0131] In this embodiment, the first connecting segment 103 is located in a through hole penetrating the first inter-insulating layer 403, and the second connecting segment 104 is located in a through hole penetrating the second inter-insulating layer 404, wherein the through hole corresponding to the first connecting segment 103 can be formed in the same process as the groove, thereby saving one photomask.

[0132] The present application also provides a mobile terminal, which includes the display panel and a terminal body as described above, and the display panel and the terminal body are combined into one.

[0133] In this embodiment, the terminal may be any product or component with a display function, such as a smart watch, a smart bracelet, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, or the like.

[0134] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0135] The above is a detailed introduction to a display panel and a mobile terminal provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a substrate and an array layer disposed on the substrate; wherein the array layer includes: A plurality of first thin film transistors, at least one of the first thin film transistors comprises a first active layer; a plurality of second thin film transistors, at least one of the second thin film transistors comprises a second active layer, the first active layer and the second active layer are made of different materials, and the second active layer comprises a metal oxide; Among them, the second thin film transistor also includes a first isolation layer, the first isolation layer is arranged on the side of the second active layer close to the substrate, the first isolation layer is in contact with the second active layer, and the atomic percentage of hydrogen elements in the first isolation layer is less than a first threshold; the first isolation layer covers the first active layer and extends to the second active layer; the array layer includes a first interlayer insulating layer arranged on the first isolation layer, the atomic percentage of hydrogen elements in the first interlayer insulating layer is greater than the atomic percentage of hydrogen elements in the first isolation layer, and the array layer also includes a plurality of grooves, at least one of the second thin film transistors is arranged in the groove, and the groove at least passes through the first interlayer insulating layer and a portion of the first isolation layer.

2. The display panel according to claim 1, characterized in that: A thickness of the first isolation layer corresponding to the first thin film transistor is greater than a thickness of the first isolation layer corresponding to the second thin film transistor.

3. The display panel according to claim 2, characterized in that: The array layer comprises: A first gate layer, disposed on the first isolation layer; Wherein, the first inter-insulating layer is disposed on the first gate layer.

4. The display panel according to claim 3, characterized in that: The second thin film transistor comprises: a second isolation layer, disposed on the second active layer; A second gate layer is disposed on the second isolation layer; and a second interlayer insulating layer, disposed on the second gate layer, wherein the second interlayer insulating layer covers the second gate layer and the second active layer; The second insulating layer extends from the second thin film transistor to the first thin film transistor, and the second insulating layer contacts the surface of the first insulating layer away from the first active layer, and the atomic percentage of hydrogen in the first insulating layer is greater than the atomic percentage of hydrogen in the second insulating layer.

5. The display panel according to claim 3, characterized in that: The first gate layer includes a first sub-gate layer and a second sub-gate layer, the first isolation layer includes a first sub-isolation layer and a second sub-isolation layer, the first sub-isolation layer covers the first active layer, the first sub-gate layer is arranged on the first sub-isolation layer, the second sub-isolation layer covers the first sub-gate layer, and the second sub-gate layer is arranged on the second sub-isolation layer; The atomic percentage of hydrogen in the first sub-isolation layer is less than the atomic percentage of hydrogen in the second sub-isolation layer.

6. The display panel according to claim 4, characterized in that: The second active layer comprises: a channel portion corresponding to the second isolation layer and the second gate layer; a doping portion, disposed on both sides of the channel portion; The second inter-insulating layer is in contact with the channel material in the peripheral area of ​​the channel portion.

7. The display panel according to claim 6, characterized in that: The second thin film transistor further includes: a second source and drain electrode, wherein the second source and drain electrode is electrically connected to the second active layer; An adjusting layer, disposed on the second insulating layer; The orthographic projection of the adjustment layer on the second active layer at least partially overlaps with the second active layer, and the adjustment layer contains hydrogen elements.

8. The display panel according to claim 1, characterized in that: The array layer includes a gate driving circuit area and a pixel circuit area. The plurality of first thin film transistors are located in the gate driving circuit area, and the plurality of second thin film transistors are located in the pixel circuit area.

9. The display panel according to claim 1, characterized in that: The first thin film transistor further includes a first source-drain electrode electrically connected to the first active layer, the first source-drain electrode includes a first connecting segment and a second connecting segment which are continuously arranged, and the first connecting segment and the second connecting segment are made of different materials.

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