Low voltage dual input power supply switching circuit

Abstract

The application relates to a low-voltage double-input power supply switching circuit which is used for detecting the sizes of two input power supplies, automatically switching the larger one of the two input power supplies as an output voltage according to the priority order of the input power supplies, and supplying power by a main power supply when the two power supply voltages are the same. The low-voltage double-input power supply switching circuit comprises MOS tube peak current source circuit 1, MOS tube peak current source circuit 2, a power supply input detection circuit, a logic control circuit and a power supply switching module. The current I1 generated under the main power supply VIN1 is superposed with the current I2 generated under the standby power supply VIN2 in the MOS tube peak current source circuit 2, and then is mirrored to the power supply input detection circuit through a current mirror structure. The circuit structure of the application is simple, the low-voltage double-input power supply switching function is realized, the switching between the power supplies is realized in time when the main power supply appears abnormal conditions in a high-reliability multi-power supply system, and the long-term stable work of an electronic equipment system is ensured.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a low-voltage dual-input power switching circuit. Background Technology

[0002] In low-voltage microcircuit systems with high reliability requirements, dual or multiple power supplies are typically used to improve the reliability and lifespan of electronic devices. The electronic devices operate normally under the main power supply, and immediately switch to the backup power supply in case of an anomaly, ensuring long-term, stable, and reliable operation. If the switching time between a main power failure and the backup power supply is too long, it can lead to discontinuous operation or even system crashes. Therefore, it is crucial to determine how to effectively switch between the main and backup power supplies while ensuring the entire switching process is sufficiently short.

[0003] Therefore, a low-voltage dual-input power supply circuit is needed to solve the above problems. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problem of how to switch between the main power supply and the backup power supply when the main power supply is abnormal in a high-reliability dual power supply or multi power supply system, and to ensure that the time taken for the entire switching process is short enough to ensure the long-term stable operation of the system.

[0005] To solve the above technical problems, the present invention provides a low-voltage dual-input power switching circuit, which is used to detect the magnitude of two input power supplies and automatically switch the larger of the two input power supplies as the output voltage according to the priority order of the input power supplies. When the two power supply voltages are the same, the main power supply provides power.

[0006] The low-voltage dual-input power switching circuit includes a MOSFET peak current source circuit 1, a MOSFET peak current source circuit 2, a power input detection circuit, a logic control circuit, and a power switching module.

[0007] The peak current source circuit 1 of the MOSFET will superimpose the current I1 generated under the main power supply VIN1 and the current I2 generated under the backup power supply VIN2 in the peak current source circuit 2 of the MOSFET will be mirrored to the power input detection circuit through the current mirror structure.

[0008] The peak current source circuit 2 of the MOSFET will mirror the current I2 generated under the backup power supply VIN2 to the peak current source circuit 1 of the MOSFET through the current mirror structure.

[0009] The power input detection circuit is used to compare the magnitudes of the main power supply VIN1 and the backup power supply VIN2, convert the comparison result into a digital control signal and output it.

[0010] The logic control circuit is used to perform logic preprocessing on the digital output control signal generated by the power input detection circuit, and the processed output signal controls the working state of the power switching module.

[0011] The power switching module is used to switch between the main power supply VIN1 and the backup power supply VIN2, and switch the larger one to the output voltage INTVIN.

[0012] Optionally, the low-voltage dual-input power switching circuit is characterized in that the MOS transistor peak current source circuit 1 includes a first current source I1, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a first resistor R1, a second resistor R2, a first P-type MOS transistor MP1, and a second P-type MOS transistor MP2.

[0013] The positive terminal of the first current source I1 is connected to the main power supply VIN1, and the negative terminal is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the drain of the first N-type MOSFET MN1; the gate of the first N-type MOSFET MN1 is connected to the negative terminal of the first current source I1, and the source is connected to the common ground VSS; the gate of the second N-type MOSFET MN2 is connected to the drain of the first N-type MOSFET MN1, the source is connected to the common ground VSS, and the drain is connected to the gate and drain of the first P-type MOSFET MP1; the source of the first P-type MOSFET MP1 is connected to the main power supply VIN1; the source of the second P-type MOSFET MP2 is connected to the main power supply VIN1, the gate is connected to the gate of the first P-type MOSFET MP1, and the drain is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to the drain of the third N-type MOSFET MN3; the gate of the third N-type MOSFET MN3 is connected to the drain of the second P-type MOSFET MP2, and the source is connected to the common ground VSS.

[0014] Optionally, the low-voltage dual-input power switching circuit is characterized in that the MOS transistor peak current source circuit 2 includes a second current source I2, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a third resistor R3, a tenth P-type MOS transistor MP10, and an eleventh P-type MOS transistor MP11.

[0015] The positive terminal of the second current source I2 is connected to the backup power supply VIN2, and the negative terminal is connected to one end of the third resistor R3; the other end of the third resistor R3 is connected to the drain of the twelfth N-type MOSFET MN12; the gate of the twelfth N-type MOSFET MN12 is connected to the negative terminal of the second current source I2, and the source is connected to the common ground VSS; the gate of the thirteenth N-type MOSFET MN13 is connected to the drain of the twelfth N-type MOSFET MN12, the source is connected to the common ground VSS, and the drain is connected to the gate and drain of the tenth P-type MOSFET MP10; the source of the tenth P-type MOSFET MP10 is connected to the backup power supply VIN2; the source of the eleventh P-type MOSFET MP11 is connected to the backup power supply VIN2, the gate is connected to the gate of the tenth P-type MOSFET MP10, and the drain is connected to the MOSFET peak current source circuit 1.

[0016] Optionally, the low-voltage dual-input power switching circuit is characterized in that the power input detection circuit includes a fourth N-type MOSFET MN4, a fifth N-type MOSFET MN5, a sixth N-type MOSFET MN6, a seventh N-type MOSFET MN7, an eighth N-type MOSFET MN8, a ninth N-type MOSFET MN9, a tenth N-type MOSFET MN10, an eleventh N-type MOSFET MN11, a third P-type MOSFET MP3, a fourth P-type MOSFET MP4, a fifth P-type MOSFET MP5, a sixth P-type MOSFET MP6, a seventh P-type MOSFET MP7, an eighth P-type MOSFET MP8, a ninth P-type MOSFET MP9, a twelfth P-type MOSFET MP12, and a thirteenth P-type MOSFET MP13.

[0017] The gate of the fourth N-type MOSFET MN4 is connected to the drain of the third N-type MOSFET MN3, its source is connected to the common ground VSS, and its drain is connected to the gate and drain of the third P-type MOSFET MP3; the gate of the fifth N-type MOSFET MN5 is connected to the gate of the fourth N-type MOSFET MN4, its source is connected to the common ground VSS, and its drain is connected to the gate and drain of the fifth P-type MOSFET MP5; the gate and drain of the sixth N-type MOSFET MN6 are connected to the drain of the sixth P-type MOSFET MP6, and its source is connected to the common ground VSS; the gate of the seventh N-type MOSFET MN7 is connected to the gate of the sixth N-type MOSFET MN6, its source is connected to the common ground VSS, and its drain is connected to the drain of the thirteenth P-type MOSFET MP13; The gate of the eighth N-type MOSFET MN8 is connected to the gate of the seventh N-type MOSFET MN7, its source is connected to the common ground VSS, and its drain is connected to the drain of the seventh P-type MOSFET MP7; the gate and drain of the ninth N-type MOSFET MN9 are connected to the drain of the eighth P-type MOSFET MP8, and its source is connected to the common ground VSS; the gate of the tenth N-type MOSFET MN10 is connected to the gate of the ninth N-type MOSFET MN9, its source is connected to the common ground VSS, and its drain is connected to the drain of the thirteenth P-type MOSFET MP13; the gate of the eleventh N-type MOSFET MN11 is connected to the gate of the tenth N-type MOSFET MN10, its source is connected to the common ground VSS, and its drain is connected to the drain of the ninth P-type MOSFET MP9.

[0018] The gate-drain terminal of the third P-type MOSFET MP3 is connected to the gate-drain terminal of the twelfth P-type MOSFET MP12, and its source terminal is connected to the main power supply VIN1. The gate terminal of the fourth P-type MOSFET MP4 is connected to the gate of the third P-type MOSFET MP3, its source terminal is connected to the main power supply VIN1, and its drain terminal is connected to the drain terminal of the sixth N-type MOSFET MN6. The gate-drain terminals of the fifth P-type MOSFET MP5 are both connected to the drain terminals of the fifth N-type MOSFET MN5, and its source terminal is connected to the output voltage INTVCC. The gate terminal of the sixth P-type MOSFET MP6 is connected to the gate of the fifth P-type MOSFET MP5, and its source terminal is connected to the output voltage IN. The TVCC connection is established, with its drain terminal connected to the drain terminal of the sixth N-type MOSFET MN6; the gate terminal of the seventh P-type MOSFET MP7 is connected to the gate of the sixth P-type MOSFET MP6, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the logic control circuit; the gate terminal of the eighth P-type MOSFET MP8 is connected to the gate of the seventh P-type MOSFET MP7, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the drain terminal of the ninth N-type MOSFET MN9; the gate terminal of the ninth P-type MOSFET MP9 is connected to the gate of the eighth P-type MOSFET MP8, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the logic control circuit.

[0019] The gate and drain terminals of the twelfth P-type MOSFET MP12 are both connected to the drain terminal of the third P-type MOSFET MP3, and the source terminal is connected to the backup power supply VIN2; the gate terminal of the thirteenth P-type MOSFET MP13 is connected to the gate of the twelfth P-type MOSFET MP12, the source terminal is connected to the backup power supply VIN2, and the drain terminal is connected to the drain terminal of the tenth N-type MOSFET MN10.

[0020] Optionally, the low-voltage dual-input power switching circuit is characterized in that the logic control circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first two-input NOR gate NOR1.

[0021] The input terminal of the first inverter INV1 is connected to the drain terminal of the seventh P-type MOSFET MP7 in the power input detection circuit, and its output terminal is connected to the input terminal of the second inverter INV2. Its power supply is connected to the main power supply VIN1. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and its output terminal Y1 is connected to the power switching module. Its power supply is connected to the output voltage INTVIN. The first input terminal of the first two-input NOR gate NOR1 is connected to the output terminal of the second inverter INV2, and its second input terminal is connected to the drain terminal of the ninth P-type MOSFET MP9 in the power input detection circuit. Its output terminal is connected to the input terminal of the third inverter IN3. Its power supply is connected to the backup power supply VIN2. The input terminal of the third inverter INV3 is connected to the output terminal of the first two-input NOR gate NOR1. Its power supply is connected to the output voltage INTVIN, and its output terminal Y2 is connected to the power switching module.

[0022] Optionally, the low-voltage dual-input power switching circuit is characterized in that the power switching module includes a first P-type MOS switch SW1, a second P-type MOS switch SW2, and a first capacitor C1.

[0023] The drain of the first P-type MOS switch SW1 is connected to the main power supply VIN1, the gate is connected to the first output Y1 of the logic control circuit, and the source is connected to the output voltage INTVIN; the drain of the second P-type MOS switch SW2 is connected to the backup power supply VIN2, the gate is connected to the second output Y2 of the logic control circuit, and the source is connected to the source of the first P-type MOS switch SW1; the positive terminal of the first capacitor C1 is connected to the source of the first P-type MOS switch SW1, and the negative terminal is connected to the common ground VSS.

[0024] The low-voltage dual-input power switching circuit provided by this invention includes a MOSFET peak current source circuit 1, a MOSFET peak current source circuit 2, a power input detection circuit, a logic control circuit, and a power switching module. The MOSFET peak current source circuit 1 superimposes the current I1 generated under the main power supply VIN1 and the current I2 generated under the backup power supply VIN2 in the MOSFET peak current source circuit 2, and then mirrors the result to the power input detection circuit through a current mirror structure. The MOSFET peak current source circuit 2 mirrors the current I2 generated under the backup power supply VIN2 to the MOSFET peak current source circuit 1 through a current mirror structure. The power input detection circuit compares the magnitudes of the main power supply VIN1 and the backup power supply VIN2, converts the comparison result into a digital control signal, and outputs it. The logic control circuit preprocesses the digital output control signal generated by the power input detection circuit, and outputs the processed signal to control the working state of the power switching module. The power switching module switches between the main power supply VIN1 and the backup power supply VIN2, switching the larger one to the output voltage INTVIN.

[0025] The circuit structure of this invention is simple, realizes the low-voltage dual-input power switching function, and the switching time is very small. It solves the problem that in a high-reliability multi-power supply system, when the main power supply is abnormal, the switching between the main power supply and the backup power supply cannot be realized in time, which leads to the inability of the electronic equipment system to work stably for a long time. Attached Figure Description

[0026] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0027] Figure 1 This is a schematic diagram of the low-voltage dual-input power switching circuit provided by the present invention.

[0028] Figure 2 This is a waveform diagram of the low-voltage dual-input power switching circuit provided by the present invention when it is working normally. Detailed Implementation

[0029] The low-voltage dual-input power switching circuit provided by this invention includes a MOSFET peak current source circuit 1, a MOSFET peak current source circuit 2, a power input detection circuit, a logic control circuit, and a power switching module. The MOSFET peak current source circuit 1 superimposes the current I1 generated under the main power supply VIN1 and the current I2 generated under the backup power supply VIN2 in the MOSFET peak current source circuit 2, and then mirrors the result to the power input detection circuit through a current mirror structure. The MOSFET peak current source circuit 2 mirrors the current I2 generated under the backup power supply VIN2 to the MOSFET peak current source circuit 1 through a current mirror structure. The power input detection circuit compares the magnitudes of the main power supply VIN1 and the backup power supply VIN2, converts the comparison result into a digital control signal, and outputs it. The logic control circuit preprocesses the digital output control signal generated by the power input detection circuit, and outputs the processed signal to control the working state of the power switching module. The power switching module switches between the main power supply VIN1 and the backup power supply VIN2, switching the larger one to the output voltage INTVIN.

[0030] like Figure 1 As shown, the low-voltage dual-input power switching circuit is characterized in that the MOS transistor peak current source circuit 1 includes a first current source I1, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a first resistor R1, a second resistor R2, a first P-type MOS transistor MP1, and a second P-type MOS transistor MP2.

[0031] The positive terminal of the first current source I1 is connected to the main power supply VIN1, and the negative terminal is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the drain of the first N-type MOSFET MN1; the gate of the first N-type MOSFET MN1 is connected to the negative terminal of the first current source I1, and the source is connected to the common ground VSS; the gate of the second N-type MOSFET MN2 is connected to the drain of the first N-type MOSFET MN1, the source is connected to the common ground VSS, and the drain is connected to the gate and drain of the first P-type MOSFET MP1; the source of the first P-type MOSFET MP1 is connected to the main power supply VIN1; the source of the second P-type MOSFET MP2 is connected to the main power supply VIN1, the gate is connected to the gate of the first P-type MOSFET MP1, and the drain is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to the drain of the third N-type MOSFET MN3; the gate of the third N-type MOSFET MN3 is connected to the drain of the second P-type MOSFET MP2, and the source is connected to the common ground VSS.

[0032] The low-voltage dual-input power switching circuit is characterized in that the MOS transistor peak current source circuit 2 includes a second current source I2, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a third resistor R3, a tenth P-type MOS transistor MP10, and an eleventh P-type MOS transistor MP11.

[0033] The positive terminal of the second current source I2 is connected to the backup power supply VIN2, and the negative terminal is connected to one end of the third resistor R3; the other end of the third resistor R3 is connected to the drain of the twelfth N-type MOSFET MN12; the gate of the twelfth N-type MOSFET MN12 is connected to the negative terminal of the second current source I2, and the source is connected to the common ground VSS; the gate of the thirteenth N-type MOSFET MN13 is connected to the drain of the twelfth N-type MOSFET MN12, the source is connected to the common ground VSS, and the drain is connected to the gate and drain of the tenth P-type MOSFET MP10; the source of the tenth P-type MOSFET MP10 is connected to the backup power supply VIN2; the source of the eleventh P-type MOSFET MP11 is connected to the backup power supply VIN2, the gate is connected to the gate of the tenth P-type MOSFET MP10, and the drain is connected to the MOSFET peak current source circuit 1.

[0034] The low-voltage dual-input power switching circuit is characterized in that the power input detection circuit includes a fourth N-type MOSFET MN4, a fifth N-type MOSFET MN5, a sixth N-type MOSFET MN6, a seventh N-type MOSFET MN7, an eighth N-type MOSFET MN8, a ninth N-type MOSFET MN9, a tenth N-type MOSFET MN10, an eleventh N-type MOSFET MN11, a third P-type MOSFET MP3, a fourth P-type MOSFET MP4, a fifth P-type MOSFET MP5, a sixth P-type MOSFET MP6, a seventh P-type MOSFET MP7, an eighth P-type MOSFET MP8, a ninth P-type MOSFET MP9, a twelfth P-type MOSFET MP12, and a thirteenth P-type MOSFET MP13.

[0035] The gate of the fourth N-type MOSFET MN4 is connected to the drain of the third N-type MOSFET MN3, its source is connected to the common ground VSS, and its drain is connected to the gate and drain of the third P-type MOSFET MP3; the gate of the fifth N-type MOSFET MN5 is connected to the gate of the fourth N-type MOSFET MN4, its source is connected to the common ground VSS, and its drain is connected to the gate and drain of the fifth P-type MOSFET MP5; the gate and drain of the sixth N-type MOSFET MN6 are connected to the drain of the sixth P-type MOSFET MP6, and its source is connected to the common ground VSS; the gate of the seventh N-type MOSFET MN7 is connected to the gate of the sixth N-type MOSFET MN6, its source is connected to the common ground VSS, and its drain is connected to the drain of the thirteenth P-type MOSFET MP13; The gate of the eighth N-type MOSFET MN8 is connected to the gate of the seventh N-type MOSFET MN7, its source is connected to the common ground VSS, and its drain is connected to the drain of the seventh P-type MOSFET MP7; the gate and drain of the ninth N-type MOSFET MN9 are connected to the drain of the eighth P-type MOSFET MP8, and its source is connected to the common ground VSS; the gate of the tenth N-type MOSFET MN10 is connected to the gate of the ninth N-type MOSFET MN9, its source is connected to the common ground VSS, and its drain is connected to the drain of the thirteenth P-type MOSFET MP13; the gate of the eleventh N-type MOSFET MN11 is connected to the gate of the tenth N-type MOSFET MN10, its source is connected to the common ground VSS, and its drain is connected to the drain of the ninth P-type MOSFET MP9.

[0036] The gate-drain terminal of the third P-type MOSFET MP3 is connected to the gate-drain terminal of the twelfth P-type MOSFET MP12, and its source terminal is connected to the main power supply VIN1. The gate terminal of the fourth P-type MOSFET MP4 is connected to the gate of the third P-type MOSFET MP3, its source terminal is connected to the main power supply VIN1, and its drain terminal is connected to the drain terminal of the sixth N-type MOSFET MN6. The gate-drain terminals of the fifth P-type MOSFET MP5 are both connected to the drain terminals of the fifth N-type MOSFET MN5, and its source terminal is connected to the output voltage INTVCC. The gate terminal of the sixth P-type MOSFET MP6 is connected to the gate of the fifth P-type MOSFET MP5, and its source terminal is connected to the output voltage IN. The TVCC connection is established, with its drain terminal connected to the drain terminal of the sixth N-type MOSFET MN6; the gate terminal of the seventh P-type MOSFET MP7 is connected to the gate of the sixth P-type MOSFET MP6, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the logic control circuit; the gate terminal of the eighth P-type MOSFET MP8 is connected to the gate of the seventh P-type MOSFET MP7, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the drain terminal of the ninth N-type MOSFET MN9; the gate terminal of the ninth P-type MOSFET MP9 is connected to the gate of the eighth P-type MOSFET MP8, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the logic control circuit.

[0037] The gate and drain terminals of the twelfth P-type MOSFET MP12 are both connected to the drain terminal of the third P-type MOSFET MP3, and the source terminal is connected to the backup power supply VIN2; the gate terminal of the thirteenth P-type MOSFET MP13 is connected to the gate of the twelfth P-type MOSFET MP12, the source terminal is connected to the backup power supply VIN2, and the drain terminal is connected to the drain terminal of the tenth N-type MOSFET MN10.

[0038] The low-voltage dual-input power switching circuit is characterized in that the logic control circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first two-input NOR gate NOR1.

[0039] The input terminal of the first inverter INV1 is connected to the drain terminal of the seventh P-type MOSFET MP7 in the power input detection circuit, and its output terminal is connected to the input terminal of the second inverter INV2. Its power supply is connected to the main power supply VIN1. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and its output terminal Y1 is connected to the power switching module. Its power supply is connected to the output voltage INTVIN. The first input terminal of the first two-input NOR gate NOR1 is connected to the output terminal of the second inverter INV2, and its second input terminal is connected to the drain terminal of the ninth P-type MOSFET MP9 in the power input detection circuit. Its output terminal is connected to the input terminal of the third inverter IN3. Its power supply is connected to the backup power supply VIN2. The input terminal of the third inverter INV3 is connected to the output terminal of the first two-input NOR gate NOR1. Its power supply is connected to the output voltage INTVIN, and its output terminal Y2 is connected to the power switching module.

[0040] The low-voltage dual-input power switching circuit is characterized in that the power switching module includes a first P-type MOS switch SW1, a second P-type MOS switch SW2, and a first capacitor C1.

[0041] The drain of the first P-type MOS switch SW1 is connected to the main power supply VIN1, the gate is connected to the first output Y1 of the logic control circuit, and the source is connected to the output voltage INTVIN; the drain of the second P-type MOS switch SW2 is connected to the backup power supply VIN2, the gate is connected to the second output Y2 of the logic control circuit, and the source is connected to the source of the first P-type MOS switch SW1; the positive terminal of the first capacitor C1 is connected to the source of the first P-type MOS switch SW1, and the negative terminal is connected to the common ground VSS.

[0042] The detailed working process of this invention is as follows:

[0043] When the main power supply VIN1 is powered on before the backup power supply VIN2, the MOSFET peak current source circuit 1 will preferentially generate current I1 under the main power supply VIN1. Current I1 is replicated to the drain of the second N-type MOSFET MN2 through the peak current source composed of the first resistor R1, the first N-type MOSFET MN1, and the second N-type MOSFET MN2. Then, I1 is mirrored to the drain of the second P-type MOSFET MP2 through the current mirror structure composed of the first P-type MOSFET MP1 and the second P-type MOSFET MP2. Since the backup power supply VIN2 is not powered on at this time, the MOSFET peak current source circuit 2 and the current mirror composed of the twelfth P-type MOSFET MP12 and the thirteenth P-type MOSFET MP13 are not working. Therefore, only current I1 flows into the peak current source composed of the second resistor R2, the third N-type MOSFET MN3, the fourth N-type MOSFET MN4, and the fifth N-type MOSFET MN5, and replicates current I1 to the drains of the fourth N-type MOSFET MN4 and the fifth N-type MOSFET MN5, respectively. During the power-on process of the main power supply VIN1, the output voltage INTVIN changes with VIN1. The output voltage INTVIN is approximately equal to VIN1 minus the parasitic body diode voltage of the first switching transistor SW1. The output voltage INTVIN serves as the power supply for the current mirror circuit composed of the fifth P-type MOSFET MP5, the sixth P-type MOSFET MP6, the seventh P-type MOSFET MP7, the eighth P-type MOSFET MP8, and the ninth P-type MOSFET MP9. During operation, it provides a weak pull-up effect on the drain terminals of the sixth N-type MOSFET MN6, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, and the eleventh N-type MOSFET MN11. The current I1 generated by the peak current source circuit 1 of the MOSFET flows into the current mirror structure composed of the third P-type MOSFET MP3 and the fourth P-type MOSFET MP4 through the drain of the fourth N-type MOSFET MN4. I1 is mirrored to the drain of the fourth P-type MOSFET MP4 and superimposed with the current flowing through the drain of the sixth P-type MOSFET MP6. A high pull-up level is applied to the gate of the current mirror structure composed of the sixth N-type MOSFET MN6, the seventh N-type MOSFET MN7 and the eighth N-type MOSFET MN8, so that the eighth N-type MOSFET MN8 is turned on because its gate is connected to a high level. Therefore, its drain (i.e., point A indicated by the arrow in the figure) outputs a low level. This low level at point A is input from the input of the first inverter INV of the logic control circuit and outputs a low level from the output of the second inverter INV2. This low level is connected to the gate of the first switching transistor SW1 of the power switching module. The first switching transistor SW1 is turned on, and the main power supply VIN1 is transmitted from its drain to its source, that is, the main power supply VIN1 is officially switched to the output power supply INTVIN.

[0044] Similarly, when the backup power supply VIN2 is powered on before the main power supply VIN1, the MOSFET peak current source circuit 2 will preferentially generate current I2 under the backup power supply VIN2. Current I2 is replicated to the drain of the thirteenth N-type MOSFET MN13 through the peak current source composed of the third resistor R3, the twelfth N-type MOSFET MN12, and the thirteenth N-type MOSFET MN13. Then, I2 is mirrored to the drain of the eleventh P-type MOSFET MP11 through the current mirror structure composed of the tenth P-type MOSFET MP10 and the eleventh P-type MOSFET MP11. Since the main power supply VIN1 is not powered on at this time, the MOSFET peak current source circuit 1 is not working. Therefore, only current I2 flows into the peak current source composed of the second resistor R2, the third N-type MOSFET MN3, the fourth N-type MOSFET MN4, and the fifth N-type MOSFET MN5, and replicates current I2 to the drains of the fourth N-type MOSFET MN4 and the fifth N-type MOSFET MN5, respectively. During the power-on process of the backup power supply VIN2, the output voltage INTVIN changes with VIN2. The output voltage INTVIN is approximately equal to VIN2 minus the parasitic body diode voltage of the second switching transistor SW2. The output voltage INTVIN serves as the power supply for the current mirror circuit composed of the fifth P-type MOSFET MP5, the sixth P-type MOSFET MP6, the seventh P-type MOSFET MP7, the eighth P-type MOSFET MP8, and the ninth P-type MOSFET MP9. During operation, it provides a weak pull-up effect on the drain terminals of the sixth N-type MOSFET MN6, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, and the eleventh N-type MOSFET MN11.The current I2 generated by the MOSFET peak current source circuit 2 flows through the drain of the fourth N-type MOSFET MN4 into the current mirror structure composed of the twelfth P-type MOSFET MP12 and the thirteenth P-type MOSFET MP13. I2 is mirrored to the drain of MP13 and superimposed with the current flowing through the drain of the eighth P-type MOSFET MP8. Together, they apply a high pull-up level to the gate of the current mirror structure composed of the ninth N-type MOSFET MN9, the tenth N-type MOSFET MN10, and the eleventh N-type MOSFET MN11. This causes the eleventh N-type MOSFET MN11 to conduct due to its gate being connected to a high level, thus its drain (point B indicated by the arrow in the diagram) outputs a low level. This low level at point B is transmitted from the first two inputs of the logic control circuit. The second input terminal of the NOR gate is input. At the same time, because the pull-up effect of the seventh P-type MOSFET MP7 is stronger than the pull-down effect of the eighth N-type MOSFET MN8, point A presents a high level. After being inverted by the first inverter INV, point A outputs a low level. This low level is input from the first input terminal of the first two-input NOR gate NOR1, so the output terminal of the first two-input NOR gate NOR1 outputs a high level. This high level is inverted by the third inverter INV3 and outputs a low level. This low level is connected to the gate of the second switching transistor SW2 of the power switching module. The second switching transistor SW2 is turned on, transferring the backup power supply VIN2 from its drain terminal to its source terminal, that is, officially switching the backup power supply VIN2 to the output power supply INTVIN.

[0045] like Figure 2 As shown, when the main power supply VIN1 and the backup power supply VIN2 are powered on simultaneously,

[0046] If VIN1≥VIN2, then the peak current source circuit 1 of the MOSFET will generate a current I1 under the main power supply VIN1, which is greater than the peak current source circuit 2 of the MOSFET will generate a current I2 under the backup power supply VIN2. The currents I1 and I2 are superimposed at the drain of the second P-type MOSFET MP2 and then pass through the peak current source composed of the second resistor R2, the third N-type MOSFET MN3, the fourth N-type MOSFET MN4, and the fifth N-type MOSFET MN5. The superimposed current I is then copied to the drains of the fourth N-type MOSFET MN4 and the fifth N-type MOSFET MN5, respectively. During the synchronous power-on process of the two power supplies, the output voltage INTVIN follows the large change of VIN1. The output voltage INTVIN is approximately equal to VIN1 minus the parasitic body diode voltage of the first switching transistor SW1. The output voltage INTVIN serves as the power supply for the current mirror circuit composed of the fifth P-type MOSFET MP5, the sixth P-type MOSFET MP6, the seventh P-type MOSFET MP7, the eighth P-type MOSFET MP8, and the ninth P-type MOSFET MP9. During operation, it generates a weak pull-up effect on the drain terminals of the sixth N-type MOSFET MN6, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, and the eleventh N-type MOSFET MN11, respectively. Current I flows through the drain of the fourth N-type MOSFET MN4 into the current mirror structure composed of the third P-type MOSFET MP3 and the fourth P-type MOSFET MP4, and the current mirror structure composed of the twelfth P-type MOSFET MP12 and the thirteenth P-type MOSFET MP13. This mirror image of I is projected onto the drains of the fourth P-type MOSFET MP4 and the thirteenth P-type MOSFET MP13. This current is superimposed on the current flowing through the drains of the sixth P-type MOSFET MP6 and the eighth P-type MOSFET MP8, applying a high pull-up level to the gate of the current mirror structure composed of the sixth N-type MOSFET MN6, the seventh N-type MOSFET MN7, and the eighth N-type MOSFET MN8. This causes the eighth N-type MOSFET... MN8 is turned on because its gate is connected to a high level, so its drain (point A in the diagram) outputs a low level. This low level at point A is input from the input of the first inverter INV of the logic control circuit and outputs a low level from the output of the second inverter INV2. At the same time, the high level output from the output of the first inverter INV is connected to the first input of the first two-input NOR1 gate, which shields the influence of VIN2. The low level output from the output of the second inverter INV2 is connected to the gate of the first switching transistor SW1 of the power switching module. The first switching transistor SW1 is turned on, and the main power supply VIN1 is transferred from its drain to its source, that is, the main power supply VIN1 is officially switched to the output power supply INTVIN.

[0047] Similarly, when VIN1 < VIN2, VIN2 will officially switch to the output power supply INTVIN.

[0048] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A low-voltage dual-input power switching circuit, used to detect the magnitude of two input power supplies, and automatically switch the larger of the two input power supplies as the output voltage according to the priority order of the input power supplies; when the main power supply and the backup power supply voltage are the same, the main power supply provides power, characterized in that... The low-voltage dual-input power switching circuit includes a MOSFET peak current source circuit 1, a MOSFET peak current source circuit 2, a power input detection circuit, a logic control circuit, and a power switching module. The peak current source circuit 1 of the MOSFET will superimpose the current I1 generated under the main power supply VIN1 and the current I2 generated under the backup power supply VIN2 in the peak current source circuit 2 of the MOSFET will be mirrored to the power input detection circuit through the current mirror structure. The peak current source circuit 2 of the MOSFET will mirror the current I2 generated under the backup power supply VIN2 to the peak current source circuit 1 of the MOSFET through the current mirror structure. The power input detection circuit is used to compare the magnitudes of the main power supply VIN1 and the backup power supply VIN2, convert the comparison result into a digital control signal and output it; specifically, the power input detection circuit includes the fourth N-type MOSFET MN4, the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the seventh N-type MOSFET MN7, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, the tenth N-type MOSFET MN10, the eleventh N-type MOSFET MN11, the third P-type MOSFET MP3, the fourth P-type MOSFET MP4, the fifth P-type MOSFET MP5, the sixth P-type MOSFET MP6, the seventh P-type MOSFET MP7, the eighth P-type MOSFET MP8, the ninth P-type MOSFET MP9, the twelfth P-type MOSFET MP12, and the thirteenth P-type MOSFET MP13; The gate of the fourth N-type MOSFET MN4 is connected to the drain of the third N-type MOSFET MN3, its source is connected to the common ground VSS, and its drain is connected to the gate and drain of the third P-type MOSFET MP3; the gate of the fifth N-type MOSFET MN5 is connected to the gate of the fourth N-type MOSFET MN4, its source is connected to the common ground VSS, and its drain is connected to the gate and drain of the fifth P-type MOSFET MP5; the gate and drain of the sixth N-type MOSFET MN6 are connected to the drain of the sixth P-type MOSFET MP6, and its source is connected to the common ground VSS; the gate of the seventh N-type MOSFET MN7 is connected to the gate of the sixth N-type MOSFET MN6, its source is connected to the common ground VSS, and its drain is connected to the drain of the thirteenth P-type MOSFET MP13; The gate of the eighth N-type MOSFET MN8 is connected to the gate of the seventh N-type MOSFET MN7, its source is connected to the common ground VSS, and its drain is connected to the drain of the seventh P-type MOSFET MP7; the gate and drain of the ninth N-type MOSFET MN9 are connected to the drain of the eighth P-type MOSFET MP8, and its source is connected to the common ground VSS; the gate of the tenth N-type MOSFET MN10 is connected to the gate of the ninth N-type MOSFET MN9, its source is connected to the common ground VSS, and its drain is connected to the drain of the thirteenth P-type MOSFET MP13; the gate of the eleventh N-type MOSFET MN11 is connected to the gate of the tenth N-type MOSFET MN10, its source is connected to the common ground VSS, and its drain is connected to the drain of the ninth P-type MOSFET MP9. The logic control circuit is used to perform logic preprocessing on the digital output control signal generated by the power input detection circuit, and the processed output signal controls the working state of the power switching module. The power switching module is used to switch between the main power supply VIN1 and the backup power supply VIN2, and switch the larger one to the output voltage INTVIN.

2. The low-voltage dual-input power switching circuit according to claim 1, characterized in that, The MOS transistor peak current source circuit 1 includes a first current source I1, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a first resistor R1, a second resistor R2, a first P-type MOS transistor MP1, and a second P-type MOS transistor MP2; The positive terminal of the first current source I1 is connected to the main power supply VIN1, and the negative terminal is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the drain of the first N-type MOSFET MN1; the gate of the first N-type MOSFET MN1 is connected to the negative terminal of the first current source I1, and the source is connected to the common ground VSS; the gate of the second N-type MOSFET MN2 is connected to the drain of the first N-type MOSFET MN1, the source is connected to the common ground VSS, and the drain is connected to the gate and drain of the first P-type MOSFET MP1; the source of the first P-type MOSFET MP1 is connected to the main power supply VIN1; the source of the second P-type MOSFET MP2 is connected to the main power supply VIN1, the gate is connected to the gate of the first P-type MOSFET MP1, and the drain is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to the drain of the third N-type MOSFET MN3; the gate of the third N-type MOSFET MN3 is connected to the drain of the second P-type MOSFET MP2, and the source is connected to the common ground VSS.

3. The low-voltage dual-input power switching circuit according to claim 1, characterized in that, The MOS transistor peak current source circuit 2 includes a second current source I2, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a third resistor R3, a tenth P-type MOS transistor MP10, and an eleventh P-type MOS transistor MP11; The positive terminal of the second current source I2 is connected to the backup power supply VIN2, and the negative terminal is connected to one end of the third resistor R3; the other end of the third resistor R3 is connected to the drain of the twelfth N-type MOSFET MN12; the gate of the twelfth N-type MOSFET MN12 is connected to the negative terminal of the second current source I2, and the source is connected to the common ground VSS; the gate of the thirteenth N-type MOSFET MN13 is connected to the drain of the twelfth N-type MOSFET MN12, the source is connected to the common ground VSS, and the drain is connected to the gate and drain of the tenth P-type MOSFET MP10; the source of the tenth P-type MOSFET MP10 is connected to the backup power supply VIN2; the source of the eleventh P-type MOSFET MP11 is connected to the backup power supply VIN2, the gate is connected to the gate of the tenth P-type MOSFET MP10, and the drain is connected to the MOSFET peak current source circuit 1.

4. The low-voltage dual-input power switching circuit according to claim 1, characterized in that: The gate-drain terminal of the third P-type MOSFET MP3 is connected to the gate-drain terminal of the twelfth P-type MOSFET MP12, and its source terminal is connected to the main power supply VIN1. The gate terminal of the fourth P-type MOSFET MP4 is connected to the gate of the third P-type MOSFET MP3, its source terminal is connected to the main power supply VIN1, and its drain terminal is connected to the drain terminal of the sixth N-type MOSFET MN6. The gate-drain terminals of the fifth P-type MOSFET MP5 are both connected to the drain terminals of the fifth N-type MOSFET MN5, and its source terminal is connected to the output voltage INTVCC. The gate terminal of the sixth P-type MOSFET MP6 is connected to the gate of the fifth P-type MOSFET MP5, and its source terminal is connected to the output voltage IN. The TVCC connection is established, with its drain terminal connected to the drain terminal of the sixth N-type MOSFET MN6; the gate terminal of the seventh P-type MOSFET MP7 is connected to the gate of the sixth P-type MOSFET MP6, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the logic control circuit; the gate terminal of the eighth P-type MOSFET MP8 is connected to the gate of the seventh P-type MOSFET MP7, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the drain terminal of the ninth N-type MOSFET MN9; the gate terminal of the ninth P-type MOSFET MP9 is connected to the gate of the eighth P-type MOSFET MP8, its source terminal is connected to the output voltage INTVCC, and its drain terminal is connected to the logic control circuit. The gate and drain terminals of the twelfth P-type MOSFET MP12 are both connected to the drain terminal of the third P-type MOSFET MP3, and the source terminal is connected to the backup power supply VIN2; the gate terminal of the thirteenth P-type MOSFET MP13 is connected to the gate of the twelfth P-type MOSFET MP12, the source terminal is connected to the backup power supply VIN2, and the drain terminal is connected to the drain terminal of the tenth N-type MOSFET MN10.

5. The low-voltage dual-input power switching circuit according to claim 1, characterized in that, The logic control circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first two-input NOR gate NOR1; The input terminal of the first inverter INV1 is connected to the drain terminal of the seventh P-type MOSFET MP7 in the power input detection circuit, and its output terminal is connected to the input terminal of the second inverter INV2. Its power supply is connected to the main power supply VIN1. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and its output terminal Y1 is connected to the power switching module. Its power supply is connected to the output voltage INTVIN. The first input terminal of the first two-input NOR gate NOR1 is connected to the output terminal of the second inverter INV2, and its second input terminal is connected to the drain terminal of the ninth P-type MOSFET MP9 in the power input detection circuit. Its output terminal is connected to the input terminal of the third inverter INV3, and its power supply is connected to the backup power supply VIN2. The input terminal of the third inverter INV3 is connected to the output terminal of the first two-input NOR gate NOR1. Its power supply is connected to the output voltage INTVIN, and its output terminal Y2 is connected to the power switching module.

6. The low-voltage dual-input power switching circuit according to claim 1, characterized in that, The power switching module includes a first P-type MOS switch SW1, a second P-type MOS switch SW2, and a first capacitor C1; The drain of the first P-type MOS switch SW1 is connected to the main power supply VIN1, the gate is connected to the first output Y1 of the logic control circuit, and the source is connected to the output voltage INTVIN; the drain of the second P-type MOS switch SW2 is connected to the backup power supply VIN2, the gate is connected to the second output Y2 of the logic control circuit, and the source is connected to the source of the first P-type MOS switch SW1; the positive terminal of the first capacitor C1 is connected to the source of the first P-type MOS switch SW1, and the negative terminal is connected to the common ground VSS.

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