Control Circuit with Power Saving Mode for Power Supply Circuit

Abstract

A control circuit with a power-saving mode for a power supply circuit. The control circuit is used to control a power supply circuit to supply power to a system device having a communication circuit. The control circuit includes: a pulse width modulation controller for switching a transformer of the power supply circuit to generate a first output voltage; a switched capacitor converter for converting the first output voltage to generate a second output voltage; wherein the second output voltage is used to supply power to the communication circuit, and the communication circuit generates a power-saving signal to control the pulse width modulation controller and the switched capacitor converter. When the power-saving signal is enabled, the first output voltage decreases and the duty cycle of the switched capacitor converter increases.

Description

Technical Field

[0001] The present invention relates to a control circuit for a power supply circuit, and particularly to a control circuit having a power saving mode, and the power supply circuit controlled thereby is used to supply power to a system device having a communication circuit. Background Art

[0002] Figure 1 A prior art power supply circuit is shown. The power supply circuit 1000 is used to generate an output voltage Vo to supply power to a system device. In an operation mode, when the main device in the system device operates, the output voltage Vo is relatively high. In a power saving mode, only a communication circuit in the system device still needs to operate, so the output voltage Vo can be reduced. However, since the variation range of the output voltage Vo may be very large (for example, 3V to 48V), it is difficult to design the low dropout regulator 40 that actually supplies power to the communication circuit, and the power conversion efficiency is not good.

[0003] In view of this, the present invention aims at the above deficiencies of the prior art and provides a novel power supply circuit, a control circuit and a hybrid power conversion circuit therein, which can reduce costs and circuit size at the same time. Summary of the Invention

[0004] In one aspect, the present invention provides a control circuit for controlling a power supply circuit to supply power to a system device having a communication circuit. The control circuit includes: a pulse width modulation (PWM) controller for switching a transformer of the power supply circuit to generate a first output voltage; and a switched capacitor converter for converting the first output voltage to generate a second output voltage; wherein the second output voltage is used to supply power to the communication circuit, and the communication circuit generates a power saving signal to control the PWM controller and the switched capacitor converter. When the power saving signal is enabled, the first output voltage is reduced, and the duty cycle of the switched capacitor converter is increased.

[0005] In one embodiment, the control circuit further includes an output voltage controller for generating a first control signal and a second control signal. The first control signal is used to adjust the first output voltage, and the second control signal is used to control the second output voltage.

[0006] In one embodiment, the switched capacitor converter is a buck converter having a duty cycle lower than 50%.

[0007] In one embodiment, when the power saving signal is enabled, the switching frequency of the switched capacitor converter is reduced.

[0008] In one embodiment, the level of the first output voltage is higher than the level of the second output voltage.

[0009] In one embodiment, when the power saving signal is enabled, the level of the first output voltage is twice the level of the second output voltage.

[0010] In one embodiment, when the output load of the power supply circuit decreases, the switching frequency of the PWM controller decreases.

[0011] In one embodiment, the switched-capacitor converter operates in discontinuous conduction mode.

[0012] In one embodiment, the control circuit further includes a synchronous rectifier for generating the first output voltage.

[0013] In one embodiment, when the power saving signal is enabled, the duty cycle of the switched-capacitor converter is close to 50%.

[0014] In one embodiment, the control circuit further includes a low dropout regulator for converting the second output voltage to generate a regulated power supply for powering the communication circuit.

[0015] In one embodiment, the output voltage controller includes a first error amplifier and a second error amplifier. The first error amplifier is coupled to the first output voltage for generating the first control signal, and the second error amplifier is coupled to the second output voltage for generating the second control signal.

[0016] In one embodiment, when the power saving signal is enabled, the second error amplifier is open.

[0017] In one embodiment, the first control signal is coupled to the PWM controller through an optocoupler.

[0018] In one embodiment, the switched-capacitor converter includes: an inductor, a plurality of capacitors, and a plurality of switches coupled to each other; wherein when the power saving signal is disabled, the plurality of switches are used to switch the inductor, the plurality of capacitors, and the plurality of switches to make the switched-capacitor converter operate in a buck switching mode; and wherein when the power saving signal is enabled, the plurality of switches are used to switch the inductor, the plurality of capacitors, and the plurality of switches to make the switched-capacitor converter operate in a capacitive power conversion mode.

[0019] In one embodiment, the plurality of capacitors includes a first capacitor and a second capacitor, and the plurality of switches includes an upper-bridge switch, a second upper-bridge switch, a first lower-bridge switch, and a second lower-bridge switch; wherein the first upper-bridge switch and the second upper-bridge switch are serially connected between the first output voltage and a switching node in sequence, wherein the first upper-bridge switch and the second upper-bridge switch are coupled to each other at an upper-bridge intermediate node, the first lower-bridge switch and the second lower-bridge switch are serially connected between the ground potential and the switching node in sequence, wherein the first lower-bridge switch and the second lower-bridge switch are coupled to each other at a lower-bridge intermediate node, the inductor is coupled between the switching node and the second output voltage, the first capacitor is coupled between the upper-bridge intermediate node and the lower-bridge intermediate node, and the second capacitor is coupled to the second output voltage.

[0020] In one embodiment, the first upper-bridge switch and the second lower-bridge switch are switched according to a first switching signal based on a switching period and a duty cycle, wherein the second upper-bridge switch and the first lower-bridge switch are switched according to a second switching signal based on the switching period and the duty cycle; wherein when the power-saving signal is disabled, the duty cycle is less than 50%; wherein when the power-saving signal is enabled, the duty cycle is substantially equal to 50%.

[0021] In one embodiment, the plurality of switches further includes a bypass switch connected in parallel with the inductor, wherein when the power-saving signal is disabled, the bypass switch is not conducting, and wherein when the power-saving signal is enabled, the bypass switch is conducting.

[0022] In one embodiment, the plurality of switches further includes an upper-bridge auxiliary switch and a lower-bridge auxiliary switch, wherein the upper-bridge auxiliary switch is coupled between the second output voltage and the upper-bridge intermediate node, and the lower-bridge auxiliary switch is coupled between the second output voltage and the lower-bridge intermediate node; wherein when the power-saving signal is disabled, the upper-bridge auxiliary switch and the lower-bridge auxiliary switch are not conducting; wherein when the power-saving signal is enabled, the second upper-bridge switch and the second lower-bridge switch are not conducting.

[0023] In one embodiment, when the power-saving signal is disabled, the first upper-bridge switch and the second lower-bridge switch are switched according to a first switching signal based on a switching period and a duty cycle, wherein the second upper-bridge switch and the first lower-bridge switch are switched according to a second switching signal based on the switching period and the duty cycle, and wherein the duty cycle is less than 50%; wherein when the power-saving signal is enabled, the first upper-bridge switch and the lower-bridge auxiliary switch are switched according to the first switching signal based on the switching period and the duty cycle, and the upper-bridge auxiliary switch and the first lower-bridge switch are switched according to the second switching signal based on the switching period and the duty cycle, and wherein the duty cycle is substantially equal to 50%.

[0024] In one embodiment, when the power saving signal is disabled, the first upper bridge switch, the second upper bridge switch, the first lower bridge switch, and the second lower bridge switch switch the inductor and the plurality of capacitors based on a switching period to perform power conversion with 3-order PWM; wherein when the power saving signal is enabled, the first upper bridge switch, the upper bridge auxiliary switch, the first lower bridge switch, and the lower bridge auxiliary switch switch the inductor and the plurality of capacitors based on the switching period to perform capacitive power conversion.

[0025] The following will be described in detail through specific embodiments, and it will be easier to understand the purpose, technical content, features, and achieved effects of the present invention. Brief Description of the Drawings

[0026] Figure 1 shows a power supply circuit of the prior art.

[0027] Figure 2 is a circuit schematic diagram showing a control circuit for controlling a power supply circuit according to an embodiment of the present invention.

[0028] Figure 3 is a circuit schematic diagram showing a control circuit for controlling a power supply circuit according to another embodiment of the present invention.

[0029] Figure 4 is a switching frequency characteristic curve diagram showing a control circuit for controlling a power supply circuit according to an embodiment of the present invention.

[0030] Figure 5 is a circuit schematic diagram showing a switching capacitive converter according to an embodiment of the present invention.

[0031] Figure 6A , Figure 6B is corresponding to Figure 2 , Figure 5 the operation waveform schematic diagram of the embodiment.

[0032] Figure 7 is a circuit schematic diagram showing a controller for controlling a switching capacitive converter according to an embodiment of the present invention.

[0033] Figure 8 is an operation waveform diagram showing a signal generator according to an embodiment of the present invention.

[0034] Figure 9 is a circuit schematic diagram showing a switching capacitive converter according to an embodiment of the present invention.

[0035] Figure 10 is a circuit schematic diagram showing a switching capacitive converter according to an embodiment of the present invention.

[0036] Figure 11 It is a circuit schematic diagram showing a control circuit for controlling a power supply circuit according to an embodiment of the present invention.

[0037] Symbol Explanation in the Figure

[0038] 10: Transformer

[0039] 100: Output Voltage Controller

[0040] 1000: Power Supply Circuit

[0041] 110: First Error Amplifier

[0042] 111, 112: Resistors

[0043] 116: Capacitor

[0044] 117, 118: Switches

[0045] 119: Inverter

[0046] 120: Second Error Amplifier

[0047] 130: Comparator

[0048] 135: Current Source

[0049] 136: Resistor

[0050] 20: Transistor

[0051] 200, 205, 209, 2010: Switched Capacitor Converter

[0052] 210: Time Delay Circuit

[0053] 215: Oscillator

[0054] 220: Signal Generator

[0055] 230: Flip - Flop

[0056] 235: Comparator

[0057] 25: Transistor

[0058] 250: OR Gate

[0059] 260, 270: AND Gates

[0060] 30, 45: Capacitors

[0061] 40: Low Drop - Out Regulator

[0062] 50, 55: PWM Controllers

[0063] 500, 500’: Control Circuit

[0064] 60: System device

[0065] 61: Communication circuit

[0066] 90: Opto-coupler

[0067] C2: Capacitor

[0068] CFY: Capacitor

[0069] D: Duty cycle

[0070] G1~G6: Control signal

[0071] fpwm: Switching frequency

[0072] iL: Switching current

[0073] L: Inductor

[0074] LX: Switching node

[0075] NU, NL: Node

[0076] Q1~Q6: Switch

[0077] Qb, QU, QL: Switch

[0078] S1: First control signal

[0079] S2: Second control signal

[0080] S3: Third control signal

[0081] SA: Duty cycle adjustment signal

[0082] SB: Frequency division signal

[0083] SDT: Dead time signal

[0084] Sosc: Oscillation signal

[0085] SP: Power saving signal

[0086] SPD: Delayed power saving signal

[0087] TDT: Dead time

[0088] Ts: Switching period

[0089] t0~t4: Time point

[0090] P1, P2: Switching signal

[0091] RMP: Ramp signal

[0092] VCC: Regulated power supply

[0093] VD’: Offset signal

[0094] Vo: Output voltage

[0095] VO1: First output voltage

[0096] VO2: Second output voltage

[0097] VRA, VRB: Reference voltage

[0098] VS1: Voltage level

[0099] Vsw: Switching node voltage

[0100] VT1: Threshold value Detailed implementation manners

[0101] The drawings in the invention are only schematic, mainly intended to show the coupling relationship between each circuit and the relationship between each signal waveform. As for the circuit, signal waveform and frequency, they are not drawn according to the proportion.

[0102] Figure 2A preferred embodiment of a control circuit for controlling a power supply circuit according to the present invention (power supply circuit 1002 and control circuit 500). The control circuit 500 includes a pulse width modulation (PWM) controller 50 and a switching capacitor converter (SCC) 200. The PWM controller 50 is configured to control the transistor 20 in a pulse width modulation manner according to a first control signal S1 to switch the transformer 10 of the power supply circuit to convert the input voltage Vin to generate a first output voltage VO1. The first output voltage VO1 is, for example, used to supply power to a household appliance (system device 60). Specifically, the first output voltage VO1 is, for example, a power source for driving a motor in the system device and / or for controlling a main device (62) such as a relay. The switching capacitor converter 200 is configured to convert the first output voltage VO1 according to a second control signal S2 to generate a second output voltage VO2. In one embodiment, the level of the first output voltage VO1 is higher than the level of the second output voltage VO2. The output voltage controller 100 is configured to generate the first control signal S1 and the second control signal S2, which are respectively used to regulate the first output voltage VO1 and control the switching capacitor converter 200. In one embodiment, the control circuit 500 further includes a low dropout regulator 40, and the low dropout regulator 40 further converts the second output voltage VO2 to provide a regulated power source VCC to the communication circuit 61 in the system device 60. The communication circuit 61 generates a power saving signal SP through its general purpose input / output interface (GPIO) or through an interface such as UART (universal asynchronous receiver / transmitter) or I 2 C (inter-integrated circuit). The power saving signal SP is coupled to the output voltage controller 100 to save power. In one embodiment, when the power saving signal SP for saving power is enabled, the level of the first output voltage VO1 can be reduced.

[0103] Capacitors 30 and 45 are output filters for the first output voltage VO1 and the regulated power source VCC, respectively.

[0104] Please also refer to Figure 3 , Figure 3This is a preferred embodiment of the output voltage controller 100. Through resistors 111 and 112, the first error amplifier 110 is connected to the first output voltage VO1, thereby generating a first control signal S1 according to the first output voltage VO1. The reference voltage VRA or VRB of the first error amplifier 110 can be selected by the power-saving signal SP. Therefore, the level of the first output voltage VO1 can be set by the power-saving signal SP. The second error amplifier 120 receives the second output voltage VO2 to generate a second control signal S2. In one embodiment, the comparator 130 is used to compare a reference signal (such as the ground potential) with the offset signal VD’ to generate a third control signal S3 for controlling the transistor 25. The transistor 25 serves as a synchronous rectifier (SR) to generate the first output voltage VO1 with higher efficiency.

[0105] Continuing to refer to Figure 3 , the resistor 115 and the capacitor 116 form a compensation network for the first error amplifier 110. The inverter 119 and the switches 117, 118 are configured to select the reference voltage VRA or VRB according to the power-saving signal SP. The resistor 125 and the capacitor 126 form a compensation network for the second error amplifier 120. The current source 135 and the resistor 136 are used to offset the drain voltage VD of the transistor 25 to generate the offset signal VD’.

[0106] Figure 4 is a graph showing the relationship between the switching frequency fpwm of the PWM controller 50 and the level of the first control signal S1. When the voltage level VS1 of the first control signal S1 is lower than the threshold value VT1, the switching frequency decreases as the voltage level VS1 decreases. As described above, the first control signal S1 is a signal generated by the feedback of the first output voltage VO1. When the output load of the power supply circuit decreases, the level of the first control signal S1 also decreases. It should be noted that the “decrease in the output load” of the power supply circuit means, for example, a decrease in the power consumption or current consumption of the system device 60.

[0107] Figure 5 This is a preferred embodiment of the switched-capacitor converter according to the present invention (switched-capacitor converter 205). Figure 6A and Figure 6B is a schematic diagram showing a preferred waveform of the switched-capacitor converter 200 according to the present invention. As Figure 5As shown, in this embodiment, the switched-capacitor converter 205 includes a first high-side switch Q1 and a second high-side switch Q2, which are serially connected in sequence between the first output voltage VO1 and the switching node LX. The first high-side switch Q1 and the second high-side switch Q2 are coupled to each other at the high-side intermediate node NU. The plurality of low-side switches include a first low-side switch Q4 and a second low-side switch Q3, which are serially connected in sequence between the ground potential and the switching node LX. The first low-side switch Q4 and the second low-side switch Q3 are coupled to each other at the low-side intermediate node NL. In this embodiment, the inductor L is coupled between the switching node LX and the second output voltage VO2, and the capacitor CFY is coupled between the high-side intermediate node NU and the low-side intermediate node NL. The above-mentioned first high-side switch Q1, second high-side switch Q2, first low-side switch Q4, and second low-side switch Q3 are respectively controlled by corresponding control signals G1~G2, G4~G3. The capacitor C2 is coupled to the second output voltage VO2.

[0108] In one aspect, the switched-capacitor converter 205 is a buck converter that includes a flying capacitor (i.e., CFY). Referring also to Figure 6A and Figure 6B , in one embodiment, the switched-capacitor converter 205 operates in the discontinuous conduction mode (DCM), and its maximum duty cycle is close to but lower than 50%. It should be noted that its maximum duty cycle can substantially be 50%, but considering the dead time reserved to avoid short circuits between switches, its maximum duty cycle is close to but lower than 50%. In one embodiment, optionally, the capacitance value of the capacitor CFY can be made equal to the capacitance value of the capacitor C2.

[0109] Referring to Figure 6A , in this embodiment, when the aforementioned power-saving signal SP is prohibited, the switched-capacitor converter 205 operates in the buck switching mode. Specifically, during the first period (t0~t1) of the switching period Ts, the switches Q1 and Q3 are controlled by the switching signal P1 to conduct, and the first output voltage VO1 charges the capacitors CFY and C2 through the inductor L. The capacitors CFY and C2 are connected in series with each other. During the second period (t2~t3) of the switching period Ts, the switches Q2 and Q4 are controlled by the switching signal P2 to conduct, and the voltage of the capacitor CFY charges the capacitor C2 through the inductor L. The capacitors CFY and C2 are connected in parallel with each other through the inductor L.

[0110] The switching period Ts is the switching period of the switched-capacitor converter 200. The duty cycle D is the duty cycle of the switching signals P1 and P2 of the switched-capacitor converter 200 relative to the switching period Ts. Io2 is the output current of the second output voltage VO2.Figure 6A Waveforms of the switched-capacitor converter 205 in the buck switching mode, where the second control signal S2 adjusts the second output voltage VO2 by controlling the duty cycle D of the switching signals P1 and P2. As Figure 6A shown, when the duty cycle D is less than 50%, outside the duty cycle, for example, during t1 - t2 or t3 - t4, switches Q1 - Q4 are all non-conducting. Since the inductor current is still a positive current, the switching node voltage Vsw drops to near 0V due to the conduction of the parasitic diodes of switches Q3 and Q4. From one perspective, in the buck switching mode of this embodiment, the switched-capacitor converter 205 makes one end of the inductor L switch between 0.5*VO1 and the ground potential through the aforementioned switch switching, and adjusts the duty cycle D according to the feedback control, thereby adjusting the required second output voltage VO2 to a preset level.

[0111] In another embodiment, optionally, as Figure 6A during t1 - t2 or t3 - t4 of

[0112] Figure 6B shown, switches Q3 and Q4 can be controlled to conduct to reduce the on-resistance and improve the power conversion efficiency. Figure 6B shown, the ripple current of the switching current iL (i.e., the inductor current) of the inductor L will be significantly reduced. Therefore, the power loss of the switched-capacitor converter 205 will be reduced.

[0113] In addition, in one embodiment, when the power-saving signal SP is enabled, the switching period Ts of the switched-capacitor converter 205 will increase, that is, the switching frequency of the switched-capacitor converter 205 will decrease to reduce the switching loss.

[0114] Figure 7A preferred embodiment of a controller for controlling a switched-capacitor converter 205 according to the present invention. In this embodiment, an oscillator 215 generates an oscillation signal Sosc, which determines the switching frequency fpwm of the switched-capacitor converter 200. A time-delay circuit 210 provides a time delay for a power-saving signal SP and generates a delayed power-saving signal SPD. When the delayed power-saving signal SPD is enabled, the frequency of the oscillation signal Sosc is reduced. The oscillation signal Sosc is coupled to a signal generator 220 for generating a ramp signal RMP, a dead-time signal SDT, and a frequency-divided signal SB. Specifically, the frequency of the frequency-divided signal SB is 1 / 2 of the oscillation signal Sosc.

[0115] Please also refer to Figure 8 , Figure 8 which shows the waveforms of the signal generator 220. The rising edge of the oscillation signal Sosc generates a dead-time signal SDT, which is a negative pulse in this embodiment. The rising edge of the dead-time signal SDT changes the state of the frequency-divided signal SB. The dead-time signal SDT is further used to generate a ramp signal RMP. The rising edge of the dead-time signal SDT triggers the set state of a flip-flop 230. The sum of the inductor current signal ViL and the ramp signal RMP is coupled to the input of a comparator 235 for comparison with a second control signal S2, and a reset signal is generated at the output of the comparator 235 for the flip-flop 230. The output of the comparator 235 is connected to the flip-flop 230 to reset the flip-flop 230. An OR gate 250 generates a duty-cycle adjustment signal SA according to the output of the flip-flop 230 and the delayed power-saving signal SPD. When the switched-capacitor converter 200 operates in a buck switching mode (i.e., when the aforementioned power-saving signal SP is disabled), the duty-cycle adjustment signal SA adjusts the duty cycle D of the switching signals P1 and P2 according to the second control signal S2. When the power-saving signal SP is enabled, the duty-cycle adjustment signal SA will be set to a high level, and the second error amplifier 120 and the second control signal S2 are thus open in the feedback control of the second output voltage VO2. The duty-cycle adjustment signal SA, the frequency-divided signal SB, and the dead-time signal SDT are connected to an AND gate 260 for generating a signal P1. The frequency-divided signal SB is further coupled to an AND gate 270 through an inverter 265, and the frequency-divided signal SB and the dead-time signal SDT are also connected to the AND gate 270 for generating a signal P2. Thus, when the power-saving signal SP is enabled, the duty cycles of the signal P1 and the signal P2 are determined according to the frequency-divided signal SB, i.e., 50%. The dead-time signal SDT provides a dead time TDT between the switching signals P1 and P2.

[0116] Figure 9 is a circuit schematic diagram showing a switched-capacitor converter according to an embodiment of the present invention. The switched-capacitor converter 209 of this embodiment is the same as Figure 5The embodiment is similar, with the difference that the switched-capacitor converter 209 further includes a bypass switch Qb. When the power-saving signal SP is enabled, the bypass switch Qb is controlled to conduct, so as to avoid oscillations that may be caused, for example, by instantaneous changes in the load.

[0117] Figure 10 FIG. 4 is a circuit schematic diagram showing a switched-capacitor converter (switched-capacitor converter 2010) according to an embodiment of the present invention. The switched-capacitor converter 2010 is similar to Figure 5 the embodiment, with the difference that the switched-capacitor converter 2010 further includes an upper-bridge auxiliary switch Q5 and a lower-bridge auxiliary switch Q6. In this embodiment, the upper-bridge auxiliary switch Q5 is coupled between the second output voltage VO2 and the upper-bridge intermediate node NU, the lower-bridge auxiliary switch Q6 is coupled between the second output voltage VO2 and the lower-bridge intermediate node NL, and the capacitor CF is coupled between the upper-bridge intermediate node NU and the lower-bridge intermediate node NL. The above-mentioned upper-bridge auxiliary switch Q5 and lower-bridge auxiliary switch Q6 are respectively controlled by corresponding control signals G5 and G6.

[0118] In an embodiment, the control signal G5 is the logical AND result of the power-saving signal SP and the switching signal P2, and the control signal G6 is the logical AND result of the power-saving signal SP and the switching signal P1. On the other hand, the control signal G2 is the logical AND result of the inverse of the power-saving signal SP and the switching signal P2, and the control signal G3 is the logical AND result of the inverse of the power-saving signal SP and the switching signal P1. Referring also to Figure 6A and Figure 6B , in this embodiment, when the power-saving signal SP is enabled, the second upper-bridge switch Q2 and the second lower-bridge switch Q3 are non-conductive, and the upper-bridge auxiliary switch Q5 switches according to the switching signal P2 as shown in Figure 6B , and the lower-bridge auxiliary switch Q6 switches according to the switching signal P1 as shown in Figure 6B . On the other hand, when the power-saving signal SP is disabled, the upper-bridge auxiliary switch Q5 and the lower-bridge auxiliary switch Q6 are non-conductive, and the second upper-bridge switch Q2 switches according to the switching signal P2 as shown in Figure 6A , and the second lower-bridge switch Q3 switches according to the switching signal P1 as shown in Figure 6A . Thus, in addition to avoiding oscillations that may be caused by instantaneous changes in the load, the power conversion efficiency during heavy loads can be further improved.

[0119] In one embodiment, when the switched-capacitor converters (205, 209, 2010) operate in the buck switching mode (the power-saving signal SP is disabled), optionally, 3-level PWM switching can be performed. Specifically, in this embodiment, the switched-capacitor converter repeats switching in one switching period. In the first period of the switching cycle, the first high-side switch Q1 and the second low-side switch Q3 are turned on, the second high-side switch Q2 and the first low-side switch Q4 are turned off. And in the second period of the switching cycle, the first low-side switch Q4 and the second low-side switch Q3 are turned on, the first high-side switch Q1 and the second high-side switch Q2 are turned off. And in the third period of the switching cycle, the second high-side switch Q2 and the first low-side switch Q4 are turned on, the first high-side switch Q1 and the second low-side switch Q3 are turned off. And in the fourth period of the switching cycle, the first high-side switch Q1 and the second high-side switch Q2 are turned on, the first low-side switch Q4 and the second low-side switch Q3 are turned off. Thus, the voltage of the switching node LX is periodically switched among three different voltage levels, namely the first output voltage VO1, the ground potential, and 0.5*VO1, so as to achieve 3-level PWM power conversion.

[0120] On the other hand, in this embodiment, when the power-saving signal SP is enabled, the second high-side switch Q2 and the second low-side switch Q3 are turned off, while the first high-side switch Q1 and the low-side auxiliary switch Q6 are switched according to the switching signal P1 as shown in Figure 6B shown, the first low-side switch Q4 and the high-side auxiliary switch Q5 are switched according to the switching signal P2 as shown in Figure 6B shown, thereby performing capacitive power conversion.

[0121] In one aspect, Figure 9 In the embodiment of Figure 10 when the power-saving signal SP is enabled, the switched-capacitor converters 209, 2010 only perform capacitive power conversion in the form of capacitor charging and discharging with the capacitor CFY and the capacitor C2.

[0122] Figure 11 Another preferred embodiment of the control circuit for controlling the power supply circuit according to the present invention. This embodiment is similar to the embodiment of Figure 2 In this embodiment of the control circuit 500', the first control signal S1 is coupled to the PWM controller 55 through the optocoupler 90. The primary circuit and the secondary circuit of the power supply circuit are electrically isolated.

[0123] As described above, the present invention provides a control circuit for controlling a power supply circuit. By controlling the duty cycle of the switch in the switched-capacitor converter, the switched-capacitor converter can operate in a buck switching mode (i.e., when the aforementioned power-saving signal SP is disabled) or a capacitive switching mode (i.e., when the aforementioned power-saving signal SP is enabled). In the buck switching mode, the switched-capacitor converter can adjust the charging and discharging of the inductor current according to the duty cycle, thereby regulating the second output voltage VO2. On the other hand, when the power-saving signal SP is enabled, the switched-capacitor converter can be operated in the capacitive switching mode, thereby reducing the ripple current of the inductor L and improving the power conversion efficiency.

[0124] The present invention has been described above with reference to the preferred embodiments. However, the above description is only for the convenience of those skilled in the art to understand the content of the present invention, and is not used to limit the broadest scope of the present invention. The described embodiments are not limited to being applied alone, and can also be combined. For example, two or more embodiments can be combined, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, in the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention's so-called "processing or calculating or generating a certain output result according to a certain signal" is not limited to the signal itself, but also includes, when necessary, converting the signal between voltage and current, current and voltage, and / or ratio conversion, etc., and then processing or calculating according to the converted signal to generate a certain output result. It can be seen that in the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combination methods, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A control circuit for controlling a power supply circuit to supply power to a system device having a communication circuit, the control circuit comprising: A pulse width modulation controller for switching a transformer of the power supply circuit to generate a first output voltage; and A switched capacitor converter for converting the first output voltage to generate a second output voltage; Among them, The second output voltage is used to supply power to the communication circuit, and the communication circuit generates a power saving signal to control the pulse width modulation controller and the switched capacitor converter. Wherein, when the power saving signal is enabled, the first output voltage decreases, and the duty cycle of the switched capacitor converter increases.

2. The control circuit according to claim 1, wherein, It further comprises an output voltage controller for generating a first control signal and a second control signal, the first control signal being used to adjust the first output voltage, and the second control signal being used to control the second output voltage.

3. The control circuit according to claim 1, wherein The switched capacitor converter is a buck converter with a duty cycle lower than 50%.

4. The control circuit according to claim 1, wherein When the power saving signal is enabled, the switching frequency of the switched capacitor converter decreases.

5. The control circuit according to claim 1, wherein, The level of the first output voltage is higher than the level of the second output voltage.

6. The control circuit according to claim 1, wherein, When the power saving signal is enabled, the level of the first output voltage is twice the level of the second output voltage.

7. The control circuit according to claim 1, wherein, When the output load of the power supply circuit decreases, the switching frequency of the pulse width modulation controller decreases.

8. The control circuit according to claim 1, wherein, The switched capacitor converter operates in discontinuous conduction mode.

9. The control circuit according to claim 1, wherein It further comprises a synchronous rectifier for generating the first output voltage.

10. The control circuit according to claim 1, wherein, When the power saving signal is enabled, the duty cycle of the switched capacitor converter approaches 50%.

11. The control circuit according to claim 1, wherein, It further comprises a low dropout regulator for converting the second output voltage to generate a regulated power supply for supplying power to the communication circuit.

12. The control circuit according to claim 2, wherein, The output voltage controller comprises a first error amplifier and a second error amplifier. The first error amplifier is coupled to the first output voltage to generate the first control signal, and the second error amplifier is coupled to the second output voltage to generate the second control signal.

13. The control circuit according to claim 12, wherein, When the power saving signal is enabled, the second error amplifier is open.

14. The control circuit according to claim 2, wherein, The first control signal is coupled to the pulse width modulation controller through an optocoupler.

15. The control circuit according to claim 3, wherein, The switched capacitor converter includes: An inductor, a plurality of capacitors, and a plurality of switches coupled to each other; Wherein, when the power saving signal is disabled, the plurality of switches are used to switch the inductor, the plurality of capacitors, and the plurality of switches to make the switched capacitor converter operate in a buck switching mode; Wherein, when the power saving signal is enabled, the plurality of switches are used to switch the inductor, the plurality of capacitors, and the plurality of switches to make the switched capacitor converter operate in a capacitive power conversion mode.

16. The control circuit according to claim 15, wherein, The plurality of capacitors include a first capacitor and a second capacitor, and the plurality of switches include a first upper bridge switch, a second upper bridge switch, a first lower bridge switch, and a second lower bridge switch; Wherein, the first upper-bridge switch and the second upper-bridge switch are serially connected in sequence between the first output voltage and a switching node. The first upper-bridge switch and the second upper-bridge switch are coupled to each other at an upper-bridge intermediate node. The first lower-bridge switch and the second lower-bridge switch are serially connected in sequence between a ground potential and the switching node. The first lower-bridge switch and the second lower-bridge switch are coupled to each other at a lower-bridge intermediate node. The inductor is coupled between the switching node and the second output voltage. The first capacitor is coupled between the upper-bridge intermediate node and the lower-bridge intermediate node. The second capacitor is coupled to the second output voltage.

17. The control circuit according to claim 16, wherein, The first upper-bridge switch and the second lower-bridge switch are switched according to a first switching signal based on a switching period and a duty cycle. The second upper-bridge switch and the first lower-bridge switch are switched according to a second switching signal based on the switching period and the duty cycle. Wherein, when the power-saving signal is disabled, the duty cycle is less than 50%. Wherein, when the power-saving signal is enabled, the duty cycle is substantially equal to 50%.

18. The control circuit according to claim 16, wherein, The plurality of switches further includes a bypass switch connected in parallel with the inductor. When the power-saving signal is disabled, the bypass switch is not conducting. When the power-saving signal is enabled, the bypass switch is conducting.

19. The control circuit according to claim 16, wherein, The plurality of switches further includes an upper-bridge auxiliary switch and a lower-bridge auxiliary switch. The upper-bridge auxiliary switch is coupled between the second output voltage and the upper-bridge intermediate node. The lower-bridge auxiliary switch is coupled between the second output voltage and the lower-bridge intermediate node. Wherein, when the power-saving signal is disabled, the upper-bridge auxiliary switch and the lower-bridge auxiliary switch are not conducting. Wherein, when the power-saving signal is enabled, the second upper-bridge switch and the second lower-bridge switch are not conducting.

20. The control circuit according to claim 19, wherein, When the power-saving signal is disabled, the first upper-bridge switch and the second lower-bridge switch are switched according to a first switching signal based on a switching period and a duty cycle. The second upper-bridge switch and the first lower-bridge switch are switched according to a second switching signal based on the switching period and the duty cycle. The duty cycle is less than 50%. Wherein, when the power-saving signal is enabled, the first upper-bridge switch and the lower-bridge auxiliary switch are switched according to the first switching signal based on the switching period and the duty cycle. The upper-bridge auxiliary switch and the first lower-bridge switch are switched according to the second switching signal based on the switching period and the duty cycle. The duty cycle is substantially equal to 50%.

21. The control circuit according to claim 19, wherein, When the power-saving signal is disabled, the first upper-bridge switch, the second upper-bridge switch, the first lower-bridge switch, and the second lower-bridge switch switch the inductor and the plurality of capacitors based on a switching period to perform power conversion with 3rd-order pulse width modulation. Wherein, when the power-saving signal is enabled, the first upper-bridge switch, the upper-bridge auxiliary switch, the first lower-bridge switch, and the lower-bridge auxiliary switch switch the inductor and the plurality of capacitors based on the switching period to perform capacitive power conversion.

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