Analog-to-digital converter based on time-interleaved noise and method of application thereof

Abstract

This invention discloses an analog-to-digital converter (ADC) based on time-interleaved noise and its application method. The ADC includes: a first-channel conversion circuit, a second-channel conversion circuit, a multiplexer, a shared dynamic amplifier, a first feedback error circuit, a second feedback error circuit, and a feedforward error circuit. This invention processes the signal to be converted using the dual-channel conversion circuits. The first-channel conversion circuit receives a common-mode level based on a first preset period, and the second-channel conversion circuit receives a common-mode level based on a second preset period, thereby achieving interleaved time conversion between the two channels. The shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit, and the feedforward error circuit enable dynamic power consumption across the entire ADC circuit, thus meeting different bandwidth and accuracy application requirements depending on the sampling frequency and oversampling rate.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to an analog-to-digital converter based on time-interleaved noise and its application method. Background Technology

[0002] The noise-shaping successive approximation digital-to-analog converter NS-SAR combines the advantages of Δ-Σ ADC and SAR ADC, and is a novel ADC structure that can achieve high resolution and high power efficiency.

[0003] However, as the capacitor size in the capacitive digital-to-analog converter (CDAC) increases, the settling time of the digital-to-analog conversion in the successive approximation analog-to-digital converter (SAR) becomes significantly longer to meet the requirements of high resolution. Furthermore, achieving a sharp noise transfer function (NTF) requires margin amplification to compensate for signal attenuation; this margin amplification process consumes the time available for digital-to-analog conversion calculations, resulting in less time left for SAR conversion.

[0004] Existing noise-shaping successive approximation digital-to-analog converters (NS-SAR) can improve bandwidth, but they negatively impact noise-shaping performance and digital-to-analog conversion efficiency. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a successive approximation analog-to-digital converter based on time-interleaved noise, as detailed below:

[0006] In a first aspect, embodiments of this application provide an analog-to-digital converter based on time-interleaved noise, the analog-to-digital converter comprising: a first channel conversion circuit, a second channel conversion circuit, a multiplexer, a shared dynamic amplifier, a first feedback error circuit, a second feedback error circuit, and a feedforward error circuit;

[0007] Both the first channel conversion circuit and the second channel conversion circuit include two comparison input terminals. The first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit are used to connect to the level to be converted. The first comparison input terminal and the third comparison input terminal of the first channel conversion circuit are used to connect to the common-mode level in a first preset time period. The second comparison input terminal and the fourth comparison input terminal of the second channel conversion circuit are used to connect to the common-mode level in a second preset time period.

[0008] The first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit are also connected to the non-inverting input terminal of the shared dynamic amplifier;

[0009] The inverting output terminal of the shared dynamic amplifier is connected to the first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit through the first feedback error circuit, respectively. The non-inverting output terminal of the shared dynamic amplifier is connected to the first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit through the second feedback error circuit, respectively.

[0010] The non-inverting output of the shared dynamic amplifier is also connected to the third comparator input of the first channel conversion circuit and the fourth comparator input of the second channel conversion circuit through the feedforward error circuit.

[0011] The output terminals of the first channel conversion circuit and the second channel conversion circuit are respectively connected to the input terminal of a multiplexer. The multiplexer is used to output a digital signal based on the first conversion signal of the first channel conversion circuit and the second conversion signal of the second channel conversion circuit.

[0012] According to a specific embodiment of the present application, the first channel conversion circuit and the second channel conversion circuit are the same, and the conversion circuit includes a DAC array with a preset number of capacitors, a data weight averaging circuit, a comparator and a successive approximation logic circuit.

[0013] The first non-inverting input of the comparator is used to access the level to be converted through the DAC array. The first non-inverting input of the comparator is also used to access the common-mode level. The first non-inverting input of the comparator is connected to the outputs of the first feedback error circuit and the second feedback error circuit, respectively. The first non-inverting input of the comparator is connected to the non-inverting input of the shared dynamic amplifier.

[0014] The second input terminal of the comparator is used to connect to the common-mode level, and the second input terminal of the comparator is also connected to the output terminal of the feedforward error circuit;

[0015] Each capacitor in the DAC array is connected to a preset electrical signal branch through a capacitor switch. The successive approximation logic circuit is connected to the first part of the capacitor switches in the DAC array. The successive approximation logic circuit is also connected to the second part of the capacitor switches in the DAC array through the data weight averaging circuit.

[0016] The output of the comparator is connected to the input of the successive approximation logic circuit, and the output of the successive approximation logic circuit is connected to the output of the conversion circuit.

[0017] According to a specific embodiment of this application, the DAC array includes i+1 capacitors, an upper plate branch, a lower plate branch, and an input level branch. The capacitors are connected to the upper plate branch, the lower plate branch, and the input level branch according to a preset ratio.

[0018] Among them, i number of capacitors are set to 2 for each bit position according to a preset order. i Redundancy range of LSBs;

[0019] A capacitor covering a preset numerical redundancy range is set between the fifth and sixth bits.

[0020] According to a specific embodiment of this application, the gain ratio of the first comparison input terminal and the third comparison input terminal of the first channel conversion circuit is 2:1;

[0021] The gain ratio between the second comparison input terminal and the fourth comparison input terminal of the second channel conversion circuit is 2:1.

[0022] According to a specific embodiment of the present application, the first feedback error circuit includes a first channel first-order feedback error branch and a second channel first-order feedback error branch, and the second feedback error circuit includes a first channel second-order feedback error branch and a second channel second-order feedback error branch.

[0023] The output terminal of the second-order feedback error branch of the first channel and the output terminal of the first-order feedback branch of the second channel are both connected to the first comparison input terminal of the first channel conversion circuit.

[0024] The output of the second-order feedback error branch of the second channel and the output of the first-order feedback branch of the first channel are both connected to the second comparison input of the second channel conversion circuit.

[0025] According to a specific embodiment of the present application, the working states of both the first channel conversion circuit and the second channel conversion circuit include a sampling stage, a conversion stage, and a margin amplification stage.

[0026] The sampling phase and the margin amplification phase take up 1 / 2 of the time period, and the conversion phase takes up 1 / 2 of the time period.

[0027] Furthermore, when the first channel conversion circuit is in the sampling stage or the margin amplification stage, the second channel conversion circuit is in the conversion stage.

[0028] When the first channel conversion circuit is in the conversion stage, the second channel conversion circuit is in the sampling stage or the margin amplification stage.

[0029] According to a specific embodiment of the present application, after the first channel conversion circuit completes the margin amplification, the first feedback error circuit outputs a first-order feedback error to the second channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the first channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the first channel conversion circuit.

[0030] After the second channel conversion circuit completes the margin amplification, the first feedback error circuit outputs a first-order feedback error to the first channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the second channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the second channel conversion circuit.

[0031] According to a specific embodiment of this application, the shared dynamic amplifier includes a floating inverting amplifier circuit, a first channel input branch, a second channel input branch, a first channel output branch, and a second channel output branch;

[0032] The floating inverting amplifier circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the first channel input branch, the second input terminal is connected to the second channel input branch, the first output terminal is connected to the first channel output branch, and the second output terminal is connected to the second channel output branch.

[0033] Secondly, embodiments of this application provide an application method for an analog-to-digital converter based on time-interleaved noise, applied to the analog-to-digital converter based on time-interleaved noise described in the first aspect and any embodiment of the first aspect, the application method comprising:

[0034] The first conversion circuit processes the level to be converted and the common-mode level in the first preset cycle to obtain the first conversion signal;

[0035] The second-channel conversion circuit processes the level to be converted and the common-mode level in a second preset period to obtain a second conversion signal;

[0036] A digital circuit signal is output by performing preset calculations based on the first conversion signal and the second conversion signal using a multiplexer.

[0037] According to a specific embodiment of this application, the formula for calculating the combined noise transfer function of the first converted signal and the second converted signal is as follows:

[0038] Where NTF represents the noise transfer function, K FB K represents the feedback error.FF z represents the feedforward error. -1 K FB z represents the first-order feedback error. -2 K FB Z represents the second-order feedback error. -2 K FF This represents the second-order feedforward error.

[0039] This application provides an analog-to-digital converter (ADC) based on time-interleaved noise and its application method. The ADC includes: a first-channel conversion circuit, a second-channel conversion circuit, a multiplexer, a shared dynamic amplifier, a first feedback error circuit, a second feedback error circuit, and a feedforward error circuit. This application uses the dual-channel conversion circuit to process the signal to be converted. The first-channel conversion circuit receives a common-mode level based on a first preset period, and the second-channel conversion circuit receives a common-mode level based on a second preset period, thereby achieving interleaved time conversion between the two channels. The shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit, and the feedforward error circuit enable dynamic power consumption across the entire ADC circuit, allowing it to meet different bandwidth and accuracy requirements depending on the sampling frequency and oversampling rate. Attached Figure Description

[0040] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.

[0041] Figure 1 A schematic diagram of the circuit structure of an analog-to-digital converter based on time-interleaved noise provided in an embodiment of this application is shown;

[0042] Figure 2 This paper illustrates a block diagram of a dual-channel TI-NS-SAR based analog-to-digital converter with second-order feedback error and feedforward error, according to an embodiment of this application.

[0043] Figure 3 The diagram shows the timing diagram of the first channel conversion circuit and the second channel conversion circuit of an analog-to-digital converter based on time-interleaved noise according to an embodiment of this application.

[0044] Figure 4a This illustration shows an interactive connection diagram of a shared dynamic amplifier for an analog-to-digital converter based on time-interleaved noise, according to an embodiment of this application.

[0045] Figure 4bThis paper illustrates a circuit structure diagram of a shared dynamic amplifier for an analog-to-digital converter based on time-interleaved noise, according to an embodiment of this application.

[0046] Figure 4c This illustration shows the timing diagram of different signals operating in a shared dynamic amplifier of an analog-to-digital converter based on time-interleaved noise, according to an embodiment of this application.

[0047] Figure 5 The illustration shows a flowchart of an application method for an analog-to-digital converter based on time-interlaced noise, according to an embodiment of this application. Detailed Implementation

[0048] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0049] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0050] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0051] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0052] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0053] refer to Figure 1This is a schematic diagram of the circuit structure of a successive approximation analog-to-digital converter based on time-interleaved noise, provided in an embodiment of this application. The successive approximation analog-to-digital converter based on time-interleaved noise provided in this embodiment of the application, such as... Figure 1 As shown, the successive approximation analog-to-digital converter based on time-interleaved noise includes:

[0054] The circuit consists of a first channel conversion circuit, a second channel conversion circuit, a multiplexer, a shared dynamic amplifier, a first feedback error circuit, a second feedback error circuit, and a feedforward error circuit.

[0055] Both the first channel conversion circuit and the second channel conversion circuit include two comparison input terminals. The first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit are used to connect to the level to be converted. The first comparison input terminal and the third comparison input terminal of the first channel conversion circuit are used to connect to the common-mode level in a first preset time period. The second comparison input terminal and the fourth comparison input terminal of the second channel conversion circuit are used to connect to the common-mode level in a second preset time period.

[0056] The first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit are also connected to the non-inverting input terminal of the shared dynamic amplifier;

[0057] The inverting output terminal of the shared dynamic amplifier is connected to the first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit through the first feedback error circuit, respectively. The non-inverting output terminal of the shared dynamic amplifier is connected to the first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit through the second feedback error circuit, respectively.

[0058] The non-inverting output of the shared dynamic amplifier is also connected to the third comparator input of the first channel conversion circuit and the fourth comparator input of the second channel conversion circuit through the feedforward error circuit.

[0059] The output terminals of the first channel conversion circuit and the second channel conversion circuit are respectively connected to a multiplexer. The multiplexer is used to output a digital circuit signal based on the first conversion signal of the first channel conversion circuit and the second conversion signal of the second channel conversion circuit.

[0060] In a specific embodiment, the first channel conversion circuit #CH1 and the second channel conversion circuit #CH2 have the same structure. Both the first channel conversion circuit and the second channel conversion circuit are a time-interlaced noise-shaping successive approximation analog-to-digital amplifier (TI-NS-SAR).

[0061] like Figure 1 As shown, the analog-to-digital converter based on time-interleaved noise proposed in this embodiment has dual-channel TI-NS-SAR, namely the first channel conversion circuit and the second channel conversion circuit.

[0062] The first comparison input terminal and the third comparison input terminal of the first channel conversion circuit are connected through the first magnetic flux switch. Access common-mode level V CM The second comparison input and the fourth comparison input of the second channel conversion circuit are connected via a second flux switch. Access common-mode level V CM .

[0063] The third and fourth comparison input terminals are connected to a common-mode voltage V. CM This is for comparator reset processing.

[0064] In a specific implementation, the startup time of the first channel conversion circuit is different from that of the second channel conversion circuit. The first channel conversion circuit performs a sampling, conversion, and amplification cycle according to a first preset time period. The second channel conversion circuit performs a sampling, conversion, and amplification cycle according to a second preset time period.

[0065] The first preset time period and the second preset time period occupy the same amount of time, and the first preset time period cycles before the second preset time period by 1 / 2 of a cycle length.

[0066] Meanwhile, this embodiment also includes a feedforward error circuit, which is used to provide second-order feedforward error for the first channel conversion circuit and the second channel conversion circuit to enhance the noise shaping performance of TI-NS-SAR at high frequencies, while avoiding the dynamic range loss caused by the rising peak of the noise transfer function NTF.

[0067] This embodiment also includes a shared dynamic amplifier and a one-time intermediate error feedback, thereby reducing the redundancy bits of the first channel conversion circuit and the second channel conversion circuit, reducing the redundancy bits of the first channel conversion circuit and the second channel conversion circuit to 1 bit, thereby obtaining higher bandwidth and more time for SAR conversion.

[0068] The non-inverting input of the shared dynamic amplifier is connected to the first channel flux switch. Connected to the first channel conversion circuit, the non-inverting input of the shared dynamic amplifier is also connected to the second channel flux switch. Connect to the second channel conversion circuit.

[0069] Specifically, in this embodiment, each flux switch switches on and off according to the specific operating states of the first channel conversion circuit and the second channel conversion circuit, so as to achieve control functions such as signal acquisition, output, and redundancy adjustment.

[0070] According to a specific embodiment of the present application, the working states of both the first channel conversion circuit and the second channel conversion circuit include a sampling stage, a conversion stage, and a margin amplification stage.

[0071] The sampling phase and the margin amplification phase take up 1 / 2 of the time period, and the conversion phase takes up 1 / 2 of the time period.

[0072] Furthermore, when the first channel conversion circuit is in the sampling stage or the margin amplification stage, the second channel conversion circuit is in the conversion stage.

[0073] When the first channel conversion circuit is in the conversion stage, the second channel conversion circuit is in the sampling stage or the margin amplification stage.

[0074] In a specific implementation, the sampling phase is the period during which the first channel conversion circuit and the second channel conversion circuit presample the input level. The conversion phase is the period during which the TI-NS-SAR analog-to-digital converter performs SAR conversion. The margin amplification phase is the period during which the TI-NS-SAR samples the residual value through an FIR filter and amplifies it through an amplifier.

[0075] Specifically, assuming Ts is the sampling period of a single channel, the sampling stage, the conversion stage, and the margin amplification stage occupy 1 / 4, 1 / 2, and 1 / 4 of Ts, respectively.

[0076] The above time allocation method can balance the time required for residual amplification and the redundancy range of intermediate error feedback.

[0077] In practical applications, the time of the sampling stage and the margin amplification stage may not be equal, but it is necessary to ensure that the time of the sampling stage and the margin amplification stage is equal to the time of the conversion stage.

[0078] Specifically, such as Figure 3 As shown, for conversion circuits of different channels, the sampling stage, the conversion stage, and the margin amplification stage are non-overlapping. The sampling period of a single channel can be adaptively adjusted according to the actual application scenario, and is not limited here.

[0079] Since the operating states of the conversion circuits of different channels do not overlap, when the first channel conversion circuit operates according to the first preset cycle and the second channel conversion circuit operates according to the second preset cycle, the clocks of the first channel conversion circuit and the second channel conversion circuit are truncated during different analog-to-digital conversion processes.

[0080] It is worth noting that when the first channel conversion circuit starts up according to the first preset cycle, the second channel conversion circuit starts up later than the first channel conversion circuit, according to the second preset cycle. At this time, the processing state of the first channel is the sampling stage, and the processing state of the second channel is empty.

[0081] Alternatively, the second channel conversion circuit can also be started according to the first preset cycle. In this case, the first channel conversion circuit is started according to the second preset cycle. This embodiment does not specifically limit the startup order.

[0082] According to a specific embodiment of the present application, after the first channel conversion circuit completes the margin amplification, the first feedback error circuit outputs a first-order feedback error to the second channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the first channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the first channel conversion circuit.

[0083] After the second channel conversion circuit completes the margin amplification stage, the first feedback error circuit outputs a first-order feedback error to the first channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the second channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the second channel conversion circuit.

[0084] In a specific embodiment, when the first channel conversion circuit or the second channel conversion circuit is in the margin amplification stage, it means that the first channel conversion circuit or the second channel conversion circuit has completed the sampling stage and conversion stage within one cycle. The first channel conversion circuit or the second channel conversion circuit will amplify the margin in the conversion stage.

[0085] The first feedback error circuit, the second feedback error circuit, and the feedforward error circuit perform error feedback and error feedforward based on the residual amplification. Specifically, the error feedforward and error feedback processes occur in the intermediate error feedback stage after the residual amplification stage is completed.

[0086] After the error feedforward and error feedback are completed in the intermediate error feedback stage after the current sampling period, the feedforward error and feedback error will be used for corresponding calculations in the conversion stage of the next sampling period.

[0087] Specifically, when the first channel conversion circuit and the second channel conversion circuit complete the SAR conversion, the residual value is sampled and amplified by the shared dynamic amplifier, and then sampled on the preset FIR filter capacitor.

[0088] like Figure 1 As shown, in the intermediate error feedback stage, C FB and 2C FB The sampling residual will be cross-coupled to other channels z through charge sharing of the DAC array. -1 Or self-coupled to z -2 .

[0089] like Figure 1 As shown, the intermediate sharing of SAR conversion starts after the margin amplification stage and continues until the conversion of the last bit of SAR is completed. In FIR, z... -1 and z -2 The capacitance ratio is 2:1, and they together form (2z) -1 –z -2 ) / 3. The gain G and signal attenuation factor of the shared dynamic amplifier will be affected by the charge sharing definition K. FB The value of G. Therefore, G can be used to implement zero-point optimization of NTF.

[0090] In the error feedforward stage, the sampling margin is generated through self-coupling and transferred to the capacitor to facilitate charge sharing between the input nodes of multi-input comparators in the same channel. The gain G of the shared dynamic amplifier is determined by the signal attenuation factor due to charge sharing and the ratio of multiple input pairs. FF The CDAC's upper plate is connected to one input of the comparator with a gain of 1, while the feedforward path is connected to another input of the comparator with a gain of 0.5. This results in lower power consumption and less noise in the feedforward path.

[0091] According to a specific embodiment of the present application, the first channel conversion circuit and the second channel conversion circuit are the same conversion circuit, and the conversion circuit includes a DAC array with a preset number of capacitors, a data weight averaging circuit, a comparator and a successive approximation logic circuit.

[0092] The first non-inverting input of the comparator is used to access the level to be converted through the DAC array. The first non-inverting input of the comparator is also used to access the common-mode level. The first non-inverting input of the comparator is connected to the outputs of the first feedback error circuit and the second feedback error circuit, respectively. The first non-inverting input of the comparator is connected to the non-inverting input of the shared dynamic amplifier.

[0093] The second input terminal of the comparator is used to connect to the common-mode level, and the second input terminal of the comparator is also connected to the output terminal of the feedforward error circuit;

[0094] Each capacitor in the DAC array is connected to a preset electrical signal branch through a capacitor switch. The successive approximation logic circuit is connected to the first part of the capacitor switches in the DAC array. The successive approximation logic circuit is also connected to the second part of the capacitor switches in the DAC array through the data weight averaging circuit.

[0095] The output of the comparator is connected to the input of the successive approximation logic circuit, and the output of the successive approximation logic circuit is connected to the output of the conversion circuit.

[0096] In specific implementation methods, such as Figure 1 As shown, the conversion circuit includes a digital-to-analog converter array with a preset number of capacitors, wherein the digital-to-analog converter array is a DAC array.

[0097] The DAC array can also be referred to as a capacitive digital-to-analog converter (CDAC).

[0098] The capacitive digital-to-analog converter (CDAC) includes an upper plate branch V. REFP Lower electrode branch V REFN and input level branch V IN Furthermore, on each branch, a capacitor switch corresponding to each capacitor in the CDAC is provided.

[0099] By controlling the closing of the capacitor switch, the redundancy range of the CDAC can be adjusted.

[0100] In this embodiment, the control of the capacitor switch is achieved through a successive approximation logic circuit. The successive approximation logic circuit is directly connected to the capacitors of bits 0 to 5 of the CDAC and a capacitor switch of a preventive capacitor. Signal control is achieved through the digital signal D1<5:0>.

[0101] The successive approximation logic link also connects the capacitor switches of the 7th to 22nd bits of the CDAC through the data weight averaging circuit, i.e., the DWA circuit, and realizes signal control through the digital signal D1<9:6>.

[0102] Specifically, in this embodiment, the 9-bit asynchronous split monotonic switch SAR is implemented by sampling the lower plate, thereby avoiding additional signal attenuation caused by parasitic CDAC upper plate.

[0103] The upper plate of the CDAC is connected to the first positive input terminal of the comparator to output the level signal to be converted to the comparator.

[0104] The input terminal of the comparator is also used to connect to the common-mode level and the output terminal of the multiple error circuit, and the comparator is a multiple input comparator.

[0105] The comparator, through multiple input levels and error correction, can calculate the noise transfer function (NTF) according to preset rules.

[0106] The Data Weighted Average (DWA) circuit reassembles the four most significant bits (MSBs) of the SAR to mitigate the damage caused by capacitor mismatch in the CDAC.

[0107] According to a specific embodiment of this application, the DAC array includes i+1 capacitors, an upper plate branch, a lower plate branch, and an input level branch. The capacitors are connected to the upper plate branch, the lower plate branch, and the input level branch according to a preset ratio.

[0108] Among them, i number of capacitors are set to 2 for each bit position according to a preset order. i Redundancy range of LSBs;

[0109] A preventative capacitor covering a preset range of numerical redundancy is set between the fifth and sixth bits.

[0110] In a specific implementation, a 1-bit redundancy is introduced between the 5th bit 8C and the 6th bit 16C to cover the range of 14 least significant bits (LSBs), which can effectively prevent the overload risk caused by intermediate error feedback and the offset of the shared amplifier.

[0111] Among them, such as Figure 1 As shown, the capacitors from right to left are each set to 2. i The redundancy range of LSBs, where the rightmost capacitor is the 0th bit capacitor, and the bits increase sequentially to the left.

[0112] Specifically, the value of i can be adaptively replaced according to the actual application scenario. This embodiment does not impose specific limitations on the value of i.

[0113] According to a specific embodiment of this application, the gain ratio of the first comparison input terminal and the third comparison input terminal of the first channel conversion circuit is 2:1;

[0114] The gain ratio between the second comparison input terminal and the fourth comparison input terminal of the second channel conversion circuit is 2:1.

[0115] In a specific implementation, the gain of the first comparison input terminal and the second comparison input terminal is 1, and the gain of the third comparison input terminal and the fourth comparison input terminal is 0.5.

[0116] Of course, the specific values ​​of the first comparison input terminal, the second comparison input terminal, the third comparison input terminal, and the fourth comparison input terminal can be adaptively replaced according to the actual application scenario. Here, the specific values ​​of each comparison input terminal are not limited.

[0117] In this embodiment, the upper plate of the CDAC is connected to one input of the comparator with a gain of 1, while the feedforward path is connected to another input of the comparator with a gain of 0.5. This results in lower power consumption and less noise in the feedforward path.

[0118] Capacitor switching circuits are used to reduce the settling time required for charge sharing. If z is injected immediately after the sampling phase... -2 With second-order feedback error, the capacitor switch may break down due to the large signal swing on the CDAC array during SAR conversion of the highest effective MSB bit. -2 Second-order feedback error is injected during SAR conversion to mitigate the risk of breakdown.

[0119] There is no risk of breakdown for capacitor switches with feedforward error because they are injected into capacitor C, which is isolated from the main CDAC. A Above. With the noise shaping enhancement provided by second-order error feedback, the signal-to-noise ratio (SNDR) can be maintained above 78 dB with a gain variation of ±20% (the rated gain G of the shared dynamic amplifier is 12). This allows the circuit to achieve high bandwidth while maintaining sufficient noise shaping, despite a small OSR, without requiring any calibration to reduce the gain variation of the shared dynamic amplifier.

[0120] The analog-to-digital converter in this embodiment achieves a bandwidth of 30MHz at a sampling frequency of 330MHz and an OSR of 5.5.

[0121] According to a specific embodiment of the present application, the first feedback error circuit includes a first channel first-order feedback error branch and a second channel first-order feedback error branch, and the second feedback error circuit includes a first channel second-order feedback error branch and a second channel second-order feedback error branch.

[0122] The output terminal of the second-order feedback error branch of the first channel and the output terminal of the first-order feedback branch of the second channel are both connected to the first comparison input terminal of the first channel conversion circuit.

[0123] The output of the second-order feedback error branch of the second channel and the output of the first-order feedback branch of the first channel are both connected to the second comparison input of the second channel conversion circuit.

[0124] In a specific implementation, Figure 2 The diagram shown is a block diagram of a dual-channel TI-NS-SAR with second-order feedback error and feedforward error. This is because there is an inherent delay z between the two channels. -1 The existence of this means that the residual of a channel will be generated when it is coupled to the same channel in the next stage. At this time, the intermediate error will feed back to generate a second-order high-pass transfer function, which can be used as the numerator of the target noise transfer function.

[0125] For z -1 Cross-coupling and intermediate error feedback are unavoidable because the amplification residual is unavailable at the beginning of the SAR conversion. For z... -2 The self-coupling can also utilize intermediate error feedback.

[0126] like Figure 2 As shown, in order to further improve the (1-z) in the second-order NTF -1 ) 2 A K FF ×z -2 The second-order feedforward error forms a low-pass transfer function TF in the denominator of the noise transfer function NTF, which leads to... FF With a value of 0.5, there will be 3.5dB of quantization noise suppression in the low-frequency band.

[0127] In a specific embodiment, the denominator term TF(1+0.5z) is implemented with a first-order feedforward error. -1 Compared to ), the proposed 1+0.5z -2 The term has fewer out-of-band peaks (-5.5dB), thus resulting in less dynamic range (DR) loss. For example... Figure 3 As shown in the timing diagram, the proposed second-order feedforward error is achieved through a self-coupled feedforward channel in this dual-channel TI-NS-SAR, without introducing any additional cross-coupling injection in the middle of the process. This feedforward injection can be introduced before the first bit of SAR conversion, thus avoiding additional redundancy and mitigating the overload problem caused by intermediate errors in the SAR conversion process.

[0128] According to a specific embodiment of this application, the shared dynamic amplifier includes a floating inverting amplifier circuit, a first channel input branch, a second channel input branch, a first channel output branch, and a second channel output branch;

[0129] The floating inverting amplifier circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the first channel input branch, the second input terminal is connected to the second channel input branch, the first output terminal is connected to the first channel output branch, and the second output terminal is connected to the second channel output branch.

[0130] The first channel input branch, the second channel input branch, the first channel output branch, and the second channel output branch are all connected to the common-mode level.

[0131] In specific implementations, such as Figure 4a , Figure 4b and Figure 4c As shown, a floating inverting amplifier (FIA) and a stable output common-mode (CM) level are used for margin amplification to compensate for signal attenuation and noise that always comes from the FIR capacitor.

[0132] The circuit structure of the floating inverting amplifier (FIA) can be any FIA circuit structure in the prior art, and this embodiment does not limit it.

[0133] Since the margin amplification stages of the two channels do not overlap, the FIA ​​can be shared by both channels. The biggest advantage of this sharing is that it relaxes the redundancy requirements, thus covering the entire offset range. The offset of the FIA ​​is provided to the SAR through an intermediate error feedback loop; introducing an additional redundancy range to avoid the risk of overload is necessary. Compared to a separate FIA, a shared FIA contributes a smaller offset to each channel, thus resulting in lower redundancy requirements.

[0134] The analog-to-digital converter circuit based on time-interleaved noise provided in this application uses dynamic power consumption throughout the circuit, thereby meeting different application requirements for bandwidth and accuracy depending on different sampling frequencies and oversampling rates (OSR).

[0135] When the DWA circuit is turned on, the measured signal-to-noise ratio (SNDR), signal-to-noise ratio (SNR), and spurious-free dynamic range (SFDR) are 73.5 dB, 74.4 dB, and 86.6 dB, respectively. With two input signals of -7.5 dBFs, the IMD3 was measured at 25.7 MHz and 26.2 MHz, respectively, at -81.6 dB and -80 dB. The DR test result was 74.7 dB, and the total power consumption at a 1 V supply was 3.07 mW. Therefore, the calculated Schreier FoM is 173.4 dB, and the SNDR varied by only 0.8 dB across five different chip samples. The analog-to-digital converter proposed in this embodiment significantly improves the FoM.

[0136] refer to Figure 5 This is a flowchart illustrating an application method for an analog-to-digital converter (ADC) based on time-interleaved noise, provided in an embodiment of this application. The application method for an ADC based on time-interleaved noise provided in this embodiment of the application is as follows: Figure 5 As shown, the application method of the analog-to-digital converter based on time-interleaved noise includes:

[0137] Step S501: The first channel conversion circuit processes the level to be converted and the common-mode level in the first preset cycle to obtain the first conversion signal;

[0138] Step S502: The level to be converted and the common-mode level are processed by the second channel conversion circuit in the second preset period to obtain the second conversion signal;

[0139] Step S503: The multiplexer performs a preset calculation based on the first conversion signal and the second conversion signal to output a digital circuit signal.

[0140] According to a specific embodiment of this application, the formula for calculating the noise transfer function of the first converted signal or the second converted signal is as follows:

[0141] Where NTF represents the noise transfer function, K FB K represents the feedback error. FF z represents the feedforward error. -1 K FB z represents the first-order feedback error. -2 K FB Z represents the second-order feedback error. -2 K FF This represents the second-order feedforward error.

[0142] In a specific embodiment, such as Figure 1 From the connection relationship of the first feedback error circuit, it can be seen that the feedback error K FB The calculation formula is:

[0143] like Figure 1 From the connection relationship of the feedforward error circuit, it can be seen that the feedforward error K FF The calculation formula is:

[0144]

[0145] Where G represents the gain of the shared dynamic amplifier, and C FF C is the capacitance value at the ground terminal of the capacitor in the feedforward error circuit. FB C is the capacitance value at the ground terminal of the capacitor in the feedback error circuit. DAC The capacitance value is for the DAC array.

[0146] In one feasible implementation provided in this embodiment, the values ​​of the above-mentioned capacitors and gain values ​​can be taken as follows:

[0147] C DAC =1.4pF(single-end); C FB =138fF; C FF =15fF;C A =170fF; G=12.

[0148] In summary, this application provides an analog-to-digital converter (ADC) based on time-interleaved noise and its application method. By using a dual-channel TI-NS-SAR ADC circuit, the bandwidth can be effectively expanded, avoiding the bandwidth limitations faced by single-channel NS-SAR. Furthermore, the ADC in this embodiment enhances noise shaping through second-order feedback error, ensuring that the shared dynamic amplifier can meet the required noise shaping effect without any calibration. Through the addition of extra redundant bits, this embodiment also avoids the reduced ADC conversion efficiency caused by the time-interleaved structure in SAR. Additionally, the specific implementation process of the application method of the ADC based on time-interleaved noise mentioned in the above embodiments can be found in the specific implementation process of the above device embodiments, and will not be repeated here.

[0149] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0150] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0151] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0152] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An analog-to-digital converter based on time-interleaved noise, characterized in that, The analog-to-digital converter includes: a first channel conversion circuit, a second channel conversion circuit, a multiplexer, a shared dynamic amplifier, a first feedback error circuit, a second feedback error circuit, and a feedforward error circuit; Both the first channel conversion circuit and the second channel conversion circuit include two comparison input terminals. The first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit are used to connect to the level to be converted. The first comparison input terminal and the third comparison input terminal of the first channel conversion circuit are used to connect to the common-mode level in a first preset time period. The second comparison input terminal and the fourth comparison input terminal of the second channel conversion circuit are used to connect to the common-mode level in a second preset time period. The first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit are also connected to the non-inverting input terminal of the shared dynamic amplifier; The inverting output terminal of the shared dynamic amplifier is connected to the first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit through the first feedback error circuit, respectively. The non-inverting output terminal of the shared dynamic amplifier is connected to the first comparison input terminal of the first channel conversion circuit and the second comparison input terminal of the second channel conversion circuit through the second feedback error circuit, respectively. The non-inverting output of the shared dynamic amplifier is also connected to the third comparator input of the first channel conversion circuit and the fourth comparator input of the second channel conversion circuit through the feedforward error circuit. The output terminals of the first channel conversion circuit and the second channel conversion circuit are respectively connected to a multiplexer. The multiplexer is used to output a digital circuit signal based on the first conversion signal of the first channel conversion circuit and the second conversion signal of the second channel conversion circuit.

2. The analog-to-digital converter according to claim 1, characterized in that, The first channel conversion circuit and the second channel conversion circuit are the same conversion circuit. The conversion circuit includes a DAC array with a preset number of capacitors, a data weight averaging circuit, a comparator, and a successive approximation logic circuit. The first non-inverting input of the comparator is used to access the level to be converted through the DAC array. The first non-inverting input of the comparator is also used to access the common-mode level. The first non-inverting input of the comparator is connected to the outputs of the first feedback error circuit and the second feedback error circuit, respectively. The first non-inverting input of the comparator is connected to the non-inverting input of the shared dynamic amplifier. The second input terminal of the comparator is used to connect to the common-mode level, and the second input terminal of the comparator is also connected to the output terminal of the feedforward error circuit; Each capacitor in the DAC array is connected to a preset electrical signal branch through a capacitor switch. The successive approximation logic circuit is connected to the first part of the capacitor switches in the DAC array. The successive approximation logic circuit is also connected to the second part of the capacitor switches in the DAC array through the data weight averaging circuit. The output of the comparator is connected to the input of the successive approximation logic circuit, and the output of the successive approximation logic circuit is connected to the output of the conversion circuit.

3. The analog-to-digital converter according to claim 2, characterized in that, The DAC array includes i+1 capacitors, an upper plate branch, a lower plate branch, and an input level branch. The capacitors are connected to the upper plate branch, the lower plate branch, and the input level branch according to a preset ratio. Among them, i number of capacitors are set to 2 for each bit position according to a preset order. i Redundancy range of LSBs; A preventative capacitor covering a preset range of numerical redundancy is set between the fifth and sixth bits.

4. The analog-to-digital converter according to claim 1, characterized in that, The gain ratio between the first comparison input terminal and the third comparison input terminal of the first channel conversion circuit is 2:1; The gain ratio between the second comparison input terminal and the fourth comparison input terminal of the second channel conversion circuit is 2:

1.

5. The analog-to-digital converter according to claim 1, characterized in that, The first feedback error circuit includes a first-order feedback error branch and a second-order feedback error branch, and the second feedback error circuit includes a first-order feedback error branch and a second-order feedback error branch. The output terminal of the second-order feedback error branch of the first channel and the output terminal of the first-order feedback branch of the second channel are both connected to the first comparison input terminal of the first channel conversion circuit. The output of the second-order feedback error branch of the second channel and the output of the first-order feedback branch of the first channel are both connected to the second comparison input of the second channel conversion circuit.

6. The analog-to-digital converter according to claim 1, characterized in that, The operating states of both the first channel conversion circuit and the second channel conversion circuit include a sampling stage, a conversion stage, and a margin amplification stage. The sampling phase and the margin amplification phase together account for 1 / 2 of the time period, and the conversion phase accounts for 1 / 2 of the time period. Furthermore, when the first channel conversion circuit is in the sampling stage or the margin amplification stage, the second channel conversion circuit is in the conversion stage. When the first channel conversion circuit is in the conversion stage, the second channel conversion circuit is in the sampling stage or the margin amplification stage.

7. The analog-to-digital converter according to claim 6, characterized in that, After the first channel conversion circuit completes the margin amplification, the first feedback error circuit outputs a first-order feedback error to the second channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the first channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the first channel conversion circuit. After the second channel conversion circuit completes the margin amplification, the first feedback error circuit outputs a first-order feedback error to the first channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the second channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the second channel conversion circuit.

8. The analog-to-digital converter according to claim 1, characterized in that, The shared dynamic amplifier includes a floating inverting amplifier circuit, a first channel input branch, a second channel input branch, a first channel output branch, and a second channel output branch; The floating inverting amplifier circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the first channel input branch, the second input terminal is connected to the second channel input branch, the first output terminal is connected to the first channel output branch, and the second output terminal is connected to the second channel output branch. The first channel input branch, the second channel input branch, the first channel output branch, and the second channel output branch are all connected to the common-mode level.

9. An application method for an analog-to-digital converter based on time-interleaved noise, characterized in that, The analog-to-digital converter based on time-interleaved noise according to any one of claims 1-8, the application method comprising: The first channel conversion circuit processes the level to be converted and the common-mode level in the first preset cycle to obtain the first conversion signal; The second-channel conversion circuit processes the level to be converted and the common-mode level in a second preset period to obtain a second conversion signal; A digital signal is output by performing a preset calculation based on the first and second conversion signals using a multiplexer.

10. The application method according to claim 9, characterized in that, The formula for calculating the noise transfer function synthesized from the first converted signal and the second converted signal is as follows: Where NTF represents the noise transfer function, K FB K represents the feedback error. FF z represents the feedforward error. -1 K FB z represents the first-order feedback error. -2 K FB Z represents the second-order feedback error. -2 K FF This represents the second-order feedforward error.

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