Multi-channel parallel DAC configuration circuit structure based on single chip computer bus multiplexing

Abstract

The present invention provides a multi-channel parallel DAC configuration circuit structure based on single-chip computer bus multiplexing, comprising: a single-chip computer module, comprising a single-chip computer chip; an external read-only memory; a latch module, whose input is connected to an I / O port of the single-chip computer chip; a logic gate module, whose one input end is connected to another I / O port of the single-chip computer chip, and the other input end is connected to the write end pin of the single-chip computer chip; and a DAC module, comprising two parallel DAC chips, the clock pins of the two DAC chips are respectively connected to the output end of the logic gate module, so that the clock pins of the parallel DAC chips are configured through the WR pin of the single-chip computer chip, so as to realize the multi-channel parallel DAC configuration based on single-chip computer bus multiplexing.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a multi-channel parallel DAC configuration circuit structure based on single-chip computer bus multiplexing. Background Art

[0002] In high-level and high-reliability circuit design, 80C32 microcontrollers have been widely used in various subsystems and submodules. However, the 80C32 microcontroller was developed and designed earlier, and its I / O port resources are extremely limited, and there are often insufficient resources. In this case, the general solution is to add an I / O port expansion chip, that is, a serial-to-parallel conversion chip, which will increase the extra volume and weight. This will increase costs and reduce reliability in the aerospace field. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] Based on the above problems, the present disclosure provides a multi-channel parallel DAC configuration circuit structure based on single-chip bus multiplexing to alleviate technical problems such as increased cost and bottoming out reliability when solving the problem of limited I / O port resources of single-chip chips in the prior art.

[0005] (II) Technical solution

[0006] The present disclosure provides a multi-channel parallel DAC configuration circuit structure based on single-chip computer bus multiplexing, comprising:

[0007] The single-chip microcomputer module includes a single-chip microcomputer chip;

[0008] External read-only memory;

[0009] A latch module, the input of which is connected to an I / O port of the microcontroller chip;

[0010] A logic gate module, one input end of which is connected to another I / O port of the single-chip microcomputer chip, and the other input end of which is connected to the write-end pin of the single-chip microcomputer chip; and

[0011] The DAC module includes two parallel DAC chips, the clock pins of the two DAC chips are respectively connected to the output end of the logic gate module, so that the clock pins of the parallel DAC chips are configured through the WR pin of the microcontroller chip, thereby realizing multi-channel parallel DAC configuration based on microcontroller bus multiplexing.

[0012] According to the embodiment of the present disclosure, the model of the single-chip microcomputer chip is 80C32.

[0013] According to an embodiment of the present disclosure, the parallel DAC chip model is AD9764.

[0014] According to an embodiment of the present disclosure, an external random access memory is also included.

[0015] According to the embodiment of the present disclosure, the bus multiplexing refers to the address bus multiplexing of 80C32, and the level configuration during multiplexing is implemented based on the external access instruction of 80C32.

[0016] According to an embodiment of the present disclosure, the dedicated pin for external storage reading of the single-chip microcomputer chip is also multiplexed as a control pin.

[0017] According to the embodiment of the present disclosure, the WR pin or RD pin of the microcontroller is used for the DAC refresh control signal.

[0018] According to the embodiment of the present disclosure, the CLK signal of the DAC chip is outputted through the OR logic of the I / O port and the WR pin of the single-chip microcomputer chip.

[0019] According to the embodiment of the present disclosure, when reading multiple parallel ADCs based on the data bus multiplexing of the single-chip microcomputer chip 80C32, it can read up to 8-bit ADC values.

[0020] (III) Beneficial effects

[0021] It can be seen from the above technical solutions that the multi-channel parallel DAC configuration circuit structure based on single-chip bus multiplexing disclosed in the present invention has at least one or part of the following beneficial effects:

[0022] (1) The structure is simple and efficient, which is convenient for PCB board-level integration;

[0023] (2) The address bus multiplexing of the 80C32 microcontroller is cleverly utilized to realize the function of mounting multiple parallel DAC chips on a single 80C32 microcontroller and independently configuring them;

[0024] (3) Reliable and stable in timing, suitable for circuit design in high-level systems;

[0025] (4) It saves extra chips (such as I / O expansion chips), saves space and power consumption, and has better thermal performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The present invention is an overall block diagram of a multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing according to an embodiment of the present invention.

[0027] Figure 2 This is a timing diagram for configuring a single-chip microcomputer chip and a logic gate chip in a multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing in an embodiment of the present disclosure.

[0028] Figure 3This is a timing diagram of DAC chip configuration in a multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The present invention discloses a multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing, and a multi-channel parallel DAC configuration circuit design based on 80C32 single-chip microcomputer bus multiplexing, which can realize independent configuration of multiple parallel 14-bit DACs when only chip selection I / O port resources are needed.

[0030] Although with the continuous advancement of microelectronics technology, the resources of controller chips are increasing, but in the field of high-level, especially radiation-resistant level, single-chip microcomputers have always been favored by domestic engineers. The high-level version of the single-chip microcomputer has the advantages of radiation resistance, shock resistance, and a wide temperature range. At the same time, due to its fewer resources (I / O port resources), it also adds difficulty to engineering circuit design. This disclosure mainly solves the problem of insufficient I / O port resources encountered by the 80C32 single-chip microcomputer when configuring parallel DAC. The block diagram is shown below, and the specific example takes the AD9764 chip as an example. Figure 1 The 80C32 MCU implements independent configuration of two AD9764 chips through address bus multiplexing and OR logic gate chip 54AC32 on the basis of configuring external ROM. Regarding the timing of configuring AD9764, the timing of reading external RAM by 80C32 MCU is used, that is, the WR pin is cleverly used to configure the clock pin of AD9764. The specific chip select enable of AD9764 is realized by using other I / O ports and WR pin to do OR logic calculation.

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0032] In an embodiment of the present disclosure, a multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing is provided, such as Figure 1 As shown, the multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing includes:

[0033] The single-chip microcomputer module includes a single-chip microcomputer chip;

[0034] External read-only memory;

[0035] A latch module, the input of which is connected to an I / O port of the microcontroller chip;

[0036] A logic gate module, one input end of which is connected to another I / O port of the single-chip microcomputer chip, and the other input end of which is connected to the write-end pin of the single-chip microcomputer chip; and

[0037] The DAC module includes two parallel DAC chips, the clock pins of the two DAC chips are respectively connected to the output end of the logic gate module, so that the clock pins of the parallel DAC chips are configured through the WR pin of the microcontroller chip, thereby realizing multi-channel parallel DAC configuration based on microcontroller bus multiplexing.

[0038] like Figure 1 As shown, the multi-channel parallel DAC configuration circuit structure based on single-chip bus multiplexing includes the minimum system of 80C32 single-chip microcomputer, parallel DAC (taking AD9764 as an example) data configuration based on bus multiplexing, and DAC conversion controlled by combinational logic based on additional I / O port and WR dedicated pin. The minimum system of 80C32 single-chip microcomputer involved in the present disclosure includes a latch chip (54AC573) and an external read-only memory chip (ROM / PROM), and an additional random access chip (RAM) can also be mounted.

[0039] The embodiments of the present disclosure can realize 80C32 independently configuring multiple 14-bit parallel DACs, and further, can also be replaced with other single-chip microcomputers.

[0040] The parallel DAC data configuration and timing control based on bus multiplexing proposed in the present disclosure are exemplified by a specific case. Figure 2 and Figure 3 The following are the timing diagrams of the 80C332 microcontroller reading external memory and the configuration timing diagram of the AD9764 (a 14-bit parallel DAC chip). The main configuration process is as follows:

[0041] The DAC chip is selected through other I / O port operations. The figure shows the selection of the P2 port pin. Pulling it low is selection, and pulling it high is disable.

[0042] 80C32 performs external data writing operation, and the software programming C language is:

[0043] XBYTE[addr]=data;

[0044] and Figure 2 The timing in corresponds to the address addr is A15-A0, and the written data data is D7-D0. The level logic output by the WR pin is output to the CLK pin of the AD9764 through the OR logic gate together with the I / O strobe terminal. Figure 3 It is known that AD9764 performs digital-to-analog conversion on the rising edge of CLK, that is, it performs digital-to-analog conversion on the rising edge of WR (it passes through the or logic gate chip in the middle, the timing edge is very small and can be ignored here). Therefore, the lower eight bits of addr, i.e. A7-A0 and D7-D0, are the same, which can realize the function of configuring the input port of AD9764 to A13-A0.

[0045] Delay a few clock cycles and wait for the AD9764 to stabilize after conversion before waiting for the next operation.

[0046] To perform timing stability analysis:

[0047] This paper mainly demonstrates whether the timing configuration of AD9764 meets the timing requirements of its chip. Figure 2 and Figure 3 Timing analysis shown. Figure 3 For the configuration timing of AD9764, its main timing requirements are three points:

[0048] Before the rising edge of the CLK clock arrives, the input data D13-D0 needs to be maintained for a period of time, that is, t s >2ns.

[0049] The CLK clock pulse width needs to be greater than a certain value, that is, t LPW >4.5ns.

[0050] After the rising edge of the CLK clock, a specific time needs to be maintained until the digital-to-analog conversion is completed, that is, t PD >6ns.

[0051] Likewise, Figure 2 The timing in can be obtained according to the 80C32 microcontroller manual:

[0052] (1) The setup time of data D7-D0 relative to the rising edge of WR is t DL +t PW >200ns. Therefore, the above condition 2 is met, t LPW =t DL +t PW >200ns>4.5ns.

[0053] (2) The hold time after the WR rising edge is greater than 20ns, that is, the requirements of conditions 1 and 3 above are met at the same time.

[0054] According to the embodiment of the present disclosure, bus multiplexing refers to the multiplexing of the address bus of 80C32, and the level configuration during multiplexing is implemented based on the external access instruction of 80C32. Furthermore, the external storage read dedicated pin WR of 80C32 is also multiplexed as a control pin. Multiple parallel DAC configuration, in which the data configuration of all DACs is multiplexed with the address bus, and the WR pin or RD pin is the DAC refresh control signal. Furthermore, to realize the independent configuration of multiple DACs, it is also necessary to use other I / O ports, and the summary is attached. Figure 1The example given here is that the CLK signal of AD9764 is outputted by the OR logic of P1 port and WR pin. The same method can also be used to read multiple ADCs. In this case, it is based on the multiplexing of 80C32 data bus to read multiple parallel ADCs, which can read up to 8-bit ADC values.

[0055] In summary, this solution will not have any timing problems in theory, is very practical, and has been successfully applied to engineering projects.

[0056] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0057] Based on the above description, those skilled in the art should have a clear understanding of the multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing disclosed in the present invention.

[0058] In summary, the present invention provides a multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing. It is mainly aimed at the situation that the port resources of the single-chip microcomputer are insufficient when configuring the parallel DAC chip. A solution for configuring the multi-channel parallel DAC chip based on the address bus multiplexing method is proposed, which realizes the function of mounting multiple parallel DAC chips on a single microcontroller and configuring them independently, saves space and power consumption, and has better thermal performance.

[0059] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. In addition, the shapes and sizes of the components in the drawings do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0060] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0061] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0062] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing, comprising: The single-chip microcomputer module includes a single-chip microcomputer chip; External read-only memory; A latch module, the input of which is connected to an I / O port of the microcontroller chip; A logic gate module, one input end of which is connected to another I / O port of the single-chip microcomputer chip, and the other input end of which is connected to the write-end pin of the single-chip microcomputer chip; as well as The DAC module includes two parallel DAC chips, the clock pins of the two DAC chips are respectively connected to the output end of the logic gate module, so that the clock pins of the parallel DAC chips are configured through the WR pin of the microcontroller chip, thereby realizing multi-channel parallel DAC configuration based on microcontroller bus multiplexing.

2. According to the multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing according to claim 1, the model of the single-chip microcomputer chip is 80C32.

3. According to the multi-channel parallel DAC configuration circuit structure based on single-chip computer bus multiplexing as claimed in claim 1, the parallel DAC chip model is AD9764.

4. The multi-channel parallel DAC configuration circuit structure based on single-chip computer bus multiplexing according to claim 1 further includes an external random access memory.

5. According to the multi-channel parallel DAC configuration circuit structure based on single-chip computer bus multiplexing as claimed in claim 2, the bus multiplexing refers to the address bus multiplexing of 80C32, and the level configuration during multiplexing is implemented based on the external access instruction of 80C32.

6. According to the multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing as claimed in claim 5, the external storage reading dedicated pin of the single-chip microcomputer chip is also multiplexed as a control pin.

7. According to the multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing as claimed in claim 2, the WR pin or RD pin of the single-chip microcomputer chip is used for the DAC refresh control signal.

8. According to the multi-channel parallel DAC configuration circuit structure based on single-chip microcomputer bus multiplexing as claimed in claim 2, the CLK signal of the DAC chip is outputted through the OR logic of the I / O port and the WR pin of the single-chip microcomputer chip.

9. According to the multi-channel parallel DAC configuration circuit structure based on single-chip computer bus multiplexing as claimed in claim 1, when reading the multi-channel parallel ADC based on the data bus multiplexing of the single-chip computer chip 80C32, it can read up to 8-bit ADC value.

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