A link delay compensation method, device, equipment and computer storage medium

Abstract

The embodiment of the present application provides a link time delay compensation method, device, equipment and computer storage medium, the method comprises: obtaining the timestamp of a link, and obtaining the performance value of the link port according to the timestamp; determining the actual length of the link according to the performance value; obtaining the asymmetric compensation value according to the actual length, the sending wavelength and the receiving wavelength; and compensating the time delay of the link according to the asymmetric compensation value. According to the link time delay compensation method of the embodiment of the present application, the actual length of the link is determined by obtaining the timestamp in the link, the asymmetric compensation value is obtained according to the actual length of the link, the time synchronization time delay of the single-fiber bidirectional link can be compensated, and the precision of the time synchronization system is improved.

Description

Technical Field

[0001] This application belongs to the field of communication network clock synchronization technology, and particularly relates to a link delay compensation method, device, equipment and computer storage medium. Background Technology

[0002] Currently, the clock synchronization protocol used in communication networks is the 1588v2 protocol. 1588v2 can synchronize clocks operating independently on separate nodes within a measurement and control system to the same precision and accuracy. These clocks communicate with each other within a communication network, and all clocks ultimately obtain their time from the highest-level clock (GMC). A network or synchronization link has a master clock and a slave clock at its two ends. The master (clock) periodically sends synchronization messages carrying its own clock information, and the slave (clock) extracts the clock information from the messages and uses this information to continuously correct its own clock. The theoretical premise for 1588v2 to achieve high-precision time synchronization is that the network carrying the 1588v2 protocol packets must be a symmetrical network, meaning the transmission delay from master to slave is equal to the transmission delay from slave to master. If the network is asymmetrical, then there will be a deviation Δdelay between the transmission delay from master to slave and the transmission delay from slave to master.

[0003] In existing technologies, to ensure network symmetry, a single-fiber bidirectional optical module is introduced to build a time synchronization link, allowing the 1588V2 transmit and receive signals to travel on the same optical fiber, ensuring that the transmit and receive fiber lengths are consistent. Although this ensures consistent fiber lengths, the wavelengths of the transmit and receive signals emitted by the combined transmit and receive optical module are different. Light of different wavelengths will have different transmission delays on the same optical fiber. As the transmission distance and segments increase, the deviation will also increase. Moreover, as the time signal is transmitted from the core through aggregation to the access point, the deviation will accumulate, and the time synchronization system will be unable to meet the accuracy requirements of time synchronization.

[0004] Therefore, how to provide a link delay compensation method that can compensate for the time synchronization delay of a single-fiber bidirectional link and improve the accuracy of the time synchronization system is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a link delay compensation method, apparatus, device, and computer storage medium, which can compensate for the time synchronization delay of a single-fiber bidirectional link and improve the accuracy of the time synchronization system.

[0006] In a first aspect, embodiments of this application provide a link delay compensation method, the method comprising:

[0007] Obtain the timestamp of the link and get the performance value of the link port based on the timestamp;

[0008] Determine the actual length of the link based on performance values;

[0009] The asymmetric compensation value is obtained based on the actual link length, transmission wavelength, and reception wavelength;

[0010] The link delay is compensated based on the asymmetric compensation value.

[0011] Furthermore, based on the actual length, transmitting wavelength, and receiving wavelength, the asymmetry compensation value is obtained, including:

[0012] The actual length, transmitting wavelength, receiving wavelength, and asymmetric compensation value satisfy the following relationship:

[0013]

[0014]

[0015] Where Δdelay is the time delay deviation, Δt is the asymmetric compensation value, L is the actual length of the link, λ2 and λ1 are the transmitting and receiving wavelengths, and λ, k, d and b are constants.

[0016] Furthermore, it also includes: the receiving wavelength and the transmitting wavelength of the link are switched every hop.

[0017] Furthermore, the link mode is boundary clock mode.

[0018] Furthermore, the actual length of the link is determined based on performance values, including:

[0019] Determine whether the actual length of the link meets the compensation link length threshold;

[0020] When the actual length of the link meets the compensation link length threshold, delay compensation is performed on the link.

[0021] Secondly, embodiments of this application provide a link delay compensation device, the device comprising:

[0022] The acquisition module is used to obtain the timestamp of the link and obtain the performance value of the link port based on the timestamp;

[0023] The determination module is used to determine the actual length of the link based on performance values.

[0024] The calculation module is also used to obtain the asymmetry compensation value based on the actual length, transmission wavelength, and reception wavelength;

[0025] The compensation module is used to compensate for the link delay based on the asymmetric compensation value.

[0026] Furthermore, it includes a wavelength switching module for switching the receive wavelength and transmit wavelength of the link every hop.

[0027] Furthermore, the determination module is also used to determine whether the actual length of the link meets the compensation link length threshold.

[0028] Thirdly, embodiments of this application provide a link delay compensation device, the device including: a processor, and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the link delay compensation method as described above.

[0029] Fourthly, embodiments of this application provide a computer storage medium storing computer program instructions, which, when executed by a processor, implement the link delay compensation method described above.

[0030] The link delay compensation method, apparatus, device, and computer storage medium of this application, by obtaining the timestamp in the link, determine the actual length of the link, and obtain an asymmetric compensation value based on the actual length of the link, can compensate for the time synchronization delay of a single-fiber bidirectional link and improve the accuracy of the time synchronization system. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart illustrating a link delay compensation method provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the working principle of the 1588V2;

[0034] Figure 3 This is a graph showing the relationship between dispersion and transmission delay in G.652 optical fiber.

[0035] Figure 4 This is a schematic diagram of a 1588V2 time synchronization link constructed according to a combination of long and short wavelength intervals provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of a link delay compensation device provided in an embodiment of this application;

[0037] Figure 6This is a schematic diagram of the hardware structure of a link delay compensation device provided in an embodiment of this application. Detailed Implementation

[0038] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0039] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0040] Existing technologies introduce single-fiber bidirectional optical modules to build time synchronization links, allowing the 1588V2 transmit and receive signals to travel on the same optical fiber. While this ensures consistent fiber lengths and enables high-precision time synchronization signals, the transmit and receive wavelengths of the combined optical module are different. Different wavelengths of light have different transmission delays on the same fiber. Although the deviation per kilometer is small, it still introduces a significant deviation over long distances. Moreover, this deviation accumulates as the signal travels from the core through aggregation to the access point. If this deviation cannot be adequately compensated for, the time synchronization system will be unable to meet the requirements of ultra-high precision time synchronization, especially in certain 5G inter-site collaborative application scenarios.

[0041] The technical solution provided in this application is based on delay compensation for single-fiber bidirectional links.

[0042] To address the problems in the prior art, embodiments of this application provide a link delay compensation method, apparatus, device, and computer storage medium. Based on a single-fiber bidirectional link, the delay compensation value is calculated and compensation is performed using the timestamp carried in the 1588V2 protocol packet and the known transmit and receive wavelengths of the link.

[0043] The link delay compensation method provided in the embodiments of this application will be described below. Please refer to... Figures 1 to 2 , Figure 1 This is a flowchart illustrating a link delay compensation method provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the working principle of the 1588V2.

[0044] S1: Obtain the timestamp of the link and get the performance value of the link port based on the timestamp.

[0045] like Figure 2 As shown in the 1588V2 working principle diagram, t2 and t1 are timestamps carried in the 1588V2 protocol packet. After the 1588V2 protocol is enabled on the synchronous link port, the device gateway can collect the performance values ​​of t2-t1 on the synchronous link port, that is, the performance values ​​of the link port.

[0046] S2: Determine the actual length of the link based on the performance values.

[0047] The synchronization link is built using a combined transceiver optical module, so the transmission and reception of the 1588V2 synchronization signal travel on the same optical fiber. There is no deviation caused by different fiber lengths; the only deviation is the time difference due to the different wavelengths of the transmitted and received signals. This deviation is related not only to the transmission and reception wavelengths but also directly to the length of the optical fiber carrying the synchronization link. Based on the t2 and t1 performance values ​​of each link segment obtained in step S1, the actual length L of the (this hop of fiber synchronization) link connection can be calculated.

[0048] S3: Obtain the asymmetry compensation value based on the actual length, transmission wavelength, and reception wavelength.

[0049] Based on the relationship between fiber dispersion and transmission delay, using the length L of the fiber in each hop of the synchronous link obtained in step S2 and the known wavelength information of the transmitted and received signals, the delay deviation in the two directions of each hop of the synchronous link can be calculated, and the asymmetric compensation value can be obtained.

[0050] S4: Compensate for link delay based on asymmetric compensation value.

[0051] The compensation value is applied to both ports of the synchronous link, and the corresponding asymmetric compensation value is sent to the optical interface receiving wavelength λ2 and the optical port receiving wavelength λ1 at the other end.

[0052] Please refer to Figure 3 , Figure 3 This is a graph showing the relationship between dispersion and transmission delay in G.652 optical fiber. In one or more embodiments of this application, the asymmetry compensation value is obtained based on the actual length, the transmitting wavelength, and the receiving wavelength, including:

[0053] The actual length, the transmitting wavelength, the receiving wavelength, and the asymmetric compensation value satisfy the following relationship:

[0054]

[0055]

[0056] Where Δdelay is the time delay deviation, Δt is the asymmetric compensation value, L is the actual length of the link, λ2 and λ1 are the transmitting wavelength and the receiving wavelength, k is the dispersion slope, the horizontal axis is the wavelength λ, the vertical axis is the dispersion coefficient d, and b is a constant.

[0057] In one or more embodiments of this application, the receiving wavelength and the transmitting wavelength of the link are exchanged every hop.

[0058] In existing technologies, manual compensation via hop-by-hop measurement significantly increases initial setup costs. Especially at ultra-high precision levels, measuring instruments struggle to acquire higher-precision time source signals for reference. Using common-mode, common-view technology requires excellent telescope conditions in the tested equipment room, allowing simultaneous viewing of multiple satellites (a condition most aggregation equipment rooms lack), resulting in high measurement costs and immense difficulty. Furthermore, if fiber optic splicing or other operations are performed during subsequent fiber optic maintenance, the compensation values ​​must be readjusted, adding considerable complexity and cost to later maintenance. Therefore, manual compensation via hop-by-hop measurement significantly increases costs, particularly at high precision levels, requiring excellent telescope conditions in the tested equipment room, making measurement extremely difficult, and resulting in high construction, measurement, and subsequent maintenance costs.

[0059] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a 1588V2 time synchronization link constructed according to a combination of long and short wavelength intervals provided in an embodiment of this application.

[0060] The network's time synchronization link is built using a combined transceiver optical module (λ1 and λ2 represent different optical wavelengths), with the transmit and receive time synchronization signals carried on the same optical fiber. The time source signal is injected into the network through backbone layer equipment and, using the 1588V2 protocol, is transmitted to end users through the synchronization link of the backbone-aggregation-access layer network. When building the 1588V2 synchronization link, avoid using a networking configuration where the downlink is all short wavelengths and the uplink is all long wavelengths (or vice versa). Instead, use an interleaved deployment of long and short wavelength optical modules in the upstream and downstream synchronization links to avoid the linear accumulation of transmit and receive asymmetry caused by different wavelengths, thereby effectively improving the time accuracy of 1588V2.

[0061] For example, when using a transceiver optical module to build a time synchronization link, if according to Figure 4 The wavelength allocation method in the left diagram uses wavelength λ1 for each hop from the backbone to the access direction and wavelength λ2 for the opposite direction. This is convenient for construction and management, but it causes the error due to asymmetry to accumulate hop by hop (assuming the first hop brings a positive deviation, every subsequent hop brings a positive deviation, so the accumulated deviation will increase with the number of hops). However, if the wavelength allocation method in the right diagram is used, the first hop from the backbone to the access direction uses λ1 for transmission and λ2 for reception, the second hop reverses this to λ2 for transmission and λ1 for reception, and this trend continues downstream. Thus, assuming the first hop brings a positive deviation, the second hop brings a negative deviation, the third hop brings a positive deviation, and so on. The accumulated deviation downstream will partially cancel out by the positive and negative values, unlike the left-side networking method which increases linearly with the number of hops (where all values ​​are positive or negative).

[0062] Therefore, by constructing a 1588V2 time synchronization link according to the long and short wavelength interval combination method provided in this embodiment, and by exchanging the receiving wavelength and transmitting wavelength of the link every hop, the above problems can be effectively solved.

[0063] In one or more embodiments of this application, based on the above steps, the mode of the link is set to boundary clock mode (BC mode).

[0064] After setting up the time synchronization link according to the above rules, some of the asymmetric deviations can be offset.

[0065] After the synchronous link is established, enable the 1588V2 protocol on the synchronous link port, and set all network devices that transmit 1588V2 protocol packets to BC mode.

[0066] In one or more embodiments of this application, it is determined whether the actual length of the link meets the compensation link length threshold; when the actual length of the link meets the compensation link length threshold, delay compensation is performed on the link.

[0067] Select the synchronization set that requires automatic asymmetric compensation. The time delay deviation per kilometer caused by different wavelengths of light transmitting in optical fiber is very small, and compensation is only needed for long distances. Therefore, links connecting to the ports of equipment within the same local office do not require compensation, and these links are not included in the set of synchronization links requiring automatic asymmetric compensation.

[0068] Therefore, according to the technical solution provided in this embodiment, selecting a link whose actual length meets the preset compensation link length threshold for compensation can effectively reduce manpower and material costs.

[0069] Figure 5 This is a schematic diagram of a link delay compensation device provided in an embodiment of this application. Figure 5 As shown, the device may include an acquisition module 210, a determination module 220, and a compensation module 230.

[0070] The acquisition module 210 is used to acquire the timestamp of the link and obtain the performance value of the link port based on the timestamp. The working process of the acquisition module 210 can be found in [reference needed]. Figure 1 Step S1.

[0071] The determination module 220 is used to determine the actual length of the link based on the performance value. The operation process of the determination module 220 can be found in [reference needed]. Figure 1 Step S2.

[0072] The compensation module 230 is used to compensate for the link delay based on the asymmetric compensation value. The operation of the compensation module 230 can be found in [reference needed]. Figure 1 Step S4.

[0073] Furthermore, the device may also include a wavelength switching module 200 for switching the received wavelength and the transmitted wavelength of the link per hop.

[0074] Figure 5 Each module in the illustrated device has the ability to implement Figure 1 The functions of each step in the process and their corresponding technical effects are described in detail here for the sake of brevity.

[0075] Figure 6 A schematic diagram of the hardware structure of a link delay compensation device provided in an embodiment of this application is shown.

[0076] The link delay compensation device may include a processor 301 and a memory 302 storing computer program instructions.

[0077] Specifically, the processor 301 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0078] Memory 302 may include mass storage for data or instructions. For example, and not limitingly, memory 302 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. In one instance, memory 302 may include removable or non-removable (or fixed) media, or memory 302 may be non-volatile solid-state memory. Memory 302 may be internal or external to the integrated gateway disaster recovery device.

[0079] The processor 301 reads and executes computer program instructions stored in the memory 302 to achieve... Figure 1 The methods / steps S1 to S4 in the illustrated embodiments achieve the following: Figure 1 The technical effects achieved by executing the methods / steps shown in the examples are not elaborated here for the sake of brevity.

[0080] In one example, the link delay compensation device may further include a communication interface 303 and a bus 310. Wherein, as Figure 6 As shown, the processor 301, memory 302, and communication interface 303 are connected through bus 310 and complete communication with each other.

[0081] The communication interface 303 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0082] Bus 310 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 310 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0083] This link delay compensation device can determine the actual length of the link by obtaining the timestamp in the link, obtain an asymmetric compensation value based on the actual length of the link, and execute the link delay compensation method in this embodiment of the application, thereby achieving a combination of... Figure 1 The link delay compensation method is described.

[0084] Furthermore, in conjunction with the link delay compensation methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the link delay compensation methods in the above embodiments.

[0085] The link delay compensation method according to the embodiments of this application obtains the timestamp in the link, determines the actual length of the link, and obtains the asymmetric compensation value based on the actual length of the link. This method can compensate for the time synchronization delay of a single-fiber bidirectional link and improve the accuracy of the time synchronization system.

[0086] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0087] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0088] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0089] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0090] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A link delay compensation method, characterized in that, include: Obtain the timestamp of the link, and obtain the performance value of the port of the link based on the timestamp; The actual length of the link is determined based on the performance value; The asymmetric compensation value is obtained based on the actual length, transmission wavelength, and reception wavelength. The latency of the link is compensated based on the asymmetric compensation value; The actual length, the transmitting wavelength, the receiving wavelength, and the asymmetric compensation value satisfy the following relationship: Where △delay is the time delay deviation, △t is the asymmetric compensation value, L is the actual length of the link, λ2 and λ1 are the transmitting wavelength and the receiving wavelength, k is the dispersion slope, λ is the wavelength, b is the dispersion coefficient, and d is the differential sign.

2. The link delay compensation method according to claim 1, characterized in that, The method further includes: The receive wavelength and the transmit wavelength of the link are swapped every hop.

3. The time delay compensation method according to claim 1, characterized in that, The link operates in boundary clock mode.

4. The link delay compensation method according to claim 1, characterized in that, Determining the actual length of the link based on the performance value includes: Determine whether the actual length of the link meets the compensation link length threshold; When the actual length of the link meets the compensation link length threshold, delay compensation is performed on the link.

5. A link delay compensation device, characterized in that, The device includes: The acquisition module is used to acquire the timestamp of the link and obtain the performance value of the port of the link based on the timestamp; A determining module is used to determine the actual length of the link based on the performance value; and to obtain an asymmetric compensation value based on the actual length, the transmitting wavelength, and the receiving wavelength. The compensation module is used to compensate for the delay of the link based on the asymmetric compensation value; The actual length, the transmitting wavelength, the receiving wavelength, and the asymmetric compensation value satisfy the following relationship: Where △delay is the time delay deviation, △t is the asymmetric compensation value, L is the actual length of the link, λ2 and λ1 are the transmitting wavelength and the receiving wavelength, k is the dispersion slope, λ is the wavelength, b is the dispersion coefficient, and d is the differential sign.

6. The link delay compensation device according to claim 5, characterized in that, The device further includes: A wavelength switching module is used to switch the received wavelength and the transmitted wavelength of the link every hop.

7. The link delay compensation device according to claim 5, characterized in that, The determining module is specifically used for: Determine whether the actual length of the link meets the compensation link length threshold; When the actual length of the link meets the compensation link length threshold, delay compensation is performed on the link.

8. A link delay compensation device, characterized in that, The device includes: a processor and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the link delay compensation method as described in any one of claims 1-4.

9. A computer storage medium, characterized in that, The computer storage medium stores computer program instructions, which, when executed by a processor, implement the link delay compensation method as described in any one of claims 1-4.

Images