Semiconductor layout environment around points of interest

Abstract

Systems and methods for analyzing a semiconductor layout design around a point of interest (POI) are disclosed. The semiconductor layout design is a representation of an integrated circuit based on the planar geometry of components that make up the integrated circuit and is used to manufacture the integrated circuit. The layout design can be analyzed using one or more POI-based methods to determine whether to modify the layout design. In one POI-based method, a set of kernels customized for a downstream application are convolved with a representation of the layout design around or surrounding the POI to generate a feature code associated with the POI. In turn, the feature code can be analyzed based on the downstream application. Another POI-based method includes analyzing geometric parameters associated with the POI, which can be used during a design phase to identify and modify problem areas in the layout design.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor layout analysis, and more specifically, to determining the semiconductor layout environment around a point of interest. Background Technology

[0002] Electronic circuits (such as integrated microcircuits) are used in a wide variety of products, from automobiles to microwave ovens to personal computers. Designing and fabricating integrated circuit devices typically involves many steps, sometimes referred to as a “design flow.” Specific steps in the design flow often depend on the type of integrated circuit, its complexity, the design team, and the integrated circuit manufacturer or foundry that will fabricate the microcircuit. Software “tools” and hardware “tools” are typically used to validate the design at various stages of the design flow by running software simulators and / or hardware simulators. These steps help identify errors in the design and allow designers and engineers to correct or otherwise improve it.

[0003] For example, a layout design (which may be interchangeably referred to as a layout) can be derived from an electronic circuit design. A layout design can include integrated circuit (IC) layout, IC mask layout, or mask design. Specifically, a layout design can be a representation of the planar geometry of an integrated circuit corresponding to a pattern of metal, oxide, or semiconductor layers that constitute the components of the integrated circuit. A layout design can be for the entire chip or a part of a full-chip layout design.

[0004] Typically, modeling and simulation applications analyze the layout design around a Point of Interest (POI), the manufacturing behavior of the layout design around the POI, and first-principles information about the process physics of the associated layers. As an example, a POI can include a point in the layout design with coordinates (x, y).

[0005] Traditionally, the environment of a layout design is captured as some form of image or graph, with modeling and simulation applications focusing on the image or graph as part of the necessary analysis. Additionally, process physics is captured as engineering data and formula entries. However, because layout designs can be extremely complex, with each design potentially containing billions of layout pattern graphs, such analysis presents a challenge in terms of computational time and memory requirements. Summary of the Invention

[0006] In one embodiment, a computer-implemented method is disclosed for analyzing multiple points of interest (POIs) in a semiconductor layout design for a downstream application. The method includes: acquiring one or more kernels based on the downstream application; when the one or more kernels are convolved with a representation of the semiconductor layout design, the one or more kernels extract at least one feature associated with the plurality of POIs, the extracted at least one feature being used by the downstream application; for a corresponding POI among the plurality of POIs, convolving the one or more kernels with the representation of the semiconductor layout design to generate a feature code for the corresponding POI, the feature code including a numerical representation indicating the extracted at least one feature associated with the corresponding POI; and analyzing the feature code for the extracted at least one feature associated with the corresponding POI based on the downstream application.

[0007] In another embodiment, a system for analyzing multiple Points of Interest (POIs) in a semiconductor layout design for a downstream application is disclosed. The system includes one or more processors programmed to perform the following methods: acquiring one or more kernels based on the downstream application; extracting at least one feature associated with the plurality of POIs when the one or more kernels are convolved with a representation of the semiconductor layout design, the extracted at least one feature being used by the downstream application; for a corresponding POI among the plurality of POIs, convolving the one or more kernels with the representation of the semiconductor layout design to generate a feature code for the corresponding POI, the feature code including a numerical representation indicating the extracted at least one feature associated with the corresponding POI; and analyzing the feature code for the extracted at least one feature associated with the corresponding POI based on the downstream application.

[0008] In another embodiment, one or more non-transitory computer-readable media are disclosed, storing computer-executable instructions that, when executed, cause one or more processors to analyze a plurality of Points of Interest (POIs) in a semiconductor layout design for a downstream application. Specifically, when executed, the computer-executable instructions cause the one or more processors to perform the following operations: obtain one or more kernels based on the downstream application; when the one or more kernels are convolved with a representation of the semiconductor layout design, the one or more kernels extract at least one feature associated with the plurality of POIs, the extracted at least one feature being used by the downstream application; for a corresponding POI among the plurality of POIs, convolve the one or more kernels with the representation of the semiconductor layout design to generate a feature code for the corresponding POI, the feature code including a numerical representation indicating the extracted at least one feature associated with the corresponding POI; and analyze the feature code for the extracted at least one feature associated with the corresponding POI based on the downstream application.

[0009] In another embodiment, a computer-implemented method is disclosed for analyzing multiple points of interest (POIs) in a semiconductor layout design for a downstream application. The method includes: for a given POI, obtaining values ​​of one or more geometric parameters relating to a polygon of the given POI and to at least one other polygon in the environment surrounding the given POI; and analyzing the values ​​of the one or more geometric parameters based on the downstream application.

[0010] In another embodiment, a system for analyzing multiple points of interest (POIs) in a semiconductor layout design for a downstream application is disclosed. The system includes one or more processors programmed to perform the following methods: for a given POI, obtaining values ​​of one or more geometric parameters relating to a polygon of the given POI and to at least one other polygon in the environment surrounding the given POI; and analyzing the values ​​of the one or more geometric parameters based on the downstream application.

[0011] In another embodiment, one or more non-transitory computer-readable media are disclosed, storing computer-executable instructions that, when executed, cause one or more processors to analyze multiple Points of Interest (POIs) in a semiconductor layout design for a downstream application. Specifically, when executed, the computer-executable instructions cause the one or more processors to perform the following operations: for a given POI, obtaining values ​​of one or more geometric parameters relating to a polygon of the given POI and at least one other polygon in the environment surrounding the given POI; and analyzing the values ​​of the one or more geometric parameters based on the downstream application. Attached Figure Description

[0012] Various aspects of the invention are illustrated in conjunction with the accompanying drawings, which are incorporated in and form part of this specification, and serve to explain its principles. For convenience, the same reference numerals will be used throughout the drawings to denote the same or similar elements.

[0013] Figure 1 Examples of computing systems that can be used to implement various embodiments of the disclosed techniques are shown.

[0014] Figure 2 Examples of multi-core processor units are shown that can be used to implement various embodiments of the disclosed techniques.

[0015] Figure 3 It is a flowchart for generating signatures by convolving the kernel with a representation of the layout design and analyzing the signatures for downstream applications (e.g., to determine feature matches).

[0016] Figure 4 This is a flowchart of an example of analyzing signatures used in downstream applications.

[0017] Figure 5 This is a block diagram of an example of OPC analysis.

[0018] Figures 6A to 6I It is a series of diagrams that use feature codes to determine feature matching.

[0019] Figures 6J to 6L It is a set of three tophat kernels used for convolution.

[0020] Figure 6M This is a table showing the relationship between the number of output clusters and the clustering tolerance.

[0021] Figure 6N This is a table showing the relationship between the number of unique POIs and the radius of the convolution halo.

[0022] Figure 7 This is a flowchart used to obtain POI physical parameter inputs and analyze POI physical parameter inputs for downstream applications.

[0023] Figures 8A to 8B This is a flowchart illustrating an example of obtaining POI physical parameter input.

[0024] Figure 9 This is the first block diagram of an example of POI physical parameters.

[0025] Figures 10A to 10C This shows the layout designs for different examples of POIs.

[0026] Figure 11 This is a sample table of parameter values ​​associated with different POIs.

[0027] Figures 12A to 12O This is an example block diagram of the parameter values ​​associated with a POI. Detailed Implementation

[0028] General considerations

[0029] Various aspects of this disclosure relate to extracting features from a layout design and analyzing those features for downstream applications. Numerous details are set forth in the following description for purposes of explanation. However, those skilled in the art will recognize that the disclosed techniques can be implemented without using these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the techniques of this disclosure.

[0030] Some of the techniques described herein can be implemented in software instructions stored on one or more non-transitory computer-readable media, software instructions executed on a computer, or some combination of both. For example, some of the disclosed techniques can be implemented as part of an Electronic Design Automation (EDA) tool. This approach can be performed on a single computer or a networked computer.

[0031] Although the operations of the disclosed methods are described in a specific order for ease of presentation, it should be understood that this descriptive approach encompasses rearrangement unless the specific language used below requires a particular order. For example, in some cases, the sequentially described operations may be rearranged or performed concurrently. Furthermore, for simplicity, the disclosed flowcharts and block diagrams typically do not show the various ways in which a particular method can be combined with other methods. Additionally, the detailed description sometimes uses terms such as "execute," "generate," "acquire," and "determine" to describe the disclosed methods. Such terms are high-level abstractions of the actual operations performed. The actual operations corresponding to these terms will vary depending on the specific implementation and are readily discernible to those skilled in the art.

[0032] Furthermore, as used herein, the term "design" is intended to encompass data describing the entire integrated circuit device. However, the term is also intended to encompass smaller sets of data describing one or more components of the entire device (e.g., a portion of an integrated circuit device). Further still, the term "design" is also intended to encompass data describing more than one microdevice, such as data intended for forming multiple microdevices on a single wafer.

[0033] Explanatory operating environment

[0034] Various electronic design processes according to embodiments of the disclosed technology can be implemented using computer-executable software instructions executed by one or more programmable computing devices. Because these embodiments of the disclosed technology can be implemented using software instructions, the components and operation of a general-purpose programmable computer system on which various embodiments of the disclosed technology can be applied will be described first. Furthermore, due to the complexity of some electronic design processes and the large size of many circuit designs, various electronic design automation tools are configured to operate on computing systems capable of running multiple processing threads simultaneously. Therefore, reference will be made to… Figure 1 This describes the components and operation of a computer network having a host or master computer and one or more remote or slave computers. However, this operating environment is merely an example of a suitable operating environment and is not intended to imply any limitation on the scope or functionality of the disclosed technology.

[0035] exist Figure 1In this embodiment, computer network 101 includes a host computer 103. In the example shown, the host computer 103 is a multiprocessor computer including multiple input / output devices 105 and memory 107. Input / output devices 105 may include any means for receiving input data from a user or providing output data to a user. Input devices may include, for example, a keyboard, microphone, scanner, or pointing device for receiving input from a user. Output devices may then include a display monitor, speaker, printer, or haptic feedback device. These devices and their connections are well known in the art and will not be discussed in detail here.

[0036] The memory 107 can be similarly implemented using any combination of computer-readable media accessible by the host computer 103. Computer-readable media may include, for example, microcircuit memory devices, such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM), or flash memory microcircuit devices, CD-ROMs, digital video disks (DVDs), or other optical storage devices. Computer-readable media may also include non-magnetic and magnetic cassette tapes, magnetic tapes, magnetic disks or other magnetic storage devices, perforated media, holographic storage devices, or any other medium suitable for storing desired information.

[0037] As will be discussed in detail below, the main control computer 103 runs a software application for performing one or more operations according to various examples of the disclosed techniques. Accordingly, memory 107 stores software instructions 109A, which, when executed, implement the software application for performing one or more operations (such as those disclosed herein). Memory 107 also stores data 109B used with the software application. In the illustrated embodiment, data 109B contains processing data used by the software application to perform operations, at least some of which may be parallel.

[0038] The main control computer 103 also includes multiple processor units 111 and interface devices 113. The processor units 111 can be any type of processor device that can be programmed to execute software instructions 109A, but are typically microprocessor devices, graphics processing unit (GPU) devices, etc. For example, one or more processor units in the processor units 111 can be commercially available programmable microprocessors, such as... (Intel) or Xeon TM Microprocessors, Athlon from Advanced Micro Devices TM Microprocessor or Motorola 68K / Microprocessor. Alternatively or additionally, one or more processor units in processor unit 111 may be custom-manufactured processors, such as microprocessors designed to optimally perform specific types of mathematical operations, including those using application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Interface device 113, processor unit 111, memory 107, and input / output device 105 are connected together via bus 115.

[0039] In some implementations of the disclosed technology, the main control computer 103 may employ one or more processing units 111 having more than one processor core. Accordingly, Figure 2 An example of a multi-core processor unit that can be used with various embodiments of the disclosed technology is shown. As seen in the figure, processor unit 111 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As known to those skilled in the art, the computing engine includes logic means for performing various computational functions (e.g., fetching software instructions) and then executing actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers; performing logical operations such as AND, OR, NOR, and XOR; and retrieving data. Each computing engine 203 may then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0040] Each processor core 201 is connected to an interconnect 207. The specific configuration of the interconnect 207 may vary depending on the architecture of the processor unit 111. For some processor cores 201, such as unit microprocessors created by Sony Corporation, Toshiba Corporation, and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. However, for other processor units 111, such as the Opteron available from Advanced Micro Devices in Sunnyvale, California... TM and Athlon TMThe dual-core processor interconnect 207 can be implemented as a system request interface device. In any case, the processor core 201 communicates with the input / output interface 209 and the memory controller 210 via interconnect 207. The input / output interface 209 provides a communication interface between the processor unit 111 and the bus 115. Similarly, the memory controller 210 controls the exchange of information between the processor unit 111 and the system memory 107. In some embodiments of the disclosed technology, the processor unit 111 may include additional components, such as an accessible advanced cache memory shared by the processor core 201.

[0041] Although Figure 2 A diagram of a processor unit 111 that may be employed by some embodiments of the disclosed technology is shown; however, it should be understood that the diagram is merely representative and not intended to be limiting. Furthermore, for some implementations, a multi-core processor unit 111 may be used instead of multiple individual processor units 111. For example, alternative implementations of the disclosed technology may employ a single processor unit 111 with six cores, two multi-core processor units each with three cores, a multi-core processor unit 111 with four cores along with two individual single-core processor units 111, etc., instead of six individual processor units 111.

[0042] Now return to Figure 1 The interface device 113 allows the master computer 103 to communicate with the slave computers 117A, 117B, 117C...117x via a communication interface. The communication interface can be any suitable type of interface, including, for example, a conventional wired network connection or an optical transmission wired network connection. The communication interface can also be a wireless connection, such as a wireless optical connection, a radio frequency connection, an infrared connection, or even an acoustic connection. The interface device 113 converts data and control signals from the master computer 103 and each slave computer 117 into network messages according to one or more communication protocols, such as Transmission Control Protocol (TCP), User Datagram Protocol (UDP), and Internet Protocol (IP). These and other conventional communication protocols are well known in the art and will not be discussed in detail here.

[0043] Each slave computer 117 may include a memory 119, a processor unit 121, an interface device 123, and one or more optional input / output devices 125 connected together via a system bus 127. Similar to the master computer 103, the optional input / output devices 125 for the slave computers 117 may include any conventional input or output devices, such as a keyboard, pointing device, microphone, display monitor, speaker, and printer. Similarly, the processor unit 121 may be any type of conventional or custom-made programmable processor device. For example, one or more processor units in the processor unit 121 may be commercially available programmable microprocessors, such as... of or Xeon TM Microprocessors, Athlon from Advanced Micro Devices TM Microprocessor or Motorola 68K / Microprocessor. Alternatively, one or more processor units in processor unit 121 may be custom-manufactured processors, such as microprocessors designed to optimally perform specific types of mathematical operations, for example, using an ASIC or FPGA. Furthermore, one or more processor units in processor unit 121 may have more than one core, as referenced above. Figure 2 As described. For example, in some embodiments of the disclosed technology, one or more processor units 121 may be cell processors. The memory 119 may then be implemented using any combination of the aforementioned computer-readable media. Similar to interface device 113, interface device 123 allows slave computer 117 to communicate with master computer 103 via a communication interface.

[0044] In the example shown, the master computer 103 is a multiprocessor unit computer with multiple processor units 111, while each slave computer 117 has a single processor unit 121. However, it should be noted that alternative implementations of the disclosed technology may employ a master computer with a single processor unit 111. Furthermore, one or more slave computers 117 may have multiple processor units 121, depending on their intended use, as discussed previously. Additionally, although only a single interface device 113 or 123 for both the master computer 103 and the slave computers is shown, it should be noted that for alternative embodiments of the disclosed technology, computer 103, or one or more slave computers 117, or some combination of both, may use two or more different interface devices 113 or 123 to communicate through multiple communication interfaces.

[0045] For various examples of the disclosed technology, the host computer 103 may be connected to one or more external data storage devices. These external data storage devices may be implemented using any combination of computer-readable media accessible by the host computer 103. Computer-readable media may include, for example, microcircuit memory devices, such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM), or flash memory microcircuit devices, CD-ROMs, digital video disks (DVDs), or other optical storage devices. Computer-readable media may also include magnetic tape cassettes, magnetic tapes, disks, or other magnetic storage devices, perforated media, holographic storage devices, or any other medium suitable for storing desired information. According to some embodiments of the disclosed technology, one or more slave computers in slave computer 117 may alternatively or additionally be connected to one or more external data storage devices. Typically, these external data storage devices will include data storage devices that are also connected to the host computer 103, but they may also be different from any data storage device accessible by the host computer 103.

[0046] It should also be understood that Figure 1 and Figure 2 The description of the computer networks shown is provided by way of example only and is not intended to imply any limitation on the scope or functionality of alternative embodiments of the disclosed technology.

[0047] Layout environment around points of interest

[0048] As discussed in the background section, the analysis of the layout environment around a point of interest typically focuses on image analysis, such as edge-based pattern matching schemes. However, traditional image analysis highlights two problems. First, the datasets used for image analysis are identical in information density and are therefore limiting, especially for different types of layout environment analysis. For example, each pixel in a bitmap dataset represents the same information for each point in the image. In particular, a layout design can be described in a layout design file containing a set of polygons (e.g., graphics) representing what should be printed on a silicon wafer on a specific layer. An example of a layout design file includes a graphics file where each coordinate represents a simple point in a grid without capturing additional information, where data storage takes the form of image data of bitmaps or compressed bitmaps or a coordinate polygon database. These datasets are essentially single-parameter inputs (i.e., polygon layer coordinates / pixel) or a small number of parameters (i.e., multi-layer coordinates / pixel). Second, focusing on image analysis for pattern matching is computationally expensive and has inherent limitations.

[0049] As discussed in the background section, there may potentially be billions of patterns to be analyzed, creating bottlenecks in performance and similarity criteria (e.g., ambiguity). For example, existing edge-based pattern matching performs the analysis, but is limited to edge-based shifting in its similarity criteria. In particular, for several semiconductor manufacturing processes, edge-based pattern matching is currently used to identify repeating patterns, but it is limited to highly repetitive patterns and precise matching types (e.g., similar arrays), and cannot be applied to randomized logic designs. Furthermore, for hotspot detection, original edge-based pattern matching is used for known hotspots; however, this analysis cannot detect the probability of a hotspot in a newly seen pattern (unless the new pattern is very similar to a known hotspot). At this point, hotspot detection, which can rely on pixel-based matching techniques, is computationally and memory-intensive. Moreover, other analyses (including yield improvement or risk assessment) are limited when using original edge-based pattern matching methods.

[0050] Therefore, in one or more embodiments, one or both of the following are performed: (1) extending the information content associated with the POI in the layout environment beyond typical image analysis; and / or (2) customizing the information content associated with the POI for a specific downstream application and / or analyzing the information content associated with the POI (e.g., customizing information content about the POI for a specific downstream application and / or analyzing information content about the POI customized for a specific downstream application). In this way, modeling applications and / or simulation applications that rely on POI representations can be improved, as discussed in more detail below.

[0051] Furthermore, POI-based analysis can be performed at one or more stages of the development process. Example stages include, but are not limited to, the design and manufacturing stages. The design stage includes generating a layout design, during which the layout designer may not know or have considered manufacturing details (e.g., exposure details and process details). Conversely, the manufacturing stage includes analyzing / modifying the layout design, during which the manufacturer may know or consider exposure details (e.g., any one, any combination, or all of the following: image expressed as resist intensity; dosage; wavelength) and resist model details (e.g., any one, any combination, or all of the following: resist K-value or resist absorbance coefficient; resist film thickness; resist model kernel and threshold).

[0052] The information content / analysis associated with a Point of Interest (POI) can be used to extract features tailored for downstream applications, and more specifically, features tailored for downstream applications at specific stages of the development process. In one or more embodiments, one way to extract features associated with a POI is by using one or more kernels tailored for the downstream application, which are convolved with a representation of a layout design around or around the POI, to generate feature codes associated with the POI. As an example, during the manufacturing stage, given knowledge of some or all of the manufacturing details (e.g., exposure details and resist model details, or both), a kernel can be selected to extract features associated with the POI for execution of downstream applications during the manufacturing stage, as discussed in more detail below.

[0053] A kernel (which may be interchangeably referred to as a convolution matrix or mask) can comprise a matrix used to extract one or more features of the environment surrounding or around the POI. As discussed further below, convolutions can be performed using kernels with a fixed relationship to the POI (e.g., the center of the kernel coincides with the POI; the kernel is positioned relative to the POI, such as to the left, right, top, or bottom of the POI). The feature codes and the resulting values ​​generated from the convolutions of the environment surrounding the POI with the defined set of kernels can then be analyzed for downstream applications (e.g., for hotspot detection; OPC; etc.). In other embodiments, another approach to extracting features associated with the POI is performed using one or more parameters that include measurements related to or associated with the POI. As discussed further below, the obtained parameters (e.g., different sets of parameters for different types of POIs and / or for different downstream applications) and / or the analysis of the parameters can be customized for the downstream application.

[0054] Various downstream applications have been conceived, including: (1) Optical Proximity Correction (OPC), for example, for generating OPC correction values ​​(see, for example, U.S. Patent Application Publication No. 2014 / 0215416A1 and U.S. Patent Application Publication No. 2019 / 0155142A1, the entire contents of which are incorporated herein by reference); (2) Sub-Resolution Assist Feature (SRAF) placement; (3) Hotspot detection (see, for example, U.S. Patent Application Publication No. 2014 / 0089877A1 and U.S. Patent Application Publication No. 2019 / 0087526A1, the entire contents of which are incorporated herein by reference); and (4) redefining the objectives of layout design (e.g., layout reduction). Other downstream applications have been conceived.

[0055] Therefore, in one or more embodiments, feature codes (interchangeably referred to as feature vectors) are generated by convolving a set of kernels (e.g., a set of 2-D images) with a representation of the layout design (e.g., a grid). Specifically, the feature code comprises a set of values, each generated by convolving a corresponding kernel in the set with a portion of the grid (or another representation of the layout design). For example, the corresponding set of kernels may include a predetermined number of kernels, such as at least 2 kernels, at least 3 kernels, at least 4 kernels, at least 5 kernels, at least 10 kernels, at least 15 kernels, at least 20 kernels, at least 25 kernels, at least 30 kernels, at least 40 kernels, at least 50 kernels, and so on. The convolution of the kernel set yields a set of values ​​for the feature code (e.g., for a kernel set having a first kernel, a second kernel, and a third kernel, the convolution of the first kernel with the grid yields a first value, the convolution of the second kernel with the grid yields a second value, and the convolution of the third kernel with the grid yields a third value). Various types of kernels can be used, as discussed below. The kernels used for convolution can be selected to extract features relevant to specific downstream applications from the representation of the layout design. In this respect, different sets of kernels can be customized to extract different features relevant to different downstream applications.

[0056] As discussed in more detail below, one or more of the said kernel sets may be selected based on any one, any combination or all of the following: (1) the type of POI (e.g., whether the POI exists on the edge (e.g., line end) of a polygon in the layout design, or whether the POI exists inside a polygon in the layout design); (2) the downstream application; or (3) one or more aspects of the layout design (e.g., the type of technology (e.g., a first nm technology (e.g., 10 nm technology) convolved using a first kernel set and a second nm technology (e.g., 20 nm technology) convolved using a second kernel set, wherein the first kernel set is different from the second kernel set) and / or the type of layer (e.g., a first material layer (e.g., a metal layer) convolved using a first kernel set and a second material layer (e.g., diffusion) convolved using a second kernel set, wherein the first kernel set is different from the second kernel set)). For example, the first kernel set may be associated with OPC and can be used to generate corresponding signatures for POIs in the layout design, the second kernel set (different from the first kernel set) may be associated with hotspot detection and can be used to generate corresponding signatures for POIs in the layout design, and so on. As another example, the number of kernels or the type of kernels, or both, can depend on the downstream application. Specifically, a first downstream application focusing on an area closer to the POI can use fewer kernels (kernel 1 and kernel 2), while a second downstream application focusing on a larger area surrounding the POI can use more kernels (kernel 1, kernel 2, and kernel 3). Therefore, by using kernels, the information extracted from the layout design can be customized for the final analysis of the signatures.

[0057] The kernel can vary based on any, any combination of, or all of the following: shape (e.g., circular, toroidal, square, rectangular); orientation (e.g., orientation-dependent versus orientation-independent); size; function (e.g., a tophat kernel following a step function; a Gaussian kernel following a Gaussian distribution); or halo / extension (e.g., different kernels can be obtained to change the halo for the same function (e.g., a Gaussian kernel function)). As discussed in more detail below, accuracy can include a granularity metric and can be limited to sampling during the simulation of both the kernel and the layout.

[0058] As an example, a set of kernels (e.g., a hotspot detection kernel) can be orientation-independent (e.g., a set of concentric circles independent of the orientation of POIs in the layout design). Another set of kernels can be orientation-dependent (e.g., a kernel convolved with a portion of the mesh positioned directly to the left of the POI; a kernel convolved with a portion of the mesh positioned to the upper left or lower left of the POI; a kernel convolved with a portion of the mesh positioned to the right of the POI; a kernel convolved with a portion of the mesh positioned to the upper right or lower right of the POI; etc.). In this way, for example, kernels can generate different values ​​for horizontal polygons than for vertical polygons, as long as this characteristic is relevant to downstream applications. Furthermore, kernels can vary relative to each other (e.g., whether kernels in the set are mutually exclusive; whether kernels in the set at least partially overlap each other; the distance between kernels in the set; etc.). Therefore, unlike traditional pixel-based image analysis, the selection of a kernel set and the feature codes generated from the kernels can extract information content (e.g., one or more features) tailored to a specific downstream application (e.g., OPC and hotspot detection).

[0059] Furthermore, the generated signatures can be analyzed for specific downstream applications. A signature can include a series of values ​​or a set of values, as described above. In addition, as discussed above, various downstream applications are conceived, including but not limited to: quantifying the similarity of various graphs from different sources / layouts; OPC runtime acceleration by identifying duplicate (e.g., previously computed) solutions; new hotspot detection based on graph similarity to known hotspots in a graph library; Subresolution Assist Feature (SRAF) placement; and redefining the goals of layout design. In a first specific embodiment, analysis (e.g., precise and fuzzy clustering, graph search, and graph similarity) can be customized for specific downstream applications (e.g., OPC, hotspot detection, etc.). In a second specific embodiment, the analysis of signatures can be based on comparison with other signatures having known properties (e.g., signatures of known hotspots).

[0060] Various types of analysis have been conceived. In one type, feature codes (including a set of values ​​for each feature code) can be compared with other feature codes (e.g., other feature codes in the same layout design or other feature codes in a set of contrasting feature codes) to determine similarity. In another type, machine learning can be used for analysis. For example, one or more machine learning methods can be used to generate mathematical models for different downstream applications (e.g., an OPC mathematical model, which involves determining whether a corresponding feature code indicates "good geometry" or "bad geometry" based on feature codes generated to extract features related to OPC; a hotspot mathematical model, which is used to determine whether individual feature codes indicate "hotspots" or "good graphics" based on feature codes generated to extract features related to hotspot detection). In an example of training a hotspot mathematical model, the machine learning method can use a training dataset including feature code data corresponding to known hotspots and feature code data corresponding to known good graphics to generate the hotspot mathematical model.

[0061] In some embodiments, one or more geometric parameters associated with the POI (e.g., measurements anchored to the POI) can be used to capture the environment surrounding or associated with the POI. Subsequently, some or all of these geometric parameters can be analyzed for use by downstream applications. As discussed above, POI-based analysis can be performed at various stages of the development process. For example, during the design phase, the designer may not be aware of manufacturing details. In this respect, parametric POI-based methods can focus specifically on geometric parameters relevant to the POI's environment and can therefore be independent of manufacturing details (including being completely independent of exposure or process details used for manufacturing). In this way, parametric POI-based methods can perform one or both of the following during the design phase: (1) identifying potential problem design areas in the layout design; and / or (2) modifying identified problem design areas.

[0062] Performing a parametric POI-based approach during the design phase and before implementing another POI-based approach (such as the kernel POI-based approach discussed above) during the manufacturing phase can reduce the number and / or severity of potential problem design regions that may need to be addressed during the manufacturing phase. Therefore, parametric POI-based approaches, even when considering a more limited scope of information (e.g., only geometric parameters), can assist the semiconductor design process.

[0063] In one or more embodiments, when applying a parameter-based POI method, the system can customize the acquisition and / or analysis of geometric parameters in various ways, including: customizing the acquired geometric parameters based on one or both of the POI type or a specific downstream application; and / or customizing the analysis based on one or both of the POI type or a specific downstream application.

[0064] As an example only, customization may include: (1) applying a knowledge-based approach, thereby identifying different features for each POI type and feeding them into the system. Through feature analysis and reduction, customization can be made for downstream applications to refine and build a minimal feature set; or (2) applying a more general approach that captures a larger set of parameters (e.g., all available parameters), where the system determines which features are more relevant until a minimal set is obtained.

[0065] Values ​​for one or more geometric parameters may include a POI parameter dataset, which represents a compressed set of information about the layout environment associated with the POI. In one or more embodiments, this compressed set of information includes values ​​for the geometric parameters and specifically excludes one or both of exposure details or process details for manufacturing. As discussed further below, POIs can significantly increase the information density within small datasets. Furthermore, POI parameter datasets can be used by downstream applications, particularly during the design phase, to improve performance in downstream applications where such datasets are applied. In some embodiments, POI parameter datasets may be customized for one or both of a specific downstream application or POI type (e.g., optimized for capturing the layout environment around the POI). Alternatively, POI parameter datasets may not be customized for a specific downstream application or POI type, and subsequent analysis may be tailored to one or both of the specific downstream application or POI type.

[0066] Therefore, in some embodiments, a standard POI parameter dataset (including values ​​for a standard parameter set and stored in a standard POI parameter data structure) can be used for each POI to capture the environment surrounding the POI for use by multiple downstream applications. In this way, the standard POI parameter dataset can be independent of both the POI type and the downstream application. Thus, the actual measured geometric values ​​can fill most or all of the standard POI parameter data structure; however, downstream analytics (e.g., machine learning) can ignore or disregard the actual measurements in the POI parameter dataset to tailor the analysis for a specific downstream application, as discussed further below.

[0067] Alternatively, the POI parameter dataset can be customized for one or both of the POI type and downstream application. Specifically, in one instance, the POI parameter dataset can be customized based on the POI type. For example, in one or more embodiments, the POI type includes, but is not limited to, edge-type POIs (e.g., line-end POIs or edges associated with minimum space) and polygon-type POIs (e.g., via-type POIs). In another instance, the POI parameter dataset can be customized for downstream applications (e.g., a hotspot POI parameter dataset, which differs from and potentially is a subset of the standard POI parameter dataset, and may include customized parameters to determine hotspot detection). In yet another instance, the POI parameter dataset can be customized for both the POI type and the downstream application. In particular, for lithography applications (including those involving edge movement), the POI type modeled using geometric parameters can be an edge-type POI. Conversely, for depressions in a Chemical Mechanical Planarization (CMP) environment, the POI type modeled using geometric parameters can be a polygon-type POI.

[0068] Therefore, different parts of the layout can be treated differently depending on the downstream application. As an example, vias (or other small openings) can be treated differently depending on the downstream application. Specifically, in response to a first type of downstream application (e.g., a downstream application analyzing CMP planarity), vias can be modeled at a polygon level using a polygon-type POI, for example, modeling CMP planarity variations, thus treating and analyzing the vias as a whole. Similarly, in cases where a downstream application analyzes the capacitance of a portion of the layout (e.g., vias or non-vias), a polygon-type POI can be used to model that portion (e.g., vias) at a polygon level. Conversely, in response to a second type of downstream application, vias can be modeled at an edge level using an edge-type POI (where the via itself can be divided into discrete sets of edges), such as a lithographic model, whereby the edges of the via can be changed or moved, where each edge of the via may be changed independently.

[0069] As an example, actual measured geometric values ​​can populate parameters in a standard POI parameter data structure relevant to downstream applications, while null values ​​can populate parameters in a standard POI parameter dataset unrelated to downstream applications. As another example, the standard POI parameter dataset can include parameters common to multiple downstream applications and can be supplemented based on specific downstream applications (e.g., the parameter set can be extended to accommodate a certain category of POI, such as in the case of insufficient line-via coverage, where additional measurements related to one or more vias (e.g., via size and distance from the via to the POI in addition to the coverage area, which can supplement the standard POI parameter dataset) can be added to the parameter set). In this way, the POI parameter dataset can include data structures for a large number of unique parameters, where the value for each geometric parameter in the POI parameter dataset represents a compressed set of information about the layout environment.

[0070] As another example, different downstream applications can have different associated POI datasets (including values ​​for a specific set of parameters). Specifically, a lithography-specific POI parameter dataset can include values ​​for parameters customized for that specific lithography application (where these values ​​are stored in a corresponding lithography-specific POI parameter data structure or in a standard POI parameter dataset with additional null values). Conversely, a hotspot POI parameter dataset can include values ​​for parameters customized for hotspot detection (where these values ​​are stored in a corresponding hotspot POI parameter data structure or in a standard POI parameter dataset with additional null values). In this way, POI parameter datasets (including geometric values ​​for a specific set of parameters) can be customized for a specific downstream application. As another example, the system can identify POI types and obtain geometric values ​​corresponding to those POI types. In some embodiments, the POI type can be specific to a specific downstream application. For example, the following are different types of POIs used as locations of potential hotspots in hotspot detection, including: (i) line-end pullback hotspots (see, for example, Figures 12a to 12b, discussed further below). Figure 12N (ii) Pinching / cut-out hotspots; (iii) Bridged hotspots; and (iv) Insufficiently covered hotspots vias. In other embodiments, the POI type may be shared by downstream applications.

[0071] Similarly, the analysis of POI parameter datasets (e.g., standard POI parameter datasets or customized POI parameter datasets) can be tailored for specific downstream applications. In some embodiments, machine learning can be customized in any of the following ways: (1) for a specific downstream application; (2) for a specific type of POI; or (3) for a specific type of POI used for a specific downstream application. As an example, a machine learning method can use a training dataset that includes POI parameter data corresponding to known hotspots and POI parameter data corresponding to known good graphics to train a machine learning model tailored for hotspot detection. As another example, a machine learning method can use a training dataset that includes POI parameter data corresponding to known line-end pullback hotspots and POI parameter data corresponding to known non-line-end pullback hotspots to train a machine learning model tailored for line-end pullback hotspot detection.

[0072] As another example, test data (e.g., scanchain test data) can be combined with parametric POI-based methods to identify problematic portions of a layout design. Specifically, scanchain testing can accumulate large amounts of data related to potential errors from Automatic Test Pattern Generation (ATPG) on actual working dies. Furthermore, scanchain test data can be analyzed to isolate portions of the layout design, including specific combinations of edges or polygons that contribute to potential errors. The identified combinations of edges or polygons can be transformed into geometric values ​​that fill an identified POI parameter dataset (e.g., a single identified POI parameter dataset or a combination of identified POI parameter datasets). As an example, through analysis of scanchain test data, specific structures (e.g., a specific type of via) can be identified as potentially error-prone (e.g., having a certain percentage of failures). Specific structures can be described in one or more identified POI parameter datasets (e.g., the problematic POI dataset for vias can be filled using geometric values ​​for a specific type of via that is potentially error-prone). In practice, for the layout design under inspection, the POI parameter dataset can be compared to the problematic POI parameter dataset. In the example of vias in the layout design under inspection, these vias can be described as geometric parameters (e.g., each via may include a corresponding via POI parameter dataset, filled with geometric values ​​for the via). The via POI parameter dataset in the layout design can be compared with the problematic POI parameter dataset to determine if a match exists (or a match within a certain tolerance) to infer whether a particular via in the layout design is prone to error (e.g., has a certain percentage probability of error). As another example, a particular structure (identified as potentially error-prone) can be transformed into a set of identified POI parameter datasets (where the particular structure is divided into a set of edges, each edge in which corresponds to a POI parameter dataset in the set of problematic POI parameter datasets). Furthermore, the POI parameter datasets in the layout design under inspection can be compared with the identified POI parameter datasets to determine if they match (or match within a certain tolerance) the set of problematic POI parameter datasets. Thus, one, some, or all of the various structures within the layout design under inspection can be analyzed and attributed to a certain percentage of potential error, and potential modifications can be ranked accordingly.

[0073] In this way, the analysis of parameter sets and / or parameters can be tailored to specific downstream applications and / or POI types, and the context of the POI can be fully captured to provide the information needed to analyze specific downstream applications (e.g., graph clustering; revenue and risk assessment; etc.).

[0074] Various types of geometric parameters have been conceived. As an example, the set of parameters may include one or both of the following: (1) one or more geometric parameters relating to the polygon in which the POI exists (e.g., a self-description of the POI polygon); and / or (2) geometric parameters relating to the polygon in which the POI exists relative to other polygons in the environment surrounding the POI polygon.

[0075] For example, regarding (1), the geometric parameters may include any one, any combination, or all of the following: the POI itself (e.g., the length of the line end for a line-end POI); the polygon of the POI relative to various aspects of the POI (e.g., horizontal or vertical lines abutting the ends of the line-end POI; the nearest edge of the POI (e.g., concave or convex); the distance from the POI to the nearest edge); or the polygon of the POI (e.g., the length or width of the polygon of the POI; the edge type of the polygon of the POI).

[0076] Regarding (2), the geometric parameters may include any one, any combination, or all of the following: the proximity of other polygons to the polygon of the POI (e.g., geometric parameters associated with the polygon closest to the polygon of the POI; geometric parameters associated with the second closest polygon to the polygon of the POI); the geometric parameters relating other polygons to the polygon of the POI (e.g., distances (e.g., edge distances from other polygons to the POI); common run lengths between the polygon of the POI and other polygons); the geometric parameters relating and directional to other polygons to the polygon of the POI (e.g., distances from the polygon of the POI to the next relative top polygon; common run lengths between the polygon of the POI and the next relative top polygon); and the descriptive geometric parameters of other polygons (e.g., width and / or height dimensions of other polygons; edge types of the edges of other polygons closest to the polygon of the POI). In this respect, the number of geometric parameters (e.g., regarding: (1) the polygon in which the POI exists and / or (2) the polygon in which the POI exists relative to other polygons in the environment surrounding the polygon of the POI) may be at least 100, at least 200, at least 230, at least 250, etc.

[0077] For example, a data point on parameter A in the POI parameter dataset could represent the distance from the POI to the right side of the vertical polygon to the POI (an example of parameters relating to the polygon to which the POI exists), while another data point on parameter B in the POI parameter dataset could represent the distance from the POI to the concave angle below the POI (an example of geometric parameters relating to the polygon to which the POI exists relative to other polygons in the environment surrounding the POI). Therefore, in some embodiments, the data used as input to downstream applications may include the POI parameter dataset. Alternatively, input to downstream applications may include the POI parameter dataset. In particular, the data used to capture the environment surrounding or associated with the POI and used for downstream applications is limited to and includes only physical layout parameter inputs.

[0078] As discussed in more detail below, geometric parameters associated with a POI can be analyzed individually or in combination. For example, machine learning can generate machine learning models configured to incorporate geometric parameters associated with the POI for analysis. Using one or more geometric parameters in a POI parameter dataset can improve one or both of performance and efficiency in downstream applications. A POI parameter dataset can include more information captured in a much smaller amount of data, resulting in downstream applications using a POI parameter dataset performing much faster and using less memory than the same downstream application using a conventional dataset. For example, efficiency can result in not requiring specific knowledge or the use of any first-principles processing of information, or modeling / simulation results, as input. This differs from the general process that may require first performing another model or simulation to create the data needed for the input. Furthermore, performance and efficiency advantages can be provided by using a POI parameter dataset and its many parameters, which have specific and dense meanings about the layout environment. In this way, downstream applications (which may include other information such as images, graphics, and lithography / etching process information) are not solely dependent on physical layout measurement parameter inputs.

[0079] Therefore, in one or more embodiments, the POI parameter dataset can replace image or graphics capture methods with a set of purely physical layout measurement parameters, where each parameter in the POI parameter dataset captures unique features related to the layout design. Furthermore, since the POI parameter dataset focuses on measurement values, no physical information from the first-principles process is required, as the use of the POI parameter dataset is physically independent.

[0080] Furthermore, each geometric parameter is likely to be completely unique in terms of the information it captures compared to the rest of the geometric parameters in the POI parameter dataset. This uniqueness significantly increases the amount of information captured in a small set (which may be specific to geometric values), inherently increasing information density and opportunities to improve runtime and memory metrics for any modeling or simulation application applied to the POI parameter dataset. In particular, this significantly increases the information density within small POI parameter datasets that can be specifically optimized to capture the layout environment surrounding the POI.

[0081] Return to the attached diagram for reference. Figure 3 This is flowchart 300, which describes a process for generating feature codes by convolving a kernel with a representation of the layout design and analyzing the feature codes for downstream applications (e.g., to determine feature matches). At 302, a representation of the layout is obtained. Various representations of the layout design are conceived. As an example, a mesh can include a representation of the layout design, where, for a graphics file, each coordinate can represent a single point in the mesh. For example, the mesh can include an equally spaced 2D point array. Polygons within the layout design can be defined relative to the mesh based on the positions where the edges of the polygons coincide with points on the mesh. Furthermore, the resolution of the mesh can be increased or decreased to obtain greater or less information density. Other representations are conceived.

[0082] At 304, retrieve one or more POIs. In some embodiments, the system may generate and store a list of POIs for later access / analysis. Alternatively, the system may generate a list of POIs in response to determining a signature for each POI. As an example, subsampling of the complete layout design may be performed to determine the location of POIs for optimization at each technology node or design layer. In some embodiments, the selection of POI locations may be performed automatically. At this point, the POIs may be geometrically constrained by a set of rules or by output from lithography (e.g., model-based) simulations.

[0083] At 306, the kernel set associated with the downstream application is obtained. As discussed above, the kernel can vary in one or more aspects, including any one, any combination, or all of the following: kernel shape; kernel size; granularity (e.g., a measure of the fineness level of the mesh used to sample the layout); kernel orientation (e.g., orientation-dependent or orientation-independent); halo extension; precision; etc. In this way, various kernels can be used to generate feature codes for analysis supporting a specific downstream application. Furthermore, different kernel sets can be assigned to different downstream applications (e.g., assigning an OPC kernel set for OPC applications; assigning a hotspot kernel set for hotspot detection; etc.). Different kernel sets can differ from each other and can capture features or environments related to a layout design tailored for a specific downstream application. For example, the kernels selected for a given set may have optical and / or lithographic considerations relevant to the corresponding downstream application. In this way, the system can define multiple types of kernels to capture different features and define multiple kernel sets for different downstream applications.

[0084] Furthermore, the selection of kernels can be optimized for different applications, such as for different technology nodes and / or different design layer styles (e.g., back-end-of-line (BEOL) processes where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer via metallization layers; where individual devices are patterned on a semiconductor, etc.). In some implementations, test data can be used to determine which kernels extract features relevant to a specific downstream application. For example, regarding hotspot detection, various kernels can be tested using test data known to be hotspots or known to be good patterns. In response to testing one or more kernels (which may be a subset of various kernels) that correctly indicate that the feature codes indicate hotspots or good patterns when convolved to generate feature codes, the one or more patterns can be assigned as a set of one or more kernels for generating feature codes for hotspot detection. Similarly, regarding OPC, kernels can be tested to identify kernels that correctly indicate "good geometry" or "bad geometry" for OPC when convolved to generate feature codes, and these kernels can then be used to extract kernels that are relevant to the features identified by OPC.

[0085] At 308, feature codes are generated by convolving the kernel with portions of the layout's representation. For example, numerical representations, such as feature codes, are computed at one, some, or all POIs in the layout design. As discussed further below, the kernel captures a large amount of context associated with the POI, unlike typical graph-based approaches where edges are unique locations that can be matched. Furthermore, kernel-generated feature codes can be used for various purposes. For example, feature codes can be analyzed to determine if a corresponding POI aligns with a geometric edge, which can then be used as a matching criterion between different graphs. The computational cost of generating feature codes (e.g., feature vectors) via kernel convolution is offset by efficiency in the overall process time, for example, through clustering, as discussed further below. In some embodiments, a special convolution algorithm is used to ensure that if the geometry around any POI is identical within the kernel's range (halo), the collected feature codes have been generated without any numerical differences.

[0086] At 310, signatures used for downstream applications can be analyzed. These signatures (which may include a series of values) can be analyzed in combination (e.g., all values ​​are within the tolerance of the value of another signature) or can be analyzed individually (e.g., if one of the values ​​in the series used for the signature is not within the tolerance of the corresponding value of another signature, then the other values ​​in the series used for the signature are not analyzed).

[0087] Figure 4 This is a flowchart illustrating an example of feature code analysis at point 310 for downstream applications. At point 400, machine learning is performed on one or more features. At point 402, clustering is performed based on machine learning.

[0088] As an example, feature codes, based on kernel selection to extract relevant features for a specific downstream application, can accurately represent unique patterns. In some embodiments, binning or clustering can be used to analyze feature codes. As an example of binning or clustering, multiple bins related to the downstream application can be generated, where these bins can be qualified based on test data. Specifically, for hotspot detection, the two bins can include a hotspot bin and a good pattern bin. Test data with known hotspots and / or known good patterns can be used to define clustering criteria (e.g., boundaries of feature code values ​​that should be assigned to the corresponding bins) for one or both of the hotspot bins and good pattern bins. After qualifying the clusters, the feature codes can be analyzed for placement in the corresponding bins and, consequently, for drawing conclusions about the feature codes. For example, after generating the range of feature codes for defining hot spot and good graphics zones, the analysis of the feature codes for POIs (whose indication of whether they are hot spots or good graphics is unknown) placed in the corresponding zones indicates the determination result regarding whether the POI is a hot spot or a good graphics (e.g., placing the feature code for the POI in the hot spot zone indicates that the POI is a hot spot; placing the feature code for the POI in the good graphics zone indicates that the POI is a good graphics).

[0089] As another example of binning or clustering, multiple bins related to downstream applications can be generated, where these feature codes are clustered in the corresponding bins for graph matching. In particular, feature codes within a predetermined tolerance can be assigned to the same bin, thereby determining that feature codes assigned to the same bin share at least one similar aspect.

[0090] The clustering criteria used for the corresponding bins (e.g., the boundaries of feature code values ​​that should be assigned to the corresponding bins) can be tested to determine the numerical tolerance that results in precise clustering of similar (e.g., the similarity from the perspective of downstream applications) patterns. For example, in some embodiments, fuzzy clustering, such as iterative fuzzy clustering, can be performed. To determine the clustering criteria, an initial tolerance or numerical increment (e.g., 0%) can be used. Thereafter, the tolerance or numerical increment can be increased, for example, to 5% or 10%, to determine a tolerance limit after which clustering leads to errors (e.g., the tolerance becomes so large that feature codes associated with hot spots are clustered together with feature codes associated with good patterns).

[0091] Clustering can be part of machine learning applications that use optimized and highly customized graph similarity criteria. Specifically, to further reduce the amount of data used in downstream applications, machine learning clustering methods can be used to consider various aspects, such as performance and the stability of clustering results. Thus, feature codes for each POI can be generated and used in downstream machine learning processes for applications such as graph matching, graph analysis, layout reduction, OPC, and hotspot detection. In this way, downstream applications can be improved by 4X-10X (e.g., clustering can improve performance). Separately from performance improvements, customizable and relevant graph clustering results can improve the consistency and accuracy of the final results. In this way, clustering techniques can provide efficient, accurate, relevant, consistent, and stable (e.g., run-to-run) results.

[0092] In, for example Figures 1 to 2 The diagram illustrates one or both of the storage used to execute machine learning applications or to store feature codes within a distributed computing environment. Specifically, to allow for further operations applied to the collected data (including feature codes), a persistent database configured to operate in a distributed environment (e.g., with at least one thousand remote computers) can be used. The database can be configured to store only a unique copy of the generated feature codes and the location from which these feature codes originated. This storage configuration can reduce the amount of data by at least one, two, or three orders of magnitude and can allow for faster and more efficient operations.

[0093] Some features can be close to a POI. Other features can be more dispersed in the layout design. For more dispersed features, there are two options for considering these features. First, the kernel used to generate feature codes for the corresponding POI can cover a larger area in the layout design; however, increasing this area may make feature code generation too computationally expensive. Second, feature codes associated with more than one POI can be combined to allow the analysis to take into account the more dispersed features. Therefore, in one embodiment, each feature code is analyzed separately (e.g., one feature vector at a time for hotspot detection, OPC, etc.). Alternatively, feature codes associated with different POIs can be combined for analysis. In particular, POIs (and their associated feature codes) can be combined based on overlay construction (e.g., windows moved to different parts of the grid (with associated window sizes)) (e.g., windows can slide across the grid point by point; windows can slide across the grid by moving by a factor of the grid geometry (e.g., 1 / 2 of the window width)). For analytical purposes, POIs within a window can be grouped together.

[0094] As another example, clustering can be performed on specific features, such as the type of corners (e.g., separating convex and concave corners into clusters). Machine learning can be applied to this type of data from the training set. Once the model is sufficiently trained, it can be used on previously unseen layout designs to identify corner features (e.g., convex and concave corners). Other features that can undergo machine learning include, but are not limited to: OPC correction values; SRAF (Sub-Resolution Assist Feature) placement; lithographic hotspots; or redefining the objectives of the layout design (e.g., layout reduction).

[0095] Figure 5 This is a block diagram 500, an example of OPC analysis, such as graphical matching that can be used in an OPC environment. Figure 5 The diagram shows input / output 502 and features added to improve consistency 504. At 506, the input target layer is defined. At 508, layout reduction can be performed. At 510, unique shapes and their copies are identified, for example, based on analysis from fragment feature codes and the OPC display database 516. At 512, OPC can be performed only for unique shapes, where mapping is applied only to copies. Furthermore, new unique shapes can be saved to the fragment feature code and OPC display database 516. At 514, consistent OPC can be applied to all copies.

[0096] Figures 6A to 6I It is a series of diagrams that use feature codes to determine feature matches. For example, Figure 6A Figure 1 (600) and Figure 2 (602) are shown, and Figure 1 (600) and Figure 2 (602) are assumed to be identical (or very similar). At this point, the corresponding feature codes generated by convolving the kernel with the grid of the layout design should be identical or within a predetermined tolerance. Figure 6B Graphic 1 (600) and graphic 2 (602) are shown, with the edges of graphics 1 (600) and graphic 2 (602) segmented by element 606 to form smaller segments. In this way, element 606 segments the edges of the corresponding graphics so that POI 608 can be placed between elements 606, as shown. Figure 6C As shown in the diagram. Alternatively, element 606 can be placed at each corner point of the graphic.

[0097] After that, regions can be clipped from the layout representation, for example in Figure 6D As shown in the diagram. In particular, Figure 6DThe radius 620 of the clipping region centered on a pivot point (e.g., POI 608) is shown. The 2-D region may include a halo / environment in which desired features are extracted. Thus, the halo / environment may include a region of interest surrounding or having a fixed relationship with the POI, in which properties or features of that region are sought.

[0098] Figure 6D A 2-D region as a circle is shown; however, other 2-D regions, including squares or rectangles, are conceived. Furthermore, the 2-D region is centered on a pivot point; alternatively, the 2-D region can be positioned relative to the pivot point, such as at the top, bottom, left, or right side of the pivot point. Figure 6D This is for illustrative purposes. The 2D region can be larger or smaller than the depicted region. For example, the radius of the clipping region can be larger, such as three times larger, so that the clipping region can take into account adjacent graphics.

[0099] Figure 6E A set of kernels (e.g., Tophat kernels) for a specific application (e.g., OPC) to capture one aspect of the layout design (e.g., graphics density) is illustrated. For example, kernel 1 (630) includes a ring with an outer diameter of "a" and an inner diameter of "b", kernel 2 (632) includes a ring with an outer diameter of "b" and an inner diameter of "c", and kernel 3 (634) includes a ring with an outer diameter of "c" and an inner diameter of "d". Thus, these rings are concentric and do not overlap with each other (e.g., they are mutually exclusive). Furthermore, fewer or more kernels are conceived. In addition, these kernels may include regions of POI (e.g., kernels inside kernel 3 (634)). Alternatively, kernels may include regions outside of POIs for convolution with regions outside of POIs. Figure 6F It is a diagram 640 that is superimposed on the layout design and has a kernel centered on POI 608.

[0100] Therefore, the number and type of kernels selected can depend on the downstream application to allow the kernels to extract the desired target features from the POI halo / environment. As mentioned above, the first downstream application may seek to obtain the environment of a larger area around the POI. In this case, kernel 1 (630), kernel 2 (632), and kernel 3 (634) can be used. Conversely, the second downstream application may seek to obtain the environment of a smaller area around the POI. In this case, one or both of kernel 1 (630) and kernel 2 (632) can be used (but kernel 3 (634) cannot be used). Furthermore, various types of extraction from the representation of the layout can be performed depending on the downstream application. In particular, the function used for convolution (e.g., tophat; Gaussian; etc.) can be selected based on the downstream application, separately from (or otherwise) the number / shape of the selected kernels.

[0101] Figure 6F The three kernels shown are an example of a set of three Tophat kernels centered around POI 608 (assuming this kernel set extracts features from a representation of a layout relevant to downstream applications). Each kernel in the example has an inner and outer radius different from the other kernels. See also Figure 6E Furthermore, each kernel, when convolved with a POI, generates a density graph within the loop of that tophat kernel. In this way, as... Figure 6F The convolution shown is equivalent to calculating the density of the pattern within the corresponding ring. Dividing the region around or near the POI into separate rings, the resulting feature codes include different values, where each value provides an indication of the density away from the POI (when examining from the inner ring to the outer ring). For ease of description, in Figure 6F The diagram illustrates a kernel associated with a POI 608. Kernels centered on one, some, or every POI in the layout design (or positioned relative to one, some, or every POI in the layout design) can be convolved to generate feature codes for one, some, or every POI in the layout design. Although Figure 6F The document shows three kernels, but fewer or more kernels have been conceived. For example, four, five, ten, fifteen, or more kernels have been conceived.

[0102] Different kernels can be used to extract features other than the density pattern. As discussed above, other types of kernels have been conceived, including but not limited to: Gaussian kernels; directional Gaussian kernels; Poisson kernels; linear kernels; exponential kernels; cosine kernels; Epanechnikov kernels; and so on. In this way, the kernel can vary depending on its shape and type (e.g., the frequency extracted via the kernel, whether low or high frequency).

[0103] In some implementations, the kernel may numerically include a numerical matrix, for example in Figures 6J to 6L As shown, it is a set of three tophat kernel matrices 660, 670, and 680 (shown as values ​​of "1" in different positions in the corresponding matrices) used for convolution. Figures 6J to 6L A 9×9 matrix is ​​shown, where the size of the matrix is ​​determined by the application and is a measure of how large the environment around the point of interest is. Furthermore, each cell in matrices 660, 670, and 680 can be convolved with a specific region of the layout, such as a 1nm×1nm region, 2nm×2nm, etc., from the layout. At this point, the area (e.g., 1nm×1nm; 2nm×2nm) can be a measure of granularity, as discussed above.

[0104] Figure 6GThis is illustration 650, a feature code set into classification engine 652, generated by convolving the kernel with the layout design. As discussed above, convolving each kernel with a portion of the layout design representation produces a number (which can be normalized to between 0 and 1). Therefore, using... Figure 6G The three kernels shown represent feature codes consisting of three numbers, each between 0 and 1, such as values ​​1, 2, and 3 (e.g., 0.25; 0.20; 0.18). As another example, a convolution with 15 kernels produces feature codes with 15 individual values ​​(e.g., K1, K2, K3…K14, K15). These feature codes can thus represent the encoding of features extracted from the representation of the layout design.

[0105] Figure 6G The process shown can be performed for all Points of Interest (POIs) in the layout design, enabling the computation of feature codes for all POIs. These feature codes can then be sent to a classification engine 652 for analysis, such as machine learning, which can cluster the feature codes based on the expected characteristics of the POIs extracted by the kernel. As an example, the corresponding value for the first feature code can be compared with the corresponding value for the second feature code (e.g., comparing the K1 value for the first feature code with the K1 value for the second feature code to obtain a percentage difference; comparing the K2 value for the first feature code with the K2 value for the second feature code to obtain a percentage difference; and so on). Depending on the comparison, the first feature code can be determined to be similar to or dissimilar to the second feature code. Furthermore, different values ​​in the feature codes can be compared depending on the downstream application. As an example, the weight of values ​​obtained from kernel convolutions closer to the POI is greater than that obtained from kernel convolutions farther from the POI, so that layout designs closer to the POI are given more emphasis than layout designs farther from the POI.

[0106] Figure 6H The classification engine 652 report confirms a unique pivot point 654, which can indicate the existence of one or more POIs that match another POI (or match within a certain tolerance). In this way, the matching performed is not graph-to-graph, but POI-to-POI (or POI-to-POI within a window).

[0107] Figure 6I The classification engine 652 highlights polygons that interact with unique pivots. Figure 6ITwo identical polygons are illustrated as examples (typically, layout designs may include far more than two identical shapes). As discussed above, for each POI, a feature code is extracted by convolving the set of kernels with the representation of the layout. Furthermore, as discussed above, POIs with the same environment will have the same associated feature code. For example, the kernels selected for downstream applications can vary based on any, any combination of, or all of the following: size; shape; number; or function. For the purposes of the selected kernels, two POIs can have the same environment and also the same feature code. Therefore, for the purpose of analysis for downstream applications, two POIs are identical. In particular, for a downstream application, a set of two kernels (e.g., kernel 2 (632) and kernel 3 (634) with a specific function (e.g., tophat). If two POIs within the regions of the two kernels are identical and a certain function extracts the same type of information, then the feature codes are the same and the two POIs are considered identical. Conversely, if another downstream application seeks a larger environment, such as kernels 1 (630), 2 (632), and 3 (634), and the two POIs within this larger environment are not identical (e.g., kernel 1 (630), which samples regions far from the two POIs, is different for the two POIs), then the feature codes for the two POIs will be different, making the two POIs not considered identical for the other downstream application. In this way, the data extracted from the representation of the layout around the POI can be tailored for the downstream application, making the extracted data relevant to the downstream application for the purpose of determining the similarity or difference of the POIs.

[0108] Its example is in Figures 6M to 6N The table shows this.

[0109] Specifically, one use case involves clustering Points of Interest (POIs) of complete layouts in different groups based on their similarity, with the goal of selecting representatives for each group or downsampling the existing graphical space within the layout. Samples / representatives can be used as training data for building various types of models in semiconductor manufacturing simulation flows. One way to perform objective sampling methods involves selecting the relevant feature vector format of the POIs based on downstream applications.

[0110] An illustrative example uses Tophat kernel convolutions to generate feature vectors, which are then numerically applied using machine learning clustering techniques to find similar POIs. The output of this process is a list of cluster counts and POI IDs for each cluster. The ratio between the original count of a POI and the corresponding count of its cluster is called the compression ratio or downsampling ratio; adjusting the clustering knob results in different compression ratios, such as... Figure 6MAs shown in the figure, the clustering knob can be tuned (e.g., tuned down to increase tolerance), which in turn reduces the number of clusters. This adjustment can, for example, be based on experience dependent on the application to identify the optimal number of clusters.

[0111] The halo radius can also be adjusted separately from (or in addition to) the tolerance, for example, by adjusting the convolutional halo radius while generating feature vectors. Figure 6M As shown in Table 685, the output of conventional edge-based graph matching is used to identify unique POIs as input to the feature vector generation process. Generally, a smaller halo results in fewer unique feature vector counts, such as... Figure 6N As shown in Table 690.

[0112] As discussed above, there are various ways to extract information from the representation of a layout design. One approach is to use one or more parameters associated with the POI (e.g., measurements anchored to the POI) to capture the environment around or associated with the POI. Figure 7 This is flowchart 700, which is used to obtain POI physical parameter inputs and analyze POI physical parameter inputs for downstream applications.

[0113] At 702, obtain the POI physical parameter input (e.g., pure physical layout measurement parameter input). For example, one or both of the following parameters may be obtained: (1) parameters concerning the polygon in which the POI exists and / or (2) parameters concerning the polygon in which the POI exists relative to other polygons in the environment surrounding the POI. At 704, analyze the POI physical parameter input to perform downstream applications (e.g., graph clustering; revenue risk management; etc.). As discussed above, various types of analysis are conceived, including clustering, such as machine learning-based clustering. The dataset used for machine learning may be based on known datasets as described above.

[0114] Figure 8A This is a first example flowchart 800 for obtaining POI physical parameter inputs. At 802, all POI physical parameter inputs are obtained. At 804, the obtained POI physical parameter inputs can be pruned based on a specific downstream application. As discussed above, there can be multiple physical parameters, some relevant to the downstream application and others irrelevant. Therefore, values ​​for more parameters needed for the downstream application can be obtained first (e.g., values ​​for all available parameters), and subsequently (before or during machine learning) a subset of the relevant parameters can be focused on or reduced.

[0115] Figure 8BThis is a second example flowchart 820 for obtaining POI physical parameter inputs. At 822, a subset of all POI physical parameter inputs is obtained. At 824, additional POI physical parameter inputs are obtained based on a specific downstream application. For example, the subset obtained in 822 can be selected as a parameter set shared by multiple downstream applications. Subsequently, the additional parameter inputs obtained in 824 can be specific to the downstream application (e.g., additional measurements associated with one or more vias can be added to the set of parameters such as via size, and, in addition to coverage area, the distance from the via to the POI can be supplemented to the standard POI parameter dataset to detect inadequate line-via coverage). Therefore, the downstream application can specify which parameters to input and then analyze those parameters. In this way, one or both of the following can depend on the downstream application: (i) the input parameters; and / or (ii) the parameters considered for analysis regarding the downstream application.

[0116] In addition, as discussed above, various POIs have been conceived, including various types of POIs such as edge-type POIs (e.g., line-edge POIs) and / or polygon-type POIs (e.g., via POIs). Figure 9 This is block diagram 900, which is an example of POI physical parameters used for line-end POIs. Specifically, Figure 9 The physical parameters that can be input and are associated with the line-end POI are shown. Figure 9 This is for illustrative purposes only. Thus, the discussion of line-end POIs can be applied to different edge-type or polygon-type POIs. The eight physical parameters shown in Table 909 include: (1) line end width (901); (2) line end to opposite line (902) (e.g., on a directly opposite polygon, the directly opposite polygon is the polygon above the polygon that includes the POI); (3) line end to the upper left sideline (903) (e.g., the distance between an adjacent polygon and the polygon that includes the POI to its left); (4) line end to the upper right sideline (904) (e.g., the distance between an adjacent polygon and the polygon that includes the POI to its right); (5) line end to the upper left sideline travel length (905) (e.g., the common travel length of the adjacent polygon and the polygon that includes the POI in (3)); (6) line end to the upper right sideline travel length (906) (e.g., the common travel length of the adjacent polygon and the polygon that includes the POI in (4)); (7) distance from the POI to the upper left convex edge (907); and (8) distance from the POI to the upper right convex edge (908). Other parameters are conceived.

[0117] Figures 10A to 10CThe layout designs 1000, 1020, and 1040 show different examples of line-end POIs (including POI_01 (1002), POI_02 (1022), and POI_03 (1042)).

[0118] Figure 11 Is with Figures 10A to 10C Example table 1100 shows parameter values ​​associated with different POIs. Specifically, table 110 associated with POI_01 includes... Figure 9 The table lists eight values ​​(in micrometers). Table 1100 can be in CSV file format, where the POI data is listed row by row and separated by commas. Additionally, the table can include values ​​for other parameters, such as line end extension and pullback. Downstream applications may seek to identify line end pullback. At this point, parameters can be added to the POI dataset, which could be line end extension or bias to overcome etching effects (e.g., it could be used for lithographic movement at edges).

[0119] Figures 12A to 12O This is an example block diagram of the parameter values ​​associated with a POI. Specifically, Figures 12A to 12D The diagrams 1200, 1208, 1212, and 1218 are block diagrams of line-end POI 1202 on polygon 1204, illustrating the line-end self-analysis (where the gray box around line-end POI 1202 highlights the POI). Specifically, Figure 12A The line tip width of POI 1202 is shown as 1206, and Figure 12B The wire end length 1210 of wire end POI 1202 is shown. Figures 12C to 12D The propagation direction of the line ends is shown, such as two horizontal line end directions (horizontal line end 1214 and horizontal line end 1216) or two vertical line end directions (vertical line end 1220 and vertical line end 1222). Although not shown, the line end POI can include a combination of vertical and horizontal line end directions, such as horizontal-vertical or vertical-horizontal.

[0120] As discussed above, separate from the polygon describing the POI, the POI can be defined by neighboring polygons (e.g., measurements of the POI (or the polygon containing the POI) relative to adjacent polygons or measurements describing the adjacent polygons themselves). For example, Figure 12EBlock diagram 1226 and first nearest neighbor polygon 1238 are shown. In some embodiments, the nearest neighbor polygon may be orientation-independent (e.g., the nearest neighbor polygon is orientation-independent). Alternatively, the nearest neighbor polygon may be orientation-dependent (e.g., the polygon closest to the top of the polygon containing the POI; the polygon closest to the bottom of the polygon containing the POI; the polygon closest to the right of the polygon containing the POI; the polygon closest to the left of the polygon containing the POI; etc.).

[0121] Various parameters from the line end POI to the first nearest neighbor can be obtained, such as first nearest neighbor angle analysis (e.g., convex and concave angle proximity (2D structure)), which can include three properties in the following four directions (e.g., top; bottom; right; left): the distance from the convex / concave edge to the line end (corner to corner) (distance of the edge from the line end 1230); the length of the convex / concave edge (e.g., first nearest neighbor height 1234; first nearest neighbor width 1236); and the type of the convex / concave edge (e.g., edge type 1232 indicating whether the edge is concave or convex).

[0122] Similarly, the same measurement can be performed on the second nearest neighbor. For example, Figure 12F Block diagram 1240 and second nearest neighbor polygon 1250 are shown. In some embodiments, the second nearest neighbor polygon may be orientation-independent or orientation-dependent. Furthermore, a similar polygon from the line endpoint POI to the second nearest neighbor can be obtained. Figure 12E Various parameters, such as second nearest neighbor angle analysis (e.g., convex and concave angle proximity (2D structure)), can include three properties in the following four directions (e.g., top; bottom; right; left): the distance from the convex / concave edge to the line end (corner to corner) (distance from the edge to the line end 1242); the length of the convex / concave edge (e.g., second nearest neighbor height 1246; second nearest neighbor width 1248); and the type of the convex / concave edge (e.g., edge type 1244).

[0123] Figures 12G to 12H The analysis of the angle from the line end to the first nearest point is shown, which can include three properties in each of four different directions. Specifically, Figure 12G A block diagram 1254 is shown on polygon 1256 near the convex corner, and Figure 12H A block diagram 1262 is shown on polygon 1264 near the concave corner.

[0124] Figure 12G The length of the convex corner edge is shown (e.g., convex edge length 1260); the distance of the convex edge from the line end POI (corner-to-corner) (e.g., convex edge distance from the line end POI 1258); and the edge type (e.g., edge type 1244). Similarly, Figure 12HThe length of the concave edge is shown (e.g., concave edge length 1270); the distance of the concave edge from the line end POI (corner-to-corner) (e.g., concave edge distance from the line end POI 1268); and the edge type (e.g., edge type 1244). Similar parameters can be obtained for the second nearest self-angle analysis (e.g., similar to...). Figure 12G -to Figure 2 The parameters shown in H are for the second nearest angle.

[0125] For example Figures 12I to 12L The parameters described herein can also be used for line-end boundary analysis. Specifically, Figure 12I A block diagram 1272 shows the distance between the line end on polygon 1276 and the left line on the left polygon 1274 (e.g., the distance 1278 between the adjacent line of the line end and the side line of the left polygon). Figure 12J A block diagram 1280 shows the common travel length 1281 between the tip of the line and the line of the left polygon. Similarly, Figure 12K A block diagram 1282 shows the distance between the line end on polygon 1276 and the right line on the right polygon 1284 (e.g., the distance 1283 between the adjacent line of the line end and the side line of the right polygon). Figure 12L A block diagram 1285 shows the common travel length 1286 between the tip of the line end and the line of the polygon on the right.

[0126] Figure 12M A block diagram 1287 shows the distance 1288 from the end of the line to the next opposing facing structure (e.g., top side structure 1289; bottom side structure; right side structure; left side structure; etc.). Furthermore, Figure 12N A block diagram 1290 shows the common travel length 1291 between the tip of the line end and the next opposite facing structure (top side structure 1289).

[0127] Figure 12O A block diagram 1292 is shown for POI 1296 on polygon 1297, which shows the first nearest angle 1293, the second nearest angle 1294, and the third nearest angle 1295. As discussed above, for each corresponding angle, parameters describing the corresponding angle itself or the corresponding angle relative to the POI can be generated.

[0128] As discussed above, the obtained parameters can be analyzed individually or in combination. As an example, weighting, rules, or machine learning can consider multiple parameters about the POI as factors. In some embodiments, the nearest feature (e.g., the nearest angle) can be weighted to have a greater influence than other features that are further away from the POI (e.g., geographically). Alternatively, depending on the rules or machine learning approach, more distant features (e.g., more distant angles) can be weighted more heavily. For example, Figure 12O The first nearest angle 1293 is shown. In the absence of other features in a more distant environment, the first nearest angle 1293 has a greater weight than other features, indicating a greater influence on the representation of the POI. However, the system, based on machine learning or rules, can analyze other factors in determining the influence of combined parameters (e.g., any one, any combination, or all of the following: angle type; length; or space). See also Figure 12O Machine learning or derived rules can determine that the third nearest angle 1295 has a more significant impact on the line-end POI than the first nearest angle 1293 and the second nearest angle 1294.

[0129] The following exemplary embodiments of the present invention are also disclosed:

[0130] Example 1:

[0131] A computer-implemented method for analyzing multiple points of interest (POIs) in a semiconductor layout design for downstream applications, the method comprising:

[0132] One or more kernels are obtained based on the downstream application. When the one or more kernels are convolved with the representation of the semiconductor layout design, the one or more kernels extract at least one feature associated with the plurality of POIs. The extracted at least one feature is used by the downstream application.

[0133] For a given POI among the plurality of POIs, the one or more kernels are convolved with the representation of the semiconductor layout design to generate a feature code for the given POI, the feature code including a digital representation indicating at least one feature extracted and associated with the given POI; and

[0134] The feature code is used to analyze the extracted at least one feature associated with the corresponding POI based on the downstream application analysis.

[0135] Example 2:

[0136] According to the method in Example 1

[0137] The first kernel set is configured to extract a first feature for a first downstream application to generate a first feature code, the first feature code including a first series of values ​​generated by convolving each kernel in the first kernel set with the representation of the semiconductor layout design;

[0138] The second kernel set is configured to extract a second feature for a second downstream application to generate a second feature code, the second feature code including a second series of values ​​generated by convolving each kernel in the second kernel set with the representation of the semiconductor layout design;

[0139] The first kernel set differs from the second kernel set in at least one aspect;

[0140] Wherein, the first feature extracted from the representation of the semiconductor layout design is different from the second feature extracted from the representation of the semiconductor layout design; and

[0141] The first downstream application is different from the second downstream application.

[0142] Example 3:

[0143] The method described according to either embodiment 1 or 2

[0144] The first downstream application includes hotspot detection;

[0145] The first feature indicates whether the corresponding POI represents a hotspot or a good graphic.

[0146] The second downstream application includes optical proximity correction; and

[0147] The second feature indicates whether the corresponding POI represents a good geometry or a bad geometry;

[0148] Example 4:

[0149] The method described according to any one of embodiments 1 to 3

[0150] The one or more kernels include a set of mutex rings centered on the corresponding POI to generate the signature.

[0151] Example 5:

[0152] The method described according to any one of embodiments 1 to 4

[0153] The shape of the one or more kernels and the functions of the one or more kernels are determined based on the downstream application.

[0154] Example 6:

[0155] The method described according to any one of embodiments 1 to 5

[0156] The kernel function is selected from either a step function or a Gaussian function.

[0157] Example 7:

[0158] The method described according to any one of embodiments 1 to 8

[0159] The shape of the kernel is selected as orientation-dependent or orientation-independent based on the downstream application.

[0160] Example 8:

[0161] The method described according to any one of embodiments 1 to 7

[0162] Specifically, for a first type of technique used for the semiconductor layout design, a first kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a first feature code; and

[0163] Specifically, for a second type of technique used for the semiconductor layout design, a second kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a second feature code, wherein the first kernel set is different from the second kernel set.

[0164] Example 9:

[0165] The method described according to any one of embodiments 1 to 8

[0166] Wherein, for a first type layer used for the semiconductor layout design, a first kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a first feature code; and

[0167] Specifically, for a second type layer used for the semiconductor layout design, a second kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a second feature code, wherein the first kernel set is different from the second kernel set.

[0168] Example 10:

[0169] The method described according to any one of embodiments 1 to 9

[0170] The feature code used for the extracted one or more features based on the downstream application analysis includes: clustering the feature code to identify the extracted one or more features.

[0171] Example 11:

[0172] According to the method described in any of Examples 1 to 10,

[0173] Clustering is performed based on machine learning.

[0174] Example 12:

[0175] The method described according to any one of the embodiments 1-11

[0176] The machine learning process uses a training dataset to perform the clustering.

[0177] Example 13:

[0178] One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform the method according to any one of embodiments 1 to 12.

[0179] Example 14:

[0180] A system includes one or more processors, said processors being programmed to perform the method according to any one of embodiments 1 to 12.

[0181] Example 15:

[0182] A computer-implemented method for analyzing multiple points of interest (POIs) in a semiconductor layout design for downstream applications, the method comprising:

[0183] For a given POI, obtain values ​​for one or more geometric parameters of the polygon with respect to the POI and of at least one other polygon in the environment surrounding the POI; and

[0184] The values ​​of the one or more geometric parameters are analyzed based on the downstream application.

[0185] Example 16:

[0186] The method according to Example 15

[0187] The one or more geometric parameters for obtaining the value are customized based on at least one of the POI type or the downstream application.

[0188] Example 17:

[0189] The method described according to any of the embodiments in Examples 15 and 16

[0190] The one or more geometric parameters for obtaining the value are customized based on both the POI type and the downstream application.

[0191] Example 18:

[0192] The method described according to any one of embodiments 15 to 17

[0193] Also includes:

[0194] Determine the POI type for the corresponding POI; and

[0195] In response to determining the POI type, a POI parameter dataset associated with the determined type is obtained; and

[0196] The value is obtained from the geometric parameters in the POI parameter dataset associated with the determined type.

[0197] Example 19:

[0198] The method described according to any one of embodiments 15 to 18

[0199] The POI type is selected from edge-type POI and polygon-type POI.

[0200] Example 20:

[0201] The method described according to any one of embodiments 15 to 19

[0202] Depending on the first downstream application, a corresponding portion of the semiconductor layout design is identified as the edge-type POI, such that the corresponding portion is divided into a plurality of edge POIs, wherein the value for the one or more geometric parameters is obtained for each of the plurality of edge POIs of the corresponding portion; and

[0203] Depending on the second downstream application, the corresponding portion of the semiconductor layout design is determined as the polygonal POI such that the corresponding portion is a polygonal POI, wherein, for the corresponding portion as a whole, values ​​for the one or more geometric parameters are obtained for the polygonal POI.

[0204] Example 21:

[0205] The method described according to any one of embodiments 15 to 20

[0206] The corresponding part includes a via.

[0207] Example 22:

[0208] The method described according to any one of embodiments 15 to 21

[0209] The geometric parameters of at least one other polygon in the environment surrounding the corresponding POI include: the geometric parameters of the at least one other polygon.

[0210] Example 23:

[0211] The method described according to any one of embodiments 15 to 22

[0212] Wherein, one or more geometric parameters relating to at least one other polygon in the environment surrounding the corresponding POI include: one or more geometric parameters of the at least one other polygon relative to the polygon of the corresponding POI.

[0213] Example 24:

[0214] The method described according to any one of embodiments 15 to 23

[0215] Wherein, the at least one other polygon's geometric parameters relative to the corresponding POI include: the distance between the corresponding POI and at least one feature on the at least one other polygon.

[0216] Example 25:

[0217] The method described according to any one of embodiments 15 to 24

[0218] The geometric parameters relating to at least one other polygon in the environment surrounding the corresponding POI include: one or more geometric parameters of a first nearest polygon relative to the corresponding POI and one or more geometric parameters of a second nearest polygon relative to the corresponding POI.

[0219] Example 26:

[0220] The method described according to any one of embodiments 15 to 25

[0221] Wherein, the one or more geometric parameters of the first nearest polygon relative to the corresponding POI include: one or more geometric parameters of the first nearest polygon and one or more geometric parameters of the first nearest polygon relative to the corresponding POI; and

[0222] Wherein, the one or more geometric parameters of the second nearest polygon relative to the corresponding POI include: one or more geometric parameters of the second nearest polygon and one or more geometric parameters of the second nearest polygon relative to the corresponding POI.

[0223] Example 27:

[0224] The method described according to any one of embodiments 15 to 26

[0225] The analysis of the downstream applications for the semiconductor layout design includes the analysis of one or more geometric parameters.

[0226] Example 28:

[0227] The method described according to any one of embodiments 15 to 27

[0228] The analysis is used to determine whether the one or more geometric parameters for the corresponding POI indicate a hotspot or a good shape.

[0229] Example 29:

[0230] The method described according to any one of embodiments 15 to 28

[0231] The analysis is performed during the design phase of the semiconductor layout design development; and

[0232] The analysis is configured to identify and correct one or more potential faults in the semiconductor layout design in order to reduce corrections to the semiconductor layout design during subsequent POI-based analysis performed during the manufacturing phase of the development of the semiconductor layout design.

[0233] Example 30:

[0234] One or more non-transitory computer-readable media storing computer-executable instructions, which, when executed, cause one or more processors to perform the method according to any one of embodiments 15 to 29.

[0235] Example 31:

[0236] A system includes one or more processors programmed to perform a method according to any one of embodiments 15 to 29.

[0237] The subject matter disclosed above is intended to be illustrative, not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of this description. Therefore, to the maximum extent permitted by law, the scope will be determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

Claims

1. A computer-implemented method for analyzing multiple points of interest (POIs) in a semiconductor layout design for a downstream application, the method comprising: One or more kernels are obtained based on downstream applications. When the one or more kernels are convolved with the representation of the semiconductor layout design, the one or more kernels extract at least one feature associated with the plurality of POIs. The extracted at least one feature is used by the downstream application. For a given POI among the plurality of POIs, the one or more kernels are convolved with the representation of the semiconductor layout design to generate a feature code for the given POI, wherein the one or more kernels include a set of mutually exclusive rings centered on the given POI to generate the feature code, the feature code including a digital representation indicating the extracted at least one feature associated with the given POI; as well as The feature code is used to analyze the extracted at least one feature associated with the corresponding POI based on the downstream application analysis.

2. The method according to claim 1, wherein, The first kernel set is configured to extract a first feature for a first downstream application to generate a first feature code, the first feature code comprising a first series of values ​​generated by convolving each kernel in the first kernel set with the representation of the semiconductor layout design; The second kernel set is configured to extract a second feature for a second downstream application to generate a second feature code, the second feature code including a second series of values ​​generated by convolving each kernel in the second kernel set with the representation of the semiconductor layout design; The first kernel set differs from the second kernel set in at least one aspect; Wherein, the first feature extracted from the representation of the semiconductor layout design is different from the second feature extracted from the representation of the semiconductor layout design; and The first downstream application is different from the second downstream application.

3. The method according to claim 2, wherein, The first downstream application includes hotspot detection; The first feature indicates whether the corresponding POI represents a hotspot or a good graphic. The second downstream application includes optical proximity correction; and The second feature indicates whether the corresponding POI represents a good geometry or a bad geometry.

4. The method according to claim 1, wherein, The shape of the one or more kernels and the functions of the one or more kernels are determined based on the downstream application.

5. The method according to claim 1, wherein, For a first type of technique used for the semiconductor layout design, a first kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a first feature code; as well as Specifically, for a second type of technique used for the semiconductor layout design, a second kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a second feature code, wherein the first kernel set is different from the second kernel set.

6. The method according to claim 1, wherein, For a first type layer used for the semiconductor layout design, a first kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a first feature code; as well as Specifically, for a second type layer used for the semiconductor layout design, a second kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a second feature code, wherein the first kernel set is different from the second kernel set.

7. The method according to claim 1, wherein, The downstream application analysis used for the extracted at least one feature code includes: clustering the feature code to identify the extracted at least one feature.

8. The method according to claim 7, wherein, Clustering is performed based on machine learning.

9. The method according to claim 8, wherein, The machine learning uses the training dataset to perform the clustering.

10. A computer-implemented method for analyzing multiple points of interest (POIs) in a semiconductor layout design for a downstream application, the method comprising: Different kernel sets are obtained based on the type of downstream application and the technology used for the semiconductor layout design. When the different kernel sets are convolved with the representation of the semiconductor layout design, one or more different kernel sets extract at least one feature associated with the plurality of POIs. The extracted at least one feature is used by the downstream application. For a given POI among the plurality of POIs, the one or more different kernel sets are convolved with the representation of the semiconductor layout design to generate a feature code for the given POI, wherein the one or more different kernel sets include a set of mutually exclusive rings centered on the given POI to generate the feature code, the feature code including a digital representation indicating the extracted at least one feature associated with the given POI; as well as The feature code is used to analyze the extracted at least one feature associated with the corresponding POI based on the downstream application analysis.

11. The method according to claim 10, wherein, The first kernel set is configured to extract a first feature for a first downstream application to generate a first feature code, the first feature code comprising a first series of values ​​generated by convolving each kernel in the first kernel set with the representation of the semiconductor layout design; The second kernel set is configured to extract a second feature for a second downstream application to generate a second feature code, the second feature code including a second series of values ​​generated by convolving each kernel in the second kernel set with the representation of the semiconductor layout design; The first kernel set differs from the second kernel set in at least one aspect; Wherein, the first feature extracted from the representation of the semiconductor layout design is different from the second feature extracted from the representation of the semiconductor layout design; and The first downstream application is different from the second downstream application.

12. The method according to claim 11, wherein, The first downstream application includes hotspot detection, and wherein... The second downstream application includes optical proximity correction.

13. The method according to claim 10, wherein, The downstream application determines the shape of the one or more different kernel sets and the function of at least one kernel in the different kernel sets.

14. The method of claim 10, wherein, For a first type layer used for the semiconductor layout design, a first kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a first feature code; as well as Specifically, for a second type layer used for the semiconductor layout design, a second kernel set is obtained and convolved with the representation of the semiconductor layout design to generate a second feature code, wherein the first kernel set is different from the second kernel set.

15. The method according to claim 10, wherein, The feature code used for the extracted at least one feature based on the downstream application analysis includes: clustering the feature code to identify the extracted at least one feature.

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