Integrated device including interconnect structure having internal interconnects, dielectric layers and conductive layers

Abstract

An integrated device includes a substrate, an interconnect portion, and an interconnect structure. The interconnect portion is located on the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located on the interconnect portion. The interconnect structure includes: an internal interconnect; a dielectric layer coupled to the internal interconnect; and an external conductive layer coupled to the dielectric layer. The external conductive layer is configured to serve as a shield for the internal interconnect.

Description

[0001] Priority claim

[0002] This patent application claims priority to application No. 16 / 665,883, entitled “INTEGRATED DEVICE COMPRISING INTERCONNECT STRUCTURES HAVING AN INNER INTERCONNECT, A DIELECTRIC LAYER AND A CONDUCTIVE LAYER,” filed on October 28, 2019, and assigned to the assignee of the present application, and is expressly incorporated herein by reference. Technical Field

[0003] Various features relate to integrated devices including interconnects, but more particularly to integrated devices including interconnect structures having internal interconnects, dielectric layers, and conductive layers. Background Art

[0004] Figure 1 A package 100 is shown that includes a die 102, a substrate 104, and an encapsulation layer 106. The die 102 is coupled to the substrate 104. The encapsulation layer 106 is formed over the substrate 104. The encapsulation layer 106 encapsulates the die 102. The substrate 104 includes a plurality of interconnects 140. A plurality of solder interconnects 130 are coupled to the substrate 104 through the plurality of interconnects 140 of the substrate 104. There is a continuing need to provide devices with improved performance. Summary of the Invention

[0005] Various features relate to integrated devices including interconnects, but more particularly to integrated devices including interconnect structures having internal interconnects, dielectric layers, and conductive layers.

[0006] One example provides an integrated device including a substrate, an interconnect portion, and an interconnect structure. The interconnect portion is located on the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located on the interconnect portion. The interconnect structure includes: an internal interconnect; a dielectric layer coupled to the internal interconnect; and an external conductive layer coupled to the dielectric layer. The external conductive layer is configured to serve as a shield for the internal interconnect.

[0007] Another example provides an apparatus comprising: a substrate; an integrated device coupled to the substrate; and a component for shielding interconnect coupled to the substrate, wherein the component for shielding interconnect is configured to provide an electrical path for a signal such that the signal is shielded when the signal travels through the component for shielding interconnect.

[0008] Another example provides a device comprising: a substrate; an integrated device coupled to the substrate; and an interconnect structure coupled to the substrate. The interconnect structure is configured to provide an electrical path for a signal such that the signal is shielded when traveling through the interconnect structure. The interconnect structure comprises: an internal interconnect; a dielectric layer coupled to the internal interconnect; and an external conductive layer coupled to the dielectric layer. The external conductive layer is configured to serve as a shield for the internal interconnect.

[0009] Another example provides a method for manufacturing an integrated device. The method provides a substrate. The method forms an interconnect portion on the substrate. The method forms an interconnect structure on the interconnect portion. The interconnect structure includes: an internal interconnect; a dielectric layer coupled to the internal interconnect; and an external conductive layer coupled to the dielectric layer. The external conductive layer is configured to serve as a shield for the internal interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various features, properties and advantages will become apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which like reference numerals identify correspondingly throughout.

[0011] Figure 1 A side view of an integrated device including solder interconnects is illustrated.

[0012] Figure 2 A diagram of an exemplary interconnect structure including internal interconnects, dielectric layers, and conductive layers is illustrated.

[0013] Figure 3 A side view of an exemplary interconnect structure including internal interconnects, dielectric layers, and conductive layers is illustrated.

[0014] Figure 4 A view of multiple interconnect structures including internal interconnects, dielectric layers, and conductive layers is illustrated.

[0015] Figure 5 A view illustrating an arrangement of interconnections is shown.

[0016] Figure 6 A side view of an exemplary integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0017] Figure 7 A side view of an exemplary integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0018] Figure 8 A side view of an exemplary integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0019] Figure 9A side view of an exemplary integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0020] Figure 10 A side view of an exemplary integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0021] Figure 11 A side view of an exemplary integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0022] Figure 12 (including Figures 12A-12F ) illustrates an exemplary sequence for fabricating an integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers.

[0023] Figure 13 (including Figures 13A-13E ) illustrates an exemplary sequence for fabricating an integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers.

[0024] Figure 14 An exemplary flow chart of a method for fabricating an integrated device including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0025] Figure 15 A side view of an exemplary package including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0026] Figure 16 A side view of an exemplary package including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0027] Figure 17 A side view of an exemplary package including an interconnect structure having internal interconnects, dielectric layers, and conductive layers is illustrated.

[0028] Figure 18 Various electronic devices are illustrated that may integrate the dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION

[0029] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these aspects with unnecessary detail. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring aspects of the present disclosure.

[0030] The present disclosure describes an integrated device including a substrate, an interconnection portion, and an interconnection structure. The interconnection portion is located on the substrate. The interconnection portion includes a plurality of interconnects and at least one dielectric layer. The interconnection structure is located on the interconnection portion. The interconnection structure includes an internal interconnection, a dielectric layer coupled to the internal interconnection, and an external conductive layer coupled to the dielectric layer. The external conductive layer may include a conductive layer. The external conductive layer is configured to serve as a shield for the internal interconnection (e.g., an electromagnetic interference (EMI) shield). The interconnection structure may be a shielded interconnection structure. As will be further described below, using an interconnection structure including an external conductive layer configured to serve as a shield for the internal interconnection (e.g., an EMI shield), an integrated device with less crosstalk between interconnections can be provided, thereby providing improved signal integrity in the integrated device. When multiple interconnection structures each including an external conductive layer configured to serve as a shield for the internal interconnection are implemented together with the integrated device, crosstalk can be further reduced.

[0031] Exemplary interconnect structure including inner interconnect, dielectric layer and outer conductive layer

[0032] Figure 2 The diagram illustrates an interconnect structure 200 that can be implemented using an integrated device and / or package. The interconnect structure 200 can be configured as a shielded interconnect structure. The interconnect structure 200 can be a component for shielding an interconnect. The interconnect structure 200 is configured to provide an electrical path with improved signal integrity. As will be described further below, the interconnect structure 200 (e.g., a component for shielding an interconnect) can be configured to provide an electrical path for a signal (input / output signal) such that the signal is shielded when the signal travels through the interconnect structure 200. Signals traveling through the interconnect structure 200 can be shielded from electromagnetic interference (EMI) that may originate from signals traveling through other interconnects, components, and / or devices.

[0033] like Figure 2 and Figure 3As shown in FIG, interconnect structure 200 includes an internal interconnect 210, a dielectric layer 220, and an outer conductive layer 230. Dielectric layer 220 is coupled to internal interconnect 210 such that dielectric layer 220 surrounds (e.g., laterally surrounds) lateral sides of internal interconnect 210. Outer conductive layer 230 is coupled to dielectric layer 220 such that outer conductive layer 230 surrounds (e.g., laterally surrounds) lateral sides of dielectric layer 220. Dielectric layer 220 is between internal interconnect 210 and outer conductive layer 230. Outer conductive layer 230 may laterally surround internal interconnect 210. Outer conductive layer 230 may include a conductive layer. Outer conductive layer 230 is configured to not electrically contact internal interconnect 210. Outer conductive layer 230 may be configured to serve as a shield for internal interconnect 210, thereby providing improved isolation of signals traveling through internal interconnect 210. For example, outer conductive layer 230 may be configured to provide EMI shielding for internal interconnect 210. In some embodiments, the outer conductive layer 230 can be coupled to ground. The internal interconnect 210 can include a metal, such as copper. The internal interconnect 210 can be a pillar (e.g., a pillar interconnect, a copper pillar). The outer conductive layer 230 can include a metal, such as copper. The dielectric layer 220 can include a photosensitive dielectric layer, such as a SiO2-based material, and / or a combination thereof. The interconnect structure 200 can be coupled to an interconnect (e.g., a pad 250). In particular, the internal interconnect 210 of the interconnect structure 200 is coupled to the pad 250. The pad 250 can be an interconnect from an integrated device and / or a substrate. The interconnect structure 200 can be a bump interconnect structure. As will be further described below, one or more interconnect structures in the interconnect structure 200 can be coupled to an integrated device, a substrate, a package, and / or a printed circuit board (PCB).

[0034] Figure 4 A plurality of interconnect structures 300 are shown. The plurality of interconnect structures 300 include interconnect structures 200a-200h (e.g., a first interconnect structure, a second interconnect structure, a third interconnect structure, etc.). The plurality of interconnect structures 300 are arranged in rows and / or columns of the interconnect structures 200 (e.g., 200a-200h). The plurality of interconnect structures 300 can be configured to provide electrical paths for input / output (I / O) signals. Because the interconnect structures 200a-200h are close to each other, there is a possibility of a large amount of crosstalk between the signals traveling through the interconnect structures 200a-200h. However, since each interconnect structure (e.g., 200a-200h) includes an outer conductive layer 230 configured to serve as a shield (e.g., an EMI shield), the amount of crosstalk between the signals traveling through the interconnect structure 200 is reduced and minimized, thereby providing improved signal integrity for the integrated device. The plurality of interconnect structures 300 can be coupled to an integrated device, a substrate, a package, and / or a printed circuit board (PCB).

[0035] Figure 5 The diagram illustrates an arrangement of interconnect 500. The arrangement of interconnect 500 may represent an arrangement of interconnects between (i) an integrated device and a substrate, (ii) an integrated device and a PCB, and / or (iii) a substrate and a PCB. However, the arrangement of interconnect 500 may represent an interconnection between other components and / or devices. In some embodiments, one or more of the interconnects from the arrangement of interconnect 500 may include a pillar interconnect (e.g., a bump). One or more of the interconnects from the arrangement of interconnect 500 may include interconnect structure 200.

[0036] like Figure 5 As shown in , arrangement of interconnects 500 includes a first plurality of interconnects 510 , a second plurality of interconnects 520 , a third plurality of interconnects 530 , a fourth plurality of interconnects 540 , a fifth plurality of interconnects 550 , a sixth plurality of interconnects 560 , a seventh plurality of interconnects 570 , an eighth plurality of interconnects 580 , and a ninth plurality of interconnects 590 .

[0037] The first plurality of interconnects 510 is configured to provide an electrical path for ground. The second plurality of interconnects 520 is configured to provide an electrical path for a first I / O signal. The third plurality of interconnects 530 is configured to provide an electrical path for power. The fourth plurality of interconnects 540 is configured to provide an electrical path for the first I / O signal. The fifth plurality of interconnects 550 is configured to provide an electrical path for ground. The sixth plurality of interconnects 560 is configured to provide an electrical path for a second I / O signal. The seventh plurality of interconnects 570 is configured to provide an electrical path for power. The eighth plurality of interconnects 580 is configured to provide an electrical path for a second I / O signal. The ninth plurality of interconnects 590 is configured to provide an electrical path for ground.

[0038] In some embodiments, the second plurality of interconnects 520, the fourth plurality of interconnects 540, the sixth plurality of interconnects 560, and / or the eighth plurality of interconnects 580 may include one or more interconnect structures 200. When one or more interconnect structures 200 are used in the second plurality of interconnects 520, the fourth plurality of interconnects 540, the sixth plurality of interconnects 560, and / or the eighth plurality of interconnects 580, crosstalk between signals traveling through the interconnects is reduced and minimized, thereby improving the signal integrity of the signals (e.g., the first I / O signal, the second I / O signal). Note that the interconnect structure 200 may also be implemented in the first plurality of interconnects 510, the third plurality of interconnects 530, the fifth plurality of interconnects 550, the seventh plurality of interconnects 570, and / or the ninth plurality of interconnects 590.

[0039] An exemplary integrated device including an interconnect structure having an internal interconnect, a dielectric layer, and an external conductive layer

[0040] Figure 6An integrated device 600 is illustrated that includes an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The integrated device 600 includes a substrate 620, a plurality of device-level cells 622, an interconnect portion 604, and an encapsulation portion 606. The plurality of device-level cells 622 are formed over the substrate 620. The plurality of device-level cells 622 may form a device-level layer of the integrated device 600. In some embodiments, the plurality of device-level cells 622 may include portions of the substrate 620. In some embodiments, the substrate 620, the device-level layer, and the plurality of device-level cells 622 may be referred to as a substrate portion 602 of the integrated device 600. The plurality of device-level cells 622 may include logic cells and / or transistors as part of a circuit.

[0041] The interconnect portion 604 is located above the substrate portion 602. Specifically, the interconnect portion 604 is located above the plurality of device-level cells 622 and the substrate 620. The interconnect portion 604 includes a wiring layer. The interconnect portion 604 includes a plurality of interconnects 640 (e.g., traces, pads, vias) and at least one dielectric layer 642. The plurality of interconnects 640 can form the wiring layer of the interconnect portion 604.

[0042] The packaging portion 606 is formed over the interconnect portion 604. The packaging portion 606 includes a dielectric layer 660 and interconnect structures 200a-200c. Each of the interconnect structures 200a-200c can be coupled to an interconnect (e.g., pad 644), which can be part of the plurality of interconnects 640. The interconnect structures (e.g., 200a-200c) can be located over the interconnect portion 604 and / or over the interconnects of the interconnect portion 604. The interconnect structures 200a-200c can be configured to provide an electrical path for one or more I / O signals. A solder interconnect 690 is coupled to the interconnect structure 200c. In particular, the solder interconnect 690 is coupled to the internal interconnect 210.

[0043] Figure 7 Another integrated device 700 is shown including an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The integrated device 700 is similar to Figure 6 The integrated device 600 is similar to the integrated device 600 and may include components similar to the integrated device 600. The integrated device 700 includes the interconnect structures 200a-200c. Figure 7 As shown in FIG, interconnect structure 200b is coupled to interconnect 744, which is coupled to interconnect structure 200c. Interconnect 744 can be considered a portion of plurality of interconnects 640.

[0044] Figure 8Another integrated device 800 is shown including an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The integrated device 800 is similar to Figure 6 The integrated device 600 is similar to the integrated device 600 and may include components similar to the integrated device 600. The integrated device 800 includes a package portion 806 coupled to the interconnect portion 604. The package portion 806 includes the pad 644, the under-bump metallization (UBM) 844, the dielectric layer 660, the dielectric layer 760, and the interconnect structures 200a-200c. The dielectric layer 660 and / or the dielectric layer 760 may be a passivation layer. Figure 8 As shown in FIG, interconnect structure 200c is coupled to under bump metallization (UBM) 844. Specifically, internal interconnect 210 is coupled to UBM 844. UBM 844 is coupled to pad 644. Interconnect structure 200c is located above interconnect portion 604.

[0045] Figure 9 Another integrated device 900 is shown including an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The integrated device 900 is similar to Figure 8 The integrated device 800 is shown and may include components similar to the integrated device 800. The integrated device 900 includes a packaging portion 906, which includes the UBM 944, the dielectric layer 660, the dielectric layer 760, and the interconnect structures 200a-200c. Figure 9 As shown in FIG, interconnect structure 200b is coupled to UBM 944, which is coupled to interconnect structure 200c.

[0046] Figure 10 Another integrated device 1000 is shown including an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The integrated device 1000 is similar to Figure 6 The integrated device 1000 is similar to the integrated device 600 and may include components similar to the integrated device 600. The integrated device 1000 includes a package portion 1006 coupled to the interconnect portion 604. The package portion 1006 includes a pillar interconnect 1010, interconnect structures 200a and 200c, and an interconnect 1062 (e.g., a package interconnect). The pillar interconnect 1010 includes an internal interconnect 210 and a solder interconnect 690. The pillar interconnect 1010 can be coupled to a pad 1044. The pillar interconnect 1010 can be configured to provide an electrical path for grounding. Figure 10As shown in FIG, the internal interconnect 210 of the interconnect structure 200c is coupled to the pad 644. The external conductive layer 230 of the interconnect structure 200c is coupled to the interconnect 1062 (e.g., a package interconnect). The interconnect 1062 is coupled to the internal interconnect 210 and / or the pad 1044 of the pillar interconnect 1010. Because the pillar interconnect 1010 is configured to provide an electrical path for grounding and / or is configured to be coupled to ground, the external conductive layer 230 of the interconnect structure 200c is also configured to be coupled to ground. When the external conductive layer 230 of the interconnect structure 200c is configured to be coupled to ground, it helps provide better isolation for signals (e.g., I / O signals) traveling through the interconnect structure 200c.

[0047] Figure 11 Another integrated device 1100 is shown including an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The integrated device 1100 is similar to Figure 8 1 . The integrated device 1100 is similar to the integrated device 800 and may include similar components as the integrated device 800. The integrated device 1100 includes a package portion 1106 coupled to the interconnect portion 604. The package portion 1106 includes a pillar interconnect 1010, interconnect structures 200a, 200c, an interconnect 1162 (e.g., a package interconnect), and a dielectric layer 1170. The pillar interconnect 1010 includes an internal interconnect 210 and a solder interconnect 690. The pillar interconnect 1010 may be coupled to a UBM 1144.

[0048] Pillar interconnect 1010 may be configured to provide an electrical path for grounding and / or configured to couple to ground. Figure 11 As shown in FIG, the internal interconnect 210 of the interconnect structure 200c is coupled to the UBM 844. The external conductive layer 230 of the interconnect structure 200c is coupled to the interconnect 1162 (e.g., package interconnect, UBM). The interconnect 1162 is coupled to the internal interconnect 210 of the pillar interconnect 1010 and / or the UBM 1144. Because the pillar interconnect 1010 is configured to be coupled to ground, the external conductive layer 230 of the interconnect structure 200c is also configured to be coupled to ground. When the external conductive layer 230 of the interconnect structure 200c is configured to be coupled to ground, it helps provide better isolation for signals traveling through the interconnect structure 200c.

[0049] Figure 2-Figure 4 and Figures 6-11The internal interconnect 210 of the interconnect structure is shown coupled to the interconnects (e.g., 250, 644, 844, 944) without requiring a solder interconnect between the internal interconnect 210 and the interconnects of the interconnect portion 604 and / or the interconnects of the package portion. Thus, in some embodiments, the internal interconnect 210 of the interconnect structure can be coupled to the interconnects of the interconnect portion (e.g., 604) and / or the interconnects of the package portion (e.g., 904) such that the joint between the internal interconnect 210 and the interconnects (e.g., 644, 844) is free of solder interconnect. Note that Figures 6-11 The integrated device may include other interconnect structures and / or pillar interconnects that may be configured to provide electrical paths for ground, power, and / or I / O signals. Figures 6-11 One or more of the integrated devices may be examples of wafer-level package (WLP) integrated devices.

[0050] Exemplary sequence for fabricating an integrated device comprising an interconnect structure having internal interconnects, a dielectric layer, and an external conductive layer

[0051] In some embodiments, manufacturing an integrated device including an interconnect structure includes several processes. Figures 12A-12F ) illustrates an exemplary sequence for providing or manufacturing an integrated device including an interconnect structure. In some embodiments, Figures 12A-12F The sequence can be used to provide or make Figure 6 The integrated device 600 and / or other integrated devices described in this disclosure.

[0052] It should be noted that Figures 12A-12F The sequence of steps may be combined into one or more stages to simplify and / or clarify the sequence for providing or manufacturing an integrated device including an interconnect structure. In some embodiments, the order of the steps may be changed or modified. In some embodiments, one or more steps in the process may be replaced or substituted without departing from the spirit of the present disclosure.

[0053] like Figure 12A As shown in FIG, stage 1 illustrates a state after substrate formation, wherein a substrate 620 is provided or formed. Different embodiments may provide different materials for the substrate 620. In some embodiments, the substrate 620 may include silicon.

[0054] Stage 2 illustrates a state after device-level formation, where a device-level layer is formed on a substrate 620. The device-level layer may include a plurality of device-level cells 622. Thus, stage 2 may illustrate a state after forming a plurality of device-level cells 22 on substrate 620. In some embodiments, the device-level layer (e.g., the plurality of device-level cells 622) may be fabricated using a front-end-of-line (FEOL) process. The plurality of device-level cells may include logic cells and / or transistors for a circuit. Stage 2 may illustrate substrate portion 602.

[0055] Stage 3 illustrates the state after the wiring layer is formed, wherein interconnect portion 604 is formed. Interconnect portion 604 may include a plurality of interconnects 640 (and pads 644) and at least one dielectric layer 642. In some embodiments, interconnect portion 604 may be manufactured using a back-end-of-line (BEOL) process.

[0056] like Figure 12B , stage 4 illustrates a state after dielectric layer formation, wherein a dielectric layer 660 is formed over the interconnect 604. A lamination process may be used to form the dielectric layer 660. The dielectric layer 660 may be a passivation layer.

[0057] Stage 5 illustrates a state after pattern resist formation and patterning, wherein a pattern resist layer 1110 is formed and etched over the dielectric layer 660 .

[0058] like Figure 12C As shown in FIG, stage 6 illustrates a state after the internal interconnection and solder interconnection are formed, wherein the internal interconnection 210 and the solder interconnection 690 are provided. In some embodiments, the internal interconnection 210 can be formed using a plating process (e.g., electroplating). The solder interconnection 690 can be provided by a pasting process. Different embodiments may provide the internal interconnection 210 and / or the solder interconnection 690 differently.

[0059] Stage 7 illustrates the state after pattern resist removal, where the pattern resist layer 1110 is removed, leaving the internal interconnect 210 coupled to the pad (eg, 644).

[0060] like Figure 12D , stage 8 illustrates a state after dielectric layer formation, wherein dielectric layer 1120 is formed. A lamination process may be used to form dielectric layer 1120. Dielectric layer 1120 may include a photoetchable layer or a photosensitive dielectric layer.

[0061] Stage 9 illustrates a state after dielectric layer patterning, where dielectric layer 1120 is patterned to form dielectric layer 220 laterally surrounding internal interconnect 210. Dielectric layer 1120 may be patterned using an etching process (e.g., a photoetching process) to form dielectric layer 220 around internal interconnect 210.

[0062] like Figure 12E As shown in FIG, stage 10 illustrates a state after the conductive layer is formed, wherein a conductive layer 1130 (e.g., metal) is disposed over dielectric layer 660 and around dielectric layer 220. Conductive layer 1130 may be a photosensitive layer or a photoetchable layer. Conductive layer 1130 may include a conductive layer and / or a conductive material.

[0063] Stage 11 illustrates a state after the outer conductive layer is patterned and formed, wherein the conductive layer 1130 is etched to form the outer conductive layer 230 surrounding the dielectric layer 220 and the internal interconnect 210. In some embodiments, the conductive layer 1130 can be patterned into the outer conductive layer 230 using an etching process (e.g., a photolithography process).

[0064] like Figure 12F As shown in FIG, stage 12 illustrates a state after reflow, where a reflow process is used on the solder interconnect 690 to couple the solder interconnect 690 to an interconnect. The solder interconnect 690 may be coupled to a pad (e.g., a pad of a substrate, a pad of a PCB). Note that stages 11 and 12 may illustrate Figure 6 An integrated device 600.

[0065] Exemplary sequence for fabricating an integrated device comprising an interconnect structure having internal interconnects, a dielectric layer, and an external conductive layer

[0066] In some embodiments, manufacturing an integrated device including an interconnect structure includes several processes. Figures 13A-13E ) illustrates an exemplary sequence for providing or manufacturing an integrated device including an interconnect structure. In some embodiments, Figures 13A-13E The sequence can be used to provide or make Figure 11 The integrated device 1100 and / or other integrated devices described in this disclosure.

[0067] It should be noted that Figures 13A-13E The sequence of steps may be combined into one or more stages to simplify and / or clarify the sequence for providing or manufacturing an integrated device including an interconnect structure. In some embodiments, the order of the steps may be changed or modified. In some embodiments, one or more steps in the process may be replaced or substituted without departing from the spirit of the present disclosure.

[0068] like Figure 13AAs shown in FIG, stage 1 illustrates the state after the substrate, device level and wiring layers are formed. Stage 1 also illustrates the state after the dielectric layer 660 has been formed. In some embodiments, Figure 13A Phase 1 can be similar to and represent the above Figures 12A-12B Stage 1-Stage 4.

[0069] Stage 2 illustrates a state after dielectric layer formation, where dielectric layer 1160 is formed over dielectric layer 660. A lamination process may be used to form dielectric layer 1160. Dielectric layer 1160 may be a passivation layer.

[0070] like Figure 13B As shown in FIG, stage 3 illustrates a state after under bump metallization (UBM) formation, where UBM 844 is formed over pad 644. A plating process may be used to form UBM 844. However, different embodiments may form UBM 844 differently.

[0071] Stage 4 illustrates a state after dielectric layer formation, where dielectric layer 1170 is formed over dielectric layer 1160. A lamination process may be used to form dielectric layer 1170. Dielectric layer 1170 may be a passivation layer.

[0072] like Figure 13C As shown in FIG, stage 5 illustrates a state after the internal interconnect and solder interconnect are formed, wherein the internal interconnect 210 and the solder interconnect 690 are provided. In some embodiments, a pattern resist layer is formed and etched over the dielectric layer, and the internal interconnect and the solder interconnect are formed. In some embodiments, the internal interconnect 210 can be formed using a plating process (e.g., electroplating). The solder interconnect 690 can be provided by a pasting process. Different embodiments can provide the internal interconnect 210 and / or the solder interconnect 690 differently. After providing the internal interconnect 210 and the solder interconnect 690, the pattern resist layer can be removed, leaving the internal interconnect 210 coupled to the UBM (e.g., 844). Figure 12B-12C Stages 5-7 illustrate and describe examples of forming internal interconnects and providing solder interconnects.

[0073] Stage 6 illustrates a state after dielectric layer formation, where dielectric layer 220 is formed around internal interconnect 210. In some embodiments, dielectric layer formation can include forming dielectric layer 1120 and patterning the dielectric layer to form dielectric layer 220. A lamination process can be used to form dielectric layer 1120. Dielectric layer 1120 can include a photoetchable or photosensitive dielectric layer. Figure 12D Stages 8-9 illustrate and describe an example of forming a dielectric layer around internal interconnects.

[0074] like Figure 13DAs shown in FIG, stage 7 illustrates a state after outer conductive layer formation, wherein a conductive layer (e.g., 1130) is formed and then patterned to form outer conductive layer 230 for interconnect structure 200 (e.g., 200a, 200c). Stage 7 illustrates that pillar interconnect 1010 is not surrounded by dielectric layer 220 or outer conductive layer 230. Pillar interconnect 1010 can be configured to provide an electrical path for grounding. Outer conductive layer formation can include: arranging a conductive layer (e.g., 1130) over dielectric layer (e.g., 660, 1160, 1170) and surrounding dielectric layer 220. Conductive layer 1130 can be a photosensitive layer or a photoetchable layer. Conductive layer 1130 can be patterned to form outer conductive layer 230. In some embodiments, conductive layer 1130 can be patterned into outer conductive layer 230 using an etching process (e.g., a photoetching process). Figure 12D Stages 10-11 of FIG. 1 illustrate and describe an example of forming an outer conductive layer.

[0075] Stage 8 illustrates a state after interconnects are formed over the dielectric layer, wherein interconnect 1162 (e.g., a package interconnect) is formed such that interconnect 1162 is coupled to the outer conductive layer 230 of interconnect structure 200c and to the inner interconnect 210 of pillar interconnect 1010. Interconnect 1162 can be formed such that interconnect 1162 is coupled to UBM 1144. Pillar interconnect 1010 is configured to be coupled to ground. As such, outer conductive layer 230 of interconnect structure 200c can also be configured to be coupled to ground. Interconnect 1162 can be formed using a plating process.

[0076] like Figure 13E As shown in FIG, stage 9 illustrates a state after reflow, where a reflow process is used on the solder interconnect 690 to couple the solder interconnect 690 to an interconnect. The solder interconnect 690 may be coupled to a pad (e.g., a pad of a substrate, a pad of a PCB). Note that stages 8 and 9 may illustrate Figure 11 Integrated device 1100.

[0077] Exemplary flow chart of a method for fabricating an integrated device including an interconnect structure having an internal interconnect, a dielectric layer, and an external conductive layer

[0078] In some embodiments, fabricating an integrated device including an interconnect structure having internal interconnects, a dielectric layer, and an external conductive layer includes several processes. Figure 14 An exemplary flow chart of a method 1400 for providing or manufacturing an integrated device including internal interconnects, dielectric layers, and external conductive layers is illustrated. In some embodiments, Figure 14 The method 1400 may be used to provide or manufacture the Figure 6However, method 1400 may be used to provide or manufacture any integrated device and / or package described in this disclosure.

[0079] It should be noted that Figure 14 The sequence of the processes may combine one or more processes to simplify and / or clarify a method for providing or manufacturing an integrated device including internal interconnects, dielectric layers, and external conductive layers. In some embodiments, the order of the processes may be changed or modified.

[0080] The method provides (at 1405) a substrate, such as substrate 620. The substrate may comprise silicon. However, the substrate may comprise different materials.

[0081] The method forms (at 1410) a device-level layer over a substrate (e.g., 620). Forming the device-level layer may include forming a plurality of device-level cells 622. The plurality of device-level cells may include logic cells and / or transistors as part of a circuit. In some embodiments, the device-level layer may be fabricated using a front-end-of-line (FEOL) process.

[0082] The method forms (at 1420) an interconnect portion (e.g., 604) over the device-level layer and / or substrate. Forming the interconnect portion can include forming a plurality of interconnects 640 (and pads 644) and at least one dielectric layer 642. In some embodiments, the interconnect portion 604 can be manufactured using a back-end-of-line (BEOL) process. The method can also form (at 1420) a dielectric layer (e.g., 660) over the interconnect portion 604. Figures 12A-12B Stages 3-4 illustrate an example of interconnection portion formation.

[0083] The method forms (at 1425) a package portion (e.g., 606, 806, 906, 1006, 1106) over the interconnect portion. Forming the package portion may include forming dielectric layers (e.g., 1160, 1170), UBMs (e.g., 844, 944), and interconnects (e.g., 1010, 1062, 1162). The package portion may be formed using a lamination and plating process. However, different embodiments may form the package portion differently. Figures 13A-13B Stages 2-4 illustrate an example of package portion formation.

[0084] The method forms (at 1430) an interconnect structure (e.g., 200a-200h) over the interconnect portion or package portion. The interconnect structure (e.g., 200a-200h) can be considered part of the package portion and, therefore, can be formed when the package portion is formed. The interconnect structure can include an internal interconnect 210, a dielectric layer 220, and an outer conductive layer 230. The outer conductive layer 230 can include a conductive layer. The outer conductive layer 230 is configured to not electrically contact the internal interconnect 210. The outer conductive layer 230 can be configured to serve as a shield (e.g., an EMI shield) for the internal interconnect 210, thereby providing improved isolation for signals traveling through the internal interconnect 210. The outer conductive layer 230 can be configured to be coupled to ground. A solder interconnect (e.g., 690) can be coupled to the internal interconnect 210. Figure 13C-13D Stages 5-8 illustrate an example of interconnect structure formation.

[0085] An exemplary package including an interconnect structure having an internal interconnect, a dielectric layer, and an external conductive layer

[0086] Figure 15 A package 1500 is shown that includes an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an outer conductive layer 230. The package 1500 (e.g., an integrated device package) includes an integrated device 1502 (e.g., a die) and a substrate 1504 (e.g., a package substrate). The integrated device 1502 is coupled to the substrate 1504 via a plurality of solder interconnects 1520. The package 1500 also includes a plurality of interconnect structures 200 (e.g., 200a-200c), each of which includes an internal interconnect 210, a dielectric layer 220, and an outer conductive layer 230. The plurality of interconnect structures 200 are coupled to the substrate 1504 and a board 1506 (e.g., a PCB). For example, the interconnect structure 200c is coupled to an interconnect 1544 (e.g., a pad) of the substrate 1504 and an interconnect 1564 of the board 1506. The use of interconnect structures 200a-200c reduces the amount of crosstalk that may exist between signals traveling through the interconnects because outer conductive layer 230 shields and isolates signals traveling through internal interconnect 210. Outer conductive layer 230 may be configured to provide EMI shielding for signals traveling through internal interconnect 210.

[0087] Figure 16 Another package 1600 is shown including an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The package 1600 (eg, an integrated device package) is similar to Figure 15Package 1500 of FIG. 1600 includes similar components to package 1500. Package 1600 includes a substrate 1504 (eg, a package substrate). Substrate 1504 includes an interconnect 1644 coupled to interconnect structure 200b and interconnect structure 200c.

[0088] Figure 17 Another package 1700 is shown including an interconnect structure having an internal interconnect 210, a dielectric layer 220, and an external conductive layer 230. The package 1700 is similar to Figure 15 Package 1500 of FIG. 1700 includes components similar to package 1500. Package 1700 (e.g., an integrated device package) includes substrate 1504 (e.g., a package substrate). Substrate 1504 includes dielectric layer 1760, interconnect 1744, interconnect 1762 (e.g., a substrate interconnect), and interconnect 1544. Dielectric layer 1760 may be a solder resist layer. Package 1700 also includes pillar interconnect 1710 and interconnect structures 200a and 200c. Pillar interconnect 1710 includes internal interconnect 210 and solder interconnect 1790. Pillar interconnect 1710 may include copper pillars. Board 1506 (e.g., a PCB) includes interconnect 1564 and interconnect 1764.

[0089] like Figure 17 As shown in FIG, interconnect structure 200c is coupled to interconnect 1544 of substrate 1504 and to interconnect 1564 of plate 1506. Similarly, pillar interconnect 1710 is coupled to interconnect 1744 of substrate 1504 and to interconnect 1764 of plate 1506. Pillar interconnect 1710 is configured to provide an electrical path for grounding. Interconnect 1762 (e.g., a substrate interconnect) is located above dielectric layer 1760. Interconnect 1762 is coupled to interconnect 1764 and / or to internal interconnect 210 of pillar interconnect 1710. Interconnect 1762 is also coupled to outer conductive layer 230 of interconnect structure 200c. Thus, outer conductive layer 230 of interconnect structure 200c is indirectly coupled to internal interconnect 210 of pillar interconnect 1710. Because the pillar interconnect 1710 is configured to provide an electrical path for grounding (e.g., is configured to be coupled to ground), the outer conductive layer 230 of the interconnect structure 200c is also configured to provide an electrical path for grounding (e.g., is configured to be coupled to ground). When the outer conductive layer 230 of the interconnect structure 200c is configured to be coupled to ground, it helps provide better isolation for signals traveling through the internal interconnects 210 of the interconnect structure 200c.

[0090] Notice, Figure 15-17The package may include other interconnect structures and / or pillar interconnects that may be configured to provide electrical paths for ground, power, and / or I / O signals. For example, an interconnect structure (e.g., 200) may be present between the integrated device 1502 and the substrate 1504.

[0091] Exemplary electronic devices

[0092] Figure 18 Various electronic devices are shown that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, bare dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SOC). For example, a mobile phone device 1802, a laptop computer device 1804, a fixed location terminal device 1806, a wearable device 18018, or a motor vehicle 1810 can include a device 1800 as described herein. The device 1800 can be, for example, any of the devices described herein and / or integrated circuit (IC) packages. Figure 18 The devices 1802, 1804, 1806, and 18018 and the vehicle 1810 shown in the figure are merely exemplary. Other electronic devices may also feature the device 1800, including but not limited to the group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0093] exist Figure 2-Figure 11 、 Figures 12A-12F 、 Figures 13A-13E and / or Figures 14-18 One or more of the components, processes, features, and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 2-Figure 11 、 Figures 12A-12F 、 Figures 13A-13E and / or Figures 14-18 and their corresponding descriptions in this disclosure are not limited to bare chips and / or ICs. In some embodiments, Figure 2-Figure 11 、 Figures 12A-12F 、 Figures 13A-13E and / or Figures 14-18 The present invention and its corresponding description can be used to manufacture, create, provide and / or produce devices and / or integrated devices. In some embodiments, the device can include a bare die, an integrated device, an integrated passive device (IPD), a bare die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink and / or an interposer.

[0094] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the drawings may not be to scale. In some cases, for clarity, not all components and / or parts may be shown. In some cases, the positioning, location, size, and / or shape of various components and / or assemblies in the drawings may be exemplary. In some embodiments, the various components and / or parts in the drawings may be optional.

[0095] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" as used herein refers to a direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. The term "encapsulate" means that an object can partially encapsulate or completely encapsulate another object. It should also be noted that the term "on," as used herein in the context of one component being on top of another component, can be used to mean a component that is on and / or in (e.g., on the surface of or embedded in) another component. Thus, for example, a first component being on top of a second component can mean that (1) the first component is on top of the second component, but not in direct contact with the second component; (2) the first component is on (the surface of) the second component; and / or (3) the first component is in (e.g., embedded in) the second component. The term “about 'value X'” or “approximate value X” used in this disclosure means within 10% of 'value X.' For example, a value of about 1 or approximately 1 may mean a value within the range of 0.9 to 1.1.

[0096] In some embodiments, interconnection is an element or component of a device or package, and interconnection allows or promotes electrical connection between two points, elements and / or components. In some embodiments, interconnection may include traces, vias, pads, pillars, redistributed metal layers and / or under bump metallization (UBM) layers. Interconnection may include one or more metal components (e.g., seed layer+metal layer). In some embodiments, interconnection includes a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), grounding or power supply. Interconnection may be part of a circuit. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Different embodiments may use similar or different processes to form interconnection. In some embodiments, chemical vapor deposition (CVD) process and / or physical vapor deposition (PVD) process are used to form interconnection. For example, sputtering process, spraying and / or plating process may be used to form interconnection.

[0097] In addition, it is noted that various disclosures contained herein may be described as processes, which are depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe operations as a sequential process, many of the operations may be performed in parallel or concurrently. Furthermore, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0098] The various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the foregoing aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of aspects of the present disclosure is intended to be illustrative, not limiting, of the scope of the claims. As such, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An integrated device comprising: substrate; An interconnection portion is located on the substrate, wherein the interconnection portion comprises: multiple interconnections; and at least one dielectric layer; a plurality of pillar interconnects coupled to the interconnect portion, wherein the plurality of pillar interconnects are located above the substrate and the interconnect portion, and wherein the plurality of pillars interconnect comprises: a first plurality of pillar interconnects configured to provide an electrical path for ground, wherein the first plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and a second plurality of pillar interconnects configured to provide an electrical path for a power source, wherein the second plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and a plurality of interconnect structures coupled to and located over the interconnect portion, wherein the plurality of interconnect structures includes a first plurality of interconnect structures configured to provide electrical paths for input / output signals, wherein the first plurality of interconnect structures are arranged into at least one row of interconnect structures, wherein at least one row of interconnect structures from the first plurality of interconnect structures is located between (i) at least one row of pillar interconnects from the first plurality of pillar interconnects and (ii) at least one row of pillar interconnects from the second plurality of pillar interconnects, and The interconnection structures in the plurality of interconnection structures include: Internal interconnection; a dielectric layer coupled to the internal interconnect; and An outer conductive layer is coupled to the dielectric layer, wherein the outer conductive layer is configured to serve as a shield for the internal interconnect. 2 . The integrated device of claim 1 , wherein the dielectric layer laterally surrounds the internal interconnect, and the dielectric layer separates the outer conductive layer from the internal interconnect. The integrated device according to claim 1 , wherein the interconnect structure comprises a bump interconnect structure. 4 . The integrated device of claim 1 , wherein the interconnect structure is configured to provide an electrical path for input / output (I / O) signals.

5. The integrated device according to claim 4, wherein the internal interconnect is configured to provide an electrical path for the input / output signals, and The outer conductive layer is configured to shield I / O signals traveling through the internal interconnect. The integrated device of claim 1 , wherein the outer conductive layer is configured to be coupled to ground. 7 . The integrated device of claim 1 , wherein the first plurality of pillar interconnects includes a pillar interconnect located over the interconnect portion, and wherein the pillar interconnect is configured to provide an electrical path for grounding. 8 . The integrated device of claim 7 , further comprising a package interconnect coupled to the external conductive layer and the pillar interconnect such that the external conductive layer is configured to be coupled to ground.

9. The integrated device of claim 1, wherein the integrated device is a wafer-level package.

10. The integrated device of claim 1 , wherein the integrated device is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

11. A device comprising: substrate; an integrated device coupled to the substrate; a plurality of pillar interconnects coupled to the substrate, wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects configured to provide an electrical path for ground, wherein the first plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and a second plurality of pillar interconnects configured to provide an electrical path for a power source, wherein the second plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and a member for shielding interconnection, coupled to the substrate, wherein the component for shielding interconnection is configured to provide an electrical path for a signal such that the signal is shielded when the signal travels through the component for shielding interconnection, wherein the means for shielding interconnection comprises a first plurality of interconnect structures configured to provide electrical paths for input / output signals, wherein the first plurality of interconnect structures are arranged into at least one row of interconnect structures, and wherein at least one row of interconnect structures from the first plurality of interconnect structures is located between (i) at least one row of pillar interconnects from the first plurality of pillar interconnects and (ii) at least one row of pillar interconnects from the second plurality of pillar interconnects.

12. The apparatus of claim 11, wherein the means for shielding the interconnection comprises: Internal interconnection; a dielectric layer coupled to the internal interconnect; as well as An outer conductive layer is coupled to the dielectric layer, wherein the outer conductive layer is configured to serve as a shield for the internal interconnect.

13. The device of claim 12, wherein the dielectric layer laterally surrounds the internal interconnect and separates the outer conductive layer from the internal interconnect.

14. The device according to claim 12, wherein the internal interconnect is configured to provide an electrical path for input / output (I / O) signals, and The outer conductive layer is configured to shield I / O signals traveling through the internal interconnect. The apparatus of claim 12 , wherein the outer conductive layer is configured to be coupled to ground. 16 . The apparatus of claim 11 , wherein the first plurality of pillar interconnects comprises a pillar interconnect coupled to the substrate, and wherein the pillar interconnect is configured to provide an electrical path for ground. 17 . The apparatus of claim 16 , further comprising a substrate interconnect coupled to the pillar interconnect and an outer conductive layer of the member for shielding interconnection, such that the outer conductive layer is configured to be coupled to a ground.

18. The apparatus of claim 11, wherein the apparatus is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

19. A device comprising: substrate; an integrated device coupled to the substrate; a plurality of pillar interconnects coupled to the substrate, and wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects configured to provide an electrical path for ground, wherein the first plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and a second plurality of pillar interconnects configured to provide an electrical path for a power source, wherein the second plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and a plurality of interconnect structures coupled to the substrate, wherein the plurality of interconnect structures includes a first plurality of interconnect structures configured to provide electrical paths for input / output signals, wherein the first plurality of interconnect structures are arranged into at least one row of interconnect structures, wherein at least one row of interconnect structures from the first plurality of interconnect structures is located between (i) at least one row of pillar interconnects from the first plurality of pillar interconnects and (ii) at least one row of pillar interconnects from the second plurality of pillar interconnects, wherein an interconnect structure of the plurality of interconnect structures is configured to provide an electrical path for a signal such that the signal is shielded when the signal travels through the interconnect structure, and The interconnect structure comprises: Internal interconnection; a dielectric layer coupled to the internal interconnect; and An outer conductive layer is coupled to the dielectric layer, wherein the outer conductive layer is configured to serve as a shield for the internal interconnect.

20. The device of claim 19, wherein the outer conductive layer is configured to be coupled to ground.

21. The device of claim 19, wherein the first plurality of pillar interconnects includes a pillar interconnect coupled to the substrate, and wherein the pillar interconnect is configured to provide an electrical path for ground.

22. The device of claim 21, further comprising a package interconnect coupled to the outer conductive layer and the pillar interconnect such that the outer conductive layer is configured to be coupled to ground.

23. A method for manufacturing an integrated device, comprising: providing a substrate; forming an interconnection portion over the substrate; forming a plurality of pillar interconnects coupled to the interconnect portion, wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects configured to provide an electrical path for ground, wherein the first plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and a second plurality of pillar interconnects configured to provide an electrical path for a power source, wherein the second plurality of pillar interconnects are arranged in at least one row of pillar interconnects, and forming a plurality of interconnect structures coupled to and over the interconnect portion, wherein the plurality of interconnect structures includes a first plurality of interconnect structures configured to provide electrical paths for input / output signals, wherein the first plurality of interconnect structures are arranged into at least one row of interconnect structures, wherein at least one row of interconnect structures from the first plurality of interconnect structures is located between (i) at least one row of pillar interconnects from the first plurality of pillar interconnects and (ii) at least one row of pillar interconnects from the second plurality of pillar interconnects, and The interconnection structures in the plurality of interconnection structures include: Internal interconnection; a dielectric layer coupled to the internal interconnect; and An outer conductive layer is coupled to the dielectric layer, wherein the outer conductive layer is configured to serve as a shield for the internal interconnect.

24. The method of claim 23, wherein the interconnect structure is configured to provide an electrical path for input / output (I / O) signals.

25. The method according to claim 24, wherein the internal interconnect is configured to provide an electrical path for the input / output signals, and The outer conductive layer is configured to shield I / O signals traveling through the internal interconnect.

26. The method of claim 23, wherein the outer conductive layer is configured to be coupled to ground.

27. The method of claim 23, wherein the first plurality of pillar interconnects includes pillar interconnects over the interconnect portion, and wherein the pillar interconnects are configured to provide an electrical path for grounding.

28. The method of claim 27, further comprising forming a package interconnect coupling the outer conductive layer and the pillar interconnect such that the outer conductive layer is configured to couple to ground.

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