Method, device, equipment and storage medium for implementing large number modulus

Abstract

The present application relates to a method, device, equipment and storage medium for implementing large number modulus. The method includes reading a modulus and a modulus to be taken; calculating a perfect square difference corresponding to the modulus and the modulus to be taken; using a shift combination logic circuit to determine the existence of a quotient of the perfect square difference to the modulus, and estimating the quotient of the perfect square difference to the modulus; using the quotient and the modulus, obtaining a modulus result corresponding to the square of the modulus to be taken and the modulus. Since a shift combination logic circuit can be used to determine the existence of a quotient of the perfect square difference to the modulus, and to estimate the quotient of the perfect square difference to the modulus, the determination and estimation of the quotient are realized through a hardware circuit, thereby saving the consumption of software resources.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a method, device, equipment and storage medium for implementing large number modulus. Background Art

[0002] In the process of implementing public key algorithms, large number modulus operation is a common operation method. Both the modulus and the modulus to be taken are large numbers. Usually, the length of the modulus and the modulus to be taken will exceed 1024 bits. In order to meet the security strength requirements, the length of the modulus and the modulus to be taken is required to be more than 3072 bits.

[0003] For operation data of such length, CPU-based operations will consume a lot of CPU multiplication and subtraction resources and occupy CPU scheduling resources, which is not conducive to improving the overall large number operation performance. Summary of the invention

[0004] The present application provides a method, device, equipment and storage medium for implementing large number modulo operation, so as to solve the problem of excessive consumption of CPU resources when using software algorithm to implement large number modulo operation.

[0005] In a first aspect, a method for implementing large number modulus is provided, comprising:

[0006] Read the modulus and the taken modulus;

[0007] Calculating a perfect square difference corresponding to the modulus and the taken modulus;

[0008] Using a shift combinational logic circuit, determining that there is a quotient of the perfect square difference value to the modulus, and estimating the quotient of the perfect square difference value to the modulus;

[0009] Using the quotient and the modulus, a modulo result corresponding to the square of the modulus and the modulus is obtained.

[0010] Optionally, calculating the perfect square difference corresponding to the modulus and the taken modulus includes:

[0011] Calling a large number subtraction circuit to obtain a first difference between the modulus and the taken modulus;

[0012] Calling a large number multiplication circuit to obtain the square value of the first difference;

[0013] The square value returned by the large number multiplication circuit is obtained, and the square value is used as the perfect square difference value.

[0014] Optionally, the shift combination logic circuit includes a shift logic circuit and a judgment logic circuit;

[0015] Determining the existence of a quotient of the perfect square difference value to the modulus using a shift combinational logic circuit comprises:

[0016] Utilizing the shift logic circuit, right-shifting the perfect square difference by a first bit from the lowest bit to obtain right-shifted result data, wherein the first bit has the same bit length as the modulus;

[0017] The judgment logic circuit is used to determine whether the right-shift result data are not all first preset values, wherein when the right-shift result data are not all first preset values, it is determined that there is a quotient of the perfect square difference value to the modulus.

[0018] Optionally, estimating a quotient of the perfect square difference to the modulus comprises:

[0019] The right-shift result data returned by the shift logic circuit is acquired, and the right-shift result data is used as the quotient value.

[0020] Optionally, using the quotient and the modulus to obtain a modulo result corresponding to the square of the modulus and the modulus includes:

[0021] Calling the large number multiplication circuit to calculate the product value of the right-shifted result data and the modulus;

[0022] Calling the large number subtraction circuit to calculate a second difference between the perfect square difference and the product value;

[0023] The second difference returned by the large number subtraction circuit is obtained, and the second difference is used as the modulo result.

[0024] Optionally, before determining whether there is a quotient of the perfect square difference value to the modulus, the method further includes:

[0025] It is determined that the perfect square difference is greater than the modulus.

[0026] Optionally, determining that the perfect square difference is greater than the modulus comprises:

[0027] Extracting first data of a second digit from the perfect square difference, wherein the first data is a first group of bit values ​​from a high bit position to a low bit position in the perfect square difference;

[0028] Calling the large number subtraction circuit to calculate a third difference between the first data and the second data, where the second data is the first preset value of the second length;

[0029] The judgment logic circuit is called to determine that the value of the most significant bit of the third difference is a second preset value, wherein when the value of the most significant bit of the difference is the first preset value, it is determined that the perfect square difference is greater than the modulus.

[0030] In a second aspect, a device for implementing large number modulus is provided, comprising:

[0031] A reading unit, used for reading the modulus and the taken modulus;

[0032] A calculation unit, used for calculating a perfect square difference corresponding to the modulus and the taken modulus;

[0033] A first determining unit, configured to determine, by using a shift combinational logic circuit, that there is a quotient of the perfect square difference value to the modulus, and to estimate the quotient of the perfect square difference value to the modulus;

[0034] The second determining unit is used to obtain a modulo result corresponding to the square of the modulus and the modulus by using the quotient value and the modulus to be taken.

[0035] In a third aspect, an electronic device is provided, comprising: a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0036] The memory is used to store computer programs;

[0037] The processor is used to execute the program stored in the memory to implement the method for taking the modulus of a large number described in the first aspect.

[0038] In a fourth aspect, a computer-readable storage medium is provided, storing a computer program, wherein when the computer program is executed by a processor, the method for implementing the large number modulus described in the first aspect is implemented.

[0039] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0040] The technical solution provided in this embodiment can use a shift combinational logic circuit to determine the existence of a quotient of the perfect square difference to the modulus and estimate the quotient of the perfect square difference to the modulus, that is, the determination and estimation of the quotient are realized through a hardware circuit, thereby saving the consumption of software resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0043] Figure 1 A flowchart of a method for implementing large number modulus in an embodiment of the present application;

[0044] Figure 2 A flowchart of another method for implementing large number modulus in an embodiment of the present application;

[0045] Figure 3 A flowchart of another method for implementing large number modulus in an embodiment of the present application;

[0046] Figure 4 A flowchart of another method for implementing large number modulus in an embodiment of the present application;

[0047] Figure 5 A flowchart of another method for implementing large number modulus in an embodiment of the present application;

[0048] Figure 6 This is a structural diagram of a system for implementing large number modulus in an embodiment of the present application;

[0049] Figure 7 This is a flow chart of a device for implementing large number modulus in an embodiment of the present application;

[0050] Figure 8 Schematic diagram of the structure of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0052] The embodiment of the present application provides a method for implementing large number modulus, which can be applied to hardware programmable devices.

[0053] The hardware programmable device includes, but is not limited to, an FPGA (Field Programmable Gate Array, hardware programmable logic circuit) that can implement a finite state machine.

[0054] like Figure 1 As shown, the method specifically comprises the following steps:

[0055] Step 101, read the modulus and the taken modulus.

[0056] In this embodiment, the modulus and the modulus to be taken can be pre-stored in a static random access memory (SRAM). When the modulus and the modulus to be taken need to be read, the read circuit (SRAM RW) of the static random access memory is called to read the modulus and the modulus to be taken from the SRAM.

[0057] In this embodiment, the modulus and the extracted modulus are both binary data, and the bit lengths of the modulus and the extracted modulus are the same.

[0058] Step 102: Calculate the perfect square difference corresponding to the modulus and the taken modulus.

[0059] After simplifying the formula, we can know that R 2 The result of mod N operation is equivalent to (RN) 2 mod N, that is, R 2 The modulo result of N is equivalent to (RN) 2 The modulo result of N, so when calculating R 2 When taking the modulo result of N, you need to calculate (RN) 2 , to utilize (RN) 2 Get the result of taking the square of the modulus modulo the modulus.

[0060] Among them, R is the modulus to be taken, and N is the modulus.

[0061] Optionally, this embodiment can call a large number subtraction circuit and a large number multiplication circuit to calculate the complete square difference. Specifically, call the large number subtraction circuit to obtain the first difference between the modulus and the modulus to be taken; call the large number multiplication circuit to obtain the square value of the first difference; obtain the square value returned by the large number multiplication circuit, and use the square value as the complete square difference.

[0062] Among them, the large number subtraction circuit and the large number multiplication circuit are circuits existing in the prior art and will not be elaborated in detail here.

[0063] Step 103: using a shift combinational logic circuit, determine whether there is a quotient of the perfect square difference to the modulus, and estimate the quotient of the perfect square difference to the modulus.

[0064] In order to reduce the consumption of hardware resources, in this embodiment, a shift operation is used to replace the traditional division operation to determine and estimate the quotient of the perfect square difference to the modulus.

[0065] Optionally, in this embodiment, the shift combination logic circuit includes a shift logic circuit and a judgment logic circuit.

[0066] Exemplarily, based on the shift combinational logic circuit, when it is determined that there is a quotient of the perfect square difference to the modulus, such as Figure 2 As shown, the following steps may be included:

[0067] Step 201: Utilize a shift logic circuit to right-shift the perfect square difference by the first digit from the lowest bit to obtain right-shift result data.

[0068] The first digit has the same bit length as the modulus.

[0069] Optionally, the perfect square difference is right-shifted by the first digit from the lowest bit to obtain right-shifted result data. The formula used may be:

[0070] R[2k-1:k]

[0071] Wherein, R is the perfect square difference, k is the first digit, and 2k-1 is the bit length of the perfect square difference.

[0072] It can be understood that since the right-shifted result data is the data after the perfect square difference is right-shifted by the first digit, the right-shifted result data can be understood as the data remaining after removing the bit data of the first low-order digit in the perfect square difference.

[0073] Step 202: Using a judgment logic circuit, determine whether the right shift result data is not entirely the first preset value.

[0074] When the right-shift result data is not entirely the first preset value, it is determined that there is a quotient of the complete square difference to the modulus.

[0075] Optionally, the first preset value may be binary 0.

[0076] Optionally, when it is determined that the right-shift result data is not entirely the first preset value, the right-shift result data is used as the quotient of the complete square difference value to the modulus.

[0077] Optionally, when it is determined that the right shift result data are all the first preset value, it means that there is no quotient of the perfect square difference to the modulus. At this time, the large number subtraction circuit can be called to calculate the fourth difference between the perfect square difference and the modulus, and the fourth difference is used as the modulus result corresponding to the square and modulus of the modulus.

[0078] In practical applications, A is defined as the modulus and B is the modulus. Since when A>B, there exists a quotient of A and B and a modulus of A and B, in order to save the amount of computation, before determining that there exists a quotient of the perfect square difference and the modulus, it is possible to first determine that the perfect square difference is greater than the modulus.

[0079] Alternatively, if Figure 3 As shown, an implementation process for determining that the perfect square difference is greater than the modulus is provided, which specifically includes the following steps:

[0080] Step 301: extract the first data of the second digit from the perfect square difference.

[0081] The first data is a first group of bit values ​​from high bits to low bits in the perfect square difference.

[0082] Exemplarily, the second digit may be 32 bits. In this case, the first data is the high 32 bits extracted from the perfect square difference.

[0083] Exemplarily, when acquiring the first data, the first data may be divided according to the principle of from low bits to high bits with the second bit number as the length to obtain a bit array, and the first data may be extracted from the bit array.

[0084] Step 302: Call a large number subtraction circuit to calculate a third difference between the first data and the second data.

[0085] The second data is a first preset value of the second digit.

[0086] For example, the second data may be 32 bits of binary 0.

[0087] Step 303: call the judgment logic circuit to determine that the value of the highest bit of the third difference is the second preset value.

[0088] When the value of the most significant bit of the third difference is a second preset value, it is determined that the perfect square difference is greater than the modulus.

[0089] The second preset value may be 1 in binary.

[0090] Step 104: Using the quotient and the modulus, obtain a modulo result corresponding to the square and modulus of the modulus to be taken.

[0091] Optionally, this embodiment provides an implementation process of obtaining a modulus result by using a quotient value and a modulus, such as Figure 4 As shown, step 104 may include:

[0092] Step 401, calling a large number multiplication circuit to calculate the product value of the right shift result data and the modulus;

[0093] Step 402, calling a large number subtraction circuit to calculate a second difference between the perfect square difference and the product value;

[0094] Step 403: Obtain the second difference returned by the large number subtraction circuit, and use the second difference as the modulo result.

[0095] The following Figure 1 The corresponding process is applied to the FPGA that implements the finite state machine as an example to illustrate Figure 1 The execution process:

[0096] first, Figure 1 It can correspond to the following four states in the finite state machine:

[0097] A first state, corresponding to the reading state of step 101;

[0098] The second state corresponds to the multiplication operation and the subtraction operation of step 102;

[0099] The third state corresponds to the shift state of step 103, and the shift state corresponds to a shift combinational logic circuit;

[0100] The fourth state corresponds to the multiplication operation and the subtraction operation in step 104 .

[0101] When the finite state machine is powered on, the external reading circuit is called according to the first state to read the modulus and the modulus to be taken, and then the state is switched to the second state, and the complete square difference is calculated by calling the large number multiplication circuit and the large number subtraction circuit, and then the state is switched to the third state, and the shift combination logic circuit is used to determine the existence of the quotient of the complete square difference to the modulus, and the quotient is estimated, and finally the state is switched to the fourth state to obtain the modulus result.

[0102] It should be noted that in this embodiment, the finite state machine Figure 1 The state is not limited to the above four states. For example, step 102 can be changed from corresponding to the second state to corresponding to the fifth state, and the fifth state is a complete square difference state, etc. This embodiment does not make specific limitations on this.

[0103] In view of the implementation logic of large number modulus in the above embodiment, this embodiment may also have other logics, such as corresponding Figure 2 , Figure 3 as well as Figure 4 The status of each step.

[0104] Secondly, when FPGA implements the above finite state machine, the implementation process can be:

[0105] In the reading state, the FPGA calls the reading circuit of the static random access memory to read the modulus and the modulus to be taken; when switched to the first state, the FPGA calls the large number multiplication circuit and the large number subtraction circuit to calculate the perfect square difference; when switched to the third state, a shift combination logic circuit is generated, and the shift combination logic circuit is used to determine the existence of a quotient of the perfect square difference to the modulus, and estimate the quotient; when switched to the fourth state, the large number multiplication circuit and the large number subtraction circuit are called to obtain the modulus result.

[0106] The technical solution provided in this embodiment can use a shift combinational logic circuit to determine the existence of a quotient of the perfect square difference to the modulus and estimate the quotient of the perfect square difference to the modulus, that is, the determination and estimation of the quotient are realized through a hardware circuit, thereby saving the consumption of software resources.

[0107] The present application also provides a method for implementing large number modulus, such as Figure 5 As shown, the following steps are included:

[0108] Step 501, read the modulus and the taken modulus;

[0109] Step 502, calling a large number subtraction circuit to obtain a first difference between the modulus and the modulus to be taken;

[0110] Step 503, calling a large number multiplication circuit to obtain the square value of the first difference;

[0111] Step 504: Obtain the square value returned by the large number multiplication circuit, and use the square value as the perfect square difference;

[0112] Step 505, determine whether the perfect square difference is greater than the modulus, if so, execute step 506, otherwise end the process;

[0113] Step 506: Utilize a shift logic circuit to right-shift the perfect square difference by the first digit from the lowest bit to obtain right-shift result data;

[0114] Step 507, using a judgment logic circuit to determine whether the right shift result data is not all the first preset value, if so, execute step 508, otherwise execute step 512;

[0115] Step 508: Obtain the right shift result data returned by the shift logic circuit, and use the right shift result data as the quotient value;

[0116] Step 509, calling the large number multiplication circuit to calculate the product value of the right shift result data and the modulus;

[0117] Step 510, calling a large number subtraction circuit to calculate a second difference between the perfect square difference and the product value;

[0118] Step 511, obtaining a second difference returned by the large number subtraction circuit, and using the second difference as a modulo result corresponding to the square and modulus of the modulo to be taken;

[0119] Step 512: call the large number subtraction circuit to calculate the fourth difference between the perfect square difference and the modulus, and use the fourth difference as the modulus result corresponding to the square and modulus of the modulus to be taken.

[0120] The present application also provides a schematic diagram of a structure of a large number modulus implementation system, such as Figure 6 As shown, it may include:

[0121] CPU 601, configuration module 602, modulus control logic circuit 603, static random access memory reading circuit 604, static random access memory 605, large number multiplication circuit 606, and large number subtraction circuit 607;

[0122] The CPU 601 is used to configure the storage address and length of the variables in the configuration module 602 , wherein the variables include the modulus and the taken modulus.

[0123] For example, the length of the variable may be 1024 or 3072, etc.

[0124] The configuration module 602 stores the storage address and length of the variable.

[0125] The modulo control logic circuit 603 is stored in a finite state machine and is used to implement the large number modulo implementation method in the above embodiment.

[0126] The static random access memory reading circuit 604 is used to read variables from the static random access memory 605 based on the call of the finite state machine.

[0127] The static random access memory 605 is used to store variables and intermediate variables that appear in the implementation method of large number modulus in the above embodiment.

[0128] Exemplarily, the intermediate variable may be a perfect square difference, a quotient, or the like.

[0129] The large number multiplication circuit 606 and the large number subtraction circuit 607 are used to accept the call of the finite state machine and execute the multiplication operation or subtraction operation in the large number modulo implementation method of the above embodiment.

[0130] Based on the same concept, a device for implementing large number modulus is provided in the embodiment of the present application. The specific implementation of the device can be found in the description of the method embodiment part, and the repeated parts will not be repeated. Figure 7 As shown, the device mainly includes:

[0131] A reading unit 701, used for reading the modulus and the taken modulus;

[0132] A calculation unit 702, used for calculating a perfect square difference corresponding to the modulus and the taken modulus;

[0133] A first determining unit 703 is used to determine the existence of a quotient of the perfect square difference to the modulus by using a shift combinational logic circuit, and estimate the quotient of the perfect square difference to the modulus;

[0134] The second determining unit 704 is used to obtain a modulo result corresponding to the square of the modulus and the modulus by using the quotient and the modulus.

[0135] Based on the same concept, an electronic device is also provided in the embodiment of the present application, such as Figure 8 As shown, the electronic device mainly includes: a processor 801, a communication interface 802, a memory 803 and a communication bus 804, wherein the processor 801, the communication interface 802 and the memory 803 communicate with each other through the communication bus 804. The memory 803 stores a program that can be executed by the processor 801, and the processor 801 executes the program stored in the memory 803 to implement the following steps:

[0136] Read the modulus and the taken modulus;

[0137] Calculate the perfect square difference corresponding to the modulus and the modulus taken;

[0138] Using a shift combinational logic circuit, determining that there is a quotient of the perfect square difference to the modulus, and estimating the quotient of the perfect square difference to the modulus;

[0139] Using the quotient and the modulus, a modulo result corresponding to the square and modulus of the modulus is obtained.

[0140] The communication bus 804 mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 804 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0141] The communication interface 802 is used for communication between the above electronic device and other devices.

[0142] The memory 803 may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Alternatively, the memory may also be at least one storage device located away from the processor 801.

[0143] The above-mentioned processor 801 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0144] In another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program runs on a computer, the computer executes the implementation method of large number modulo described in the above embodiment.

[0145] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instruction can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instruction is transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD) or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0146] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0147] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for implementing large number modulus, It is characterized in that include: Read the modulus and the taken modulus; Calculating a perfect square difference corresponding to the modulus and the taken modulus; Using a shift combinational logic circuit, determining that there is a quotient of the perfect square difference value to the modulus, and estimating the quotient of the perfect square difference value to the modulus; Using the quotient and the modulus, a modulo result corresponding to the square of the modulus and the modulus is obtained; Wherein, calculating the complete square difference corresponding to the modulus and the taken modulus includes: calling a large number subtraction circuit to obtain a first difference between the modulus and the taken modulus; calling a large number multiplication circuit to obtain a square value of the first difference; obtaining the square value returned by the large number multiplication circuit, and using the square value as the complete square difference; Among them, the shift combination logic circuit includes a shift logic circuit and a judgment logic circuit; using the shift combination logic circuit, determining whether there is a quotient of the perfect square difference to the modulus, including: using the shift logic circuit, right-shifting the perfect square difference by the first digit starting from the lowest bit to obtain right-shifted result data, and the first digit is the same as the bit length of the modulus; using the judgment logic circuit, determining that the right-shifted result data is not entirely a first preset value, wherein when the right-shifted result data is not entirely the first preset value, it is determined that there is a quotient of the perfect square difference to the modulus.

2. The method according to claim 1, It is characterized in that Estimating a quotient of the perfect square difference to the modulus comprises: The right-shift result data returned by the shift logic circuit is acquired, and the right-shift result data is used as the quotient value.

3. The method according to claim 2, It is characterized in that Using the quotient and the modulus, obtaining a modulo result corresponding to the square of the modulus and the modulus, comprising: Calling the large number multiplication circuit to calculate the product value of the right-shifted result data and the modulus; Calling the large number subtraction circuit to calculate a second difference between the perfect square difference and the product value; The second difference returned by the large number subtraction circuit is obtained, and the second difference is used as the modulo result.

4. The method according to claim 1, It is characterized in that Before determining whether there is a quotient of the perfect square difference value to the modulus, the method further includes: It is determined that the perfect square difference is greater than the modulus.

5. The method according to claim 4, It is characterized in that Determining that the perfect square difference is greater than the modulus includes: Extracting first data of a second digit from the perfect square difference, wherein the first data is a first group of bit values ​​from a high bit position to a low bit position in the perfect square difference; Calling the large number subtraction circuit to calculate a third difference between the first data and the second data, where the second data is the first preset value of the second digit; The judgment logic circuit is called to determine that the value of the most significant bit of the third difference is a second preset value, wherein when the value of the most significant bit of the difference is the first preset value, it is determined that the perfect square difference is greater than the modulus.

6. A device for implementing large number modulus, It is characterized in that include: A reading unit, used for reading the modulus and the taken modulus; A calculation unit, used for calculating a perfect square difference corresponding to the modulus and the taken modulus; A first determining unit, configured to determine, by using a shift combinational logic circuit, that there is a quotient of the perfect square difference value to the modulus, and to estimate the quotient of the perfect square difference value to the modulus; A second determining unit is used to obtain a modulo result corresponding to the square of the modulus and the modulus using the quotient and the modulus; Wherein, calculating the complete square difference corresponding to the taken modulus and the modulus includes: calling a large number subtraction circuit to obtain a first difference between the modulus and the taken modulus; calling a large number multiplication circuit to obtain a square value of the first difference; obtaining the square value returned by the large number multiplication circuit, and using the square value as the complete square difference; Among them, the shift combination logic circuit includes a shift logic circuit and a judgment logic circuit; using the shift combination logic circuit, determining whether there is a quotient of the perfect square difference to the modulus, including: using the shift logic circuit, right-shifting the perfect square difference by the first digit starting from the lowest bit to obtain right-shifted result data, and the first digit is the same as the bit length of the modulus; using the judgment logic circuit, determining that the right-shifted result data is not entirely a first preset value, wherein when the right-shifted result data is not entirely the first preset value, it is determined that there is a quotient of the perfect square difference to the modulus.

7. An electronic device, It is characterized in that include: A processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; The memory is used to store computer programs; The processor is used to execute the program stored in the memory to implement the large number modulus implementation method described in any one of claims 1-6.

8. A computer-readable storage medium storing a computer program, It is characterized in that When the computer program is executed by a processor, the method for implementing large number modulo according to any one of claims 1 to 6 is implemented.

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