A method and apparatus for simulating a digital-analog hybrid circuit

Abstract

The embodiment of the application provides a kind of digital-analog hybrid circuit simulation method and device, obtain the circuit information of black box circuit including black box analog circuit and black box digital circuit, determine simulation configuration information for black box circuit, after replacing black box analog circuit with to-be-tested analog circuit, replace black box digital circuit with to-be-tested digital circuit, simulation configuration information is used to simulate to-be-tested circuit including to-be-tested analog circuit and to-be-tested digital circuit, wherein to-be-tested analog circuit has the same input pin information and output pin information as black box analog circuit, and to-be-tested digital circuit has the same input interface information and output interface information as black box digital circuit.That is, in the embodiment of the application, the construction of simulation system can be set in the design stage of to-be-tested analog circuit and to-be-tested digital circuit, the time length before the design completion node of circuit and the simulation operation node of circuit is reduced, and the development cycle of chip is shortened.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a method and apparatus for simulating mixed-signal circuits. Background Technology

[0002] In the field of chip design, with the continuous increase in chip integration and the diversification of market demands, designs that integrate digital and analog circuits into a single chip are gradually gaining a larger share of the chip market. This situation has brought greater difficulties to chip verification and simulation. Although mainstream electronic design automation (EDA) tools and domestic EDA tools on the market all provide functions for mixed-signal circuit simulation, these functions are performed after the completion of both digital and analog circuit design. This means that the initial stage of simulation verification must be carried out after the completion of both digital and analog circuit design phases, thus greatly extending the chip development cycle. Summary of the Invention

[0003] To address the aforementioned technical problems, embodiments of this application provide a mixed-signal circuit simulation method and apparatus, which can realize the construction of a simulation system during the design stages of digital and analog circuits, saving simulation time and shortening the chip development cycle.

[0004] This application provides a method for simulating mixed-signal circuits, including:

[0005] Obtain circuit information of a black-box circuit, including a black-box analog circuit and a black-box digital circuit; the circuit information of the black-box circuit includes the input pin information and output pin information of the black-box analog circuit, and the black-box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes the input interface information and output interface information of the black-box digital circuit.

[0006] Determine the simulation configuration information for the black box circuit;

[0007] The black-box analog circuit is replaced with the analog circuit under test (DUT), and the black-box digital circuit is replaced with the digital circuit under test (DUT). The simulation configuration information is updated based on the storage locations of the DUT and the black-box digital circuit. The DUT has the same input pin information and output pin information as the black-box analog circuit, and the DUT has the same input interface information and output interface information as the black-box digital circuit.

[0008] The circuit under test, including the analog circuit under test and the digital circuit under test, is simulated using the updated simulation configuration information.

[0009] Optionally, replacing the black-box analog circuit with the analog circuit under test, replacing the black-box digital circuit with the digital circuit under test, and updating the simulation configuration information based on the storage location of the analog circuit under test and the storage location of the black-box digital circuit include:

[0010] Replace the Verilog netlist of the black-box digital circuit with the Verilog netlist of the digital circuit under test at the storage location of the black-box digital circuit.

[0011] Replace the netlist of the black-box analog circuit with the netlist of the analog circuit under test at the storage location of the black-box analog circuit.

[0012] Update the storage location of the Verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and replace the storage location of the Verilog netlist of the digital circuit under test in the simulation configuration information with the storage location of the netlist of the analog circuit under test.

[0013] Optionally, the simulation configuration information determined for the black-box circuit and the updated simulation configuration information further include: the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit, and the storage location of the netlist of the excitation circuit, wherein the excitation circuit is used to provide excitation signals; the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit is the same as the storage location of the Verilog code of the outsourced test item layer of the digital circuit under test.

[0014] Optionally, the method further includes:

[0015] Based on the simulation configuration information and the storage location of the Verilog netlist of the digital circuit under test, as well as the netlist of the analog circuit under test, a simulation configuration script is obtained.

[0016] Then, the step of simulating the circuit under test (DUT) including the analog circuit under test and the digital circuit under test using the simulation configuration information includes:

[0017] Run the simulation configuration script to invoke the simulation EDA tool to perform simulation operations on the circuit under test, which includes the analog circuit under test and the digital circuit under test.

[0018] Optionally, obtaining the input interface information and output interface information of the black-box digital circuit includes: obtaining the declaration information of the input interface and output interface of the black-box digital circuit based on Verilog syntax; and generating the Verilog netlist of the black-box digital circuit based on the declaration information.

[0019] The step of obtaining the input pin information and output pin information of the black box analog circuit includes: obtaining the circuit information of the black box analog circuit, and generating the netlist of the black box analog circuit based on the circuit information.

[0020] This application provides a mixed-signal circuit simulation device, including:

[0021] The circuit information acquisition unit is used to acquire circuit information of a black-box circuit, including a black-box analog circuit and a black-box digital circuit; the circuit information of the black-box circuit includes the input pin information and output pin information of the black-box analog circuit, and the black-box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes the input interface information and output interface information of the black-box digital circuit.

[0022] A configuration information determination unit is used to determine simulation configuration information for the black box circuit;

[0023] A circuit replacement unit is used to replace the black-box analog circuit with the analog circuit under test (DUT) and the black-box digital circuit with the digital circuit under test (DUT), and to update the simulation configuration information based on the storage locations of the DUT and the black-box digital circuit. The DUT has the same input pin information and output pin information as the black-box analog circuit, and the DUT has the same input interface information and output interface information as the black-box digital circuit.

[0024] The simulation unit is used to simulate the circuit under test, including the analog circuit under test and the digital circuit under test, using updated simulation configuration information.

[0025] Optionally, the circuit replacement unit includes:

[0026] The first circuit replacement subunit is used to replace the Verilog netlist of the black box digital circuit with the Verilog netlist of the digital circuit under test at the storage location of the Verilog netlist of the black box digital circuit.

[0027] The second circuit replacement subunit is used to replace the netlist of the black-box analog circuit with the netlist of the analog circuit under test at the storage location of the netlist of the black-box analog circuit.

[0028] The configuration information replacement subunit is used to update the storage location of the Verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and to replace the storage location of the Verilog netlist of the digital circuit under test in the simulation configuration information to the storage location of the netlist of the analog circuit under test.

[0029] Optionally, the simulation configuration information determined for the black-box circuit and the updated simulation configuration information further include: the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit, and the storage location of the netlist of the excitation circuit, wherein the excitation circuit is used to provide excitation signals; the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit is the same as the storage location of the Verilog code of the outsourced test item layer of the digital circuit under test.

[0030] Optionally, the device further includes:

[0031] The script determination unit is used to obtain the simulation configuration script based on the simulation configuration information, the storage location of the Verilog netlist of the digital circuit under test, and the netlist of the analog circuit under test.

[0032] Therefore, the simulation unit is specifically used for:

[0033] Run the simulation configuration script to invoke the simulation EDA tool to perform simulation operations on the circuit under test, which includes the analog circuit under test and the digital circuit under test.

[0034] Optionally, the circuit information acquisition unit includes:

[0035] A digital circuit acquisition subunit is used to acquire the declaration information of the input and output interfaces of a black-box digital circuit based on Verilog syntax; and to generate a Verilog netlist of the black-box digital circuit based on the declaration information.

[0036] The analog circuit acquisition subunit is used to acquire the circuit information of the black box analog circuit and generate the netlist of the black box analog circuit based on the circuit information.

[0037] This application provides a method and apparatus for simulating mixed-signal circuits. It acquires circuit information of a black-box circuit, including a black-box analog circuit and a black-box digital circuit. The circuit information of the black-box circuit includes the input pin information and output pin information of the black-box analog circuit. The black-box analog circuit includes a test resistor connected in series between the input pins and output pins. The circuit information also includes the input interface information and output interface information of the black-box digital circuit. Simulation configuration information is determined for the black-box circuit. After replacing the black-box analog circuit with the analog circuit under test (DUT) and the black-box digital circuit with the DUT, the simulation configuration information is updated based on the storage locations of the DUT and the black-box digital circuit. The updated simulation configuration information can be used to simulate the DUT circuit, which includes both the DUT and the DUT. The DUT analog circuit has the same input pin information and output pin information as the black-box analog circuit, and the DUT digital circuit has the same input interface information and output interface information as the black-box digital circuit. In other words, in this embodiment, a black-box analog circuit can be pre-built based on the input and output pin information of the analog circuit under test, and a black-box digital circuit can be built based on the input and output interface information of the digital circuit under test. Simulation configuration information is then determined for the black-box circuit. This sets up the simulation system during the design phase of the analog and digital circuits under test. After the design of the analog and digital circuits under test is completed, simulation operations can be performed using the pre-built test system. This reduces the time between the design completion node of the analog and digital circuits under test and the simulation operation node of the analog and digital circuits under test, thus shortening the chip development cycle. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0039] Figure 1 A flowchart illustrating a mixed-signal circuit simulation method provided in this application embodiment;

[0040] Figure 2 A schematic diagram of an interface declaration for a black-box digital circuit provided in an embodiment of this application;

[0041] Figure 3 A schematic diagram of a black-box analog circuit provided in an embodiment of this application;

[0042] Figure 4 A schematic diagram of a simulation system provided in an embodiment of this application;

[0043] Figure 5A schematic diagram of a simulation environment structure provided in this application embodiment;

[0044] Figure 6 This is a structural block diagram of a mixed-signal circuit simulation device provided in an embodiment of this application. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0046] Currently, the simulation process for mixed-signal circuits involves using the graphical interface of a relevant EDA tool to read in the analog circuit schematic and digital circuit design file, then creating a test environment and setting stimuli, and finally running the simulation and viewing the results. While EDA tools provide this method for mixed-signal circuit simulation, the requirement that both the digital and analog circuits be fully designed from the moment the design is read in means that the simulation verification phase can only begin after the digital and analog circuit design phases are complete. This increases the chip development cycle.

[0047] Based on the above technical problems, this application provides a method and apparatus for simulating mixed-signal circuits. It acquires circuit information of a black-box circuit, including a black-box analog circuit and a black-box digital circuit. The circuit information of the black-box circuit includes the input pin information and output pin information of the black-box analog circuit. The black-box analog circuit includes a test resistor connected in series between the input pins and output pins. The circuit information also includes the input interface information and output interface information of the black-box digital circuit. Simulation configuration information is determined for the black-box circuit. After replacing the black-box analog circuit with the analog circuit under test (DUT) and the black-box digital circuit with the DUT, the simulation configuration information is updated based on the storage locations of the DUT and the black-box digital circuit. The updated simulation configuration information can be used to simulate the DUT circuit, which includes both the DUT and the DUT. The DUT analog circuit has the same input pin information and output pin information as the black-box analog circuit, and the DUT digital circuit has the same input interface information and output interface information as the black-box digital circuit. In other words, in this embodiment, a black-box analog circuit can be pre-built based on the input and output pin information of the analog circuit under test, and a black-box digital circuit can be built based on the input and output interface information of the digital circuit under test. Simulation configuration information is then determined for the black-box circuit. This sets up the simulation system during the design phase of the analog and digital circuits under test. After the design of the analog and digital circuits under test is completed, simulation operations can be performed using the pre-built test system. This reduces the time between the design completion node of the analog and digital circuits under test and the simulation operation node of the analog and digital circuits under test, thus shortening the chip development cycle.

[0048] The following, in conjunction with the accompanying drawings, describes in detail the specific implementation of the mixed-signal circuit simulation method and apparatus in the embodiments of this application.

[0049] refer to Figure 1 The diagram shown is a flowchart of a mixed-signal circuit simulation method provided in an embodiment of this application. The method may include the following steps:

[0050] S101, Obtain circuit information of the black-box circuit, including black-box analog circuit and black-box digital circuit.

[0051] In this embodiment, black-box analog circuits and black-box digital circuits can be constructed first. The black-box analog circuit is an analog circuit that only includes pin information, with other information unknown. The black-box digital circuit is a digital circuit that only includes interface information, with other information unknown. After constructing the black-box analog circuit and black-box digital circuit, circuit information including the black-box analog circuit and black-box digital circuit can be obtained. Then, a simulation system platform is built based on the black-box circuit including the black-box analog circuit and black-box digital circuit. The circuit information of the black-box circuit includes the input pin information and output pin information of the black-box analog circuit, and the input interface information and output interface information of the black-box digital circuit.

[0052] Specifically, the black-box digital circuit is generated based on the digital circuit under test. The black-box digital circuit has the same input interface information and output interface information as the digital circuit under test. Since the input interface information and output interface information of the digital circuit under test are determined before the end of the design phase of the digital circuit under test, the generation of the black-box digital circuit can be carried out in parallel with the design of the digital circuit under test.

[0053] The input interface information of a black-box digital circuit indicates the function of each input interface, and the output interface information indicates the function of each output interface. For example, the first input interface is used to input a reset signal (RESET), the second input interface is used for input (PD), and so on; for example, the first output interface is used to output a PDB signal, the second output interface is used to output a PDBB signal, and so on.

[0054] Since the front end of the digital circuit under test is designed using the hardware description language Verilog, a Verilog view can be created in the EDA tool to create a black-box digital circuit. In the opened editable window, the interface information of the black-box digital circuit is declared according to the Verilog syntax. The interface information includes input interface information and output interface information. Since different interfaces are distinguished by the order of declaration, the declaration order of the interface information of the black-box digital circuit is consistent with the declaration order of the interface information of the digital circuit under test. This ensures that the interface information of the black-box digital circuit and the interface information of the digital circuit under test are the same.

[0055] refer to Figure 2 The diagram shown is an interface declaration diagram of a black box digital circuit provided in an embodiment of this application. The input interface is represented by input, and the input signals of each input interface are as follows: RESET, PD, FIN, [8:0]M, [4:0]N, [1:0]OD, OE, BP, SOUT, [1:0]TST. The output signals of each output interface are as follows: PDB, PDBB, DN, DNB, UP, UPB, FOUT, TST_OUT.

[0056] In this embodiment, after obtaining the declaration information of the input and output interfaces of the black-box digital circuit based on Verilog syntax, the EDA tool can generate a view corresponding to the circuit symbols of each interface element of the black-box digital circuit based on the declaration information. This completes the creation of the black-box digital circuit and the acquisition of its input and output interface information. In this embodiment, a Verilog netlist of the black-box digital circuit can also be generated based on the declaration information.

[0057] Specifically, the black-box analog circuit is generated based on the analog circuit under test. The black-box analog circuit has the same input pin information and output pin information as the analog circuit under test. Since the input pin information and output pin information of the analog circuit under test are determined before the end of the design phase of the analog circuit under test, the generation of the black-box analog circuit can be carried out in parallel with the design of the analog circuit under test.

[0058] For black-box analog circuits, a schematic can be created containing only the pins of the analog circuit under test. These pins include input and output pins. All pins are connected appropriately, for example, by connecting test resistors in series between input and output pins. The number of test resistors can be determined based on the number of input and output pins. Each input pin should be connected to at least one test resistor; different input pins can be connected to the same or different test resistors. Connecting test resistors in series between input and output pins prevents them from being removed by EDA tools during subsequent netlist generation.

[0059] refer to Figure 3 The diagram shown is a schematic of a black-box analog circuit provided in an embodiment of this application. The input pins include M<8:3>, IN1, IN2, DN, DNB, UP, and UPB, and the output pin includes SOUT. The input pin M... <8> M <7> M <6> M <5> M <4> M <3> IN1, IN2, DN, DNB, UP, and UPB are connected to the output pin SOUT via test resistors R6, R7, R8, R9, R10, R11, R0, R1, R2, R3, R4, and R5, respectively.

[0060] In this embodiment, obtaining the input and output pin information of the black-box analog circuit can specifically involve obtaining the black-box analog circuit information and generating a view corresponding to the circuit symbols of the pin components of each black-box analog circuit based on the analog circuit information. Specifically, a netlist of the black-box analog circuit can also be generated based on the circuit information.

[0061] S102 determines the simulation configuration information for the black box circuit.

[0062] In this embodiment, after determining the black box circuit and obtaining its circuit information, a simulation system can be built based on the black box circuit, as described above. Figure 4 The diagram shown is a schematic of a simulation system provided in an embodiment of this application. The simulation system may include an excitation circuit (Driver) and a monitoring circuit (Monitor). The simulation system is used to simulate a test circuit that includes digital circuits and analog circuits. The excitation circuit is used to provide excitation signals, and the monitoring circuit is used to monitor the signals of the test circuit according to the needs of simulation verification.

[0063] Specifically, after obtaining the circuit information of the black box circuit, the information of the excitation circuit can also be set. When using simulation EDA tools to simulate the black box circuit, the excitation circuit is used to provide excitation signals to the black box circuit. The simulation operation of the black box circuit is to simulate the response signal generated by the black box circuit under the action of the excitation signal. By analyzing the response signal, the simulation operation results of the black box circuit can be obtained. The simulation operation results of the black box circuit reflect the performance parameters of the black box circuit.

[0064] Information about the excitation circuit can include the circuit elements within it, as well as the connection relationships between the excitation circuit and the black-box circuit. This information is determined based on the testing requirements of the circuit under test, such as the simulation type and simulation analysis points. Using the excitation circuit and the black-box circuit, the circuit schematic of the simulation circuit is obtained. Information about the monitoring circuit can include the circuit elements within it, as well as the connection relationships between the monitoring circuit and the black-box circuit. This information is also determined based on the testing requirements of the circuit under test, such as the simulation type and simulation detection points. The circuit schematic of the simulation circuit may also include the monitoring circuit.

[0065] After creating the circuit schematic for the simulation circuit, a mixed-signal simulation environment can be built. Specifically, a view of type configuration information (config) can be created, and the mixed simulation type of the simulation schematic can be selected as needed. After correct settings, the simulation system schematic design is complete.

[0066] Specifically, after obtaining the circuit information of the black-box circuit, the configuration information for the simulation operation can be set. This allows the simulation EDA tool to perform circuit simulation based on the configuration information. The configuration information can include, for example, the storage location of model files required for simulation, scripts used in the simulation process, the simulation execution location and the simulation result generation location, information on the black-box digital circuits and black-box analog circuits used in the simulation, and user-defined configuration files. The simulation EDA tool can then call the necessary files to perform the simulation operation on the black-box circuit based on this configuration information.

[0067] refer to Figure 5 The diagram shown illustrates a simulation environment structure according to an embodiment of this application. The simulation environment structure includes a database, which contains folders such as Models, Scripts, Simulation, Src, and User-defined Models. The Models folder stores all model files required for simulation; the Scripts folder stores scripts used in the simulation process; the Simulation folder indicates the location where simulation runs and results are generated; the Src folder stores information about black-box digital circuits and black-box analog circuits used in the simulation; and the User-defined Models folder stores configuration files that the user needs to define during the simulation process. The information about black-box digital circuits includes RTL code files or RTL netlists, and the information about black-box analog circuits includes simulation netlist files.

[0068] In practice, you can open the simulation tool window corresponding to the simulation system schematic, set the simulation model, simulation analysis points, and simulation monitoring points as needed, and then select the simulator type, set the mixed-signal simulation type, and set the analog-to-digital conversion parameters. After setting the simulation options, run the simulation. The simulation tool will then generate simulation netlists and simulation settings files for the entire simulation system circuit. The digital circuit under test (DUT) in the netlist and files is the aforementioned black-box digital circuit, and the analog circuit under test (DUT) is the aforementioned black-box analog circuit.

[0069] After the simulation system is built, the simulation configuration information can be obtained. This information may include the storage locations of the Verilog netlists for the black-box digital circuits, the black-box analog circuits, the top-level netlist of the simulation system, the Verilog netlists for the external test items layer of the black-box digital circuits, and the excitation circuit netlists. The simulation configuration information may also include the storage location of the simulation model files, simulation analysis points, simulation monitoring points, simulator type, mixed-signal simulation type, and analog-to-digital conversion parameters.

[0070] S103, replace the black-box analog circuit with the analog circuit under test, replace the black-box digital circuit with the digital circuit under test, and update the simulation configuration information based on the storage location of the analog circuit under test and the storage location of the black-box digital circuit.

[0071] In this embodiment, the mixed-signal circuit simulation system platform can be built after the black-box circuit is established. This advances the construction time of the mixed-signal circuit simulation system platform to the stage of digital and analog circuit design, or even to the initial stage of digital and analog circuit design. In this way, circuit design and simulation platform construction can be carried out simultaneously, solving the problem of excessive dependence of the construction of the mixed-signal circuit simulation system platform on the speed of circuit design, effectively reducing the chip development cycle and lowering development costs.

[0072] After the design of the digital circuit under test (DUT) and the analog circuit under test (AUT) is completed, the analog black-box circuit under test can be replaced with the analog circuit under test, and the black-box digital circuit can be replaced with the digital circuit under test. The input and output pin information of the analog circuit under test is the same as that of the black-box analog circuit, and the input and output interface information of the digital circuit under test is the same as that of the black-box digital circuit. In this way, even if the black-box circuit is replaced with the circuit under test, the connection between the black-box circuit and the excitation circuit will not change, and the connection between the circuit under test and the excitation circuit will not change. Therefore, the required simulation configuration information remains unchanged, and the previously built mixed-signal circuit simulation system platform can be used for the simulation of the circuit under test.

[0073] Specifically, replacing the black-box analog circuit with the analog circuit under test (DUT) can be achieved by replacing the black-box analog circuit's netlist with the DUT's netlist in the black-box analog circuit's storage location. Similarly, replacing the black-box digital circuit with the DUT can be achieved by replacing the black-box digital circuit's Verilog netlist with the DUT's Verilog netlist in the black-box digital circuit's storage location. Of course, the storage location of the black-box digital circuit's Verilog netlist in the simulation configuration information is also updated to the same location as the DUT's Verilog netlist, and the storage location of the black-box analog circuit's netlist is also updated accordingly.

[0074] S104 uses simulation configuration information to simulate the circuit under test, including the analog circuit under test and the digital circuit under test.

[0075] After replacing the black-box digital circuit with the digital circuit under test and the black-box analog circuit with the analog circuit under test, the connection between the black-box circuit and the excitation circuit, and the connection between the circuit under test and the excitation circuit, will not change. Therefore, the required simulation configuration information remains unchanged, and the previously built mixed-signal circuit simulation system platform can be used for the simulation of the circuit under test.

[0076] In this embodiment, the updated simulation configuration information can be used to simulate the circuit under test (DUT), which includes both analog and digital circuits under test (DUTs), to obtain simulation results. These simulation results represent the performance parameters of the DUT, allowing for optimization of the DUT based on the simulation results. The updated simulation configuration information also includes the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code for the outsourced test item layer of the digital circuit under test, and the storage location of the netlist of the excitation circuit, which provides the excitation signal. Notably, the storage location of the Verilog code for the outsourced test item layer of the black-box digital circuit in the simulation configuration information remains unchanged and is the same as the storage location of the Verilog code for the outsourced test item layer of the digital circuit under test.

[0077] Because the construction time of the mixed-signal circuit simulation system platform can be advanced to the stage of digital and analog circuit design, or even to the initial stage of digital and analog circuit design, circuit design and simulation platform construction can be carried out simultaneously. This solves the problem of the mixed-signal circuit simulation system platform construction being overly dependent on the speed of circuit design, effectively reducing the chip development cycle and lowering development costs.

[0078] In this embodiment, a simulation configuration script can be obtained based on the simulation configuration information and the storage locations of the Verilog netlist of the digital circuit under test and the netlist of the analog circuit under test. The simulation configuration script can include first configuration information, which includes the storage locations of the Verilog netlist of the digital circuit under test and the netlist of the analog circuit under test. Specifically, simulating the circuit under test (including both the analog and digital circuits) using the simulation configuration information involves running the simulation configuration script to perform simulation operations on the circuit under test using a simulation EDA tool. The first configuration information can also include the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code of the outer test item layer of the digital circuit under test, and the storage location of the netlist of the excitation circuit.

[0079] In this embodiment, a simulation configuration script can be obtained based on the simulation configuration information, the storage location of the Verilog code file of the digital circuit under test (DUT), and the storage location of the netlist of the analog circuit under test (DUT). The simulation configuration script can include second configuration information, which includes the storage location of the Verilog code file of the DUT and the storage location of the netlist of the analog circuit under test. Specifically, using the simulation configuration information to simulate the DUT, which includes both the analog and digital circuits under test, can be achieved by running the simulation configuration script and utilizing simulation EDA tools to perform simulation operations on the DUT. The Verilog code file of the DUT is designed by the design engineer, thus eliminating the need for the simulation engineer to input information about the relevant circuit units, reducing the possibility of errors. The second configuration information can also include the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code of the outsourced test item layer of the DUT, and the storage location of the netlist of the excitation circuit.

[0080] This application provides a method for simulating mixed-signal circuits. It acquires circuit information of a black-box circuit, including a black-box analog circuit and a black-box digital circuit. The circuit information includes the input and output pin information of the black-box analog circuit, and a test resistor connected in series between the input and output pins. The circuit information also includes the input and output interface information of the black-box digital circuit. Simulation configuration information is determined for the black-box circuit. After replacing the black-box analog circuit with the analog circuit under test (DUT) and the black-box digital circuit with the DUT, the simulation configuration information is updated based on the storage locations of the DUT and the black-box digital circuit. The updated simulation configuration information can be used to simulate the DUT circuit, which includes both the analog circuit under test and the DUT. The DUT analog circuit has the same input and output pin information as the black-box analog circuit, and the DUT digital circuit has the same input and output interface information as the black-box digital circuit. In other words, in this embodiment, a black-box analog circuit can be pre-built based on the input and output pin information of the analog circuit under test, and a black-box digital circuit can be built based on the input and output interface information of the digital circuit under test. Simulation configuration information is then determined for the black-box circuit. This sets up the simulation system during the design phase of the analog and digital circuits under test. After the design of the analog and digital circuits under test is completed, simulation operations can be performed using the pre-built test system. This reduces the time between the design completion node of the analog and digital circuits under test and the simulation operation node of the analog and digital circuits under test, thus shortening the chip development cycle.

[0081] Based on the above mixed-signal circuit simulation method, this application also provides a mixed-signal circuit simulation device, see reference. Figure 6 The diagram shown is a structural block diagram of a mixed-signal circuit simulation device provided in an embodiment of this application. The device may include:

[0082] The circuit information acquisition unit 110 is used to acquire circuit information of a black box circuit, including a black box analog circuit and a black box digital circuit; the circuit information of the black box circuit includes the input pin information and output pin information of the black box analog circuit, and the black box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes the input interface information and output interface information of the black box digital circuit.

[0083] The configuration information determination unit 120 is used to determine simulation configuration information for the black box circuit.

[0084] The circuit replacement unit 130 is used to replace the black-box analog circuit with the analog circuit under test, and the black-box digital circuit with the digital circuit under test, and to update the simulation configuration information based on the storage location of the analog circuit under test and the storage location of the black-box digital circuit; the analog circuit under test has the same input pin information and output pin information as the black-box analog circuit, and the digital circuit under test has the same input interface information and output interface information as the black-box digital circuit;

[0085] The simulation unit 140 is used to simulate the circuit under test, including the analog circuit under test and the digital circuit under test, using the updated simulation configuration information.

[0086] Optionally, the circuit replacement unit includes:

[0087] The first circuit replacement subunit is used to replace the Verilog netlist of the black box digital circuit with the Verilog netlist of the digital circuit under test at the storage location of the Verilog netlist of the black box digital circuit.

[0088] The second circuit replacement subunit is used to replace the netlist of the black-box analog circuit with the netlist of the analog circuit under test at the storage location of the netlist of the black-box analog circuit.

[0089] The configuration information replacement subunit is used to update the storage location of the Verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and to replace the storage location of the Verilog netlist of the digital circuit under test in the simulation configuration information to the storage location of the netlist of the analog circuit under test.

[0090] Optionally, the simulation configuration information determined for the black-box circuit and the updated simulation configuration information further include: the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit, and the storage location of the netlist of the excitation circuit, wherein the excitation circuit is used to provide excitation signals; the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit is the same as the storage location of the Verilog code of the outsourced test item layer of the digital circuit under test.

[0091] Optionally, the device further includes:

[0092] The script determination unit is used to obtain the simulation configuration script based on the simulation configuration information, the storage location of the Verilog netlist of the digital circuit under test, and the netlist of the analog circuit under test.

[0093] Therefore, the simulation unit is specifically used for:

[0094] Run the simulation configuration script to invoke the simulation EDA tool to perform simulation operations on the circuit under test, which includes the analog circuit under test and the digital circuit under test.

[0095] Optionally, the circuit information acquisition unit includes:

[0096] A digital circuit acquisition subunit is used to acquire the declaration information of the input and output interfaces of a black-box digital circuit based on Verilog syntax; and to generate a Verilog netlist of the black-box digital circuit based on the declaration information.

[0097] The analog circuit acquisition subunit is used to acquire the circuit information of the black box analog circuit and generate the netlist of the black box analog circuit based on the circuit information.

[0098] This application provides a mixed-signal circuit simulation device that acquires circuit information of a black-box circuit, including a black-box analog circuit and a black-box digital circuit. The circuit information of the black-box circuit includes the input pin information and output pin information of the black-box analog circuit, and the black-box analog circuit includes a test resistor connected in series between the input pins and the output pins. The circuit information also includes the input interface information and output interface information of the black-box digital circuit. Simulation configuration information is determined for the black-box circuit. After replacing the black-box analog circuit with the analog circuit under test and the black-box digital circuit with the digital circuit under test, the simulation configuration information is updated based on the storage location of the analog circuit under test and the storage location of the black-box digital circuit. The updated simulation configuration information can be used to simulate the circuit under test, which includes the analog circuit under test and the digital circuit under test. The analog circuit under test has the same input pin information and output pin information as the black-box analog circuit, and the digital circuit under test has the same input interface information and output interface information as the black-box digital circuit. In other words, in this embodiment, a black-box analog circuit can be pre-built based on the input and output pin information of the analog circuit under test, and a black-box digital circuit can be built based on the input and output interface information of the digital circuit under test. Simulation configuration information is then determined for the black-box circuit. This sets up the simulation system during the design phase of the analog and digital circuits under test. After the design of the analog and digital circuits under test is completed, simulation operations can be performed using the pre-built test system. This reduces the time between the design completion node of the analog and digital circuits under test and the simulation operation node of the analog and digital circuits under test, thus shortening the chip development cycle.

[0099] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0100] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device and system embodiments described above are merely illustrative. Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0101] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A simulation method for mixed-signal circuits, characterized in that, include: Obtain circuit information for black-box circuits, including black-box analog circuits and black-box digital circuits; The circuit information of the black box circuit includes the input pin information and output pin information of the black box analog circuit, and the black box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes the input interface information and output interface information of the black box digital circuit. Determine the simulation configuration information for the black box circuit; The black-box analog circuit is replaced with the analog circuit under test, and the black-box digital circuit is replaced with the digital circuit under test. The simulation configuration information is updated based on the storage location of the analog circuit under test and the storage location of the black-box digital circuit. The analog circuit under test has the same input pin information and output pin information as the black box analog circuit, and the digital circuit under test has the same input interface information and output interface information as the black box digital circuit; Using the updated simulation configuration information, the circuit under test, including the analog circuit under test and the digital circuit under test, is simulated; The step of replacing the black-box analog circuit with the analog circuit under test, replacing the black-box digital circuit with the digital circuit under test, and updating the simulation configuration information based on the storage location of the analog circuit under test and the storage location of the black-box digital circuit includes: Replace the Verilog netlist of the black-box digital circuit with the Verilog netlist of the digital circuit under test at the storage location of the black-box digital circuit. Replace the netlist of the black-box analog circuit with the netlist of the analog circuit under test at the storage location of the black-box analog circuit. Update the storage location of the Verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and replace the storage location of the Verilog netlist of the digital circuit under test in the simulation configuration information with the storage location of the netlist of the analog circuit under test; The simulation configuration information determined for the black-box circuit and the updated simulation configuration information also include: the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit, and the storage location of the netlist of the excitation circuit, wherein the excitation circuit is used to provide excitation signals; the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit is the same as the storage location of the Verilog code of the outsourced test item layer of the digital circuit under test.

2. The method according to claim 1, characterized in that, The method further includes: Based on the simulation configuration information and the storage location of the Verilog netlist of the digital circuit under test, as well as the netlist of the analog circuit under test, a simulation configuration script is obtained. Then, the step of simulating the circuit under test (DUT) including the analog circuit under test and the digital circuit under test using the simulation configuration information includes: Run the simulation configuration script to invoke the simulation EDA tool to perform simulation operations on the circuit under test, which includes the analog circuit under test and the digital circuit under test.

3. The method according to any one of claims 1-2, characterized in that, The step of obtaining the input interface information and output interface information of the black-box digital circuit includes: obtaining the declaration information of the input interface and output interface of the black-box digital circuit based on Verilog syntax; and generating the Verilog netlist of the black-box digital circuit based on the declaration information. The step of obtaining the input pin information and output pin information of the black box analog circuit includes: obtaining the circuit information of the black box analog circuit, and generating the netlist of the black box analog circuit based on the circuit information.

4. A mixed-signal circuit simulation device, characterized in that, include: The circuit information acquisition unit is used to acquire circuit information of black-box circuits, including black-box analog circuits and black-box digital circuits. The circuit information of the black box circuit includes the input pin information and output pin information of the black box analog circuit, and the black box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes the input interface information and output interface information of the black box digital circuit. A configuration information determination unit is used to determine simulation configuration information for the black box circuit; The circuit replacement unit is used to replace the black-box analog circuit with the analog circuit under test, replace the black-box digital circuit with the digital circuit under test, and update the simulation configuration information based on the storage location of the analog circuit under test and the storage location of the black-box digital circuit. The analog circuit under test has the same input pin information and output pin information as the black box analog circuit, and the digital circuit under test has the same input interface information and output interface information as the black box digital circuit; The simulation unit is used to simulate the circuit under test, including the analog circuit under test and the digital circuit under test, using updated simulation configuration information; The circuit replacement unit includes: The first circuit replacement subunit is used to replace the Verilog netlist of the black box digital circuit with the Verilog netlist of the digital circuit under test at the storage location of the Verilog netlist of the black box digital circuit. The second circuit replacement subunit is used to replace the netlist of the black-box analog circuit with the netlist of the analog circuit under test at the storage location of the netlist of the black-box analog circuit. The configuration information replacement subunit is used to update the storage location of the Verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and to replace the storage location of the Verilog netlist of the digital circuit under test in the simulation configuration information to the storage location of the netlist of the analog circuit under test; The simulation configuration information determined for the black-box circuit and the updated simulation configuration information also include: the storage location of the top-level netlist of the simulation system, the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit, and the storage location of the netlist of the excitation circuit, wherein the excitation circuit is used to provide excitation signals; the storage location of the Verilog code of the outsourced test item layer of the black-box digital circuit is the same as the storage location of the Verilog code of the outsourced test item layer of the digital circuit under test.

5. The apparatus according to claim 4, characterized in that, The device further includes: The script determination unit is used to obtain the simulation configuration script based on the simulation configuration information, the storage location of the Verilog netlist of the digital circuit under test, and the netlist of the analog circuit under test. Therefore, the simulation unit is specifically used for: Run the simulation configuration script to invoke the simulation EDA tool to perform simulation operations on the circuit under test, which includes the analog circuit under test and the digital circuit under test.

6. The apparatus according to any one of claims 4-5, characterized in that, The circuit information acquisition unit includes: A digital circuit acquisition subunit is used to acquire the declaration information of the input and output interfaces of a black-box digital circuit based on Verilog syntax; and to generate a Verilog netlist of the black-box digital circuit based on the declaration information. The analog circuit acquisition subunit is used to acquire the circuit information of the black box analog circuit and generate the netlist of the black box analog circuit based on the circuit information.

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