Memory device and method of operating the same

Abstract

The present disclosure relates to a memory device and a method of operating the memory device. The memory device may include a plurality of memory cells, peripheral circuits, and control logic. The peripheral circuits may perform a programming operation on the plurality of memory cells and may perform a programming verification operation corresponding to a plurality of programming states programmed in the programming operation, each programming verification operation including at least one verification cycle. The control logic may control the peripheral circuits to perform a verification pulse application operation and, when a target verification cycle count exceeds a reference count corresponding to a target programming state, may control the peripheral circuits to perform an additional verification pulse application operation, and the control logic may determine a failure of the programming verification operation corresponding to the target programming state based on results of the verification pulse application operation and results of the additional verification pulse application operation. A verification voltage of the additional verification pulse application operation is higher than a verification voltage of the verification pulse application operation.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0172420, filed on Dec. 10, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device in which data is stored, and a memory controller that controls the memory device. The memory device is classified into a volatile memory device and a non-volatile memory device.

[0005] A volatile memory device is a device that stores data only when power is supplied and loses the stored data when the power supply is cut off. The volatile memory device includes a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0006] A non-volatile memory device is a device that does not lose data even when the power is cut off. The non-volatile memory device includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, and the like. Summary of the Invention

[0007] Embodiments of the present disclosure provide a memory device having improved programming verification performance, and a method of operating the memory device.

[0008] According to an embodiment of the present disclosure, a memory device may include a plurality of memory cells, peripheral circuits, and control logic. The peripheral circuits may perform a programming operation on the plurality of memory cells and may perform a program verification operation corresponding to a plurality of program states programmed in the programming operation, each program verification operation including at least one verification cycle. The control logic may control the peripheral circuits to perform a verification pulse application operation and, when a target verification cycle count exceeds a reference count corresponding to a target program state, may control the peripheral circuits to perform an additional verification pulse application operation, the target verification cycle count being the number of verification cycles performed in the program verification operation corresponding to the target program state among the plurality of program states, and the control logic may determine whether the program verification operation corresponding to the target program state fails based on the result of the verification pulse application operation and the result of the additional verification pulse application operation. In the additional verification pulse application operation, a verification voltage higher than the verification voltage of the verification pulse application operation is applied to the memory cells.

[0009] According to an embodiment of the present disclosure, a method of operating a memory device may include: performing a programming operation on a plurality of memory cells; and performing a program verification operation corresponding to a plurality of program states programmed in the programming operation, each program verification operation including at least one verification cycle. Performing the program verification operation corresponding to a target program state among the plurality of program states includes: performing a verification pulse application operation; and when a target verification cycle count exceeds a reference count corresponding to the target program state, performing an additional verification pulse application operation, in which a verification voltage higher than the verification voltage of the verification pulse application operation is applied to the memory cells, the target verification cycle count being the number of verification cycles performed in the program verification operation corresponding to the target program state.

[0010] According to an embodiment of the present disclosure, a method of operating a memory device may include: performing a predetermined number of programming cycles on a memory cell; and when the memory cell is not programmed to a target program state despite the predetermined number of programming cycles, performing one or more additional programming cycles on the memory cell. Each programming cycle in the programming cycles includes a programming voltage application step and a program verification step. During the predetermined number of programming cycles, the program verification step is performed based on a first comparison between a reference and the number of memory cells among the memory cells having a threshold voltage lower than a lower verification voltage. During the additional programming cycles, the program verification step is performed based on the first comparison and based on a second comparison between the reference and the number of memory cells among the memory cells having a threshold voltage higher than a higher verification voltage, and wherein the failure to program the memory cell to the target program state depends on the second comparison.

[0011] According to the present technology, a memory device having improved programming verification performance and a method of operating the memory device are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating the Figure 1 structure of a memory device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram illustrating the Figure 2 memory cell array according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram illustrating a programming operation according to an embodiment of the present disclosure.

[0016] Figure 5 is a diagram illustrating the threshold voltage distribution of memory cells according to an embodiment of the present disclosure.

[0017] Figure 6 is a diagram illustrating passes and fails of a programming verification operation according to an embodiment of the present disclosure.

[0018] Figure 7 is a diagram illustrating the Figure 1 programming verification table storage device according to an embodiment of the present disclosure.

[0019] Figure 8 is a flowchart illustrating passes / fails of a programming operation according to an embodiment of the present disclosure.

[0020] Figure 9 is a diagram illustrating a verification cycle according to an embodiment of the present disclosure.

[0021] Figure 10 is a diagram illustrating the Figure 9 programming verification operation according to an embodiment of the present disclosure.

[0022] Figure 11 is a diagram illustrating a verification cycle according to an embodiment of the present disclosure.

[0023] Figure 12 is a diagram illustrating the Figure 11 programming verification operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The description of the specific structures or functions of the embodiments of the concepts disclosed in this specification is only for describing the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure can be implemented in various forms, and the description is not limited to the embodiments described in this specification.

[0025] Figure 1 FIG. is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0026] Referring Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device. The storage device 50 is a device that stores data under the control of a host, such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0027] According to the host interface as a communication method with the host, the storage device 50 can be manufactured as one type of various types of storage devices. For example, the storage device 50 can be configured as any type of various types of storage devices, such as an SSD, a multimedia card (in the form of MMC, eMMC, RS-MMC, and micro MMC), a secure digital card (in the form of SD, mini SD, and micro SD), a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) card type storage device, a PCI Express (PCI-E) card type storage device, a CompactFlash (CF) card, a SmartMedia card, and a Memory Stick.

[0028] The storage device 50 can be manufactured as any type of various types of packages. For example, the storage device 50 can be manufactured as any type of various types of package types, such as Package on Package (POP), System in Package (SIP), System on Chip (SOC), Multi-Chip Package (MCP), Chip on Board (COB), Wafer-Form Package (WFP), and Wafer-Level Stacked Package (WSP).

[0029] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array that includes a plurality of memory cells that store data.

[0030] Each memory cell in the memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that stores four data bits.

[0031] The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In one embodiment, a page may be a unit for storing data in or reading data stored in the memory device 100.

[0032] A memory block may be a unit for erasing data. In one embodiment, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for convenience of description, the memory device 100 is a NAND flash memory.

[0033] The memory device 100 is configured to: receive commands and addresses from the memory controller 200, and access a region of the memory cell array selected by the address. That is, the memory device 100 may perform an operation indicated by the command on the region selected by the address. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 may program data into the region selected by the address. During the read operation, the memory device 100 may read data from the region selected by the address. During the erase operation, the memory device 100 may erase the data stored in the region selected by the address.

[0034] In one embodiment, the memory device 100 may perform a programming operation of programming a plurality of memory cells into corresponding programming states among a plurality of programming states. The memory device 100 may perform programming verification operations corresponding to the plurality of programming states, respectively.

[0035] The memory device 100 may determine whether the programming operation fails based on the results of the programming verification operations corresponding to the plurality of programming states, respectively. When all the programming verification operations corresponding to the plurality of programming states pass, the memory device 100 may determine that the programming operation passes. When at least one of the programming verification operations corresponding to the plurality of programming states fails, the memory device 100 may determine that the programming operation fails.

[0036] In one embodiment, each programming verification operation in the programming verification operations may include at least one verification loop. In the at least one verification loop, the memory device 100 may perform at least one of the following: a verification pulse application operation of applying a verification voltage to a word line connected to a plurality of memory cells, and an additional verification pulse application operation of applying an additional verification voltage to the word line.

[0037] In one embodiment, when the target verification loop count is less than or equal to a reference count corresponding to a target programming state, the memory device 100 may perform a verification pulse application operation in the verification loop. The target verification loop count may be the number of verification loops executed in the programming verification operation corresponding to the target programming state. The reference count may be the maximum number of verification loops to be executed in the programming verification operation. When the target verification loop count is greater than the reference count corresponding to the target programming state, the memory device 100 may perform a verification pulse application operation and an additional verification pulse application operation in the verification loop.

[0038] In one embodiment, the verification voltage applied in the additional verification pulse application operation may be higher than the verification voltage applied in the verification pulse application operation. For example, the verification voltage applied in the verification pulse application operation may be the minimum voltage in the threshold voltage distribution corresponding to the target programming state. The verification voltage applied in the additional verification pulse application operation may be the maximum voltage in the threshold voltage distribution corresponding to the target programming state.

[0039] The memory device 100 may determine whether the programming verification operation corresponding to the target programming state fails based on the results of the verification pulse application operation and the additional verification pulse application operation. When the verification pulse application operation or the additional verification pulse application operation fails, the memory device 100 may determine that the programming verification operation corresponding to the target programming state fails. When both the verification pulse application operation and the additional verification pulse application operation pass, the memory device 100 may determine that the programming verification operation corresponding to the target programming state passes.

[0040] The memory device 100 may determine whether the verification pulse application operation fails based on the result of comparing the number of memory cells having a threshold voltage lower than the verification voltage applied in the verification pulse application operation among the memory cells to be programmed to the target programming state with a reference allowable bit number. The reference allowable bit number may be the maximum number of bits that can be error-corrected.

[0041] The memory device 100 may determine whether the additional verification pulse application operation fails based on the result of comparing the number of memory cells having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation among the memory cells to be programmed to the target programming state with the reference allowable bit number.

[0042] The memory controller 200 controls the overall operation of the storage device 50.

[0043] When power is applied to the storage device 50, the memory controller 200 may execute the firmware FW. When the memory device 100 is a flash memory device, the memory controller 200 may operate firmware such as a flash translation layer (FTL) to control communication between the host and the memory device 100.

[0044] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host and convert the LBA into a physical block address (PBA), which indicates the address of the memory cells in the memory device 100 in which the data included is to be stored.

[0045] The memory controller 200 may control the memory device 100 to perform a programming operation, a read operation, or an erase operation in response to a request from the host. During the programming operation, the memory controller 200 may provide a write command, a PBA, and data to the memory device 100. During the read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During the erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0046] In one embodiment, the memory controller 200 may generate commands, addresses, and data and transmit the commands, addresses, and data to the memory device 100 regardless of a request from the host. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a programming operation for wear leveling and a programming operation for garbage collection.

[0047] In one embodiment, the memory controller 200 may control at least two memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be an operation method for overlapping the operation periods of at least two memory devices 100.

[0048] The host can communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial ATA (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM).

[0049] Figure 2 is a diagram showing the Figure 1 structure of a memory device according to an embodiment of the present disclosure.

[0050] Referring to Figure 2 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130.

[0051] The memory cell array 110 includes a plurality of memory blocks BLKl to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to an address decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to a read and write circuit 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells are defined as one physical page. That is, the memory cell array 110 is configured by a plurality of physical pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one of the dummy cells may be connected in series between the drain select transistor and the memory cell, and between the source select transistor and the memory cell.

[0052] Each memory cell in the memory device 100 of the memory device may be configured as a Single-Level Cell (SLC) storing one data bit, a Multi-Level Cell (MLC) storing two data bits, a Triple-Level Cell (TLC) storing three data bits, or a Quad-Level Cell (QLC) storing four data bits.

[0053] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sense circuit 125.

[0054] The peripheral circuit 120 drives the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a programming operation, a read operation, and an erase operation.

[0055] The address decoder 121 is connected to the memory cell array 110 through the row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and a common source line. According to an embodiment of the present disclosure, the word lines may include normal word lines and dummy word lines. According to an embodiment of the present disclosure, the row lines RL may further include pipe select lines.

[0056] The address decoder 121 is configured to operate in response to the control of the control logic 130. The address decoder 121 receives the address ADDR from the control logic 130.

[0057] The address decoder 121 is configured to decode the block address of the received address ADDR. The address decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 is configured to decode the row address of the received address ADDR. The address decoder 121 may select at least one word line among the word lines of the selected memory block according to the decoded row address. The address decoder 121 may apply the operation voltage Vop supplied from the voltage generator 122 to the selected word line.

[0058] During a programming operation, the address decoder 121 may apply a programming voltage to the selected word line and apply a pass voltage to the unselected word lines, and the level of the pass voltage is less than the level of the programming voltage. During a programming verification operation, the address decoder 121 may apply a verification voltage to the selected word line and apply a verification pass voltage to the unselected word lines, and the level of the verification pass voltage is greater than the level of the verification voltage.

[0059] During a read operation, the address decoder 121 may apply a read voltage to the selected word line and apply a read pass voltage to the unselected word lines, and the level of the read pass voltage is greater than the level of the read voltage.

[0060] According to an embodiment of the present disclosure, the erase operation of the memory device 100 is performed in units of memory blocks. The address ADDR input to the memory device 100 during the erase operation includes a block address. The address decoder 121 may decode the block address and select at least one memory block according to the decoded block address. During the erase operation, the address decoder 121 may apply a ground voltage to the word lines input to the selected memory block.

[0061] According to an embodiment of the present disclosure, the address decoder 121 may be configured to decode the column address of the transmitted address ADDR. The decoded column address may be transmitted to the read and write circuit 123. As an example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0062] The voltage generator 122 is configured to generate a plurality of operating voltages Vop by using an external power voltage supplied to the memory device 100. The voltage generator 122 operates in response to the control of the control logic 130.

[0063] In one embodiment, the voltage generator 122 may generate an internal power voltage by regulating the external power voltage. The internal power voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0064] In one embodiment, the voltage generator 122 may use the external power voltage or the internal power voltage to generate a plurality of operating voltages Vop. The voltage generator 122 may be configured to generate various voltages required by the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of programming voltages, a plurality of pass voltages, a plurality of selected read voltages, and a plurality of unselected read voltages.

[0065] To generate a plurality of operating voltages Vop having various voltage levels, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal voltage, and selectively activate the plurality of pumping capacitors in response to the control logic 130 to generate a plurality of operating voltages Vop.

[0066] The plurality of generated operating voltages Vop may be supplied to the memory cell array 110 through the address decoder 121.

[0067] The read and write circuit 123 includes a first page buffer PB1 to an mth page buffer PBm. The first page buffer PB1 to the mth page buffer PBm are respectively connected to the memory cell array 110 through a first bit line BL1 to an mth bit line BLm. The first page buffer PB1 to the mth page buffer PBm operate in response to the control of the control logic 130.

[0068] The first page buffer PB1 to the mth page buffer PBm communicate data DATA with the data input / output circuit 124. During programming, the first page buffer PB1 to the mth page buffer PBm receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0069] During a programming operation, when a programming voltage is applied to a selected word line, the first page buffer PB1 to the m-th page buffer PBm can transfer the data DATA to be stored (i.e., the data DATA received through the data input / output circuit 124) to the selected memory cells via the bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming inhibit voltage (e.g., power voltage) is applied can be maintained. During a programming verification operation, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the memory cells from the selected memory cells via the bit lines BL1 to BLm.

[0070] During a read operation, the read and write circuit 123 can read the data DATA from the memory cells of the selected page via the bit lines BL1 to BLm and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0071] During an erase operation, the read and write circuit 123 can float the bit lines BL1 to BLm. In one embodiment, the read and write circuit 123 can include a column selection circuit.

[0072] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data lines DL. The data input / output circuit 124 operates in response to the control of the control logic 130.

[0073] The data input / output circuit 124 can include a plurality of input / output buffers (not shown) for receiving the input data DATA. During a programming operation, the data input / output circuit 124 receives the data DATA to be stored from an external controller (not shown). During a read operation, the data input / output circuit 124 outputs the normal data DATA to the external controller, and the normal data DATA is transferred from the first page buffer PB1 to the m-th page buffer PBm included in the read and write circuit 123.

[0074] During a read operation or a verification operation, the sense circuit 125 can generate a reference current in response to a signal of the enable bit VRYBIT generated by the control logic 130, and can compare the sense voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic 130.

[0075] The control logic 130 may be connected to an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125. The control logic 130 may be configured to control all operations of the memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device.

[0076] The control logic 130 may generate various signals in response to the command CMD and the address ADDR to control the peripheral circuit 120. For example, the control logic 130 may generate an operation signal OPSIG, an address ADDR, a read and write circuit control signal PBSIGNALS, and an enable bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 may output the operation signal OPSIG to the voltage generator 122, the address ADDR to the address decoder 121, the read and write control signal to the read and write circuit 123, and the enable bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 may determine whether the verification operation passes or fails in response to a pass signal PASS or a fail signal FAIL output by the sensing circuit 125.

[0077] In one embodiment, the control logic 130 may control the peripheral circuit 120 to perform a programming operation of programming a plurality of memory cells into corresponding programming states among a plurality of programming states. The control logic 130 may control the peripheral circuit 120 to perform programming verification operations respectively corresponding to the plurality of programming states.

[0078] In one embodiment, each programming verification operation in the programming verification operations may include at least one verification cycle. In the at least one verification cycle, at least one of the following may be performed: a verification pulse application operation of applying a verification voltage to a word line connected to a plurality of memory cells, and an additional verification pulse application operation of applying an additional verification voltage to the word line.

[0079] In one embodiment, the control logic 130 may include a programming verification table storage device 131 and a programming verification controller 132.

[0080] The programming verification table storage device 131 may store reference counts respectively corresponding to a plurality of programming states. Each of the reference counts may be the maximum number of verification cycles to be performed in a programming verification operation for a corresponding programming state (e.g., a target programming state) among the plurality of programming states.

[0081] The programming verification controller 132 can determine whether a programming operation fails based on the results of programming verification operations respectively corresponding to multiple programming states. When all the programming verification operations respectively corresponding to the multiple programming states pass, the programming verification controller 132 can determine that the programming operation passes. When at least one of the programming verification operations respectively corresponding to the multiple programming states fails, the programming verification controller 132 can determine that the programming operation fails.

[0082] The programming verification controller 132 can receive a reference count corresponding to a target programming state from the programming verification table storage device 131.

[0083] When the target verification cycle count is less than or equal to the reference count corresponding to the target programming state, the programming verification controller 132 can control the peripheral circuit 120 to perform a verification pulse application operation in a verification cycle. The target verification cycle count can be the number of verification cycles performed in the programming verification operation corresponding to the target programming state. When the target verification cycle count is greater than the reference count corresponding to the target programming state, the programming verification controller 132 can control the peripheral circuit 120 to perform a verification pulse application operation and an additional verification pulse application operation in a verification cycle.

[0084] In one embodiment, the verification voltage applied in the additional verification pulse application operation can be higher than the verification voltage applied in the verification pulse application operation. For example, the verification voltage applied in the verification pulse application operation can be the minimum voltage in the threshold voltage distribution corresponding to the target programming state. The verification voltage applied in the additional verification pulse application operation can be the maximum voltage in the threshold voltage distribution corresponding to the target programming state.

[0085] The programming verification controller 132 can obtain the results of the verification pulse application operation and the additional verification pulse application operation through the sensing circuit 125. The programming verification controller 132 can determine whether the programming verification operation corresponding to the target programming state fails based on the results of the verification pulse application operation and the additional verification pulse application operation. When the verification pulse application operation or the additional verification pulse application operation fails, the programming verification controller 132 can determine that the programming verification operation corresponding to the target programming state fails. When both the verification pulse application operation and the additional verification pulse application operation pass, the programming verification controller 132 can determine that the programming verification operation corresponding to the target programming state passes.

[0086] The programming verification controller 132 can determine whether a verification pulse application operation fails based on the result of comparing the number of memory cells having a threshold voltage lower than the verification voltage applied in the verification pulse application operation among the memory cells to be programmed to the target programming state with a reference allowable bit number. The reference allowable bit number can be the maximum number of bits for which error correction can be performed.

[0087] When the number of memory cells having a threshold voltage lower than the verification voltage applied in the verification pulse application operation is greater than the reference allowable bit number, the programming verification controller 132 can determine that the verification pulse application operation fails. When the number of memory cells having a threshold voltage lower than the verification voltage applied in the verification pulse application operation is less than or equal to the reference allowable bit number, the programming verification controller 132 can determine that the verification pulse application operation passes.

[0088] The result of the verification pulse application operation can include a left margin check result of the threshold voltage distribution corresponding to the target programming state. For example, it can be determined that as the number of memory cells having a threshold voltage lower than the verification voltage applied in the verification pulse application operation decreases, the left margin of the threshold voltage distribution becomes larger. Conversely, it can be determined that as the number of memory cells having a threshold voltage lower than the verification voltage applied in the verification pulse application operation increases, the left margin of the threshold voltage distribution becomes smaller.

[0089] The programming verification controller 132 can determine whether an additional verification pulse application operation fails based on the result of comparing the number of memory cells having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation among the memory cells to be programmed to the target programming state with a reference allowable bit number.

[0090] When the number of memory cells having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation is greater than the reference allowable bit number, the programming verification controller 132 can determine that the additional verification pulse application operation fails. When the number of memory cells having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation is less than or equal to the reference allowable bit number, the programming verification controller 132 can determine that the additional verification pulse application operation passes.

[0091] The result of the additional verification pulse application operation can include a right margin check result of the threshold voltage distribution corresponding to the target programming state. For example, it can be determined that as the number of memory cells having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation decreases, the right margin of the threshold voltage distribution becomes larger. Conversely, it can be determined that as the number of memory cells having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation increases, the right margin of the threshold voltage distribution becomes smaller.

[0092] Figure 3 is a diagram of a memory cell array according to an embodiment of the present disclosure Figure 2 of.

[0093] Referring to Figure 3 , the first memory block BLK1 to the z-th memory block BLKz are commonly connected to the first bit line BL1 to the m-th bit line BLm. In Figure 3 , for convenience of description, elements included in the first memory block BLK1 among the plurality of memory blocks BLK1 to BLKz are shown, and elements included in each of the remaining memory blocks BLK2 to BLKz are omitted. It can be understood that each of the remaining memory blocks BLK2 to BLKz is configured similarly to the first memory block BLK1.

[0094] The memory block BLK1 may include a plurality of cell strings CS1_1 to CS1_m (m is a positive integer). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first cell string CS1_1 to the m-th cell string CS1_m includes a drain select transistor DST, a plurality of memory cells MC1 to MCn (n is a positive integer) connected in series, and a source select transistor SST.

[0095] The gate terminals of the drain select transistors DST included in each of the first cell string CS1_1 to the m-th cell string CS1_m are connected to the drain select line DSL1. The gate terminals of each of the first memory cells MC1 to the n-th memory cells MCn included in each of the first cell string CS1_1 to the m-th cell string CS1_m are connected to the first word line WL1 to the n-th word line WLn. The gate terminals of the source select transistors SST included in each of the first cell string CS1_1 to the m-th cell string CS1_m are connected to the source select line SSL1.

[0096] For convenience of description, the structure of the cell string is described based on the first cell string CS1_1 among the plurality of cell strings CS1_1 to CS1_m. However, it can be understood that each of the remaining cell strings CS1_2 to CS1_m is configured similarly to the first cell string CS1_1.

[0097] The drain terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the first bit line BL1. The source terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the drain terminal of the first memory cell MC1 included in the first cell string CS1_1. The first memory cell MC1 to the nth memory cell MCn are connected in series with each other. The drain terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the source terminal of the nth memory cell MCn included in the first cell string CS1_1. The source terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the common source line CSL. In one embodiment, the common source line CSL may be commonly connected to the first memory block BLK1 to the zth memory block BLKz.

[0098] The drain select line DSL1, the first word line WL1 to the nth word line WLn, and the source select line SSL1 are included in Figure 2 the row line RL of. The drain select line DSL1, the first word line WL1 to the nth word line WLn, and the source select line SSL1 are controlled by the address decoder 121. The common source line CSL is controlled by the control logic 130. The first bit line BL1 to the mth bit line BLm are controlled by the read and write circuit 123.

[0099] Figure 4 is a diagram illustrating a programming operation according to an embodiment of the present disclosure.

[0100] In Figure 4 , for convenience of description, the memory cell is a multi-level cell (MLC) that stores 2-bit data. However, the scope of the present disclosure is not limited thereto, and the memory cell may be a triple-level cell (TLC) that stores 3-bit data or a quad-level cell (QLC) that stores 4-bit data. The number of data bits stored in the memory cell may be one or more.

[0101] The memory device may perform a plurality of programming cycles PL1 to PLn to program the selected memory cell to have a threshold voltage corresponding to any of the plurality of programming states P1, P2, and P3.

[0102] Each of the plurality of programming cycles PL1 to PLn may include: a programming voltage application step PGM Step of applying a programming voltage to the selected word line connected to the selected memory cell, and a programming verification step Verify Step of determining whether the memory cell is programmed by applying a verification voltage.

[0103] For example, when executing the first programming cycle PL1, after applying the first programming voltage Vpgm1, the first verification voltage V_vfy1 to the third verification voltage V_vfy3 are sequentially applied to verify the programming state of the selected memory cells. At this time, the verification of the memory cells whose target programming state is the first programming state P1 can be performed by the first verification voltage V_vfy1, the verification of the memory cells whose target programming state is the second programming state P2 can be performed by the second verification voltage V_vfy2, and the verification of the memory cells whose target programming state is the third programming state P3 can be performed by the third verification voltage V_vfy3.

[0104] The memory cells verified through the verification voltages V_vfy1 to V_vfy3 can be determined to have the target programming state, and then, the programming of the memory cells verified through the verification voltages V_vfy1 to V_vfy3 can be prohibited in the second programming cycle PL2. In other words, starting from the second programming cycle PL2, a programming prohibition voltage can be applied to the bit line connected to the memory cells verified through it.

[0105] In the second programming cycle PL2, a second programming voltage Vpgm2, which is higher than the first programming voltage Vpgm1 by a unit voltage △Vpgm, is applied to the selected word line to program the remaining memory cells except for the memory cells whose programming is prohibited. Thereafter, a verification operation is performed in the same manner as the verification operation of the first programming cycle PL1. A successful verification indicates that the memory cell is read as an off cell through the corresponding verification voltage.

[0106] As described above, when the memory device programs a multi-level cell (MLC) storing 2 bits, the memory device uses the first verification voltage V_vfy1 to the third verification voltage V_vfy3 to verify each of the memory cells whose programming state becomes the target programming state.

[0107] During the verification operation, the verification voltage is applied to the selected word line, which is the word line connected to the selected memory cells, and Figure 2 the page buffer can determine whether the verification of the memory cells is successful based on the current flowing through the bit line respectively connected to the selected memory cells or the voltage applied to the bit line.

[0108] In one embodiment, the programming verification step Verify Step can be referred to as the verification cycle described with reference to Figure 1 and Figure 2 described.

[0109] Figure 5 is a diagram illustrating the threshold voltage distribution of memory cells according to an embodiment of the present disclosure.

[0110] In Figure 5 this embodiment, the memory cell is an MLC that stores 2-bit data. The number of data bits stored in the memory cell is not limited to this embodiment.

[0111] The memory cell can be programmed to any of the erase state E and the first to third programming states P1 to P3. Figure 5 A first threshold voltage distribution D1 corresponding to each of the erase state E and the first to third programming states P1 to P3 is shown. For convenience of description, the second threshold voltage distribution D2 only shows the threshold voltage distribution corresponding to the second programming state P2.

[0112] In one embodiment, the minimum voltage PV and the maximum voltage PV* in the threshold voltage distribution corresponding to each programming state can be used as verification voltages for the programming verification operation.

[0113] For example, in the programming verification operation corresponding to the second programming state P2, the verification voltage PV2 can be the verification voltage applied in the verification pulse application operation. The verification voltage PV2* can be the verification voltage applied in the additional verification pulse application operation.

[0114] The result of the verification pulse application operation applying the verification voltage PV2 can include the left margin check result for the second programming state P2. For example, it can be determined that as the number of memory cells among those programmed to the second programming state P2 and having a threshold voltage lower than the verification voltage PV2 increases, the left margin becomes smaller. It can be determined that as the number of memory cells among those programmed to the second programming state P2 and having a threshold voltage lower than the verification voltage PV2 decreases, the left margin becomes larger.

[0115] The result of the additional verification pulse application operation applying the verification voltage PV2* can include the right margin check result for the second programming state P2. For example, it can be determined that as the number of memory cells among those programmed to the second programming state P2 and having a threshold voltage higher than the verification voltage PV2* increases, the right margin becomes smaller. It can be determined that as the number of memory cells among those programmed to the second programming state P2 and having a threshold voltage higher than the verification voltage PV2* decreases, the right margin becomes larger.

[0116] In Figure 5 this embodiment, when comparing the first threshold voltage distribution D1 and the second threshold voltage distribution D2 corresponding to the second programming state P2, both the left margin and the right margin of the first threshold voltage distribution D1 are greater than the left margin and the right margin of the second threshold voltage distribution D2.

[0117] Figure 6It is a diagram showing the pass and fail of a programming verification operation according to an embodiment of the present disclosure.

[0118] Reference Figure 6 , in a programming verification operation corresponding to a target programming state, a verification pulse application operation using a verification voltage PV and an additional verification pulse application operation using a verification voltage PV* can be performed. The verification voltage PV* applied in the additional verification pulse application operation can be higher than the verification voltage PV applied in the verification pulse application operation.

[0119] In one embodiment, the verification voltage PV can be the minimum voltage in a reference threshold voltage distribution corresponding to the target programming state. The verification voltage PV* can be the maximum voltage in the reference threshold voltage distribution corresponding to the target programming state. However, the levels of the verification voltage PV* and the verification voltage PV are not limited to this embodiment.

[0120] The pass or fail of the programming verification operation VFY can be determined based on the results of the verification pulse application operation and the results of the additional verification pulse application operation. For example, when both the verification pulse application operation and the additional verification pulse application operation pass, the programming verification operation VFY passes. When the verification pulse application operation or the additional verification pulse application operation fails, the programming verification operation VFY fails.

[0121] In Figure 6 , when the number of memory cells having a threshold voltage lower than the verification voltage PV is less than the reference allowable bit number REF_AB, the verification pulse application operation can pass. When the number of memory cells having a threshold voltage higher than the verification voltage PV* is less than the reference allowable bit number REF_AB, the additional verification pulse application operation can pass. In this case, since both the verification pulse application operation and the additional verification pulse application operation pass, the programming verification operation VFY can pass.

[0122] When the number of memory cells having a threshold voltage higher than the verification voltage PV* is greater than the reference allowable bit number REF_AB, the additional verification pulse application operation can fail. In this case, since the additional verification pulse application operation fails, the programming verification operation VFY can fail.

[0123] Figure 7 It is a diagram showing a programming verification table storage device according to an embodiment of the present disclosure Figure 2

[0124] Reference Figure 7, when the memory cell is a TLC that stores 3-bit data, the memory cell can be programmed to any programming state among the first programming state P1 to the seventh programming state P7. The number of data bits stored in the memory cell and the number of programming states to which the memory cell can be programmed are not limited to this embodiment.

[0125] The programming verification table storage device can store reference counts, and the reference counts respectively correspond to multiple programming states to which the memory cell is to be programmed. Each of the reference counts in the reference counts can be the maximum number of verification cycles to be executed in a programming verification operation for the corresponding programming state (e.g., the target programming state) among the multiple programming states.

[0126] In Figure 7 it, the programming verification table storage device can store reference counts corresponding to the respective first programming state P1 to the seventh programming state P7. The reference count PV1_LM corresponding to the first programming state P1 can be the maximum number of verification cycles to be executed in a programming verification operation corresponding to the first programming state P1. The reference count PV2_LM corresponding to the second programming state P2 can be the maximum number of verification cycles to be executed in a programming verification operation corresponding to the second programming state P2. In the same way, the reference count PV7_LM corresponding to the seventh programming state P7 can be the maximum number of verification cycles to be executed in a programming verification operation corresponding to the seventh programming state P7.

[0127] Figure 8 is a flowchart showing the pass / fail of a programming operation according to an embodiment of the present disclosure.

[0128] Refer to Figure 8 , in operation S801, N can be set to 1.

[0129] In operation S803, a programming verification operation for the Nth programming state can be executed.

[0130] In operation S805, it can be determined whether the programming verification operation for the Nth programming state passes. When the programming verification operation passes, the operation proceeds to operation S807, and when the programming verification operation fails, the operation proceeds to operation S813.

[0131] In operation S807, it can be determined whether the Nth programming state is the last programming state. When the Nth programming state is the last programming state, the operation proceeds to operation S809, and when the Nth programming state is not the last programming state, the operation proceeds to operation S811. The last programming state can be the highest programming state among the multiple programming states to which the memory cell is to be programmed.

[0132] In operation S809, the programming operation can be determined to pass.

[0133] In operation S811, N can be incremented by 1.

[0134] In operation S813, the programming operation can be determined to fail.

[0135] In Figure 8 as described, the pass or fail of the programming operation can be determined based on the results of the programming verification operations corresponding to each of the multiple programming states. When all the programming verification operations corresponding to the multiple programming states pass respectively, the programming operation can be a pass. When at least one of the programming verification operations corresponding to the multiple programming states fails, the programming operation can be a fail.

[0136] Figure 9 is a diagram showing a verification loop according to an embodiment of the present disclosure.

[0137] Refer to Figure 9 , the programming loop can include a programming pulse application loop and a verification loop. In Figure 9 the case of, a verification pulse application operation for applying a verification voltage PV corresponding to the target programming state can be performed in the verification loop. After performing the verification pulse application operation in the verification loop, a verification check operation can be performed. When the verification check operation passes, the verification pulse application operation for the target programming state can be completed.

[0138] In Figure 9 the embodiment, the reference count PV2_LM corresponding to the second programming state can be 5. The reference count PV2_LM corresponding to the second programming state is not limited to this embodiment.

[0139] The verification loop count PV2_LC can be 7, and the verification loop count PV2_LC is the number of verification loops performed in the programming verification operation corresponding to the second programming state.

[0140] In Figure 9 the embodiment, since the verification loop count PV2_LC exceeds the reference count PV2_LM, the programming verification operation corresponding to the second programming state can be a fail. Since the programming verification operation corresponding to the second programming state is a fail, the programming operation on the memory cell can be a fail.

[0141] Figure 10 is a flowchart showing the Figure 9 programming verification operation according to an embodiment of the present disclosure.

[0142] Refer to Figure 10, in operation S1001, a verification pulse application operation corresponding to the target programming state can be performed.

[0143] In operation S1003, it can be determined whether the verification pulse application operation passes. As a result of this determination, when the verification pulse application operation passes, the operation proceeds to operation S1007, and when the verification pulse application operation fails, the operation proceeds to operation S1005.

[0144] In operation S1005, the verification loop count can be incremented.

[0145] In operation S1007, it can be determined whether the verification loop count exceeds a reference count. When the verification loop count is greater than the reference count, the operation proceeds to operation S1011, and when the verification loop count is less than or equal to the reference count, the operation proceeds to operation S1009.

[0146] In operation S1009, the programming verification operation can be determined to pass.

[0147] In operation S1011, the programming verification operation can be determined to fail.

[0148] Reference Figure 9 and Figure 10 , even if the verification pulse application operation corresponding to the second programming state passes, when the verification loop count (which is executed until the verification pulse application operation passes) exceeds the reference count, the programming verification operation is determined to fail.

[0149] is a diagram illustrating a verification loop according to an embodiment of the present disclosure.

[0150] Reference Figure 11 , in the verification loop, a verification pulse application operation for applying a verification voltage PV and an additional verification pulse application operation for applying a verification voltage PV* can be performed.

[0151] In Figure 11 , the reference count PV2_LM corresponding to the second programming state can be 5. The reference count PV2_LM corresponding to the second programming state is not limited to this embodiment.

[0152] The verification loop count PV2_LC can be 7, and the verification loop count PV2_LC is the number of verification loops performed in the programming verification operation corresponding to the second programming state.

[0153] In Figure 11In an embodiment, when it is verified that the verification loop count PV2_LC is less than or equal to the reference count PV2_LM, the verification pulse application operation can be performed in the verification loop. When the verification loop count PV2_LC is greater than the reference count PV2_LM, the verification pulse application operation and the additional verification pulse application operation can be performed in the verification loop.

[0154] In Figure 11 an embodiment, even if the verification loop count PV2_LC exceeds the reference count PV2_LM, when both the verification pulse application operation and the additional verification pulse application operation pass, the programming verification operation corresponding to the second programming state can be determined to pass, as described in reference Figure 11 as described.

[0155] Figure 6 is a flowchart illustrating the Figure 12 programming verification operation according to an embodiment of the present disclosure.

[0156] Referring to Figure 11 , in operation S1201, it can be determined whether the verification loop count is greater than the reference count. The verification loop count is the number of verification loops performed in the programming verification operation corresponding to the target programming state. When the verification loop count is greater than the reference count, the operation proceeds to operation S1219, and when the verification loop count is less than or equal to the reference count, the operation proceeds to operation S1203.

[0157] In operation S1203, the verification pulse application operation can be performed.

[0158] In operation S1205, it can be determined whether the verification pulse application operation passes. As a result of this determination, when the verification pulse application operation passes, the operation proceeds to operation S1207, and when the verification pulse application operation fails, the operation proceeds to operation S1209.

[0159] In operation S1207, the programming verification operation can be determined to pass.

[0160] In operation S1209, the verification loop count can be incremented.

[0161] In operation S1211, the verification pulse application operation and the additional verification pulse application operation can be performed.

[0162] In operation S1213, it can be determined whether the verification pulse application operation passes. As a result of this determination, when the verification pulse application operation passes, the operation proceeds to operation S1215, and when the verification pulse application operation fails, the operation proceeds to operation S1209.

[0163] In operation S1215, it is possible to determine whether the additional verification pulse application operation has passed. As a result of this determination, when the additional verification pulse application operation has passed, the operation proceeds to operation S1207, and when the verification pulse application operation has failed, the operation proceeds to operation S1217.

[0164] In operation S1217, the programming verification operation can be determined to have failed.

[0165] In operation S1219, it is possible to determine whether the additional verification cycle count is greater than the additional reference count, where the additional verification cycle count is the number of verification cycles, including the additional verification pulse application operation, that are executed in the programming verification operation corresponding to the target programming state. When the additional verification cycle count is greater than the additional reference count, the operation proceeds to operation S1217, and when the additional verification cycle count is less than or equal to the additional reference count, the operation proceeds to operation S1211. The additional reference count can be the maximum number of verification cycles, including the additional verification pulse application operation, that are to be executed in the programming verification operation.

[0166] Reference Figure 12 and Figure 11 , even if the verification cycle count (which is executed until the verification pulse application operation corresponding to the second programming state has passed) exceeds the reference count, the programming verification operation can be determined to have passed when both the verification pulse application operation and the additional verification pulse application operation have passed.

[0167] In Figure 12 the case of the embodiment of Figure 10 the programming verification operation is determined to have failed when the verification cycle count exceeds the reference count. In

[0168] Slow memory cells can be programmed more slowly than normal memory cells. That is, since slow memory cells are programmed more slowly than normal memory cells, more verification cycles can be executed. Even in slow memory cells, when both the verification pulse application operation and the additional verification pulse application operation have passed, it can be determined that the slow memory cells have been programmed normally.

[0169] In Figure 12 the case of the embodiment of

[0170] In Figure 10 Figure 12In the case of the embodiment, even if the verification cycle count exceeds the reference count, when the programming is executed normally, it can be determined that the programming operation has passed. Therefore, unnecessary overkill can be prevented and the yield can be improved.

[0171] Although the detailed description of the present disclosure describes specific embodiments, various changes are possible without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above embodiments, and should be determined by the equivalents of the claims of the present disclosure and the appended claims.

Claims

1. A memory device, comprising: A plurality of memory cells; Peripheral circuitry configured to perform a programming operation on the plurality of memory cells and perform a programming verification operation corresponding to a plurality of programming states programmed in the programming operation, each programming verification operation including at least one verification cycle; And Control logic configured to control the peripheral circuitry to perform a verification pulse application operation and, when a target verification cycle count exceeds a reference count corresponding to a target programming state among the plurality of programming states, control the peripheral circuitry to perform an additional verification pulse application operation, the target verification cycle count being the number of verification cycles performed in the programming verification operation corresponding to the target programming state; And determine whether the programming verification operation corresponding to the target programming state fails based on results of the verification pulse application operation and results of the additional verification pulse application operation, Wherein in the additional verification pulse application operation, a verification voltage higher than the verification voltage of the verification pulse application operation is applied to the memory cells.

2. The memory device according to claim 1, wherein the control logic includes: A programming verification table storage device configured to store reference counts respectively corresponding to the plurality of programming states; And A programming verification controller configured to control the peripheral circuitry to perform the verification pulse application operation or both the verification pulse application operation and the additional verification pulse application operation based on a result of comparing the target verification cycle count with the reference count corresponding to the target programming state.

3. The memory device according to claim 2, wherein when the target verification cycle count is less than or equal to the reference count corresponding to the target programming state, the programming verification controller controls the peripheral circuitry to perform the verification pulse application operation in each of the at least one verification cycle.

4. The memory device according to claim 2, wherein when the target verification cycle count is greater than the reference count corresponding to the target programming state, the programming verification controller controls the peripheral circuitry to perform both the verification pulse application operation and the additional verification pulse application operation in each of the at least one verification cycle.

5. The memory device according to claim 2, wherein the programming verification controller is further configured to determine that the programming verification operation corresponding to the target programming state passes when both the verification pulse application operation and the additional verification pulse application operation pass.

6. The memory device according to claim 2, wherein the programming verification controller is further configured to determine that the programming verification operation corresponding to the target programming state fails when the verification pulse application operation or the additional verification pulse application operation fails.

7. The memory device according to claim 2, wherein the programming verification controller is further configured to: determine whether the verification pulse application operation fails based on a result of comparing the number of memory cells having a threshold voltage lower than the verification voltage applied in the verification pulse application operation among the memory cells to be programmed to the target programming state with a reference allowable bit number.

8. The memory device according to claim 2, wherein the programming verification controller is further configured to: determine whether the additional verification pulse application operation fails based on a result of comparing the number of memory cells having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation among the memory cells to be programmed to the target programming state with a reference allowable bit number.

9. The memory device according to claim 2, wherein the programming verification controller is further configured to: determine whether the programming operation fails based on results of the programming verification operations respectively corresponding to the plurality of programming states.

10. The memory device according to claim 9, wherein when all the programming verification operations respectively corresponding to the plurality of programming states pass, the programming verification controller determines that the programming operation passes.

11. The memory device according to claim 1, wherein the verification voltage applied in the verification pulse application operation performed in the programming verification operation corresponding to the target programming state is the minimum voltage in the threshold voltage distribution corresponding to the target programming state.

12. The memory device according to claim 1, wherein the verification voltage applied in the additional verification pulse application operation performed in the programming verification operation corresponding to the target programming state is the maximum voltage in the threshold voltage distribution corresponding to the target programming state.

13. The memory device according to claim 1, wherein a result of the verification pulse application operation performed in the programming verification operation corresponding to the target programming state includes: The left margin check result of the threshold voltage distribution corresponding to the target programming state.

14. The memory device according to claim 1, wherein a result of the additional verification pulse application operation performed in the programming verification operation corresponding to the target programming state includes: The right margin check result of the threshold voltage distribution corresponding to the target programming state.

15. A method of operating a memory device, the method comprising: performing a programming operation on a plurality of memory cells; and performing a programming verification operation corresponding to a plurality of programming states programmed in the programming operation, each programming verification operation including at least one verification cycle, wherein performing the programming verification operation corresponding to a target programming state among the plurality of programming states includes: performing a verification pulse application operation; and performing an additional verification pulse application operation when a target verification cycle count exceeds a reference count corresponding to the target programming state, in which a verification voltage higher than the verification voltage of the verification pulse application operation is applied to the memory cells, the target verification cycle count being the number of verification cycles performed in the programming verification operation corresponding to the target programming state.

16. The method according to claim 15, further comprising: Determining whether the programming verification operation corresponding to the target programming state fails based on the result of the verification pulse application operation and the result of the additional verification pulse application operation.

17. The method according to claim 16, wherein the result of the verification pulse application operation is determined based on a comparison result between the number of memory cells among those to be programmed to the target programming state and having a threshold voltage lower than the verification voltage applied in the verification pulse application operation and a reference allowable bit number.

18. The method according to claim 16, wherein the result of the additional verification pulse application operation is determined based on a comparison result between the number of memory cells among those to be programmed to the target programming state and having a threshold voltage higher than the verification voltage applied in the additional verification pulse application operation and a reference allowable bit number.

19. The method according to claim 16, Performing the verification pulse application operation in the programming verification operation corresponding to the target programming state includes: applying the minimum voltage in the threshold voltage distribution corresponding to the target programming state as the verification voltage, and wherein performing the additional verification pulse application operation in the programming verification operation corresponding to the target programming state includes: applying the maximum voltage in the threshold voltage distribution corresponding to the target programming state as the verification voltage.

20. The method according to claim 16, further comprising: determining whether the programming operation fails based on the results of the programming verification operations respectively corresponding to the plurality of programming states.

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