Data recovery system for memory device

Abstract

Systems, methods, and apparatus related to data recovery in a memory device. In one method, a memory device encodes stored data. The memory device reads a codeword from a storage medium and determines that the number of errors in the codeword exceeds the error correction capability of the memory device. For example, the errors are caused by one or more stuck bits. In response to this determination, one or more data patterns are written to the same address of the storage medium from which the codeword was read. The data patterns are read to identify the bit positions of the stuck bits. The identified positions are used to correct the bit errors in the read codeword corresponding to the identified positions. The corrected codeword is sent to a host device (e.g., which has requested data from the memory device using a read command).

Description

Technical Field

[0001] At least some embodiments disclosed herein relate generally to memory devices, and more particularly, but not limited to, data recovery for errors occurring in data stored in the memory devices. Background Art

[0002] In some cases, recurring errors occur when writing data to memory. For example, memory may exhibit so-called static or hard errors in memory cells. A hard error can refer to a repeatable error that consistently returns incorrect data. Some hard errors can occur due to memory cells being stuck in a particular state (e.g., errors caused by a stuck bit).

[0003] As an example, a binary memory cell with a hard error will return a logic-0 value regardless of whether a logic-0 or logic-1 is written to the memory cell. In this example, the memory cell will experience the same failure when reading data from the memory cell with the hard error. More specifically, a memory cell stuck in the logic-0 state will experience a failure to read a logic-0 when attempting to read a logic-1 written to the memory cell.

[0004] Hard errors can occur in various types of memory, such as phase change memory (PCM), also known as PCRAM or PRAM. PCM is a form of non-volatile memory made from phase change material. An example of a phase change material is germanium antimony telluride (GST). When a cell of GST material is heated above its melting point and cooled relatively quickly, the cell's phase change material is in an amorphous state and may have a resistance associated with a first state (e.g., a logical 0). When a cell of GST material is heated and cooled relatively slowly, the cell's phase change material is in a crystalline state and may have a resistance associated with a second state (e.g., a logical 1). A cell of GST material can also be heated to relatively low temperatures, such as the temperature associated with crystallization to achieve a crystalline state. Intermediate states of multiple levels of cells are also possible. Summary of the Invention

[0005] In one aspect, the present disclosure provides a system comprising: at least one memory configured to store data in a memory cell; a buffer configured to store data read from the memory cell; and at least one processing device configured to: read first data from a location in the memory; store the first data in the buffer; detect one or more errors in the first data; in response to detecting an error in the first data, write a data pattern to the location in the memory; read the data pattern from the location in the memory; identify at least one faulty bit in the read data pattern; and in response to identifying the faulty bit, correct the identified faulty bit in the stored first data to provide corrected data.

[0006] On the other hand, the present disclosure provides a method comprising: reading data from a location in a memory; detecting an error in the read data; in response to detecting the error, writing at least one data pattern to the location in the memory; reading the data pattern from the location in the memory; identifying at least one bit error based on reading the data pattern; and in response to identifying the bit error, correcting the bit error in the read data to provide corrected data.

[0007] In yet another aspect, the present disclosure provides a non-transitory computer-readable medium storing instructions that, when executed on at least one processing device, cause the at least one processing device to, in response to receiving a read command from a host device, perform the following operations: read data from a memory; detect an error in the read data; in response to detecting the error, write at least one data pattern to the memory; read the data pattern from the memory; identify at least one stuck bit based on reading the data pattern; in response to identifying the stuck bit, correct the read data to provide corrected data; and send the corrected data to the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements.

[0009] Figure 1 A system is shown that implements data recovery for errors occurring in data stored in a memory device, according to some embodiments.

[0010] Figure 2 An example of correcting data to recover from data errors stored in memory is shown according to some embodiments.

[0011] Figure 3 A system for performing data recovery of a memory of a storage device based on an operating environment according to some embodiments is shown.

[0012] Figure 4 A method for correcting data errors stored in a memory by using one or more data patterns is shown in accordance with some embodiments.

[0013] Figure 5 Methods for correcting errors in stored data based on sensor data and / or output of an artificial neural network are shown in accordance with some embodiments.

[0014] Figure 6 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0015] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0016] The following disclosure describes various embodiments of a data recovery system for correcting errors that occur in data stored in a memory device. At least some embodiments herein relate to stuck bits or other failed bits that cause bit errors in data read from a memory device (e.g., a memory array). In one example, the memory device can be any of various types of volatile or non-volatile memory devices (e.g., storage devices). In some examples, the memory device can use phase change memory (PCM) and / or NAND flash memory. For example, the memory device can store data for use by a host device (e.g., a computing device of an autonomous vehicle, or another computing device that accesses data stored in the memory device). In one example, the memory device is a solid-state drive. Other types of memory devices may include devices using random access memory (RAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), and resistive RAM (RRAM).

[0017] Memory devices sometimes include error correction capabilities. For example, when storing data, the memory device may implement error correction code (ECC) to identify and correct errors. However, the error correction capability may often be very limited (e.g., 3-bit error correction capability). If the number of errors that occur when reading data from the memory exceeds the error correction capability (e.g., 4-bit errors or greater), the memory device may be unable to fully correct the data. For example, this may prevent the memory device from sending appropriate and correct data to a host device that has issued a read command to the memory device. The inability to send correct data to the host device may cause software executing on the host device to malfunction.

[0018] In one example, a host device executes software that controls the operation of an autonomous vehicle. The inability of the memory device to send correct data to the host device can cause the vehicle to crash or malfunction. This can result in physical damage and / or personal injury.

[0019] To address these and other technical issues, a data recovery system and method for use in a memory device is described herein. Data recovery is performed in response to identifying one or more errors in data read from a memory device. In response to detecting an error, one or more data patterns (e.g., a test pattern of all ones or all zeros) are selected and written to the memory, and the data patterns are read from the memory to identify errors in the data.

[0020] In one example, the identified error is caused by a stuck bit.For example, a stuck bit can be caused by a defective memory cell in a memory array (eg, a PCM memory array).

[0021] In one embodiment, a memory device determines that data read from a memory array (e.g., a sensed codeword) contains errors. These errors include one or more errors caused by stuck bits that occur during the useful life of the memory device in the field. For example, these errors may occur one or more years after the memory device is manufactured.

[0022] The number of errors is determined to be greater than the error correction capability of the memory device, but detection of the errors is within the detection capability of the memory device. In one example, the memory device uses an error correction code that can only correct three bits in a codeword but is able to detect four bits in the codeword as defective.

[0023] In response to determining that the number of bit errors detected in a codeword read from a memory is greater than an error correction capability, a data recovery process is initiated to determine the location of a faulty bit in the codeword. A test data pattern is selected for writing to the same location from which the defective word was read. The data pattern is then read from the same location. The location of the faulty bit is determined by comparing bits of the read data pattern with the written data pattern (e.g., to look for bit value mismatches).

[0024] If the first data pattern written above cannot be used to identify the failed bit, an inverse data pattern is written to the same location (for example, all logic 0 values in the first data pattern are inverted to logic 1 values in the second data pattern). The inverse second data pattern is then read from the same location and used to identify the location of the failed bit.

[0025] In one embodiment, once the location of the failed bit is identified, the failed bit is flipped in the codeword read from the memory. The remaining errors in the codeword are then corrected using error correction capabilities (e.g., ECC3). The corrected codeword can then be sent to the host device and / or written to the same location in the memory so that the memory now stores the proper and correct data.

[0026] In another embodiment, first data is read from a location in a memory. The first data is stored in a buffer. One or more errors in the first data are detected. In response to detecting the errors in the first data, a data pattern is written to the location in the memory. The data pattern is read from the location in the memory, and at least one failed bit in the read data pattern is identified. In response to identifying the failed bit, the identified failed bit is corrected in the stored first data to provide corrected data.

[0027] In one example, in response to receiving a read command from a host device, first data is read from the memory. In a reply to the read command, corrected data is sent to the host device. In another example, the first data can be read during execution of an on-die management or other maintenance process (e.g., wear leveling) without prompting or interaction with the host device.

[0028] Advantages provided by various embodiments described herein include providing a means for systems to correct more bits than existing error correction code systems would otherwise allow. This is particularly advantageous in systems that accept out-of-order memory requests. Another advantage is the ability to correct errors caused by stuck bits while the memory device is in operation.

[0029] Figure 1 A system for implementing data recovery for errors occurring in data stored in memory device 101 according to some embodiments is shown. An error is detected while reading data from the memory. Storage medium 103 stores data 109 in memory cells. These memory cells include cell 105 and cell 107. In one example, cell 105 corresponds to the first row in the memory array, and cell 107 corresponds to the second row in the memory array. In one example, the memory cells are NAND flash memory cells or PCM memory cells. In one example, the first row stores a codeword containing user data and ECC data 117. ECC data 117 is obtained by encoding the user data using error correction capability 123. The second row stores a codeword containing the user data and ECC data 119.

[0030] In one embodiment, memory device 101 receives a read command from host device 127. In response to receiving the read command, processing device 121 reads data 109, such as a codeword stored in cell 105, from storage medium 103. The read codeword is stored in buffer 151. Buffer 151 is, for example, a random access memory.

[0031] Processing device 121 uses error detection 123 to detect one or more errors in a codeword read from storage medium 103. In response to detecting the one or more errors, processing device 121 writes a data pattern to the same location (e.g., the same physical address) of storage medium 103 from which the codeword was read. For example, the location is an address in a memory array, and the address indicates a row in the memory array that includes cell 105. In one example, one of the errors detected in the codeword is caused by a defective phase change memory (PCM) or flash memory cell 105.

[0032] In one example, the data pattern written is a bit pattern in which every bit is a logic 0. A data pattern is then read from the same location in the memory where the data pattern was written. The read data pattern is compared bit by bit with the written data pattern. If the read bits have different logic values than the written bits, the location of the faulty bit is identified. In some cases, more than one faulty bit location may be identified.

[0033] In response to identifying the one or more failing bits, which includes determining the locations of the failing bits, the codeword stored in buffer 151 is corrected by flipping the logic value of the bits at the bit positions corresponding to the identified failing bits.

[0034] In some cases, a first data pattern read from the memory (e.g., all logic 0s) completely matches the first data pattern written and cannot be used to identify a failed bit. In this case, a second data pattern is written to the memory location. The second data pattern is the inverse of the first data pattern (e.g., all logic 1s). One or more failed bits (e.g., the location of a stuck bit corresponding to a bit position in the read codeword) are revealed by comparing the read second data pattern with the written second data pattern.

[0035] In some embodiments, data recovery for correcting errors in data stored in memory device 101 is alternatively and / or additionally performed by host device 127. In one embodiment, a codeword is read from storage medium 103 and stored in buffer 152 of host device 127. The codeword includes ECC data 135, which is used by error detection 141 to identify one or more errors in the codeword. For example, error detection 141 detects a number of errors in the codeword that exceeds the correction capability of error correction 141. In one example, ECC data 135 includes ECC data 117.

[0036] In response to detecting a number of errors that exceeds the correction capability, host device 127 selects a first data pattern to write to the same address of memory device 101 from which the codeword was read. For example, the first data pattern may be all logic 1s or 0s. For example, the first data pattern may be a random or arbitrary mix of logic 1s or 0s. For example, the first data pattern may be selected based on the operating environment of memory device 101 (e.g., the age of memory device 101 and / or the operating temperature of memory device 101).

[0037] After selecting the first data pattern, host device 127 writes the first data pattern to the same address from which the codeword was read. Host device 127 then reads the first data pattern from this same address. Host device 127 compares the written pattern with the read pattern and determines that the read first pattern does not indicate any failed bits in storage medium 103.

[0038] In response to this determination, host device 127 selects a second data pattern. For example, the second data pattern is the opposite of the first data pattern. For example, the second data pattern is selected based on one or more operating characteristics of memory device 101 determined by writing and / or reading the first data pattern. For example, the second data pattern may additionally and / or alternatively be selected based on the operating environment of memory device 101.

[0039] Host device 127 writes a second data pattern to the same address from which the codeword was read. Host device 127 reads the second data pattern. Based on reading the second data pattern, host device 127 identifies one or more bit errors and the corresponding bit positions of the errors.

[0040] Host device 127 uses the identified bit errors and corresponding bit positions to correct one or more bit errors in the codeword stored in buffer 152. For example, host device 127 determines that a stuck bit exists at bit position 23-128 in the codeword. Host device 127 changes the logic value of bit position 23 in the stored codeword (e.g., by flipping the value from 0 to 1).

[0041] After correcting the error in the codeword based on reading the second data pattern, host device 127 corrects other errors in the codeword using error correction 141 and ECC data 135. The corrected codeword is then available for further use by host device 127 and / or memory device 101. In one example, host device 127 writes the corrected codeword to the same location in memory device 101 from which the codeword was initially read before error correction.

[0042] In one embodiment, various data patterns may be selected. In one example, each data pattern is selected for a specific write operation to store data in memory. In one example, the data pattern is alternating zeros and ones, or ones and zeros. In one example, the data pattern is selected so that correctable bits are corrected before the data pattern is written to memory, resulting in a reduced number of identified failed bits (e.g., to make it easier to identify stuck bits).

[0043] In one embodiment, host device 127 includes a memory management unit (MMU) 136 that maintains a logical-to-physical address mapping of data stored in memory device 101. In one example, a mapping of pages stored as data 109 in memory device 101 is stored by host device 127 as page map 138. MMU 136 updates page map 138 during operation of host device 127.

[0044] In one example, after determining that there are one or more fault bits associated with a page stored in storage medium 103, MMU 136 updates page map 138 to change the mapping of the page to a different physical location in storage medium 103. In one example, the MMU evicts the defective page rather than changing the page mapping for the page.

[0045] In one embodiment, memory device 101 is a flash memory device, and error correction codes are used in the flash memory device to recover stored data in the event of a detected error. In one example, the error correction code supplements user data with parity bits that store additional information so that the data can be recovered if one or more data bits are damaged. The number of correctable data bit errors in the stored data increases as the number of error bits in the error correction code increases.

[0046] In the flash memory device described above, user data and error correction code information for the user data (e.g., ECC data 117) are stored in memory locations of the memory device (e.g., at physical addresses of a memory array implemented using storage medium 103). The user data and ECC data are written to the memory location in a single write operation or read from the memory location in a single read operation. The error correction code is implemented by a controller or other processing device of the flash memory device.

[0047] In one example, the error correction code generates parity bits that are stored with the user data. In various examples, the error correction code can be based on a Hamming coding scheme, a Reed-Solomon coding scheme, a Turbo coding scheme, or a Low Density Parity Check (LDPC) coding scheme.

[0048] In one embodiment, data recovery as described above may be implemented by a system (e.g., a host device or memory controller) that manages data recovery at the system level. For example, the system identifies corrupted data and determines whether to initiate a data recovery process (e.g., if the number of errors detected in a codeword exceeds a threshold determined by the host device or controller).

[0049] In one example, a system implementing data recovery uses Compute Express Link (CXL) for communication between a host device or controller and a memory device (e.g., memory device 101) in which data is stored. For example, Compute Express Link (CXL) is an interconnect that provides high-speed central processing unit (CPU)-to-device and CPU-to-memory communication (e.g., to accelerate data center performance). CXL is built on the PCI Express (PCIe) physical and electrical interface and has three protocol aspects: input / output (I / O), memory, and cache coherency.

[0050] In one embodiment, other systems that can be used to implement the data recovery described above include a host system attached to a memory subsystem (e.g., memory device 101) using an interconnect. For example, the Cache Coherent Interconnect for Accelerators (CCIX) standard describes a suitable type of interconnect that enables hardware accelerators and processors to maintain cache coherence across shared memory in heterogeneous multiprocessor systems. For example, the CCIX interface supports a coherent interconnect between general-purpose processors and acceleration devices to enable heterogeneous computing. CCIX supports interconnects focused on accelerating applications such as machine learning, network processing, storage offload, in-memory databases, and 4G / 5G wireless technologies.

[0051] For example, the CCIX interconnect allows processors based on different instruction set architectures to extend the benefits of cache coherence and peer processing to many acceleration devices, including FPGAs, GPUs, network / storage adapters, intelligent networks, and custom ASICs.

[0052] Figure 2 An example of correcting data to recover from data errors stored in memory according to some embodiments is shown. In the example shown, correct data initially written to the memory (e.g., at a time prior to receiving a read command from a host device) is shown as data 200. In one example, data 200 is correct data previously written to storage medium 103 of memory device 101 in response to a write command previously received from host device 127.

[0053] In an initial step, data is read from memory (e.g., in response to a read command from host device 127 or processing device 121). The data contains one or more errors. For example, the logic values of bits 201 and 203 are incorrect when compared to correct data 200. In one example, these errors in the read data are determined as discussed above. The data read from memory is saved (e.g., stored in buffer 151 or 152).

[0054] As discussed above, as shown, a first data pattern is selected. This data pattern is written to the memory. Then, the data pattern is read from the memory. In the example shown, the written data pattern and the read data pattern are identical. Therefore, no stuck bits are identified.

[0055] In response to failing to identify any stuck bits using the first data pattern, a second data pattern is selected, such as described above. As shown, the second data pattern is the inverse of the first data pattern.

[0056] The second data pattern is written to the memory, such as discussed above. The second data pattern is then read from the memory. Based on reading the second data pattern, a stuck bit 205 is identified, including the bit position of the stuck bit in the memory.

[0057] Identification of stuck bit 205 is used to flip a bit in the stored read data (e.g., a codeword read from memory and stored in buffer 151 or 152). For example, the logic value of the bit at the identified bit position in the read data is inverted, as shown.

[0058] Correct other bit errors in the data read from the memory. For example, bit 207 is corrected to match data 200. In one example, bit 207 and other bits are corrected using an error correction code (e.g., using error correction 123 or 141 based on ECC data 117 or 119).

[0059] After correcting the stuck bits and other bits in the read data, corrected data is provided that can be further used by the computer system. For example, the corrected data can be sent to a host (e.g., host device 127 or processing device 121). For example, the corrected data can be written additionally and / or alternatively to the same location in the memory from which the read data was initially obtained.

[0060] In one embodiment, a data recovery manager is implemented by a computing system to correct more bits than can be corrected by an error correction code used by the computing system.The computing system accepts out-of-order memory requests.

[0061] Figure 3A system for implementing data recovery of a memory of a storage device 301 based on an operating environment according to some embodiments is shown. Storage device 301 includes memory 303, where data is stored at respective addresses 304 and 306. For example, data is stored at address 304 of memory row 305. ECC data 317 is stored in memory row 305 along with corresponding user data. Similarly, data is stored at address 306 of memory row 307. ECC data 319 is stored in memory row 307 along with corresponding user data. In one example, storage device 301 is an example of memory device 101.

[0062] In one example, the addresses 304 , 306 are physical addresses of the memory array. In one example, the physical addresses 304 , 306 correspond to logical addresses of data pages stored in the page map 138 and managed by the MMU 136 .

[0063] Controller 321 executes a data recovery management process (e.g., using a data recovery manager in firmware stored in the memory of storage device 301) to detect errors in the data stored in memory 303 and correct one or more of the identified errors. Some errors are corrected by ECC decoder 323 using ECC data 317, 319. In some cases, the number of errors in the data read from memory 303 exceeds the error correction capability of ECC decoder 323. In response to determining that the number of errors exceeds the error correction capability, one or more data patterns can be selected and written to memory 303, such as discussed above. Reading these data patterns can be used to identify and correct, for example, stuck bits in memory rows 305, 307.

[0064] Host device 327 communicates with storage device 301, for example, via a serial bus or other interconnect (e.g., a CXL or CCIX interconnect). Host device 327 is an example of host device 127. In some cases, data recovery management is controlled by host device 327, instead of and / or in addition to controller 321. As part of data recovery, host device 327 detects errors using error detection 341 (e.g., parity check, CRC, hash value comparison, etc.). In addition, host device 327 corrects some errors using error correction 341 (e.g., ECC1 or ECC3).

[0065] As mentioned above, in response to detecting one or more errors in the read data, one or more data patterns are selected. In some embodiments, each respective data pattern is selected based on the operating environment of the storage device 301, the host device 327, and / or another system that uses data from the storage device 301. The environment at the time of selection determines the mode.

[0066] Memory device 301 includes a temperature sensor 351, a counter 353, and an artificial neural network 355. Temperature sensor 351 provides sensor data regarding the temperature associated with memory 303 to controller 321. Controller 321 may use the sensor data to select a data pattern to write to memory 303.

[0067] Counter 353 can be used to record activity associated with various locations and / or memory cells in memory 303. For example, counter 353 can record programming cycles performed for each of several corresponding blocks in a flash memory device. When selecting a data pattern for writing to a location in memory 303, the value of counter 353 associated with that location can be used to select the data pattern. For example, counter 353 can indicate extensive programming of a block. The data pattern for writing to that block is selected based on the value of counter 353 corresponding to that block.

[0068] In one embodiment, the output of an artificial neural network (ANN) 355 may be used by controller 321 to select a data pattern. Inputs to ANN 355 may include operating characteristics and / or history associated with memory 303. Other inputs may include sensor data from temperature sensor 351 and / or a value from counter 353. In one embodiment, inputs to ANN 355 may include the age of storage device 301.

[0069] In one embodiment, host device 327 includes sensor 359 and / or ANN 357. For example, sensor 359 may be a temperature sensor or another type of sensor. Host device 327 may use the output of ANN 357 to select a data pattern to be written to memory 303. The data from sensor 359 may be an input to ANN 357. In one example, the input to ANN 357 may also include one or more of the inputs described above for ANN 355. In one example, host device 327 executes software to implement a data recovery manager that uses the output of ANN 357 to select a data pattern to be written to memory 303 as part of correcting errors caused by stuck bits, such as described above.

[0070] In some embodiments, additionally and / or alternatively, characteristics associated with the write data pattern and / or the read data pattern are altered. In one example, the timing associated with the read data pattern is altered. In one case, a read operation for reading the data pattern is performed more slowly than a read operation normally performed for reading the data. In one example, the codeword is read from the memory array using a first access time associated with a normal operating mode. However, the data pattern used to detect the fault bit is read using a different operating mode in which the read access time is longer (e.g., the read operation is slower).

[0071] Figure 4 Methods for correcting data errors stored in a memory by using one or more data patterns are shown according to some embodiments. For example, Figure 4 The method can be Figure 1 In one example, the memory is a phase change memory or a flash memory.

[0072] Figure 4 The method may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, Figure 4 The method is at least partially performed by one or more processing devices (e.g., Figure 1 Executed by the processing device 121 or host device 127).

[0073] Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise indicated. Therefore, the illustrated embodiments should be understood to be illustrative only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processing flows are also possible.

[0074] At block 401 , data is read from a location in memory. In one example, data is read from address 304 of memory 303 .

[0075] At block 403 , the data read from the memory is stored in a buffer or otherwise saved for subsequent use. In one example, the read data is stored in buffers 151 and / or 152 .

[0076] At block 405, one or more errors are detected in data read from the memory. In one example, four bit errors are detected in a read codeword by implementing a memory device that can only correct up to three bit errors.

[0077] At block 407, in response to detecting an error, one or more data patterns are selected and written to the memory location from which the data was read. In one example, the memory controller or host device determines that the number of bit errors detected exceeds the error correction capability. In response, the controller or host device selects and writes a first data pattern, such as described above. Based on reading the first data pattern and / or the circumstances determined (e.g., using ANN 355), the controller or host device selects and writes a second data pattern.

[0078] At block 409, the one or more data patterns are read from the location in memory.In one example, a first data pattern is read from storage medium 103, followed by a second data pattern, such as described above.

[0079] At block 411 , one or more fail bits are identified in one or more of the data patterns (eg, based on reading the second data pattern). In one example, the fail bits are stuck bits corresponding to defective cells in the memory cells 105 of the storage medium 103 .

[0080] At block 413, in response to identifying the one or more failed bits, the data stored in the buffer (or otherwise held) is corrected. In one example, the corrected data is sent to the host device whose read command was received by the memory. In one example, the corrected data is additionally written to the location in the memory so that it is available for future use (e.g., future read commands for the same data).

[0081] In one embodiment, a system includes: at least one memory configured to store data in a memory unit (e.g., 105, 107); a buffer (e.g., 151, 152) configured to store data read from the memory unit; and at least one processing device (e.g., controller 321, or a processor of host device 127) configured to: read first data from a location (e.g., address 304, 306) in the memory; store the first data in the buffer; detect one or more errors in the first data; and in response to detecting an error in the first data, convert a data pattern (e.g., Figure 2 The invention relates to a method for storing a first data pattern (a first or second data pattern shown in FIG) in a memory to the location in the memory; reading the data pattern from the location in the memory; identifying at least one failed bit (e.g., a stuck bit) in the read data pattern; and in response to identifying the failed bit, correcting the identified failed bit in the stored first data to provide corrected data.

[0082] In one embodiment, the first data is read in response to receiving a read command from a host device (eg, 127), and the processing device is further configured to send the corrected data to the host device as a reply to the read command.

[0083] In one embodiment, the errors detected in the first data include an error caused by a failed bit, and at least one other bit error; and the processing device is further configured to correct the other bit error using an error correction code before sending the corrected data to the host device.

[0084] In one embodiment, detecting an error in the first data includes detecting the error using an error correction code (e.g., ECC implemented by Error Correction 123, 141, or Error Correction 341), and determining that the detected error exceeds a correction capability of the error correction code; and the processing device is further configured to write the corrected data to the location in the memory.

[0085] In one embodiment, the system further includes an error correction code (ECC) decoder (eg, 323), wherein the ECC decoder is configured to detect errors in the first data.

[0086] In one embodiment, the identified faulty bit is a stuck bit, and the processing device is further configured to: determine a bit position of the stuck bit in the read data pattern; determine a state of the stuck bit in the read data pattern; determine a state of a bit at the bit position in the first data; and determine that the state of the stuck bit in the read data pattern (e.g., the bit value is a logic zero) matches the state of the bit in the first data.

[0087] In one embodiment, the failed bit is a stuck bit caused by a defective one of the memory cells from which the first data is read.

[0088] In one embodiment, the system further includes at least one sensor (e.g., temperature sensor 351 and / or sensor 359), wherein the processing device is further configured to: receive sensor data from the sensor; and select a data pattern for writing to the location in the memory based on the sensor data.

[0089] In one embodiment, the processing device is further configured to change the timing of at least one of the write data pattern or the read data pattern in response to detecting an error in the first data (e.g., read the data pattern using a slower read operation mode, where the read operation is performed slower than a normal mode of reading data from the memory).

[0090] Figure 5 Methods for correcting errors in stored data based on sensor data and / or output of an artificial neural network are shown according to some embodiments. For example, Figure 5 The method can be Figure 3 In one example, the memory is a storage device 301 for an autonomous vehicle. The data stored in the memory 303 (e.g., one or more non-volatile memory dies) is used by the host device 327 to control navigation and motor or engine functions of the vehicle.

[0091] Figure 5The method may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, Figure 5 The method is at least partially performed by one or more processing devices (e.g., Figure 3 Controller 321) executes.

[0092] Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise indicated. Therefore, the illustrated embodiments should be understood to be illustrative only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processing flows are also possible.

[0093] At block 501, sensor data is received from one or more sensors. In one example, the sensor data is received by the controller 321 from the temperature sensor 351. The sensor data is used to determine a temperature associated with the memory 303.

[0094] At block 503, output is received from an artificial neural network (ANN). In one example, controller 321 receives data from one or more sensors of storage device 301, sensors of host device 327, and / or sensors of a system controlled by host device 327 (e.g., an autonomous vehicle). The data received by controller 321 serves as input to an ANN (e.g., ANN 355). Other inputs to the ANN may include a value from counter 353 and / or the lifetime (e.g., service time) of storage device 301 or the usage time of respective portions of the storage media of memory 303 (e.g., storage media of different types of dies).

[0095] At block 505, an error is detected in data read from the memory. In response to detecting the error, a data pattern is selected. The data pattern is selected based on the sensor data and / or the output of the ANN. In one example, the data pattern is selected to correspond to the type of storage medium (e.g., the type of material used to store data in the memory cells of the storage medium). In another example, the data pattern is selected to correspond to the lifetime or range of use of the storage medium.

[0096] The selected data pattern is written to the memory at block 507. In one example, the data pattern is written to the same address in the memory from which the data in which the error was detected was read.

[0097] At block 509, a data pattern is read from a memory. In one example, one or more stuck bits are identified in the read data pattern. The bit positions of the stuck bits are identified.

[0098] At block 511, errors in data read from the memory are corrected based on a data pattern read from the memory. In one example, the identified bit position is used to correct a corresponding bit at the same bit position in the read data.

[0099] In one embodiment, a non-transitory computer-readable medium stores instructions that, when executed on at least one processing device, cause the at least one processing device to, in response to receiving a read command from a host device (e.g., 327), perform the following operations: read data from a memory (e.g., memory 303 or storage medium 103); detect an error in the read data; in response to detecting the error, write at least one data pattern to the memory; read the data pattern from the memory; identify at least one stuck-bit based on the read data pattern; in response to identifying the stuck-bit, correct the read data to provide corrected data; and send the corrected data to the host device.

[0100] In one embodiment, the instructions further cause the at least one processing device to perform the following operations: determine the lifetime or usage range of the memory based on at least one of the output of the counter or the artificial neural network (e.g., 355) (e.g., determined based on the value read from the counter 353 by the controller 321 for the corresponding portion of the memory where the test data pattern is to be written); and select the data pattern for writing to the memory based on the determined lifetime or usage range.

[0101] In one embodiment, a method includes: reading data from a location in a memory; detecting an error in the read data; in response to detecting the error, writing at least one data pattern to the location in the memory; reading the data pattern from the location in the memory; identifying at least one bit error based on the read data pattern; and in response to identifying the bit error, correcting the bit error in the read data to provide corrected data.

[0102] In one embodiment, the method further includes writing the corrected data to the location in memory.

[0103] In one embodiment, the corrected data includes one or more other bit errors, the method further including correcting the other bit errors before writing the corrected data.

[0104] In one embodiment, the identified bit errors in the read data pattern are stuck bits, and the other bit errors are corrected using error correction code (ECC).

[0105] In one embodiment, the read data is included in a page of data read from the memory, and the method further includes changing a mapping of the page (eg, page map 138) or reclaiming the page in response to identifying the bit error.

[0106] In one embodiment, the memory is included in a memory device; and writing the data pattern is further responsive to determining that a number of failed bits in the read data exceeds an error correction capability of the memory device.

[0107] In one embodiment, data is read from the location in memory in response to receiving a read command from a host device, and the method further includes sending the corrected data to the host device in reply to the read command.

[0108] In one embodiment, writing a data pattern includes writing a first pattern and writing a second pattern; reading a data pattern includes reading a first pattern and reading a second pattern; writing the second pattern is performed in response to determining that the read first pattern does not include a bit error; and identifying the bit error is based on reading the second pattern.

[0109] In one embodiment, the second mode is the opposite of the first mode.

[0110] Figure 6 An example computing system 700 including a memory subsystem 710 according to some embodiments of the present disclosure is illustrated. Memory subsystem 710 may include media such as one or more volatile memory devices (e.g., memory device 702), one or more non-volatile memory devices (e.g., memory device 704), or a combination thereof. Memory device 101 and storage device 301 are examples of memory subsystem 710, and host devices 127 and 327 are examples of host system 720. Controller 715 is an example of controller 321 or host device 327.

[0111] The memory subsystem 710 can be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0112] The computing system 700 may be, for example, a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0113] Computing system 700 may include a host system 720 coupled to one or more memory subsystems 710 . Figure 6 An example of a host system 720 coupled to a memory subsystem 710 is illustrated.

[0114] The host system 720 may include a processor chipset (e.g., processing device 718) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 716) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 720 uses the memory subsystem 710, for example, to write data to the memory subsystem 710 and read data from the memory subsystem 710.

[0115] The host system 720 can be coupled to the memory subsystem 710 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 720 and the memory subsystem 710. When the memory subsystem 710 is coupled to the host system 720 via a PCIe interface, the host system 720 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 704). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 710 and the host system 720 . Figure 6 Memory subsystem 710 is illustrated as an example. In general, host system 720 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0116] The processing device 718 of the host system 720 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some cases, the controller 716 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 716 controls communications via a bus coupled between the host system 720 and the memory subsystem 710. Generally speaking, the controller 716 may send commands or requests to the memory subsystem 710 for desired access to the memory devices 702, 704. The controller 716 may further include interface circuitry for communicating with the memory subsystem 710. The interface circuitry may convert responses received from the memory subsystem 710 into information for the host system 720.

[0117] The controller 716 of the host system 720 can communicate with the controller 715 of the memory subsystem 710 to perform operations such as reading, writing, or erasing data at the memory devices 702 and 704, and other such operations. In some cases, the controller 716 is integrated into the same package as the processing device 718. In other cases, the controller 716 is separate from the package of the processing device 718. The controller 716 and / or the processing device 718 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 716 and / or the processing device 718 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0118] Memory devices 702 and 704 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices (e.g., memory device 702) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0119] Some examples of non-volatile memory components include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to store bits based on changes in bulk resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0120] Each of the memory devices 704 may include one or more memory cell arrays (e.g., memory cells 105, 107). One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 704 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 704 may be grouped into pages, which may refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0121] Although non-volatile memory devices such as 3D cross-point and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device 704 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0122] The memory subsystem controller 715 (or simply controller 715) can communicate with the memory device 704 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 704 (e.g., in response to commands dispatched by the controller 716 on a command bus). The controller 715 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 715 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0123] The controller 715 may include a processing device 717 (processor) configured to execute instructions stored in a local memory 719. In the illustrated example, the local memory 719 of the controller 715 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 710, including handling communications between the memory subsystem 710 and the host system 720.

[0124] In some embodiments, local memory 719 may include memory registers that store memory pointers, fetched data, etc. Local memory 719 may also include read-only memory (ROM) for storing microcode. Figure 6 The example memory subsystem 710 in FIG. 7 has been illustrated as including a controller 715, but in another embodiment of the present disclosure, the memory subsystem 710 does not include a controller 715, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0125] In general, the controller 715 may receive commands or operations from the host system 720 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 704. The controller 715 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 704.

[0126] Controller 715 may further include host interface circuitry to communicate with host system 720 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access memory device 704, and convert responses associated with memory device 704 into information for host system 720.

[0127] The memory subsystem 710 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 710 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that receive addresses from the controller 715 and decode the addresses to access the memory device 704.

[0128] In some embodiments, memory device 704 includes a local media controller 705 that operates in conjunction with a memory subsystem controller 715 to perform operations on one or more memory cells of memory device 704. An external controller (e.g., memory subsystem controller 715) can externally manage memory device 704 (e.g., perform media management operations on memory device 704). In some embodiments, memory device 704 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 705) within the same memory device package that performs media management. An example of a managed memory device is a managed NAND (MNAND) device.

[0129] In one embodiment, computer system 700 includes a memory subsystem 710 that corrects data read from memory (e.g., as directed to Figure 4 5). In some embodiments, the controller 715 in the memory subsystem 710 includes at least a portion of the data recovery manager 714. In other embodiments, or in combination, the controller 716 and / or the processing device 718 in the host system 720 include at least a portion of the data recovery manager 714. For example, the controller 715, the controller 716, and / or the processing device 718 may include logic circuitry that implements the data recovery manager 714. For example, the controller 715 or the processing device 718 (processor) of the host system 720 may be configured to execute instructions stored in memory for performing the operations of the data recovery manager 714.

[0130] In some embodiments, data recovery manager 714 is implemented in an integrated circuit chip disposed in memory subsystem 710. In other embodiments, data recovery manager 714 is part of the host system 720's operating system, device driver, or application.

[0131] In some embodiments, the communication channel between the processing device 718 and the memory subsystem 710 includes a computer network, such as a local area network, a wireless local area network, a wireless personal area network, a cellular communication network, a broadband high-speed always-connected wireless communication connection (e.g., a mobile network link); and the processing device 718 and the memory subsystem can be configured to communicate with each other using data storage management and usage commands similar to those in the NVMe protocol.

[0132] The memory subsystem 710 may typically include non-volatile storage media. Examples of non-volatile storage media include memory cells formed in integrated circuits and magnetic materials coated on rigid magnetic disks. Non-volatile storage media can maintain the data / information stored therein without consuming power. Memory cells can be implemented using various memory / storage technologies, such as NAND logic gates, NOR logic gates, phase change memory (PCM), magnetic random access memory (MRAM), resistive random access memory, cross-point memory, and memory devices. Cross-point memory devices use transistor-free memory elements, each of which has memory cells and selectors stacked together in columns. The columns of memory elements are connected via two perpendicular layers of wires, one above the columns of memory elements and the other below them. Each memory element can be individually selected at the intersection of a wire on each of the two layers. Cross-point memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

[0133] A controller (eg, 715) of a memory subsystem (eg, 710) may execute firmware to operate in response to communications from processing device 718. Generally speaking, firmware is a type of computer program that provides control, monitoring, and data manipulation for an engineered computing device.

[0134] Some embodiments involving the operation of controller 715 may be implemented using computer instructions executed by controller 715, such as firmware for controller 715. In some cases, hardware circuitry may be used to implement at least some of the functionality. The firmware may be initially stored in a non-volatile storage medium or another non-volatile device and loaded into volatile DRAM and / or intra-processor cache memory for execution by controller 715.

[0135] Non-transitory computer-readable media may be used to store instructions for firmware of a memory subsystem (eg, 710). When the instructions are executed by the controller 715 and / or the processing device 717, the instructions cause the controller 715 and / or the processing device 717 to perform the methods discussed herein.

[0136] In one embodiment, a method (eg, implemented in memory subsystem 710) manages the process for correcting stuck-bit errors in stored data (eg, as described for Figure 1-3 The method may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method is performed at least in part by Figure 6For example, the method may be executed by the data recovery manager 714. For example, the method may be executed to recover data stored in a memory unit 105 or 107 (e.g., one or more media units such as an integrated circuit die) and then retrieved from the memory unit 105, 107 that was then found to contain an error (e.g., due to a failed bit).

[0137] Figure 7 An example machine illustrating a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 6 720) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 6 Memory subsystem 710) or may be used to perform operations of data recovery manager 714 (e.g., execute instructions to perform operations corresponding to reference Figure 6 In one example, computer system 600 corresponds to host system 127 or 327.

[0138] In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud-based computing infrastructure or environment.

[0139] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0140] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630 (which may include multiple buses).

[0141] In various embodiments, processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating via a network 620.

[0142] The data storage system 618 may include a machine-readable storage medium 624 (also referred to herein as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, with the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 6 In one embodiment, the instructions 626 include instructions for implementing a multi-level parity protection corresponding to, for example, multiple levels of parity protection and by a data recovery manager (e.g., reference Figure 6 The described data recovery manager 714) further supports instructions for functionality to correct errors caused by stuck bits.

[0143] The present disclosure includes various apparatuses that perform the methods and implement the systems described above, including data processing systems that perform the methods, and computer-readable media containing instructions that, when executed on the data processing systems, cause the systems to perform the methods.

[0144] The description and drawings are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details are not described to avoid obscuring the description. References to one or more embodiments in this disclosure are not necessarily references to the same embodiment; such references mean at least one embodiment.

[0145] As used herein, “coupled to” or “coupled with…” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0146] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The appearance of the phrase "in one embodiment" in various places in this specification does not necessarily refer to the same embodiment, nor does it necessarily refer to separate or alternative embodiments that are mutually exclusive of other embodiments. In addition, various features may be described that may be exhibited by some embodiments but not by others. Similarly, various requirements may be described that may be requirements for some embodiments but not for others.

[0147] In this specification, various functions and / or operations may be described as being performed by software code or caused by software code to simplify the description. However, those skilled in the art will recognize that this expression means that the functions and / or operations are caused by one or more processing devices executing the code, such as a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit, and / or a field programmable gate array (FPGA). Alternatively or in combination, dedicated circuits (e.g., logic circuits) may be used to implement functions and operations with or without software instructions. Embodiments may be implemented using hard-wired circuits or in combination with software instructions without software instructions. Therefore, the technology is neither limited to any particular combination of hardware circuits and software, nor to any particular source of instructions executed by a computing device.

[0148] While some embodiments may be implemented in fully functional computers and computer systems, various embodiments are capable of being distributed as computing products in various forms and are applicable regardless of the specific type of computer-readable media that actually implements the distribution.

[0149] At least some aspects of the disclosure may be embodied, at least in part, in software. That is, the techniques may be performed on a computing device or another system in response to a processing device (e.g., a microprocessor) thereof executing sequences of instructions contained in a memory (e.g., ROM, volatile RAM, non-volatile memory, cache, or remote storage device).

[0150] The routines executed to implement the embodiments may be implemented as part of an operating system, middleware, a service delivery platform, a software development kit (SDK) component, a network service, or other specific application, component, program, object, module, or sequence of instructions (sometimes referred to as a computer program). The calling interface for these routines may be exposed to the software development community as an application programming interface (API). A computer program typically includes one or more sets of instructions stored in various memories and storage devices in a computer at various times, and when the set of instructions is read and executed by one or more processors in the computer, causes the computer to perform the necessary operations to perform the elements involved in various aspects.

[0151] Computer-readable media can be used to store software and data that, when executed by a processing device or computing device, causes the device to perform various methods. Executable software and data can be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. Portions of this software and / or data can be stored in any of these storage devices. In addition, data and instructions can be obtained from a centralized server or peer-to-peer network. Different portions of data and instructions can be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions or within the same communication session. All data and instructions can be obtained before executing the application. Alternatively, portions of data and instructions can be obtained dynamically and in a timely manner as needed for execution. Therefore, it is not required that all data and instructions be on computer-readable media at a particular moment in time.

[0152] As used herein, the term "computer-readable medium" and the like includes a single medium or multiple media that store one or more sets of instructions. Examples of computer-readable media include, but are not limited to, recordable and non-recordable types of media, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, magnetic disk storage media, optical storage media (e.g., compact disk read-only memory (CD ROM), digital versatile disks (DVD), etc.), and others. Computer-readable media can store instructions. Other examples of computer-readable media include, but are not limited to, non-volatile embedded devices using NOR flash or NAND flash architectures. Media used in these architectures can include unmanaged NAND devices and / or managed NAND devices, including, for example, eMMC, SD, CF, UFS, and SSD.

[0153] Generally speaking, non-transitory computer-readable media includes any mechanism that provides (e.g., stores) information in a form accessible by a computing device (e.g., a computer, a mobile device, a network device, a personal digital assistant, a manufacturing tool with a controller, any device with a set of one or more processors, etc.).

[0154] In various embodiments, hard-wired circuitry may be used in combination with software and firmware instructions to implement the technology. Thus, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source for the instructions executed by the computing device.

[0155] The various embodiments described herein may be implemented using a wide variety of different types of computing devices. As used herein, examples of a "computing device" include, but are not limited to, a server, a centralized computing platform, a system of multiple computing processors and / or components, a mobile device, a user terminal, a vehicle, a personal communication device, a wearable digital device, an electronic self-service kiosk, a general-purpose computer, an electronic document reader, a tablet computer, a laptop computer, a smartphone, a digital camera, a residential home appliance, a television, or a digital music player.

[0156] Additional examples of computing devices include those that are part of what is known as the "Internet of Things" (IoT). Such "things" may occasionally interact with their owners or administrators, who may monitor them or modify settings related to them. In some cases, such owners or administrators act as users with respect to the "thing" devices. In some examples, a user's primary mobile device (e.g., an Apple iPhone) may be an administrator server with respect to a paired "thing" device (e.g., an Apple Watch) worn by the user.

[0157] In some embodiments, the computing device can be a computer or host system, which is implemented as, for example, a desktop computer, a laptop computer, a network server, a mobile device, or other computing device that includes a memory and a processing device. The host system can include or be coupled to a memory subsystem so that the host system can read data from the memory subsystem or write data to the memory subsystem. The host system can be coupled to the memory subsystem via a physical host interface. Generally speaking, the host system can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0158] In some embodiments, the computing device is a system including one or more processing devices. Examples of a processing device may include a microcontroller, a central processing unit (CPU), a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), a system on a chip (SoC), or another suitable processor.

[0159] In one example, the computing device is a controller of a memory system. The controller includes a processing device and a memory containing instructions that are executed by the processing device to control various operations of the memory system.

[0160] Although some of the figures illustrate multiple operations in a particular order, non-sequence dependent operations may be reordered and other operations may be combined or decomposed. While some reordering or other groupings are specifically mentioned, other reorderings or groupings will be apparent to those skilled in the art, and thus, no exhaustive list of alternatives is provided. Furthermore, it should be appreciated that the stages may be implemented in hardware, firmware, software, or any combination thereof.

[0161] In the foregoing description, the present disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: at least one memory configured to store data in the memory unit; a buffer configured to store data read from the memory cell; as well as at least one processing device configured to: Reading first data from a location in the memory; storing the first data in the buffer; detecting one or more errors in the first data; writing a data pattern to the location in the memory in response to detecting an error in the first data; reading the data pattern from the location in the memory; identifying at least one failed bit in the read data pattern; as well as In response to identifying the failed bit, the identified failed bit in the stored first data is corrected to provide corrected data. 2 . The system of claim 1 , wherein the first data is read in response to receiving a read command from a host device, and the processing device is further configured to send the corrected data to the host device as a reply to the read command.

3. The system of claim 2, wherein: the errors detected in the first data include an error caused by the failed bit and at least one other bit error; and The processing device is further configured to correct the other bit errors using an error correction code before sending the corrected data to the host device.

4. The system of claim 1 , wherein: detecting the error in the first data includes detecting the error using an error correction code, and determining that the detected error exceeds a correction capability of the error correction code; and The processing device is further configured to write the corrected data to the location in the memory.

5. The system of claim 1, further comprising an error correction code (ECC) decoder, wherein the ECC decoder is configured to detect the error in the first data.

6. The system of claim 1 , wherein the identified faulty bit is a stuck bit, and the processing device is further configured to: determining a bit position of the stuck bit in the read data pattern; determining a state of the stuck bit in the read data pattern; determining a state of a bit at the bit position in the first data; and The state of the stuck bit in the read data pattern is determined to match the state of the bit in the first data.

7. The system of claim 1, wherein the failed bit is a stuck bit caused by a defective one of the memory cells from which the first data is read.

8. The system of claim 1 , further comprising at least one sensor, wherein the processing device is further configured to: receiving sensor data from the sensor; and Based on the sensor data, the data pattern is selected for writing to the location in the memory.

9. The system of claim 1, wherein the processing device is further configured to change a timing of at least one of writing the data pattern or reading the data pattern in response to detecting the error in the first data.

10. A method comprising: Read data from a location in memory; Detect errors in read data; responsive to detecting the error, writing at least one data pattern to the location in the memory; reading the data pattern from the location in the memory; identifying at least one bit error based on reading the data pattern; as well as In response to identifying the bit error, the bit error in the read data is corrected to provide corrected data. The method of claim 10 , further comprising writing the corrected data to the location in the memory.

12. The method of claim 11, wherein the corrected data includes one or more other bit errors, the method further comprising correcting the other bit errors before writing the corrected data.

13. The method of claim 12, wherein the identified bit error in the read data pattern is a stuck bit, and the other bit errors are corrected using an error correction code (ECC).

14. The method of claim 10, wherein the read data is contained in a data page read from the memory, the method further comprising: In response to identifying the bit error, a mapping of the page is changed or the page is evicted.

15. The method of claim 10, wherein: The memory is contained in a memory device; and Writing the data pattern is further responsive to determining that a number of failed bits in the read data exceeds an error correction capability of the memory device.

16. The method of claim 10, wherein the data is read from the location in the memory in response to receiving a read command from a host device, the method further comprising sending the corrected data to the host device as a reply to the read command.

17. The method of claim 10, wherein: Writing the data pattern includes writing a first pattern and writing a second pattern; Reading the data pattern includes reading the first pattern and reading the second pattern; Writing the second pattern is performed in response to determining that the read first pattern contains no bit errors; and Identifying the bit error is based on reading the second pattern. The method of claim 17 , wherein the second mode is opposite to the first mode.

19. A non-transitory computer-readable medium storing instructions that, when executed on at least one processing device, cause the at least one processing device to, in response to receiving a read command from a host device, perform the following operations: Read data from memory; Detect errors in read data; writing at least one data pattern to the memory in response to detecting the error; reading the data pattern from the memory; identifying at least one stuck bit based on reading the data pattern; in response to identifying the stuck bit, correcting the read data to provide corrected data; as well as The corrected data is sent to the host device.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions further cause the at least one processing device to: determining a usage period or a usage range of the memory based on at least one of a counter or an output of an artificial neural network; and Based on the determined usage period or usage range, the data pattern is selected for writing to the memory.

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