Electronic packaging and method of manufacturing the same

Abstract

The present invention relates to an electronic package and a method for manufacturing the same, comprising a coating layer, at least one electronic intermediate block embedded in the coating layer and having a plurality of conductive through holes, a plurality of conductive pillars embedded in the coating layer, and at least one electronic component arranged on the coating layer, so as to improve the reliability of the electronic package by separating the conductive pillars from the electronic component.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to an electronic package and a manufacturing method thereof. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multi-function and high-performance trends. For example, integrated voltage regulators (IVRs) are embedded in high-performance processors to improve efficiency, such as switching frequency, reduce power consumption, and improve reliability and even reduce manufacturing costs. In addition, the technologies currently used in the field of chip packaging include flip-chip packaging modules such as chip scale package (CSP), direct chip attached package (DCA) or multi-chip module package (MCM).

[0003] In addition, as the electrical functions of terminal products are becoming more and more advanced, the number of semiconductor chips connected to the Through Silicon Interposer (TSI) is increasing, making the bonding area of ​​the silicon interposer larger and larger. As a result, the number of Through-silicon vias (TSV) of the silicon interposer is also increasing, resulting in various process defects and a decrease in the yield of the packaging structure.

[0004] The industry then cuts a single silicon interposer into multiple smaller silicon interposers to reduce the difficulty of the manufacturing process.

[0005] Figures 1A to 1D It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package structure 1 .

[0006] like Figure 1A As shown, a semiconductor element 10, such as a logic chip, is first disposed on a release layer 90 of a carrier board 9, and then a circuit portion 18 is formed on the semiconductor element 10, and the circuit portion 18 includes a plurality of insulating layers 180 and a plurality of redistribution layers (RDL) 181, and a plurality of copper bumps 19 are formed on the redistribution layers 181. Next, a conductive seed layer 130 is formed on the circuit portion 18, so that a plurality of copper pillars 13 are electroplated on the redistribution layer 181 through the conductive seed layer 130.

[0007] like Figure 1BAs shown, the conductive seed layer 130 not covered by the copper pillar 13 is removed, and then a plurality of silicon interposers 11 with conductive through holes 110 are fixed on the circuit portion 18 via the conductor 12 and the underfill 14, and the conductive through holes 110 are electrically connected to the copper bump 19 via the conductor 12. Then, the encapsulation layer 15 is used to encapsulate the silicon interposers 11, the underfill 14 and the copper pillars 13.

[0008] like Figure 1C As shown, a flattening process is performed to remove part of the material of the copper pillar 13 , part of the material of the silicon interposer 11 and part of the material of the cladding layer 15 by grinding, so that the end surface of the copper pillar 13 and the end surface of the conductive through-hole 110 are exposed on the surface 15 a of the cladding layer 15 .

[0009] like Figure 1D As shown, a circuit structure 16 is formed on the surface 15a of the cladding layer 15, and the circuit structure 16 electrically connects the copper pillars 13 and the conductive through-holes 110 of the silicon interposer 11. Afterwards, the carrier board 9 and the release layer 90 thereon are removed to expose the semiconductor device 10, and then a singulation process is performed.

[0010] In the above process, the conventional TSV is mainly replaced by a larger copper pillar 13 to reduce the conductive through-holes 110 which are difficult to manufacture. That is, only a small number of silicon interposers 11 are required instead of a large area conventional TSI, which is beneficial to reduce the production cost of the terminal product.

[0011] In subsequent manufacturing processes, the semiconductor package structure 1 may form a plurality of solder balls 17 on the circuit structure 16 to be connected to a package substrate (not shown) or a circuit board (not shown).

[0012] However, in the conventional method of manufacturing the semiconductor package structure 1, the copper pillar 13 of a larger size needs to be electroplated on the circuit portion 18 through the conductive seed layer 130. Therefore, during the electroplating process, Figure 1A As shown, the bottom copper material of the copper pillar 13 will be plated to the copper bump 19 adjacent to the copper pillar 13 through the conductive seed layer 130, so that when the conductive seed layer 130 outside the copper pillar 13 is removed, part of the copper material will connect the copper pillar 13 and the copper bump 19, thus causing a short circuit.

[0013] In addition, during the leveling process, if Figure 1CAs shown, since part of the material of the copper pillar 13 and part of the material of the silicon interposer 11 are ground at the same time, during the grinding process, the copper ions (or copper particles) of the copper pillar 13 with a larger end surface area will migrate (migration) to the end surface of the conductive through-hole 110 along with the grinding tool, resulting in that after the circuit structure 16 is formed, part of the copper ions (or copper particles) will conduct the copper pillar 13 and the conductive through-hole 110, thereby causing problems such as short circuit or leakage.

[0014] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem that needs to be overcome urgently in the industry. Summary of the invention

[0015] In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a manufacturing method thereof to improve product reliability.

[0016] The electronic package of the present invention comprises: a coating layer; at least one electronic intermediate block, which is embedded in the coating layer and has a plurality of conductive through-holes; a plurality of conductive pillars, which are embedded in the coating layer and have conductive blocks at the ends, wherein the width of the conductive blocks is smaller than the width of the conductive pillars; and at least one electronic component, which is arranged on the coating layer and the conductive blocks and electrically connects the conductive pillars and the conductive through-holes.

[0017] The present invention also provides a method for manufacturing an electronic package, comprising: providing at least one electronic component and a carrier board having a plurality of conductive pillars, wherein the conductive pillar has a conductive block at an end, and the width of the conductive block is smaller than the width of the conductive pillar; combining at least one electronic intermediate block on the electronic component to form an electronic structure, wherein the intermediate board has a plurality of conductive through-holes electrically connected to the electronic component; stacking the electronic structure on the carrier board via the plurality of conductive pillars so that the plurality of conductive pillars support the electronic component and the electronic component is electrically connected to the conductive block and the conductive through-holes, wherein the electronic intermediate block is located between the electronic component and the carrier board; forming a coating layer between the carrier board and the electronic component so that the coating layer covers the electronic intermediate block and the plurality of conductive pillars; and removing the carrier board.

[0018] In the aforementioned electronic package and its manufacturing method, the surface of the coating layer is flush with the surface of the electronic intermediate block.

[0019] In the aforementioned electronic packaging component and its manufacturing method, the surface of the coating layer is flush with the end surface of the conductive column.

[0020] In the aforementioned electronic packaging component and its manufacturing method, the conductive through hole is exposed on the surface of the coating layer.

[0021] In the aforementioned electronic packaging component and its manufacturing method, the end surface of the conductive column is exposed on the surface of the coating layer.

[0022] In the aforementioned electronic package and its manufacturing method, the electronic element is electrically connected to the conductive block and the conductive through-hole via a circuit portion.

[0023] In the aforementioned electronic package and the manufacturing method thereof, the electronic component has a plurality of conductive bumps, so that the plurality of conductive bumps are electrically connected to the conductive through-holes and / or the conductive block.

[0024] In the aforementioned electronic package and its manufacturing method, the electronic component is electrically connected to the conductive through-hole via a conductor, and the conductor is not connected to the conductive block.

[0025] The aforementioned electronic package and its manufacturing method further include forming a circuit structure on the coating layer, and the circuit structure electrically connects the conductive column and the conductive through hole.

[0026] The aforementioned electronic package and its manufacturing method further include a plurality of conductive elements formed on the coating layer, and the plurality of conductive elements electrically connect the conductive pillar and the conductive through hole.

[0027] As can be seen from the above, in the electronic package and the manufacturing method of the present invention, the conductive column is mainly made on the carrier board, and the conductive column does not need to be electroplated on the electronic component. Therefore, in the process of making the conductive column, the metal material making the conductive column will not be plated onto the electronic component. Therefore, after the conductive column is completed, the metal material of the conductive column will not connect the conductive column and the electronic component. Therefore, compared with the prior art, after the electronic structure of the present invention is stacked on the carrier board, the conductive column will not electrically conduct the conductive through-hole of the electronic intermediate block, thereby not causing a short circuit.

[0028] In addition, the manufacturing method of the present invention adopts a stacking method to combine the electronic structure and the conductive column to fill the coating layer between the carrier board and the electronic component, so as to cover the electronic intermediate block and the conductive columns. Therefore, after removing the carrier board, the surface of the coating layer is flush with the end face of the conductive column and the end face of the electronic intermediate block and the conductive through-hole. Therefore, compared with the prior art, the manufacturing method of the present invention does not need to perform a leveling process on the coating layer after forming the coating layer. Therefore, the copper ions (or copper particles) of the conductive column with a larger end surface area will not migrate to the end face of the conductive through-hole, thereby avoiding the problem that the copper ions (or copper particles) of the conductive column conduct the conductive column and the conductive through-hole after the circuit structure is formed, so as to effectively avoid problems such as short circuit or leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1A to 1D The figure is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor packaging structure.

[0030] Figures 2A to 2G It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.

[0031] Figure 2A 'For the corresponding Figure 2A Schematic cross-sectional view of other embodiments.

[0032] Figure 2H for Figure 2G A cross-sectional schematic diagram of the subsequent process.

[0033] Figure 2H 'for Figure 2H A cross-sectional schematic diagram of another embodiment of the present invention.

[0034] Description of Reference Numerals

[0035] 1:Semiconductor packaging structure

[0036] 10: Semiconductor components

[0037] 11: Silicon interposer

[0038] 110,210: Conductive perforation

[0039] 12,22: Conductor

[0040] 13: Copper Pillar

[0041] 130: conductive seed layer

[0042] 14: Primer

[0043] 15,25: Coating

[0044] 15a: Surface

[0045] 16,26: Line structure

[0046] 17: Solder ball

[0047] 18,28: Line Department

[0048] 180: Insulation layer

[0049] 181,261: Line redistribution layer

[0050] 19: Copper Bump

[0051] 2,2': Electronic packaging

[0052] 2a: Whole wafer

[0053] 2b: Electronic structure

[0054] 20: Electronic components

[0055] 20a: Action surface

[0056] 20b: Non-active surface

[0057] 200:Electrode pad

[0058] 21: Electronic intermediary block

[0059] 21a: First side

[0060] 21b: Second side

[0061] 210a: pad

[0062] 23: Conductive column

[0063] 23b: End face

[0064] 230: Conductive block

[0065] 24: Binding layer

[0066] 25a: First surface

[0067] 25b: Second surface

[0068] 260: Dielectric layer

[0069] 27: Conductive element

[0070] 28a: Circuit layer

[0071] 28b: Passivation layer

[0072] 28c: Insulation film

[0073] 280,280': Opening

[0074] 29,29': Conductive bump

[0075] 8: Wiring board

[0076] 9,9': Loading plate

[0077] 90,90': Release layer

[0078] 91': Adhesive layer

[0079] d1,d2: width

[0080] L, S: cutting path. DETAILED DESCRIPTION

[0081] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0082] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0083] Figures 2A to 2G It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing an electronic package 2 of the present invention.

[0084] like Figure 2A As shown, a full-panel wafer 2 a is provided, which includes a plurality of electronic components 20 arranged in an array, and a single electronic component 20 has a plurality of conductive bumps 29 .

[0085] In this embodiment, the electronic component 20 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the electronic component 20 is a semiconductor chip, such as a logic chip, which has an active surface 20a and an inactive surface 20b opposite to each other, and the active surface 20a has a plurality of electrode pads 200.

[0086] In addition, the electronic component 20 may form a circuit portion 28 on the active surface 20a, the circuit portion 28 including a plurality of passivation layers 28b and a plurality of circuit layers 28a disposed on the passivation layers 28b and electrically connected to each of the electrode pads 200, the outermost passivation layer 28b having a plurality of openings 280, 280' exposing a portion of the circuit layer 28a, so that the conductive bump 29 is disposed on the circuit layer 28a in a portion of the openings 280, so that the conductive bump 29 is electrically connected to the electrode pad 200. Alternatively, as Figure 2A As shown in FIG. 1 , the configuration of the circuit portion 28 can be omitted, so that the conductive bumps 29, 29' are directly disposed on all the electrode pads 200, and the conductive bumps 29, 29' are covered with an insulating film 28c to protect the conductive bumps 29, 29'.

[0087] In addition, the conductive bumps 29, 29' are spherical shapes such as conductive lines, solder balls, or pillars of metal materials such as copper pillars, solder bumps, or stud-shaped conductive parts made by a wire bonding machine, but are not limited to the above. Their materials can be welding metals such as titanium / copper, copper, gold, nano twin copper (Nano twin Cu) or other materials.

[0088] like Figure 2B As shown, continued Figure 2A In the manufacturing process, at least one electronic interposer 21 is disposed on the conductive bump 29 of the electronic component 20, and the electronic interposer 21 has a first side 21a and a second side 21b opposite to each other.

[0089] In the present embodiment, the electronic interposer 21 is a Through Silicon interposer (TSI) structure, which has a plurality of conductive through-holes 210 exposed on the first side 21a and the second side 21b, such as Through-silicon vias (TSV). For example, the conductive through-hole 210 has a pad 210a at the end of the first side 21a to electrically connect the electronic component 20 by bonding to the conductive bumps 29 via a plurality of conductors 22, wherein the pad 210a is a welding metal, such as copper, gold, nickel or other materials. Further, the conductors 22 can be coated with a bonding layer 24 such as a primer as required.

[0090] In addition, the other end surface of the conductive through hole 210 is exposed on the second side 21 b. For example, through a flattening process such as grinding, the surface of the second side 21 b of the electronic interposer 21 is made flush with the other end surface of the conductive through hole 210.

[0091] In addition, the conductor 22 is a soldering metal, such as titanium / copper, copper, gold, nickel, tin-silver (SnAg) or other solder materials, to solder the pad 210a and the conductive bump 29. For example, the conductor 22 can be first formed on the pad 210a of the electronic interposer 21 on the first side 21a; or, the conductor 22 can also be first formed on the conductive bump 29, such as Figure 2A ', the electronic interposer 21 is then combined with the conductor 22 by the pad portion 210a of the conductive through hole 210. Further, if the conductor 22 is first formed on the conductive bump 29, the conductor 22 is only formed on a portion of the conductive bump 29 but not on all the conductive bumps 29, 29'. Figure 2A 'shown.

[0092] In addition, the conductor 22 is not formed at another portion of the opening 280' on the electronic component 20. Figure 2B shown.

[0093] like Figure 2C As shown, along Figure 2B The cutting path L shown is used for a singulation process to obtain a plurality of electronic structures 2 b.

[0094] like Figures 2D to 2E As shown, the electronic structure 2b is disposed on a carrier board 9' having a plurality of conductive pillars 23, wherein the plurality of conductive pillars 23 are used to support the electronic component 20, so that the electronic structure 2b is stacked on the carrier board 9' via the conductive pillars 23, and the electronic component 20 is electrically connected to the conductive pillars 23, and the electronic intermediate block 21 is located between the electronic component 20 and the carrier board 9'. Next, a coating layer 25 is formed between the carrier board 9' and the active surface 20a of the electronic component 20, so that the coating layer 25 covers the electronic intermediate block 21, the bonding layer 24 and the conductive pillars 23, wherein the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the first surface 25a is bonded to the active surface 20a (or the circuit portion 28) of the electronic component 20.

[0095] In the present embodiment, the conductive pillars 23 are metal pillars or solder pillars such as titanium / copper, copper or other metal materials, which are formed by a patterning process on the carrier board 9' by means of electroplating, etching, deposition, etc., and the carrier board 9' is, for example, a plate of a semiconductor material (such as silicon or glass), on which a release layer 90' and an adhesive layer 91' are sequentially formed by coating for configuring the conductive pillars 23 and the electronic intermediate block 21.

[0096] In addition, the conductive column 23 is connected to the active surface 20a of the electronic component 20. For example, the conductive column 23 is inserted into another opening 280' of the electronic component 20 to electrically connect the circuit layer 28a of the circuit portion 28, and the conductive column 23 may be formed with a conductive block 230 corresponding to the opening 280' at the top, so that the conductive column 23 can fill the space in the opening 280' as the conductive bump 29 through the conductive block 230, wherein the conductive block 230 is a welding metal, such as copper, nano-twinned copper or other materials. It should be understood that if the connection Figure 2A ' process, the conductive block 230 of the conductive column 23 can supplement the space of the conductor 22.

[0097] In addition, the width d2 of the conductive block 230 is smaller than the width d1 of the conductive column 23, and the conductive block 230 and the conductive column 23 can be manufactured separately or integrally. For example, the conductive block 230 and the conductive column 23 can be made of the same material (such as copper) or different materials.

[0098] In addition, the coating layer 25 is an insulating material, such as an encapsulating colloid of epoxy resin, and can be formed between the carrier board 9 ′ and the active surface 20 a of the electronic component 20 by filling or molding.

[0099] like Figure 2F As shown, the carrier plate 9 ′ and the release layer 90 ′ and the adhesive layer 91 ′ thereon are removed to expose the second surface 25 b of the cladding layer 25 , so that the second side 21 b of the electronic interposer 21 and the conductive through-holes 210 and the conductive pillars 23 are exposed on the second surface 25 b of the cladding layer 25 .

[0100] In this embodiment, the second surface 25 b of the cladding layer 25 is flush with the end surface 23 b of the conductive pillar 23 , the second side 21 b of the electronic interposer 21 , and the end surface of the conductive through-via 210 .

[0101] like Figure 2G As shown in FIG. 1 , a circuit structure 26 is formed on the second surface 25b of the cladding layer 25, and the circuit structure 26 is electrically connected to the conductive pillars 23 and the conductive through-holes 210 of the electronic interposer 21. Figure 2F The cutting path S shown is used for performing a singulation process to obtain the electronic package 2 .

[0102] In this embodiment, the circuit structure 26 includes a plurality of dielectric layers 260 and a plurality of redistribution layers (RDL) 261 disposed on the plurality of dielectric layers 260, and the outermost dielectric layer 260 can be used as a solder mask so that a portion of the outermost redistribution layer 261 is exposed outside the solder mask. Alternatively, the circuit structure 26 can also include only a single dielectric layer 260 and a single redistribution layer 261.

[0103] In addition, the material forming the line redistribution layer 261 is copper, and the material forming the dielectric layer 260 is a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0104] like Figure 2H As shown, a plurality of conductive elements 27 such as solder balls are formed on the outermost redistribution layer 261 , so that the plurality of conductive elements 27 are electrically connected to the conductive pillars 23 and / or the conductive through-vias 210 .

[0105] In this embodiment, the circuit structure 26 is fan-in type, so that the layout range of the conductive elements 27 does not exceed the area of ​​the active surface 20 a of the electronic element 20 .

[0106] In addition, in subsequent manufacturing processes, the conductive elements 27 can be connected to the upper side of a wiring board 8, such as an organic material board (such as a packaging substrate having a core layer and a circuit portion or a coreless packaging substrate having a circuit portion) or an inorganic material board (such as a silicon board), and the lower side of the wiring board 8 can be connected to an electronic device such as a circuit board (not shown).

[0107] In addition, if the continuation Figure 2A 'The process shown will obtain Figure 2H 'The electronic package 2 shown'.

[0108] Therefore, the manufacturing method of the present invention mainly manufactures the conductive pillars 23 on the carrier board 9', and does not need to electroplate the conductive pillars 23 of the large-size copper pillars on the electronic component 20, that is, the conductive pillars 23 are manufactured separately from the electronic structure 2b, so that in the process of manufacturing the conductive pillars 23, Figure 2D As shown in FIG. 1 , the metal material used to make the conductive column 23 will not be plated to the conductive bump 29 on the electronic component 20. Therefore, after the conductive column 23 is made, the metal material of the conductive column 23 will not connect the conductive column 23 and the conductive bump 29 of the electronic component 20 for connecting the conductive through hole 210. Therefore, compared with the prior art, after the electronic structure 2b of the present invention is stacked on the carrier board 9', as shown in FIG. Figure 2E As shown, the single conductive pillar 23 will be electrically connected to the corresponding electrode pad 210 , but will not be directly electrically connected to the conductive through hole 210 (or the conductor 22 ) of the electronic interposer 21 , thus preventing a short circuit from occurring.

[0109] In addition, the manufacturing method of the present invention combines the electronic structure 2b and the conductive column 23 in a stacking manner, such as Figure 2D As shown, the coating layer 25 is filled between the carrier plate 9' and the electronic component 20, as shown in FIG. Figure 2E As shown, the electronic intermediate block 21 and the conductive pillars 23 can be covered. Therefore, after removing the carrier plate 9', the second surface 25b of the covering layer 25 is flush with the end surface 23b of the conductive pillar 23 and the second side 21b of the electronic intermediate block 21 and the end surface of the conductive through hole 210. Therefore, compared with the prior art, the method of the present invention does not need to perform a flattening process on the covering layer 25 after forming the covering layer 25. Figure 2F As shown, the copper ions (or copper particles) of the conductive pillar 23 with a larger end surface 23b area will not migrate to the end surface of the conductive through-hole 210, thereby avoiding the problem that the copper ions (or copper particles) of the conductive pillar 23 conduct the conductive pillar 23 and the conductive through-hole 210 after the circuit structure 26 is formed, thereby effectively avoiding problems such as short circuit or leakage.

[0110] The present invention further provides an electronic package 2 , 2 ′, comprising: a coating layer 25 , an electronic component 20 , a plurality of conductive pillars 23 and at least one electronic intermediate block 21 .

[0111] The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other.

[0112] The electronic interposer 21 is embedded in the cladding layer 25 and has a plurality of conductive through holes 210 .

[0113] The conductive pillar 23 is formed in the cladding layer 25 and has a conductive block 230 at the end thereof, wherein a width d2 of the conductive block 230 is smaller than a width d1 of the conductive pillar 23 .

[0114] The electronic component 20 is disposed on the first surface 25 a of the cladding layer 25 and the conductive block 230 and is electrically connected to the conductive pillar 23 and the conductive through-hole 210 .

[0115] In one embodiment, the second surface 25 b of the cladding layer 25 is flush with the surface of the second side 21 b of the electronic interposer 21 .

[0116] In one embodiment, the second surface 25 b of the cladding layer 25 is flush with the end surface 23 b of the conductive pillar 23 .

[0117] In one embodiment, the conductive through hole 210 is exposed on the second surface 25 b of the cladding layer 25 .

[0118] In one embodiment, the end surface 23 b of the conductive pillar 23 is exposed on the second surface 25 b of the cladding layer 25 .

[0119] In one embodiment, the electronic component 20 is electrically connected to the conductive block 230 and the conductive through-hole 210 via a circuit portion 28 .

[0120] In one embodiment, the electronic component 20 has a plurality of conductive bumps 29 , 29 ′, so that the plurality of conductive bumps 29 , 29 ′ are electrically connected to the conductive through-via 210 and / or the conductive block 230 .

[0121] In one embodiment, the electronic component 20 is electrically connected to the conductive through-hole 210 via a conductive body 22 , and the conductive body 22 does not contact the conductive block 230 .

[0122] In one embodiment, the electronic package 2 , 2 ′ further includes a circuit structure 26 formed on the second surface 25 b of the cladding layer 25 and electrically connecting the conductive pillar 23 and the conductive through-hole 210 .

[0123] In one embodiment, the electronic package 2 , 2 ′ further includes a plurality of conductive elements 27 formed on the second surface 25 b of the cladding layer 25 , and the plurality of conductive elements 27 are directly electrically connected (or indirectly electrically connected via the circuit structure 26 ) to the conductive pillar 23 and the conductive through hole 210 .

[0124] In summary, the electronic package and the manufacturing method thereof of the present invention manufacture the conductive column on the carrier board without electroplating the conductive column on the electronic component, so that during the manufacturing process of the conductive column, the metal material for manufacturing the conductive column will not be plated onto the electronic component. Therefore, after the conductive column is manufactured, the metal material of the conductive column will not connect the conductive column and the electronic component. Therefore, after the electronic structure of the present invention is stacked on the carrier board, the conductive column will not directly electrically conduct the conductive through-hole of the electronic intermediate block, so that a short circuit will not occur.

[0125] In addition, the manufacturing method of the present invention adopts a stacking method to combine the electronic structure and the conductive column to fill the coating layer between the carrier board and the electronic component, so as to cover the electronic intermediate block and the conductive columns. Therefore, after removing the carrier board, the surface of the coating layer is flush with the end face of the conductive column and the end face of the electronic intermediate block and the conductive through-hole. Therefore, after forming the coating layer, the manufacturing method of the present invention does not need to perform a leveling process on the coating layer. Therefore, the copper ions (or copper particles) of the conductive column with a larger end face area will not migrate to the end face of the conductive through-hole, thereby avoiding the problem that the copper ions (or copper particles) of the conductive column conduct the conductive column and the conductive through-hole after the circuit structure is formed, so as to effectively avoid problems such as short circuit or leakage.

[0126] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, It is characterized in that include: a coating layer; At least one electronic interposer, which is embedded in the cladding layer and has a plurality of conductive through holes; A plurality of conductive pillars embedded in the cladding layer and having conductive blocks at the ends, wherein the width of the conductive blocks is smaller than the width of the conductive pillars; as well as At least one electronic component is disposed on the cladding layer and the conductive block and electrically connects the conductive column and the conductive through-hole. The electronic component is electrically connected to the conductive through-hole via a conductor, and the conductor does not contact the conductive block.

2. The electronic package according to claim 1, It is characterized in that The surface of the coating layer is flush with the surface of the electronic interposer.

3. The electronic package as claimed in claim 1, It is characterized in that The surface of the cladding layer is flush with the end surface of the conductive column.

4. The electronic package according to claim 1, It is characterized in that The conductive through hole is exposed on the surface of the cladding layer.

5. The electronic package as claimed in claim 1, It is characterized in that The end surface of the conductive column is exposed on the surface of the cladding layer.

6. The electronic package as claimed in claim 1, It is characterized in that The electronic component is electrically connected to the conductive block and the conductive through-hole via a circuit portion.

7. The electronic package according to claim 1, It is characterized in that The electronic component has a plurality of conductive bumps, so that the plurality of conductive bumps are electrically connected to the conductive through-holes and / or the conductive block.

8. The electronic package as claimed in claim 1, It is characterized in that The electronic package also includes a circuit structure formed on the coating layer and electrically connecting the conductive column and the conductive through hole.

9. The electronic package as claimed in claim 1, It is characterized in that The electronic package also includes a plurality of conductive elements formed on the covering layer, and the plurality of conductive elements electrically connect the conductive pillar and the conductive through hole.

10. A method for manufacturing an electronic package, It is characterized in that include: Provide at least one electronic component and a carrier board having a plurality of conductive posts, wherein the conductive posts have conductive blocks at their ends, and the width of the conductive blocks is smaller than the width of the conductive posts; Combining at least one electronic interposer block on the electronic component to form an electronic structure, wherein the interposer block has a plurality of conductive through holes electrically connected to the electronic component; The electronic structure is stacked on the carrier board via the plurality of conductive pillars, so that the plurality of conductive pillars support the electronic component, and the electronic component is electrically connected to the conductive block and the conductive through-hole, wherein the electronic intermediate block is located between the electronic component and the carrier board; forming a coating layer between the carrier board and the electronic component so that the coating layer covers the electronic intermediate block and the plurality of conductive pillars; and Remove the carrier plate.

11. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The surface of the coating layer is flush with the surface of the electronic interposer.

12. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The surface of the cladding layer is flush with the end surface of the conductive column.

13. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The conductive through hole is exposed on the surface of the cladding layer.

14. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The end surface of the conductive column is exposed on the surface of the cladding layer.

15. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The electronic component is electrically connected to the conductive block and the conductive through-hole via a circuit portion.

16. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The electronic component has a plurality of conductive bumps, so that the plurality of conductive bumps are electrically connected to the conductive through-holes and / or the conductive block.

17. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The electronic component is electrically connected to the conductive through-hole via a conductive body, and the conductive body is not connected to the conductive block.

18. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The manufacturing method also includes forming a circuit structure on the cladding layer, and the circuit structure electrically connects the conductive column and the conductive through hole.

19. The method for manufacturing an electronic package as claimed in claim 10, It is characterized in that The manufacturing method also includes forming a plurality of conductive elements on the cladding layer, and the plurality of conductive elements electrically connect the conductive pillar and the conductive through hole.

Images