Chip packaging structure and manufacturing method thereof

Abstract

The present invention is a chip packaging structure and a method for manufacturing the same. The chip packaging structure includes a circuit board, a first chip, a second chip, a thermally conductive material, a molding material, and a heat dissipation portion. The circuit board includes a plurality of circuit pads. The first chip is mounted on the circuit board and electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the circuit board. The thermally conductive material is located on the circuit board and extends through the second chip and the first chip to the circuit board. The molding material is disposed on the circuit board, and the heat dissipation portion is disposed on the molding material and thermally coupled to the thermally conductive material. The thermally conductive material that penetrates the first chip and the second chip can conduct heat energy to the heat dissipation portion to help these chips dissipate heat. In addition, a method for manufacturing the above-mentioned chip packaging structure is also proposed herein.

Description

Technical Field

[0001] The present invention relates to a chip package structure and a manufacturing method thereof, and more particularly to a stacked die package structure and a manufacturing method thereof. Background Art

[0002] Conventional semiconductor packaging technology has developed a stacked chip package structure, which includes multiple stacked chips and a molding material covering the chips. The chips are typically sealed by the molding material. However, the thermal conductivity of typical molding materials is relatively low. Therefore, heat generated by the stacked chips is not easily dissipated through the molding material, resulting in heat accumulation within the chips, thereby reducing their performance. Summary of the Invention

[0003] At least one embodiment of the present invention provides a chip packaging structure, wherein the thermally conductive material included in the chip packaging structure can help dissipate heat from at least two chips.

[0004] Another embodiment of the present invention provides a method for manufacturing a chip package structure to manufacture the aforementioned chip package structure.

[0005] The chip packaging structure provided by at least one embodiment of the present invention includes a circuit board, a first chip, a second chip, a thermally conductive material, a molding material and a heat dissipation portion. The circuit board includes a main body and a plurality of circuit pads, wherein the main body has a mounting surface, and these circuit pads are located on the mounting surface. The first chip is mounted on the mounting surface and electrically connected to at least one of these circuit pads. The second chip is stacked on the first chip, wherein the first chip is located between the second chip and the circuit board. The second chip has a first surface and a second surface opposite to the first surface. The thermally conductive material is located on the circuit board and passes through the second chip and the first chip, wherein the thermally conductive material extends from the second surface of the second chip, sequentially through the second chip and the first chip to the circuit board. The molding material is arranged on the mounting surface and covers the first chip and the mounting surface, wherein the molding material surrounds the second chip. The heat dissipation portion is arranged on the molding material and thermally coupled to the thermally conductive material, wherein the molding material is located between the heat dissipation portion and the circuit board.

[0006] In at least one embodiment of the present invention, the heat dissipation portion directly contacts the thermal conductive material and the second surface of the second chip.

[0007] In at least one embodiment of the present invention, the first chip has at least one first through-hole, and the second chip has at least one second through-hole. The thermally conductive material is an electrical insulator and fills the first through-hole, the second through-hole, the first gap, and the second gap. The first gap is located between the first chip and the circuit board, and the second gap is located between the first chip and the second chip.

[0008] In at least one embodiment of the present invention, the first chip has at least one first through-hole, and the second chip has at least one second through-hole. The thermally conductive material includes at least one metal pillar, and the metal pillar extends through the first and second through-holes, and passes through the first and second chips. The first and second chips and the circuit pads are electrically insulated from the thermally conductive material.

[0009] In at least one embodiment of the present invention, the chip package structure further includes at least one conductive pillar. The conductive pillar extends through the first chip and is located between the second chip and the circuit board. The conductive pillar electrically connects at least one of the circuit pads to the second chip, and the thermally conductive material is electrically insulated from the conductive pillar.

[0010] In at least one embodiment of the present invention, the size of the first chip is larger than that of the second chip.

[0011] In at least one embodiment of the present invention, the thermal conductive material has a top surface, and the molding material has an upper surface. The top surface, the second surface, and the upper surface are aligned with each other.

[0012] At least one embodiment of the present invention provides a method for manufacturing a chip package structure, comprising: mounting a first chip and a second chip on a circuit board, wherein the first chip is positioned between the second chip and the circuit board. The first chip has at least one first through-hole, and the second chip has at least one second through-hole. Filling the first through-hole and the second through-hole with a thermally conductive material. Forming a molding material on the circuit board, wherein the molding material covers the first chip and the circuit board and surrounds the second chip. Forming a heat dissipation portion on the molding material, wherein the heat dissipation portion is thermally coupled to the thermally conductive material.

[0013] In at least one embodiment of the present invention, the thermally conductive material is filled into the first through hole and the second through hole before forming the molding material.

[0014] In at least one embodiment of the present invention, before the thermal conductive material is filled into the first and second through-holes, a jig is disposed on the circuit board. The jig covers and secures the first and second chips and has an opening exposing the second through-hole. The thermal conductive material is filled into the first and second through-holes through the opening. After the thermal conductive material is filled into the first and second through-holes and before the molding material is formed, the jig is removed.

[0015] In at least one embodiment of the present invention, forming a molding material on a circuit board includes the following steps: forming an initial molding material on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board, and the thermally conductive material; and removing a portion of the initial molding material located above the second chip to expose the thermally conductive material.

[0016] In at least one embodiment of the present invention, the method of removing a portion of the initial molding material located above the second chip includes grinding the initial molding material to expose the thermal conductive material and the second chip.

[0017] In at least one embodiment of the present invention, the thermal conductive material is filled into the first through hole and the second through hole after the molding material is formed.

[0018] In at least one embodiment of the present invention, before the thermal conductive material is filled into the first and second through-holes, a cover layer is disposed on the second chip, wherein the cover layer completely covers the second through-hole. An initial molding material is formed on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board, and the cover layer. A portion of the initial molding material located above the second chip is removed to expose the cover layer. After removing the portion of the initial molding material located above the second chip, the cover layer is removed to expose the second through-hole.

[0019] In at least one embodiment of the present invention, the method of removing a portion of the initial molding material located above the second chip includes photolithography or laser drilling.

[0020] In at least one embodiment of the present invention, the thermal conductive material is filled into the first through hole and the second through hole before the first chip and the second chip are mounted on the circuit board.

[0021] In at least one embodiment of the present invention, the method of filling the first through hole and the second through hole with the thermal conductive material includes performing through-hole electroplating on the first through hole and the second through hole to form a first sub-metal column in the first through hole and a second sub-metal column in the second through hole.

[0022] In at least one embodiment of the present invention, during the process of mounting the first chip and the second chip on a circuit board, the second sub-metal pillar is aligned with the first sub-metal pillar, and the second sub-metal pillar is connected to the first sub-metal pillar.

[0023] In at least one embodiment of the present invention, the method further includes forming at least one conductive pillar penetrating the first chip before the first chip and the second chip are mounted on the circuit board.

[0024] Based on the above, since the thermal conductive material can penetrate multiple chips (such as the second chip and the first chip mentioned above), the thermal conductive material can conduct the heat energy of these chips to the heat dissipation part, so that the heat energy of these chips can be quickly conducted to the heat dissipation part, thereby helping these chips to dissipate heat. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1A to 1J It is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to at least one embodiment of the present invention.

[0026] Figures 2A to 2C FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention.

[0027] Figures 3A to 3C FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention.

[0028]

Main component symbol description

[0029] 10: Jig 11, 252: Opening

[0030] 17: Upper cover 18: First wall

[0031] 19: Second wall 20: Covering layer

[0032] 34: Metal pillars 100, 200, 300: Chip packaging structure

[0033] 110, 110i: first chip 111, 111i, 121, 121i: chip body

[0034] 112, 113, 122, 132a, 132b: circuit pads 114: conductive pillar

[0035] 119a: through hole 119b: first through hole

[0036] 119s, 129s: sidewalls 120, 120i: second chip

[0037] 129b: Second through hole 130: Circuit board

[0038] 131: Main body 131a: Mounting surface

[0039] 131b: Back surface 133a, 133b: Insulation protection layer

[0040] 134: Metal layer 136, 137: Conductive connector

[0041] 138: Insulation layer 139: Circuit layer

[0042] 140, 240, 340: thermal conductive material 141, 241: top surface

[0043] 150, 250: Molding material 151, 251: Top surface

[0044] 160: heat dissipation portion 341: first sub-metal column

[0045] 342: Second sub-metal pillars B1, B2: Solder balls

[0046] G1: First gap G2: Second gap

[0047] P10, P11, P20, P21: Non-functional area P12, P22: Functional area

[0048] S21: first surface S22: second surface DETAILED DESCRIPTION

[0049] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be magnified in a non-proportional manner. Therefore, the description and explanation of the embodiments below are not limited to the dimensions and shapes presented by the elements in the drawings, but should cover the dimensions, shapes and deviations thereof caused by the actual process and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, and the sharp angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the patent application of the present invention.

[0050] Secondly, the words "about," "approximately," or "substantially" that appear in the present case not only cover the numerical values ​​and numerical ranges that are clearly stated, but also cover the permissible deviation range that can be understood by a person of ordinary skill in the technical field to which the invention belongs, wherein this deviation range can be determined by the error generated during measurement, and this error is caused, for example, by the limitations of the measurement system or process conditions. In addition, "about" can mean within one or more standard deviations of the above-mentioned numerical value, such as ±30%, ±20%, ±10%, or ±5%. The words "about," "approximately," or "substantially" that appear in this text can select an acceptable deviation range or standard deviation based on the optical properties, etching properties, mechanical properties, or other properties, and do not apply a single standard deviation to all properties such as the above-mentioned optical properties, etching properties, mechanical properties, and other properties.

[0051] Figures 1A to 1J is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to at least one embodiment of the present invention, wherein Figure 1J The substantially completed chip package structure 100 is shown. Figure 1A In the manufacturing method of the chip package structure of this embodiment, first, a first chip 110i is provided, wherein the first chip 110i includes a chip body 111i and a plurality of circuit pads 112, and the circuit pads 112 are located on one surface of the chip body 111i. Figure 1AFor example, the circuit pads 112 are all located on the bottom surface of the chip body 111 i.

[0052] In this embodiment, the first chip 110i may be a die, which is an unpackaged chip. Therefore, the main material of the chip body 111i may be a semiconductor material, such as silicon or gallium arsenide. However, in other embodiments, the first chip 110i may be a packaged chip, so the first chip 110i is not limited to an unpackaged die. The chip body 111i has a non-functional area P10 and a functional area P12, wherein the functional area P12 is adjacent to the non-functional area P10. The functional area P12 contains the circuitry of the first chip 110i, but the non-functional area P10 may not contain any circuitry.

[0053] See also Figure 1B Then, at least one conductive column 114 is formed. Figure 1B In the embodiment shown, multiple conductive pillars 114 may be formed, but in other embodiments, only one conductive pillar 114 may be formed. Figure 1B This is for illustration only and does not limit the number of conductive pillars 114. Figure 1A and Figure 1B In this embodiment, the method for forming the conductive pillars 114 may include the following steps.

[0054] First, a drilling process is performed on the non-functional area P10 of the first chip 110i to form the first chip 110 having at least one through hole 119a, wherein Figure 1B The example of forming multiple through-holes 119a is used. Since only one conductive pillar 114 can be formed, in other embodiments, the first chip 110 can have only one through-hole 119a. The first chip 110 also includes a chip body 111, which has a functional area P12 and a non-functional area P11. The only difference between the non-functional area P11 and P10 is the presence or absence of the through-hole 119a. No circuit system is contained in the non-functional area P11.

[0055] The drilling process may be a through silicon via (TSV) process. For example, the through hole 119a may be formed by laser drilling or etching. Next, the first chip 110 is subjected to an electroplating process to form the conductive pillars 114 in the through holes 119a, wherein the conductive pillars 114 penetrate the first chip 110. In addition, the electroplating process may be used not only to form the conductive pillars 114, but also to form at least one circuit pad 113 ( Figure 1BA plurality of circuit pads 113 are shown, wherein the circuit pads 113 and 112 are both located on the same surface of the chip body 111 , and the circuit pads 113 are connected to the conductive pillars 114 .

[0056] It should be noted that the above drilling process not only forms the through hole 119a, but also forms at least one first through hole 119b in the non-functional area P11. Therefore, the first chip 110 has not only the through hole 119a, but also the first through hole 119b, wherein the directions of the first through hole 119b and the through hole 119a can be the same. In addition, Figure 1B The embodiment shown is illustrated by taking a plurality of first through holes 119b as an example, but in other embodiments, the first chip 110 may also have a single first through hole 119b. Figure 1B The number of the first through holes 119 b in the first chip 110 is not limited.

[0057] Since no circuit system exists within the non-functional region P11, the first through-holes 119b and the through-holes 119a do not affect the overall circuit function of the circuit pads 112. Furthermore, the conductive pillars 114 and the circuit pads 113 within the non-functional region P11 do not need to be directly electrically connected to the circuit pads 112. In other words, when the first chip 110 is not mounted on the circuit board 130, both the conductive pillars 114 and the circuit pads 113 are electrically insulated from the circuit pads 112.

[0058] See also Figure 1C , providing a second chip 120i. The second chip 120i includes a chip body 121i and a plurality of circuit pads 122. The circuit pads 122 are located on one surface of the chip body 121i. Figure 1C For example, these circuit pads 122 are all located on the bottom surface of the chip body 121i. The chip body 121i also has a non-functional area P20 and a functional area P22, wherein the functional area P22 is adjacent to the non-functional area P20. The functional area P22 contains the circuit system of the second chip 120i, but the non-functional area P20 does not contain any circuit system.

[0059] The second chip 120i may also be a die, that is, an unpackaged chip. Therefore, the main material of the chip body 121i may also be a semiconductor material, such as silicon or gallium arsenide. However, in other embodiments, the second chip 120i may be a packaged chip, so the second chip 120i is not limited to an unpackaged die. In addition, Figure 1A and Figure 1C It can be seen that the size of the first chip 110 i is significantly larger than that of the second chip 120 i .

[0060] See also Figure 1DNext, a drilling process is performed on the non-functional area P20 of the second chip 120i to form the second chip 120 having at least one second through hole 129b. Specifically, the second chip 120 further has a first surface S21 and a second surface S22 opposite to the first surface S21. The second through hole 129b extends from the second surface S22 to the first surface S21. Therefore, the two ends of the second through hole 129b are exposed to the first surface S21 and the second surface S22, respectively. Furthermore, because the size of the first chip 110i is larger than that of the second chip 120i, the size of the first chip 110 is also larger than that of the second chip 120.

[0061] Figure 1D The example of forming a plurality of second through holes 129b is used for illustration. Figure 1D The number of second through-holes 129b is not limited. The method for forming the second through-holes 129b can be the same as the method for forming the first through-holes 119b, so the drilling process performed on the non-functional area P20 can be a through-silicon via (TSV) process. In addition, the second chip 120 also includes a chip body 121, and the chip body 121 has a functional area P22 and a non-functional area P21. The only difference between the non-functional area P21 and P20 is the presence or absence of the second through-hole 129b, wherein the second through-hole 129b is located in the non-functional area P21, and no circuit system is stored in the non-functional area P21.

[0062] See also Figure 1E and Figure 1F Next, the first chip 110 and the second chip 120 are mounted on the circuit board 130. The circuit board 130 includes a main body 131 and a plurality of circuit pads 132a. The main body 131 has a mounting surface 131a and a back surface 131b opposite the mounting surface 131a. The circuit pads 132a are located on the mounting surface 131a. The first chip 110 and the second chip 120 are both mounted on the mounting surface 131a, and the first chip 110 is electrically connected to at least one of the circuit pads 132a.

[0063] exist Figure 1E and Figure 1FIn the illustrated embodiment, the second chip 120 is mounted on the first chip 110 after the first chip 110 is mounted on the circuit board 130. Therefore, the second chip 120 is stacked on the first chip 110. Both the first chip 110 and the second chip 120 can be mounted on the circuit board 130 using a flip chip method. Specifically, the first chip 110 can be mounted on the mounting surface 131a of the circuit board 130 using a plurality of solder balls B1. The wiring pads 112 and 113 of the first chip 110 are electrically connected to the wiring pads 132a via the solder balls B1, so that the first chip 110 can be electrically connected to at least one of the wiring pads 132a.

[0064] See also Figure 1F , the second chip 120 can be mounted on the first chip 110. For example, the second chip 120 can be mounted on the first chip 110 using a plurality of solder balls B2, wherein the circuit pads 122 of the second chip 120 are electrically connected to the conductive pillars 114 respectively through the solder balls B2. Since the conductive pillars 114 are respectively connected to the circuit pads 113, and the circuit pads 113 are respectively electrically connected to the circuit pads 132a through the solder balls B1, the conductive pillars 114 can respectively electrically connect the circuit pads 132a and the second chip 120. In this way, the circuit pads 122 of the second chip 120 can be electrically connected to the circuit pads 132a through the solder balls B1, B2, the conductive pillars 114 and the circuit pads 113, so that the second chip 120 is electrically connected to the circuit board 130, as shown in FIG. Figure 1F shown.

[0065] Since the conductive pillars 114 and the circuit pads 113 are both located in the non-functional area P11 of the first chip 110 (see Figure 1B ), so the second chip 120 is not electrically connected to the first chip 110 only through the solder balls B1 and B2, the conductive pillars 114, and the circuit pads 113. In other words, the electrical signals generated by the second chip 120 cannot be directly transmitted to the first chip 110 through the conductive pillars 114 and must pass through the circuit board 130 to be transmitted to the first chip 110.

[0066] After the first chip 110 and the second chip 120 are mounted on the circuit board 130, the first chip 110 is located between the second chip 120 and the circuit board 130, and the first surface S21 is located between the second surface S22 and the first chip 110, wherein the conductive pillar 114 is located between the second chip 120 and the circuit board 130. A gap is formed between the first chip 110, the second chip 120 and the circuit board 130. Figure 1FFor example, a first gap G1 may be formed between the first chip 110 and the circuit board 130, and a second gap G2 may be formed between the first chip 110 and the second chip 120. In addition, since the size of the first chip 110 is larger than that of the second chip 120, the first chip 110 may protrude from the sidewall 129s of the second chip 120.

[0067] The circuit board 130 can be a printed circuit board or a package carrier, and the main body 131 comprises the components of the circuit board 130 other than the wiring pads 132a. In this embodiment, the main body 131 includes a plurality of wiring pads 132b, multiple insulating layers 138, multiple wiring layers 139, and a plurality of conductive connectors 136 and 137. The wiring pads 132b are opposite the wiring pads 132a and are located on the back surface 131b. The insulating layers 138 and the wiring layers 139 are stacked alternately, with each wiring layer 139 sandwiched between two adjacent insulating layers 138.

[0068] The conductive connectors 136 and 137 are located within the insulating layer 138 and electrically connect the circuit layers 139 and the circuit pads 132a and 132b, so that the electrical signals transmitted within the circuit layers 139 can be transmitted between the circuit layers 139 and the circuit pads 132a and 132b through the conductive connectors 136 and 137. In addition, in this embodiment, the conductive connector 136 can be a conductive blind via structure, and the conductive connector 137 can be a conductive buried via structure, such as Figure 1E and Figure 1F shown.

[0069] In this embodiment, the circuit board 130 is a multi-layer circuit board and has four circuit layers, namely, two circuit layers 139 and circuit pads 132a and 132b located on opposite sides of the circuit board 130. However, in other embodiments, the circuit board 130 may also be a single-layer circuit board or a double-sided circuit board. Alternatively, the circuit board 130 may have more than four circuit layers. Therefore, the number of circuit layers of the circuit board 130 is not limited to Figure 1E and Figure 1F For restriction.

[0070] It is worth mentioning that in Figure 1E and Figure 1FIn the embodiment shown, the first chip 110 and the second chip 120 are mounted on the circuit board 130 in a flip-chip manner. However, in other embodiments, the first chip 110 and the second chip 120 can also be mounted on the circuit board 130 in a manner other than flip-chip, such as wire bonding. Secondly, the second chip 120 can also be directly electrically connected to the circuit board 130 by wire bonding, without having to electrically connect to the circuit board 130 via the conductive pillars 114. In other words, when the second chip 120 is electrically connected to the circuit board 130 by wire bonding, Figure 1F The conductive pillars 114 shown may be omitted. Figure 1F The manner in which the first chip 110 and the second chip 120 are mounted on the circuit board 130 is merely an example and is not limited to the flip-chip mounting.

[0071] In particular, in this embodiment, the circuit board 130 may further include two insulating protective layers 133a and 133b. The insulating protective layer 133a may cover the mounting surface 131a and expose the circuit pads 132a. The insulating protective layer 133b is disposed on the main body 131 and opposite to the insulating protective layer 133a. The main body 131 may be located between the insulating protective layers 133a and 133b, while the insulating protective layer 133b may be located on the back surface 131b and expose the circuit pads 132b. Furthermore, both the insulating protective layers 133a and 133b may be solder resist layers.

[0072] In particular, circuit board 130 may further include a metal layer 134, wherein metal layer 134 is located on mounting surface 131a and is exposed by insulating protective layer 133a. Metal layer 134 is not electrically connected to circuit pads 132a, 132b. In other words, metal layer 134 may be electrically insulated from circuit pads 132a, 132b. Metal layer 134 may serve as a ground pad for circuit board 130. Furthermore, metal layer 134 and circuit pads 132a may be formed from the same metal layer through photolithography (including etching).

[0073] See also Figure 1G Then, the thermal conductive material 140 is filled into the first through hole 119b and the second through hole 129b. After the thermal conductive material 140 is filled into the first through hole 119b and the second through hole 129b, the thermal conductive material 140 is located on the circuit board 130 and passes through the second chip 120 and the first chip 110. The thermal conductive material 140 extends from the second surface S22 of the second chip 120, sequentially through the second chip 120 and the first chip 110, and then to the circuit board 130.

[0074] The thermally conductive material 140 can be an electrical insulator. The thermally conductive material 140 can be made of a material with high thermal conductivity, such as graphene or other polymer materials with high thermal conductivity. Therefore, the thermally conductive material 140 is electrically insulated from the conductive pillars 114. In other words, even if the thermally conductive material 140 directly contacts the solder balls B1 and B2 and the circuit pads 113, the thermally conductive material 140 is still not electrically connected to the conductive pillars 114, thereby preventing these conductive pillars 114 from short-circuiting.

[0075] Before the thermally conductive material 140 is filled into the first and second through-holes 119b, 129b, a jig 10 can be placed on the circuit board 130. The jig 10 covers and secures the first and second chips 110, 120, preventing relative movement between them. This facilitates smooth filling of the thermally conductive material 140 into the first and second through-holes 119b, 129b during subsequent processing.

[0076] The fixture 10 includes a top cover 17, a first wall 18, a second wall 19, and an opening 11, wherein both the first wall 18 and the second wall 19 are annular in shape. The top cover 17 is connected to the second wall 19 and is located on the second wall 19 and the first wall 18. The opening 11 is formed in the top cover 17, and the second wall 19 is located on the first wall 18. After the fixture 10 covers and secures the first chip 110 and the second chip 120, the top cover 17 covers the second chip 120, while the first wall 18 and the second wall 19 surround the first chip 110 and the second chip 120, respectively. The opening 11 exposes the second through hole 129b. Therefore, the thermal conductive material 140 can be filled into the first through holes 119b and the second through holes 129b through the opening 11.

[0077] When the thermally conductive material 140 is filled into the first through holes 119b and the second through holes 129b from the opening 11, the thermally conductive material 140 has fluidity. Therefore, the thermally conductive material 140 can flow from the second through holes 129b into the second gap G2, the first through holes 119b, and the first gap G1 in sequence, so that the thermally conductive material 140 can fill the first through holes 119b, the second through holes 129b, the first gap G1, and the second gap G2.

[0078] Since the thermal conductive material 140 can fill the first gap G1, the thermal conductive material 140 can directly contact the metal layer 134. Figure 1GIn the illustrated embodiment, the first wall 18 may contact the sidewalls 119s of the first chip 110, while the second wall 19 may not contact the sidewalls 129s of the second chip 120. This allows the flowing thermally conductive material 140 to contact the sidewalls 129s and fill the gap between the sidewalls 129s and the second wall 19. After the thermally conductive material 140 is filled into the first through-holes 119b and the second through-holes 129b, the jig 10 is removed. Before removing the jig 10, the thermally conductive material 140 may be cured by heating.

[0079] See also Figure 1H and Figure 1I After the thermal conductive material 140 is filled into the first through hole 119b and the second through hole 129b, a molding material 150 (such as Figure 1I In this embodiment, forming the molding material 150 may include the following steps.

[0080] See also Figure 1H First, an initial molding material 150i is formed on the circuit board 130, wherein the initial molding material 150i covers the first chip 110, the second chip 120, the circuit board 130 and the thermal conductive material 140, and can encapsulate the first chip 110, the second chip 120 and the thermal conductive material 140. Figure 1H In the illustrated embodiment, the initial molding material 150 i completely covers the second surface S22 of the second chip 120 and the second through holes 129 b , so that the first chip 110 , the second chip 120 , and the thermal conductive material 140 are completely sealed in the initial molding material 150 i .

[0081] See also Figure 1H and Figure 1I Then, a portion of the initial molding material 150i located above the second chip 120 is removed to expose the thermally conductive material 140 and form the molding material 150. The molding material 150 disposed on the mounting surface 131a covers the first chip 110 and the circuit board 130 and surrounds the second chip 120. In addition, in this embodiment, the molding material 150 does not contact the sidewall 129s of the second chip 120, and a portion of the thermally conductive material 140 can fill the gap between the sidewall 129s and the molding material 150. Figure 1I shown.

[0082] In this embodiment, the method for removing a portion of the initial molding material 150i can be grinding the initial molding material 150i. In this way, the portion of the initial molding material 150i above the second chip 120 can be removed to expose the thermally conductive material 140 and the second chip 120. After grinding the initial molding material 150i, the thermally conductive material 140 has a top surface 141, and the molding material 150 has an upper surface 151. The top surface 141, the second surface S22, and the upper surface 151 can be aligned with each other.

[0083] See also Figure 1J , then, a heat dissipation portion 160 is formed on the upper surface 151 of the molding material 150, wherein the molding material 150 is located between the heat dissipation portion 160 and the circuit board 130, and the heat dissipation portion 160 can be a heat dissipation glue, a heat dissipation pad or a heat dissipation fin. The heat dissipation portion 160 is thermally coupled to the thermally conductive material 140. Specifically, the heat dissipation portion 160 disposed on the molding material 150 can directly contact the thermally conductive material 140 and the second surface S22 of the second chip 120. Alternatively, a thermally conductive material (not shown) with high thermal conductivity, such as thermal paste or heat dissipation glue, can be disposed between the heat dissipation portion 160 and the thermally conductive material 140. After the heat dissipation portion 160 is formed, a chip packaging structure 100 including the circuit board 130, the first chip 110, the second chip 120, the thermally conductive material 140, the molding material 150 and the heat dissipation portion 160 is basically manufactured.

[0084] Based on the above, the heat energy of the second chip 120 can be transferred to the heat dissipation portion 160, while the heat energy of the first chip 110 can be transferred from the thermally conductive material 140 to the heat dissipation portion 160. In this way, the heat energy generated by both the first chip 110 and the second chip 120 can be quickly transferred to the heat dissipation portion 160, allowing the heat energy to dissipate from the heat dissipation portion 160, thereby preventing the performance of the first chip 110 and the second chip 120 from being reduced due to heat energy accumulation. In addition, because the thermally conductive material 140 can directly contact the metal layer 134, the heat energy of both the first chip 110 and the second chip 120 can also be transferred to the metal layer 134, helping to reduce heat energy accumulation.

[0085] Figures 2A to 2C FIG is a cross-sectional view of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. Figure 2A The manufacturing method of the chip package structure of this embodiment is similar to that of the aforementioned embodiment. Therefore, the following mainly describes the differences between the manufacturing methods of the chip package structure of this embodiment and the aforementioned embodiment. In principle, the features that are common to the aforementioned embodiments are not described again and are not shown in the drawings.

[0086] The main difference between this embodiment and the previous embodiment is that: Figures 1A to 1J), the thermal conductive material 140 is filled into the first through hole 119b and the second through hole 129b before the molding material 150 is formed. However, in this embodiment, the thermal conductive material 240 is filled into the first through hole 119b and the second through hole 129b after the molding material 250 is formed. In addition, the composition of the thermal conductive material 240 of this embodiment is the same as that of the thermal conductive material 140 of the previous embodiment.

[0087] See also Figure 2A After the first chip 110 and the second chip 120 are mounted on the circuit board 130, a cover layer 20 is placed on the second chip 120. The cover layer 20 completely covers all second through holes 129b of the second chip 120. The cover layer 20 can be a tape or a sticker and can be adhered to the second chip 120 to prevent the subsequent initial molding material 150i from entering the second through holes 129b.

[0088] Next, an initial molding material 150i is formed on the circuit board 130, where the initial molding material 150i covers the first chip 110, the second chip 120, the circuit board 130, and the cover layer 20. Since the cover layer 20 completely covers all the second through holes 129b, the initial molding material 150i substantially does not penetrate into the second through holes 129b and the first through holes 119b.

[0089] See also Figure 2A and Figure 2B Then, a portion of the initial molding material 150i located above the second chip 120 is removed to expose the cover layer 20 and form a molding material 250 having an opening 252, wherein the opening 252 exposes the cover layer 20. The method of removing a portion of the initial molding material 150i may be photolithography or laser drilling. When a portion of the initial molding material 150i is removed by photolithography or laser drilling to form the molding material 250, the upper surface 251 of the molding material 250 is not aligned with the second surface S22 of the second chip 120, wherein the height of the upper surface 251 relative to the circuit board 130 may be higher than the height of the second surface S22 relative to the circuit board 130, as shown in FIG. Figure 2B In addition, in this embodiment, the initial molding material 150 i may cover and directly contact the sidewall 129 s of the second chip 120 to encapsulate the second chip 120 .

[0090] See also Figure 2B and Figure 2C After removing the portion of the initial molding material 150i located above the second chip 120, the cover layer 20 is removed to expose the second through hole 129b. Since the cover layer 20 can be a tape or a patch, the cover layer 20 can be removed by tearing it off. Figure 2CAfter removing the cover layer 20, a thermally conductive material 240 is filled into the first through hole 119b and the second through hole 129b, so that the thermally conductive material 240 on the circuit board 130 passes through the second chip 120 and the first chip 110. Furthermore, since the composition of the thermally conductive material 240 can be the same as that of the thermally conductive material 140, the thermally conductive material 240 in the first through hole 119b and the second through hole 129b can be cured. The method for curing the thermally conductive material 240 can be heating.

[0091] Afterwards, a heat dissipation portion 160 is formed on the upper surface 251 of the molding material 250, wherein the molding material 250 is located between the heat dissipation portion 160 and the circuit board 130, and the heat dissipation portion 160 is thermally coupled to the thermal conductive material 240. At this point, a chip packaging structure 200 has been basically manufactured. Since the upper surface 251 of the molding material 250 is not aligned with the second surface S22 of the second chip 120, the top surface 241 of the thermal conductive material 240 can be aligned with the upper surface 251, but not aligned with the second surface S22, as shown in FIG. Figure 2C shown.

[0092] Figures 3A to 3C FIG2 is a cross-sectional view of a method for manufacturing a chip package structure according to another embodiment of the present invention. The method for manufacturing a chip package structure according to this embodiment is similar to the method for manufacturing a chip package structure according to the aforementioned embodiment, and the main difference between the two is that the thermal conductive material 340 (see FIG2 ) of this embodiment is Figure 3B ) is filled into the first through hole 119 b and the second through hole 129 b before the first chip 110 and the second chip 120 are mounted on the circuit board 130 .

[0093] See also Figure 3A First, a first chip 110 having at least one first through-hole 119b and at least one through-hole 119a is provided. Then, through-hole plating is performed on the first through-hole 119b and the through-hole 119a to form a first sub-metal pillar 341 within the first through-hole 119b and a conductive pillar 114 within the through-hole 119a. Thereafter, the first chip 110 is mounted on the mounting surface 131a of the circuit board 130.

[0094] After the first chip 110 is mounted on the circuit board 130, the first sub-metal pillars 341 can be thermally coupled to the metal layer 134 of the circuit board 130. For example, the first sub-metal pillars 341 can directly contact the metal layer 134. Alternatively, a thermally conductive material (not shown) with high thermal conductivity, such as thermal paste, thermal adhesive, or solder, can be disposed between the first sub-metal pillars 341 and the metal layer 134.

[0095] See also Figure 3B, providing a second chip 120 having at least one second through hole 129b. Then, through-hole plating is performed on the second through hole 129b to form a second sub-metal pillar 342 in the second through hole 129b. Thereafter, the second chip 120 is mounted on the first chip 110, wherein the second sub-metal pillars 342 are respectively aligned with the first sub-metal pillars 341, and the second chip 120 can be mounted on the first chip 110 using ultrasonic bonding so that the second sub-metal pillars 342 are respectively connected to the first sub-metal pillars 341. In addition, during the process of mounting the second chip 120 on the first chip 110, the circuit pads 122 of the second chip 120 can also be electrically connected to the conductive pillars 114 by ultrasonic bonding, so that the second chip 120 can be electrically connected to the circuit board 130 through the conductive pillars 114.

[0096] It is worth mentioning that, in this embodiment, the second chip 120 is mounted on the first chip 110 by ultrasonic bonding. However, in other embodiments, the second chip 120 may also be mounted on the first chip 110 by using a plurality of solder balls B2 (see FIG. Figure 1F ) and is installed on the first chip 110, wherein these solder balls B2 can connect the circuit pad 122, the conductive column 114, the first sub-metal column 341 and the second sub-metal column 342, so that the circuit pad 122 is electrically connected to the conductive column 114, and the first sub-metal column 341 is connected to the second sub-metal column 342.

[0097] After the first chip 110 and the second chip 120 are mounted on the circuit board 130, the first sub-metal pillar 341 and the second sub-metal pillar 342 connected to each other form a metal pillar 34, and the thermal conductive material 340 includes at least one metal pillar 34. In addition, this embodiment uses the thermal conductive material 340 including multiple metal pillars 34 as an example, and in other embodiments, the thermal conductive material 340 may also include only one metal pillar 34. Therefore, Figure 3B The number of metal pillars 34 included in the thermally conductive material 340 is not limited.

[0098] These metal pillars 34 extend through first and second through-holes 119b and 129b, respectively, through first and second chips 110 and 120. Because first through-holes 119b are located in non-functional area P11 and second through-holes 129b are located in non-functional area P21, first and second chips 110 and 120, as well as the circuit pads 132a of circuit board 130, are electrically insulated from thermally conductive material 340. Furthermore, because first sub-metal pillars 341 are thermally coupled to metal layer 134 of circuit board 130, metal pillars 34 are also thermally coupled to metal layer 134 of circuit board 130.

[0099] See also Figure 3C, then, the molding material 350 and the heat dissipation portion 160 are sequentially formed, wherein the molding material 350 can fill the first gap G1 between the first chip 110 and the circuit board 130 and the second gap G2 between the first chip 110 and the second chip 120. Thus, a chip package structure 300 including the molding material 350 and the thermal conductive material 340 is basically manufactured. In addition, the molding material 350 can be formed by the same method and material as in the example Figure 1H and Figure 1I The forming method and materials of the molding material 150 are not described here again.

[0100] It should be noted that the above embodiments are all described using two chips, namely the first chip 110 and the second chip 120. However, in other embodiments, the chip package structure may include three or more chips, so the number of chips included in the chip package structure disclosed in the above embodiments is not limited to two.

[0101] In summary, since the thermal conductive material can penetrate multiple chips (such as the second chip and the first chip mentioned above), the thermal conductive material can conduct the heat energy of these chips to the heat dissipation part, so that the heat energy of these chips can be quickly conducted to the heat dissipation part to help these chips dissipate heat, thereby helping to improve the performance of these chips.

[0102] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Those skilled in the art may make modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the patent application.

Claims

1. A chip packaging structure, characterized in that: include: The circuit board comprises a main body and a plurality of circuit pads, wherein the main body has a mounting surface, and the circuit pads are located on the mounting surface; a first chip mounted on the mounting surface and electrically connected to at least one of the circuit pads; A second chip is stacked on the first chip, wherein the first chip is located between the second chip and the circuit board, and the second chip has a first surface and a second surface opposite to the first surface; a thermally conductive material located on the circuit board and passing through the second chip and the first chip, wherein the thermally conductive material extends from the second surface of the second chip, sequentially through the second chip and the first chip, and to the circuit board; A molding material is disposed on the mounting surface and covers the first chip and the mounting surface, wherein the molding material surrounds the second chip; as well as A heat dissipation portion is configured on the molding material and thermally coupled to the thermally conductive material, wherein the molding material is located between the heat dissipation portion and the circuit board, wherein the first chip has at least one first through hole, and the second chip has at least one second through hole, and the thermally conductive material is an electrical insulator and fills the at least one first through hole, the at least one second through hole, the first gap and the second gap, wherein the first gap is located between the first chip and the circuit board, and the second gap is located between the first chip and the second chip.

2. The chip packaging structure according to claim 1, wherein: The heat dissipation portion directly contacts the thermal conductive material and the second surface of the second chip.

3. The chip packaging structure according to claim 1, wherein: The first chip has at least one first through hole, and the second chip has at least one second through hole. The thermally conductive material includes at least one metal column, and the at least one metal column passes through the first chip and the second chip from the at least one first through hole and the at least one second through hole, wherein the first chip, the second chip and the circuit pad are all electrically insulated from the thermally conductive material.

4. The chip packaging structure according to claim 1, wherein: Also includes: At least one conductive column passes through the first chip and is located between the second chip and the circuit board, wherein the at least one conductive column electrically connects at least one of the circuit pads and the second chip, and the thermal conductive material is electrically insulated from the at least one conductive column.

5. The chip packaging structure according to claim 1, wherein: The size of the first chip is larger than that of the second chip.

6. The chip packaging structure according to claim 1, wherein: The thermal conductive material has a top surface, and the molding material has an upper surface. The top surface, the second surface and the upper surface are aligned with each other.

7. A method for manufacturing a chip packaging structure, characterized in that: include: Mounting a first chip and a second chip on a circuit board, wherein the first chip is located between the second chip and the circuit board, the first chip has at least one first through hole, and the second chip has at least one second through hole, wherein a first gap is located between the first chip and the circuit board, and a second gap is located between the first chip and the second chip; Filling the at least one first through hole and the at least one second through hole with a thermally conductive material, wherein the thermally conductive material is an electrical insulator and completely fills the at least one first through hole, the at least one second through hole, the first gap, and the second gap; After the first chip and the second chip are mounted on the circuit board, a molding material is formed on the circuit board, wherein the molding material covers the first chip and the circuit board and surrounds the second chip; as well as A heat dissipation portion is formed on the molding material, wherein the heat dissipation portion is thermally coupled to the thermal conductive material.

8. The method for manufacturing a chip packaging structure according to claim 7, wherein: The thermal conductive material is filled into the at least one first through hole and the at least one second through hole before forming the molding material.

9. The method for manufacturing a chip packaging structure according to claim 8, wherein: Also includes: Before the thermally conductive material is filled into the at least one first through hole and the at least one second through hole, a jig is disposed on the circuit board, wherein the jig covers and fixes the first chip and the second chip and has an opening exposing the at least one second through hole, and the thermally conductive material is filled into the at least one first through hole and the at least one second through hole through the opening; as well as After the thermal conductive material is filled into the at least one first through hole and the at least one second through hole and before the molding material is formed, the jig is removed.

10. The method for manufacturing a chip packaging structure according to claim 8, wherein: The step of forming the molding material on the circuit board includes: forming an initial molding material on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board, and the thermally conductive material; and A portion of the initial molding material located above the second chip is removed to expose the thermal conductive material.

11. The method for manufacturing a chip packaging structure according to claim 10, wherein: The method of removing a portion of the initial molding material located above the second chip includes: The initial molding material is ground to expose the thermal conductive material and the second chip.

12. The method for manufacturing a chip packaging structure according to claim 7, wherein: The thermal conductive material is filled into the at least one first through hole and the at least one second through hole after the molding material is formed.

13. The method for manufacturing a chip packaging structure according to claim 12, wherein: Also includes: Before the thermal conductive material is filled into the at least one first through hole and the at least one second through hole, a cover layer is disposed on the second chip, wherein the cover layer completely covers the at least one second through hole; forming an initial molding material on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board, and the cover layer; removing a portion of the initial molding material located above the second chip to expose the cover layer; as well as After removing a portion of the initial molding material located above the second chip, the cover layer is removed to expose the at least one second through hole.

14. The method for manufacturing a chip packaging structure according to claim 13, wherein: Methods for removing the portion of the initial molding material located above the second chip include photolithography or laser drilling.

15. The method for manufacturing a chip packaging structure according to claim 7, wherein: The thermal conductive material is filled into the at least one first through hole and the at least one second through hole before the first chip and the second chip are mounted on the circuit board.

16. The method for manufacturing a chip packaging structure according to claim 7, wherein: Also includes: Before the first chip and the second chip are mounted on the circuit board, at least one conductive column penetrating the first chip is formed.

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