Semiconductor device for preventing pattern distortion and method of forming the same

Abstract

The application discloses a semiconductor device for preventing pattern distortion and a forming method thereof. The semiconductor device comprises a plurality of sequentially arranged strip patterns in a central region, dummy patterns at two opposite edges of the central region, the forming conditions of the strip patterns and the dummy patterns being the same, two ends of each strip pattern being electrically connected with a corresponding first metal, two ends of each dummy pattern being electrically connected with a corresponding second metal, and the second metal being used for connecting a power supply. The strip patterns and the dummy patterns belong to a first film layer of the semiconductor device, and the first metal and the second metal belong to a second film layer of the semiconductor device. Since the second metal is connected with the dummy patterns as a semiconductor structure, a well bias voltage is introduced for the power supply, the effect of which is not only to reduce the distortion of the strip patterns, but also to introduce the well bias voltage for the power supply, and further, by flexibly using the dummy patterns, a convenient condition can be provided for the development of semiconductor integration.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device for preventing pattern distortion and a method for forming the same. Background Technology

[0002] As integrated circuit patterns become increasingly smaller, the optical proximity effect (OPE) easily occurs during the manufacturing process of forming multiple high-density strip patterns, causing distortion of the strip patterns. Currently, to reduce the impact of OPE, floating dummy active patterns are typically formed at the edges of the strip pattern area under the same conditions as the strip pattern itself. This minimizes distortion and improves linewidth uniformity. However, these floating dummy active patterns only reduce distortion and thus limit the development of semiconductor integration density. Summary of the Invention

[0003] The purpose of this application is to provide a semiconductor device and a method for forming the same to prevent pattern distortion, addressing the shortcomings of the prior art. This purpose is achieved through the following technical solutions.

[0004] The first aspect of this application provides a semiconductor device for preventing pattern distortion, the semiconductor device comprising a plurality of sequentially arranged bar patterns located in a central region and dummy patterns located at two opposite edges of the central region, wherein the bar patterns and the dummy patterns are formed under the same conditions.

[0005] Each of the strip patterns has its two ends electrically connected to its corresponding first metal, and each of the dummy patterns has its two ends electrically connected to its corresponding second metal, wherein the second metal is used to connect to a power source.

[0006] The bar pattern and the dummy pattern are located in the first film layer of the semiconductor device, and the first metal and the second metal are located in the second film layer of the semiconductor device.

[0007] A second aspect of this application provides a method for forming a semiconductor device to prevent pattern distortion, the method comprising:

[0008] Multiple strip patterns are formed in sequence in the central region of the first film layer, and a dummy pattern is formed at each of the two opposite edges of the central region. The strip patterns and the dummy patterns are formed under the same conditions.

[0009] A first metal electrically connected to each of the strip patterns is formed on the second film layer, and a second metal electrically connected to each of the dummy patterns is formed on the second film layer, and the second metal is connected to a power source.

[0010] A third aspect of this application provides a semiconductor device including a semiconductor means for preventing pattern distortion as described in the first aspect above.

[0011] The semiconductor device and its method for preventing pattern distortion described in the first and second aspects above have the following advantages:

[0012] This invention forms a metal identical to the upper part of a bar pattern on the upper part of a dummy pattern, electrically connects the formed metal to the dummy pattern, and simultaneously connects the metal to a power supply. Thus, the metal and the dummy pattern together form a semiconductor structure to introduce a well bias voltage from the power supply. Since the dummy pattern in this invention not only reduces the distortion of the bar pattern but also introduces a well bias voltage to the power supply, utilizing dummy patterns can facilitate the development of semiconductor integration. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0014] Figure 1 This is a schematic diagram of the structure of a semiconductor device used in the prior art to prevent pattern distortion;

[0015] Figure 2 This is a schematic diagram illustrating the structure of a semiconductor device for preventing pattern distortion according to an exemplary embodiment of this application;

[0016] Figure 3 For along Figure 2 A schematic diagram of the cross-sectional structure obtained by cutting off AA' in the middle;

[0017] Figure 4 This is a flowchart illustrating an embodiment of a method for forming a semiconductor device to prevent pattern distortion, according to an exemplary embodiment of this application. Detailed Implementation

[0018] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0020] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0021] In existing technologies, dummy patterns are only used to reduce distortion in bar patterns and improve the uniformity of bar width. See [link to relevant documentation]. Figure 1 The semiconductor device shown includes a plurality of sequentially arranged bar patterns 700 located in the central region of a semiconductor substrate 100, and two dummy patterns 600 located at opposite edges of the central region. Both ends of each bar pattern are electrically connected to a corresponding upper metal 400 through a contact hole 500. The upper metal 400 serves as a pathway for the bar patterns to connect to other structures.

[0022] With the current trend of increasingly stringent requirements for semiconductor integration, dummy patterns, which do not play any electrical role in integrated circuits but are only used to reduce the influence of optical proximity effects, are thus restricting the development of semiconductor integration.

[0023] To address the aforementioned technical problems, this invention proposes an improved semiconductor device for preventing pattern distortion, see [link to relevant documentation]. Figure 2 As shown, the semiconductor device includes a semiconductor substrate 10, a plurality of sequentially arranged strip patterns 70 located in the central region of the semiconductor substrate 10, and two dummy patterns 60 located at opposite edges of the central region. Each strip pattern 70 has its two ends connected to a corresponding first metal 40, and the strip patterns 70 and dummy patterns 60 are formed under the same conditions, therefore their structures are completely identical.

[0024] The difference from the prior art is that each dummy pattern 60 is also electrically connected to its corresponding second metal 30 at both ends, and the second metal 30 is electrically connected to the power supply. Since the second metal 30 and the dummy pattern 60 are connected to the power supply as a semiconductor structure, a well bias voltage can be introduced to the power supply. Thus, the dummy pattern 60 can be used flexibly. It can not only reduce the distortion of the strip pattern 70, but also introduce a well bias voltage to the power supply. In this way, the flexible use of dummy patterns can provide convenient conditions for the development of semiconductor integration.

[0025] See Figure 3 As shown, Figure 2 The semiconductor device, as shown in the cross-section of AA', includes a first film layer 20 and a second film layer 80. The strip pattern 70 and the dummy pattern 60 are both located on the first film layer 20, and the first metal 40 and the second metal 30 are both located on the second film layer 80.

[0026] In some embodiments, since the strip pattern 70 and the first metal 40 are located in different film layers, contact holes 50 can be made at both ends of the strip pattern 70, and the strip pattern 70 and the first metal 40 can be electrically connected through the contact holes 50.

[0027] Based on the same principle, since the dummy pattern 60 and the second metal 30 are located in different film layers, contact holes 50 can be made at both ends of the dummy pattern 60, and the dummy pattern 60 and the second metal 30 can be electrically connected through the contact holes 50.

[0028] In one embodiment, the spacing between any two adjacent bar patterns 70 is a first preset value S1. Similarly, the spacing between each dummy pattern 60 and its adjacent bar pattern 70 is also a first preset value S1.

[0029] In this embodiment of the invention, the bar pattern 70 can be an active resistor pattern. Since the structure of the bar pattern 70 and the dummy pattern 60 are completely identical, the dummy pattern 60 is a dummy active pattern.

[0030] The active resistor pattern and the dummy active pattern can be N-doped or P-doped, and this invention does not specifically limit them.

[0031] It should be noted that, see Figure 2 As shown, in order to better prevent the bar pattern from being distorted, compared with the prior art, the first metal 40 at both ends of the bar pattern 70 will extend a portion 401 towards the center of the bar pattern 70, but the first metal 40 at both ends is not connected together, and the spacing is the second preset value S2.

[0032] When the bar pattern 70 is an active resistor pattern, since the position of the extended portion 401 corresponds to that of the bar pattern 70, the impedance value of the active resistor pattern can be adjusted by changing the number of contact holes 50 between the bar pattern 70 and the first metal 40.

[0033] Based on the same principle, the second metals 30 located at both ends of the dummy pattern 60 also extend a portion 301 towards the center of the dummy pattern 60, but the second metals 30 at both ends are not connected together, and the spacing is also the second preset value S2.

[0034] Corresponding to the aforementioned embodiments of semiconductor devices for preventing pattern distortion, this application also provides embodiments of methods for forming semiconductor devices for preventing pattern distortion.

[0035] Figure 4 This is a flowchart illustrating an embodiment of a method for forming a semiconductor device to prevent pattern distortion, according to an exemplary embodiment of this application. Figures 2 to 3 Based on the illustrated embodiment, the method for forming a semiconductor device to prevent pattern distortion includes the following steps:

[0036] Step 501: Multiple strip patterns are formed in sequence in the central region of the first film layer, and a dummy pattern is formed at each of the two opposite edges of the central region. The formation conditions of the strip patterns and the dummy patterns are the same.

[0037] Step 502: Form a first metal electrically connected to each strip pattern on the second film layer, and form a second metal electrically connected to each dummy pattern on the second film layer, and connect the second metal to the power supply.

[0038] It is worth noting that since the formation conditions of bar patterns and dummy patterns are the same, the structural construction of bar patterns and dummy patterns is identical.

[0039] For the specific implementation of steps 501 to 502 above, please refer to the above. Figures 2 to 3 The relevant descriptions of the embodiments shown are not detailed here.

[0040] This completes the above. Figure 4 The process described involves forming a metal identical to the upper part of a bar pattern on the upper part of a dummy pattern, electrically connecting the formed metal to the dummy pattern, and simultaneously connecting the metal to a power source. Thus, the metal and the dummy pattern together form a semiconductor structure, providing a well bias voltage for the power supply. Since the dummy pattern in this invention not only reduces the distortion of the bar pattern but also provides a well bias voltage for the power supply, utilizing dummy patterns can facilitate the development of semiconductor integration.

[0041] This application also proposes a semiconductor device comprising a semiconductor means for preventing pattern distortion as described in the above embodiments.

[0042] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0043] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device for preventing pattern distortion, the semiconductor device comprising a plurality of sequentially arranged bar patterns located in a central region and dummy patterns located at two opposite edges of the central region, wherein the bar patterns and the dummy patterns are formed under the same conditions, characterized in that, Each of the bar patterns has its two ends electrically connected to its corresponding first metal, and each of the dummy patterns has its two ends electrically connected to its corresponding second metal, wherein the second metal is used to connect to a power supply, and the dummy pattern is used to introduce a trap bias voltage to the power supply. The bar pattern and the dummy pattern are located in the first film layer of the semiconductor device, and the first metal and the second metal are located in the second film layer of the semiconductor device; Each of the strip patterns has its two ends electrically connected to its corresponding first metal via contact holes, and each of the dummy patterns has its two ends electrically connected to its corresponding second metal via contact holes.

2. The semiconductor device according to claim 1, characterized in that, The spacing between any two adjacent bar patterns in the plurality of sequentially arranged bar patterns is a first preset value.

3. The semiconductor device according to claim 2, characterized in that, The spacing between each of the dummy patterns and its adjacent bar pattern is also a first preset value.

4. The semiconductor device according to claim 1, characterized in that, The bar pattern is an active resistor pattern, and the dummy pattern is a dummy active pattern.

5. The semiconductor device according to claim 1, characterized in that, The spacing between the first metals corresponding to the two ends of each strip pattern is a second preset value.

6. The semiconductor device according to claim 5, characterized in that, The spacing between the second metals corresponding to the two ends of each of the dummy patterns is also a second preset value.

7. A method for forming a semiconductor device for preventing pattern distortion as described in any one of claims 1 to 6, characterized in that, The method includes: Multiple strip patterns are formed in sequence in the central region of the first film layer, and a dummy pattern is formed at each of the two opposite edges of the central region. The strip patterns and the dummy patterns are formed under the same conditions. A first metal electrically connected to each of the strip patterns is formed on the second film layer, and a second metal electrically connected to each of the dummy patterns is formed on the second film layer, and the second metal is connected to a power source.

8. A semiconductor device, characterized in that, Includes a semiconductor device for preventing pattern distortion as described in any one of claims 1 to 6 above.

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