Three-dimensional memory and methods of forming the same

Abstract

The present application relates to a three-dimensional memory and a forming method thereof. The forming method of the three-dimensional memory comprises the following steps: providing a substrate; forming a first sacrificial layer above the substrate, a stack layer above the first sacrificial layer, and a channel hole at least through the stack layer and the first sacrificial layer; forming a second sacrificial layer at the bottom of the channel hole, so that the top surface of the second sacrificial layer is above the top surface of the substrate and below the top surface of the first sacrificial layer, and the bottom surface of the second sacrificial layer is below the top surface of the substrate; forming a storage structure above the second sacrificial layer in the channel hole; removing the substrate and the second sacrificial layer; removing part of the storage structure and part of the first sacrificial layer, and the remaining first sacrificial layer forms an isolation layer; and forming a semiconductor layer covering the isolation layer and electrically connected with the storage structure. The present application simplifies the process of the three-dimensional memory, reduces the manufacturing cost of the three-dimensional memory, and improves the uniformity of the depth of the storage structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a three-dimensional memory and a forming method thereof. BACKGROUND

[0002] With the development of planar flash memory, the production process of semiconductor has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limit, existing development limit and storage electron density limit, etc. Under this background, in order to solve the difficulties encountered by planar flash memory and pursue lower production cost per storage unit, various different three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or non) flash memory and 3D NAND (3D and non) flash memory.

[0003] Among them, 3D NAND memory takes small volume and large capacity as the starting point, adopts the design concept of highly integrated storage units in three-dimensional mode layer by layer stacking, produces high storage density per unit area, and high-efficiency storage unit performance memory, which has become the mainstream process of emerging memory design and production.

[0004] However, in the process of forming the three-dimensional memory such as 3D NAND, there are problems of too deep channel hole depth and poor depth uniformity between multiple channel holes. When the back surface of the wafer is processed, the storage structure in the channel hole is easily damaged. And the manufacturing process of the current three-dimensional memory is complex, and the manufacturing cost is high.

[0005] Therefore, how to simplify the manufacturing process of three-dimensional memory, avoid damage to the bottom of the storage structure, and improve the performance of three-dimensional memory is a technical problem to be solved at present. SUMMARY

[0006] The present application provides a three-dimensional memory and a forming method thereof, which is used to solve the problem of complex manufacturing process and high manufacturing cost of the existing three-dimensional memory, and at the same time ensures the integrity of the storage structure to improve the performance of the three-dimensional memory.

[0007] In order to solve the above problems, the present application provides a forming method of a three-dimensional memory, comprising the following steps:

[0008] providing a substrate;

[0009] forming a first sacrificial layer above the substrate, a stack layer above the first sacrificial layer, and a channel hole penetrating at least the stack layer and the first sacrificial layer;

[0010] forming a second sacrificial layer at the bottom of the channel hole, so that the top surface of the second sacrificial layer is above the top surface of the substrate and below the top surface of the first sacrificial layer, and the bottom surface of the second sacrificial layer is below the top surface of the substrate;

[0011] forming a storage structure on the second sacrificial layer in the channel hole;

[0012] removing the substrate and the second sacrificial layer to expose part of the storage structure;

[0013] removing part of the storage structure and part of the first sacrificial layer, and the remaining first sacrificial layer forms an isolation layer;

[0014] forming a semiconductor layer covering the isolation layer and electrically connected with the storage structure.

[0015] Optionally, the specific step of forming a second sacrificial layer at the bottom of the channel hole comprises:

[0016] epitaxially growing the second sacrificial layer at the bottom of the channel hole.

[0017] Optionally, the material of the second sacrificial layer is monocrystalline silicon.

[0018] Optionally, the specific step of forming a storage structure on the second sacrificial layer in the channel hole comprises:

[0019] forming, in the channel hole, a blocking layer, a charge trapping layer, a tunneling layer and a channel layer in sequence along the radial direction of the channel hole.

[0020] Optionally, before removing the substrate and the second sacrificial layer, the method further comprises the following steps:

[0021] forming a virtual channel hole penetrating through the stack layer and the first sacrificial layer and extending into the substrate;

[0022] forming a virtual channel structure in the virtual channel hole, and a first air gap in the virtual channel structure is above the first sacrificial layer.

[0023] Optionally, the stack layer comprises interlayer insulating layers and third sacrificial layers alternately stacked in a direction perpendicular to the top surface of the substrate; and before removing the substrate and the second sacrificial layer, the method further comprises the following steps:

[0024] forming a gate line slot penetrating through at least the stack layer and the first sacrificial layer;

[0025] removing the third sacrificial layer along the gate line slot to form an air gap region between two adjacent interlayer insulating layers;

[0026] filling the gap region with a conductive material to form a gate layer.

[0027] Optionally, after the gate layer is formed, the method further comprises the following steps:

[0028] forming a gate trench filling layer filling the gate trench.

[0029] Optionally, the specific steps of removing the substrate and the second sacrificial layer comprise:

[0030] using the first sacrificial layer as a polishing stop layer and removing the substrate and part of the second sacrificial layer by a chemical mechanical polishing process.

[0031] Optionally, after the first sacrificial layer is used as a polishing stop layer and the substrate and part of the second sacrificial layer are removed by a chemical mechanical polishing process, the method further comprises the following steps:

[0032] removing the remaining second sacrificial layer by a wet etching process.

[0033] Optionally, the specific steps of removing part of the storage structure and part of the first sacrificial layer comprise:

[0034] removing the blocking layer, the charge trapping layer and the tunneling layer in the exposed storage structure, and simultaneously removing part of the first sacrificial layer, to expose the channel layer, and the remaining first sacrificial layer forms an isolation layer.

[0035] Optionally, the specific steps of forming a semiconductor layer covering the isolation layer and electrically connected with the storage structure comprise:

[0036] implanting a doping ion into the exposed channel layer;

[0037] depositing polysilicon on the surface of the isolation layer and the surface of the channel layer after the doping ion is implanted, to form the semiconductor layer.

[0038] To solve the above problems, the application further provides a three-dimensional memory, comprising:

[0039] a semiconductor layer;

[0040] an isolation layer located above the semiconductor layer;

[0041] a stack structure located above the isolation layer, the stack structure comprising a storage structure penetrating through the stack structure, the storage structure comprising, from the outside to the inside, a blocking layer, a charge trapping layer, a tunneling layer and a channel layer, the channel layer extending into the semiconductor layer, and the bottom surface of the blocking layer, the bottom surface of the charge trapping layer and the bottom surface of the tunneling layer being flush with the bottom surface of the isolation layer.

[0042] Optionally, further comprising:

[0043] A virtual channel structure penetrating through the stack structure and the isolation layer, and a bottom surface of the virtual channel structure being flush with a bottom surface of the isolation layer.

[0044] Optionally, the virtual channel structure further comprises:

[0045] A first air gap, a bottom surface of the first air gap being below a top surface of the isolation layer, and a top surface of the first air gap being below a top surface of the stack structure.

[0046] Optionally, further comprising:

[0047] A gate line slot filling layer penetrating through the stack structure and the isolation layer, and a bottom surface of the gate line slot filling layer being flush with a bottom surface of the isolation layer.

[0048] Optionally, the gate line slot filling layer further comprises:

[0049] A second air gap, a bottom surface of the second air gap being below a top surface of the isolation layer, and a top surface of the second air gap being below a top surface of the stack structure.

[0050] The three-dimensional memory and the forming method thereof provided by the present application only form a first sacrificial layer between a substrate and a stack layer, which simplifies the process of the three-dimensional memory and reduces the manufacturing cost of the three-dimensional memory. By forming a second sacrificial layer at the bottom of the channel hole before forming the storage structure, the depth of the storage structure is adjusted by the second sacrificial layer, which improves the uniformity of the depth of the storage structure and reduces the requirement for the uniformity of the etching depth of the channel hole, simplifies the process steps and reduces the forming cost of the three-dimensional memory. The substrate and the storage structure are isolated by the second sacrificial layer, which avoids the damage to the bottom of the storage structure caused by the wafer back processing process, thereby improving the performance of the three-dimensional memory. BRIEF DESCRIPTION OF DRAWINGS

[0051] FIG. 1 is a flow chart of the forming method of the three-dimensional memory in the embodiment of the present application; Figure 1

[0052] FIG. 3 is a schematic diagram of the structure of the three-dimensional memory in the embodiment of the present application; Figures 2A-2P

[0053] FIG. 4 is a schematic diagram of the structure of the three-dimensional memory in the embodiment of the present application. Figure 3 DETAILED DESCRIPTION The specific embodiments of the three-dimensional memory and the forming method thereof provided by the present application will be described in detail below with reference to the accompanying drawings.

[0054] The specific embodiments of the three-dimensional memory and the forming method thereof provided by the present application will be described in detail below with reference to the accompanying drawings.​​

[0055] In the manufacturing process of three-dimensional memory such as 3D NAND, a multi-layered sacrificial layer structure is usually provided between the substrate and the stack layer, so as to facilitate subsequent processes such as substrate removal and sacrificial layer removal. However, the structure process of the multi-layered sacrificial layer is complex and the manufacturing cost is high. When forming a channel hole in the stack layer by etching process, it is desired that the etching stops in the sacrificial layer. However, due to the inaccurate control of the etching endpoint, the etching depth of the channel hole is too deep (for example, extending into the substrate), and the depth uniformity of the plurality of channel holes is poor, thereby reducing the performance of the three-dimensional memory. In addition, after the channel hole extends into the substrate, in the subsequent process of removing the substrate, the storage structure at the bottom of the channel hole is easily damaged, thereby further reducing the yield of the three-dimensional memory.

[0056] In order to simplify the manufacturing process of the three-dimensional memory, reduce the manufacturing cost of the three-dimensional memory, and improve the performance of the three-dimensional memory, the present embodiment provides a forming method of a three-dimensional memory, which comprises the steps of: Figure 1 is a flow chart of the forming method of the three-dimensional memory in the present embodiment, which comprises the steps of: Figures 2A-2P is a main process cross-sectional schematic diagram in the process of forming the three-dimensional memory. As shown in Figure 1 , Figures 2A-2P The forming method of the three-dimensional memory comprises the following steps:

[0057] Step S11, providing a substrate 20.

[0058] Step S12, forming a first sacrificial layer 21 above the substrate, a stack layer 23 above the first sacrificial layer 21, and a channel hole 24 at least penetrating through the stack layer 23 and the first sacrificial layer 21, as shown in Figure 1 .

[0059] Specifically, the substrate 20 can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like. In the specific embodiment, the substrate 20 is preferably a Si substrate, serving as a support substrate of the three-dimensional memory and supporting semiconductor structures thereon. The material of the first sacrificial layer 21 can be an oxide material, such as silicon dioxide. The thickness of the first sacrificial layer 21 can be 150 nm to 250 nm, and in an embodiment, the thickness of the first sacrificial layer 21 is 200 nm. The stack layer 23 includes interlayer insulating layers 232 and third sacrificial layers 231 alternately stacked in a direction perpendicular to the top surface of the substrate 20. The material of the interlayer insulating layer 232 can be, but is not limited to, an oxide material (such as silicon dioxide), and the material of the third sacrificial layer 231 can be, but is not limited to, a nitride material (such as silicon nitride).

[0060] After the first sacrificial layer 21 and the stack layer 23 are formed on the substrate 20 as shown in Figures 2A-2P The stack layer 23, the first sacrificial layer 21, and the substrate 20 can be etched by using a dry etching process or the like to form a channel hole 24 extending through the stack layer 23 and the first sacrificial layer 21 and into the substrate 20, as shown in Figure 2B .

[0061] In step S13, a second sacrificial layer 10 is formed at the bottom of the channel hole 24, such that the top surface of the second sacrificial layer 10 is located above the top surface of the substrate 20 and below the top surface of the first sacrificial layer 21, and the bottom surface of the second sacrificial layer 10 is located below the top surface of the substrate 20, as shown in Figure 2A .

[0062] Optionally, the specific steps of filling the second sacrificial layer 10 at the bottom of the channel hole 24 include:

[0063] The second sacrificial layer 10 is epitaxially grown at the bottom of the channel hole 24.

[0064] Optionally, the material of the second sacrificial layer 10 is single crystal silicon.

[0065] Specifically, when the material of the substrate 20 is silicon, the second sacrificial layer 10 can be formed by epitaxially growing single crystal silicon or the like at the bottom of the channel hole 24. The epitaxial growth can avoid forming the second sacrificial layer 10 only on the surface of the substrate 20 exposed at the bottom of the channel hole 24, and avoid forming the second sacrificial layer 10 on other device structure surfaces.

[0066] In one embodiment, the number of the channel holes 24 is plural; the specific step of filling the second sacrificial layer 10 in the bottom of the channel hole 24 comprises:

[0067] forming the second sacrificial layer 10 in the bottom of each channel hole 24, so that the height difference between the top surfaces of any two second sacrificial layers 10 is less than or equal to a preset value.

[0068] Optionally, the preset value is 0nm-5nm.

[0069] Specifically, when the number of the channel holes 24 is plural, the depth difference of the plural channel holes 24 is large, for example, the height difference between the bottoms of two channel holes 24 is greater than or equal to 10nm. When epitaxial growth process is adopted in each channel hole 24, due to the characteristics of epitaxial growth process, i.e. epitaxial material grows from the periphery of the bottom of the channel hole 24, and when the thickness of the epitaxial material reaches a preset thickness (for example, when it reaches half of the inner diameter of the channel hole), the top opening of the epitaxial material is directly closed, so that the height difference between the top surfaces of any two second sacrificial layers 10 is less than the height difference between the bottoms of any two channel holes 24. By adjusting the process parameters of epitaxial growth of the second sacrificial layer 10, the height of the second sacrificial layer 10 can be adjusted, so as to adjust the height difference between the top surfaces of any two second sacrificial layers 10.

[0070] The specific embodiment converts the uniformity problem of the depth of the plural channel holes 24 into the uniformity problem of the height of the plural second sacrificial layers 10. The height uniformity of the plural second sacrificial layers 10 only depends on the process parameters of forming the second sacrificial layer 10, and is irrelevant to the depth uniformity of the plural channel holes 24, thereby reducing the depth uniformity requirement in the channel hole etching process and reducing the complexity of the three-dimensional memory manufacturing process. The top surface of the second sacrificial layer 10 is located above the top surface of the substrate 20 and below the top surface of the first sacrificial layer 21, on the one hand, the part of the channel hole 24 with poor bottom morphology can be truncated by filling the second sacrificial layer 10, so as to avoid forming a storage structure in the part of the channel hole 24 with poor bottom morphology, which is equivalent to increasing the B / T (bottom / top) ratio and increasing the process window; on the other hand, the storage structure formed in the channel hole 24 subsequently is limited above the substrate 20, so as to avoid damage to the storage structure caused by the peeling of the substrate 20.

[0071] Step S14, forming a storage structure 25 on the second sacrificial layer 10 in the channel hole 24, as shown in Figure 2B and Figure 2C ​

[0072] Optionally, the specific step of forming the memory structure 25 on the second sacrificial layer 10 in the channel hole 24 comprises:

[0073] The blocking layer 251, the charge trapping layer 252, the tunneling layer 253 and the channel layer 254 are sequentially formed in the channel hole 24 along the radial direction of the channel hole 24.

[0074] Specifically, after the second sacrificial layer 10 is formed, an oxide material is deposited on the sidewall of the channel hole 24 and the top surface of the second sacrificial layer 10 to form the blocking layer 251. Then, a nitride material is deposited on the surface of the blocking layer 251 to form the charge trapping layer 252. An oxide material is deposited on the surface of the charge trapping layer 252 to form the tunneling layer 253. Then, a polysilicon material is deposited on the surface of the tunneling layer 253 to form the channel layer 254, as shown in Figure 2D and Figure 2E After that, an oxide material is deposited in the channel hole 24 to form a filling layer that fills the channel hole 24 and covers the surface of the channel layer 254. Finally, a channel plug 26 (which can be made of polysilicon) is formed on the top of the channel hole 24 and contacts the channel layer 254, and a cap layer 27 (which can be made of oxide) is formed on the top surface of the stack layer 23 and the top surface of the channel plug 26, as shown in Figure 2D .

[0075] In order to facilitate the subsequent selective removal of the second sacrificial layer 10, the etching selectivity ratio between the second sacrificial layer 10 and the blocking layer 251, and the etching selectivity ratio between the second sacrificial layer 10 and the first sacrificial layer 21 are both greater than 3.

[0076] Step S15, remove the substrate 20 and the second sacrificial layer 10 to expose part of the memory structure 25, as shown in Figure 2E .

[0077] Optionally, before removing the substrate 20 and the second sacrificial layer 10, the following steps are further included:

[0078] A virtual channel hole is formed through the stack layer 23 and the first sacrificial layer 21 and extends into the substrate 20;

[0079] A virtual channel hole structure 28 is formed in the virtual channel hole, and the first air gap 29 in the virtual memory structure 28 is located above the first sacrificial layer 21, as shown in Figure 2F .

[0080] Specifically, the virtual channel hole can be formed by a dry etching process, and extends through the stack layer 23 and the first sacrificial layer 21 and into the substrate 20. The virtual channel structure includes a first virtual channel layer 281 covering the inner wall of the virtual channel hole and a second virtual channel layer 282 covering the surface of the first virtual channel layer 281 and filling the virtual channel hole. The first virtual channel layer 281 and the second virtual channel layer 282 can both be oxide materials. The virtual channel structure is used to support the stack layer 23 to avoid collapse in the subsequent metal replacement process. The first air gap 29 in the virtual channel structure 28 is located above the first sacrificial layer 21 to avoid damage to the virtual channel structure in the subsequent process of removing the first sacrificial layer 21.

[0081] Optionally, the stack layer 23 includes interlayer insulating layers 232 and third sacrificial layers 231 alternately stacked in a direction perpendicular to the top surface of the substrate 20. Before the substrate 20 and the second sacrificial layer 10 are removed, the method further includes the following steps:

[0082] forming a gate line separation groove 30 extending through at least the stack layer 23 and the first sacrificial layer 21, as shown in Figure 2M ;

[0083] removing the third sacrificial layer 231 along the gate line separation groove 30 to form an air gap region 33 between two adjacent interlayer insulating layers 232, as shown in Figure 2G ;

[0084] filling the air gap region 33 with a conductive material to form a gate layer 233, as shown in Figure 2H .

[0085] Specifically, the gate line separation groove 30 can be formed by a dry etching process, and extends through the stack layer 23 and the first sacrificial layer 21 and into the substrate 20, as shown in Figure 2I . Then, the following metal replacement steps are performed: removing the third sacrificial layer 231 in the stack layer 23 to form an air gap region 33 between two adjacent interlayer insulating layers 232; filling the air gap region 33 with a conductive material such as tungsten to form a gate layer 233, as shown in Figure 2J . The gate layer 233 and the interlayer insulating layer 232 alternately stacked in a direction perpendicular to the top surface of the substrate 20 form a stack structure 40.

[0086] Optionally, after the gate layer 233 is formed, the method further includes the following steps:

[0087] forming a gate line separation groove filling layer 31 filling the gate line separation groove 30, as shown in Figure 2H .

[0088] Specifically, first, etch part of the gate layer 233 along the gate line isolation groove 30 to form an opening at the end of the gate layer 233, which is in communication with the gate isolation groove 30, so as to sufficiently isolate the two adjacent gate layers 233. Then, form a first sub-insulating layer 311 which fills the opening and covers the sidewall of the gate isolation groove 30. Then, form a second sub-insulating layer 312 which covers the surface of the first sub-insulating layer 311 and fills the gate isolation groove 30, as shown in FIG. 3D. The first sub-insulating layer 311 and the second sub-insulating layer 312 together form the gate line isolation groove filling layer 31. The material of the first sub-insulating layer 311 and the second sub-insulating layer 312 can be oxide material. The gate line isolation groove filling layer 31 is used to avoid the leakage between the adjacent gate layers 233 and the leakage caused by subsequent processes, and is also used to balance the stress inside the three-dimensional memory and reduce the probability of warping of the three-dimensional memory. Figure 2J

[0089] Optionally, the specific steps of removing the substrate 20 and the second sacrificial layer 10 include:

[0090] using the first sacrificial layer 21 as a grinding stop layer and removing the substrate 20 and part of the second sacrificial layer 10 by a chemical mechanical grinding process, as shown in FIG. 4D. Figure 2K

[0091] Optionally, after using the first sacrificial layer 21 as a grinding stop layer and removing the substrate 20 and part of the second sacrificial layer 10 by a chemical mechanical grinding process, the method further includes the following steps:

[0092] removing the remaining second sacrificial layer 10 by a wet etching process, as shown in FIG. 4E. Figure 2K

[0093] Step S16, remove part of the storage structure 25 and part of the first sacrificial layer 21, and the remaining first sacrificial layer 21 forms an isolation layer 22, as shown in FIG. 5D. Figure 2L

[0094] Optionally, the specific steps of removing part of the storage structure 25 and part of the first sacrificial layer 21 include:

[0095] remove the blocking layer 251, the charge trapping layer 252 and the tunneling layer 253 in the exposed storage structure 25, and at the same time remove part of the first sacrificial layer 21, expose the channel layer 254, and the remaining first sacrificial layer 21 forms an isolation layer 22.

[0096] ​​​​Specifically, by using a proper etching agent, the first sacrificial layer 21 and the exposed barrier layer 251, the charge trapping layer 252 and the tunneling layer 253 in the storage structure 25 are removed by a one-step etching process, so as to expose the channel layer 254 at the bottom of the storage structure 25. Since there is no etching stop layer in the direction along the axis of the channel hole 24 (i.e. the direction from the bottom of the channel hole 24 to the top of the channel hole 24), and there is only an etching stop layer in the radial direction of the channel hole 24 (i.e. the channel layer 254), it is necessary to precisely control the etching parameters so as to remove the first sacrificial layer 21 sufficiently without damaging the isolation layer 22.

[0097] Step S17, forming a semiconductor layer 32 covering the isolation layer 22 and electrically connected with the storage structure 25, as shown in Figure 2M

[0098] Optionally, the specific steps of forming the semiconductor layer 32 covering the isolation layer 22 and electrically connected with the storage structure 25 include:

[0099] Implanting doping ions into the exposed channel layer 254, as shown in Figure 2N

[0100] Depositing polysilicon on the surface of the isolation layer 22 and the surface of the channel layer 254 after implanting the doping ions, to form the semiconductor layer 32.

[0101] Specifically, the doping ions are implanted into the exposed channel layer 254 to reduce the GIDL (Gate Induced Drain Leakage) phenomenon. Then, polysilicon is deposited on the surface of the isolation layer 22 and the surface of the channel layer 254 after implanting the doping ions, and the semiconductor layer 32 is formed after annealing. The semiconductor layer 32 is used to lead out the electrical connection contact of the storage structure 25.

[0102] After forming the semiconductor layer 32, an insulating material can also be deposited to form a cap layer covering the semiconductor layer 32, so as to avoid damage to the semiconductor layer 32 in subsequent processes. The material of the cap layer can be an oxide material, such as silicon dioxide.

[0103] Furthermore, the specific embodiment also provides a three-dimensional memory. The structure of the three-dimensional memory in the specific embodiment of the present application is shown in Figure 2P The three-dimensional memory provided by the specific embodiment can be formed by using the forming method of the three-dimensional memory as shown in Figure 2O , Figure 3 Figure 1 , and the like.​​​Figures 2A-2P Figures 2A-2P Figure 3 The three-dimensional memory is shown to include:

[0104] a semiconductor layer 32;

[0105] an isolation layer 22 located above the semiconductor layer 32;

[0106] a stack structure 40 located above the isolation layer 22, the stack structure 40 including therein a memory structure 25 extending through the stack structure 40, the memory structure 25 including, from outside to inside, a blocking layer 251, a charge trapping layer 252, a tunneling layer 253, and a channel layer 254, the channel layer 254 extending into the semiconductor layer 32, and a bottom surface of the blocking layer 251, a bottom surface of the charge trapping layer 252, and a bottom surface of the tunneling layer 253 being flush with a bottom surface of the isolation layer 22.

[0107] Optionally, the three-dimensional memory further includes:

[0108] a dummy channel structure 28 extending through the stack structure 40 and the isolation layer 22, and a bottom surface of the dummy channel structure 28 being flush with the bottom surface of the isolation layer 22.

[0109] Optionally, the dummy channel structure further includes:

[0110] a first air gap 29, a bottom surface of the first air gap 29 being located below a top surface of the isolation layer 22, and a top surface of the first air gap 29 being located below a top surface of the stack structure 40.

[0111] Optionally, the three-dimensional memory further includes:

[0112] a gate line slot filling layer 31 extending through the stack structure 40 and the isolation layer 22, and a bottom surface of the gate line slot filling layer 31 being flush with the bottom surface of the isolation layer 22.

[0113] Optionally, the gate line slot filling layer 31 further includes:

[0114] a second air gap 33, a bottom surface of the second air gap 33 being located below a top surface of the isolation layer 22, and a top surface of the second air gap 33 being located below a top surface of the stack structure 40.

[0115] The three-dimensional memory and the forming method thereof provided by the embodiment only form a first sacrificial layer between the substrate and the stack layer, simplify the process of the three-dimensional memory, and reduce the manufacturing cost of the three-dimensional memory. The second sacrificial layer is formed at the bottom of the channel hole before the storage structure is formed, the depth of the storage structure is adjusted through the second sacrificial layer, the uniformity of the depth of the storage structure is improved, the requirement for the uniformity of the etching depth of the channel hole is reduced, the process steps are simplified, and the forming cost of the three-dimensional memory is reduced. The substrate and the storage structure are isolated by the second sacrificial layer, the damage of the back surface processing of the wafer to the bottom of the storage structure is avoided, and the performance of the three-dimensional memory is improved.

[0116] The above description is only the preferred embodiment of the present application, and it should be pointed out that the ordinary skilled in the art can make several improvements and refinements without departing from the principles of the present application, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A method of forming a three-dimensional memory, comprising: The method comprises the following steps: providing a substrate; forming a first sacrificial layer above the substrate, a stack layer above the first sacrificial layer, and a plurality of channel holes at least through the stack layer and the first sacrificial layer; forming a second sacrificial layer at the bottom of each channel hole, so that the top surface of the second sacrificial layer is above the top surface of the substrate and below the top surface of the first sacrificial layer, and the bottom surface of the second sacrificial layer is below the top surface of the substrate; forming a storage structure above the second sacrificial layer in the channel hole; removing the substrate and the second sacrificial layer to expose part of the storage structure; removing part of the storage structure and part of the first sacrificial layer, and the remaining first sacrificial layer forms an isolation layer, and there is a height difference between the bottom surfaces of the channel layers in the plurality of remaining storage structures; forming a semiconductor layer directly covering the isolation layer and electrically connected with the storage structure.

2. The method of claim 1, wherein The specific step of forming a second sacrificial layer at the bottom of the channel hole comprises: epitaxially growing the second sacrificial layer at the bottom of the channel hole.

3. The method of claim 1, wherein The material of the second sacrificial layer is single crystal silicon.

4. The method of claim 1, wherein The specific step of forming a storage structure above the second sacrificial layer in the channel hole comprises: forming, in the channel hole, a blocking layer, a charge trapping layer, a tunneling layer and a channel layer in turn along the radial direction of the channel hole.

5. The method of claim 1, wherein Before removing the substrate and the second sacrificial layer, the method further comprises the following steps: forming a virtual channel hole extending through the stack layer and the first sacrificial layer and extending into the substrate; forming a virtual channel structure in the virtual channel hole, and a first air gap in the virtual channel structure is above the first sacrificial layer.

6. The method of claim 1, wherein The stack layer comprises interlayer insulating layers and third sacrificial layers alternately stacked in a direction perpendicular to the top surface of the substrate; before removing the substrate and the second sacrificial layer, the method further comprises the following steps: forming a gate line slot at least through the stack layer and the first sacrificial layer; removing the third sacrificial layer along the gate line slot to form an air gap region between two adjacent interlayer insulating layers; and filling a conductive material in the air gap region to form a gate layer.

7. The method of claim 6, wherein After forming the gate layer, the method further comprises the following steps: forming a gate line slot filling layer filling the gate line slot.

8. The method of claim 1, wherein The specific step of removing the substrate and the second sacrificial layer comprises: using a chemical mechanical polishing process to remove the substrate and part of the second sacrificial layer with the first sacrificial layer as a polishing stop layer.

9. The method of claim 8, wherein After removing the substrate and part of the second sacrificial layer with the first sacrificial layer as a polishing stop layer by using a chemical mechanical polishing process, the method further comprises the following steps: removing the remaining second sacrificial layer by using a wet etching process.

10. The method of claim 4, wherein The specific step of removing part of the storage structure and part of the first sacrificial layer comprises: removing the blocking layer, the charge trapping layer and the tunneling layer in the exposed storage structure, and at the same time removing part of the first sacrificial layer, exposing the channel layer, and the remaining first sacrificial layer forming an isolation layer.

11. The method of claim 10, wherein The specific step of forming a semiconductor layer covering the isolation layer and electrically connected with the storage structure comprises: implanting a doping ion to the exposed channel layer; depositing polysilicon on the surface of the isolation layer and the surface of the channel layer after implanting the doping ion, forming the semiconductor layer.

12. A three-dimensional memory, comprising: comprising: a semiconductor layer; an isolation layer above the semiconductor layer; a stack structure above the isolation layer, the stack structure comprising a plurality of storage structures penetrating through the stack structure, the storage structure comprising, from outside to inside, a blocking layer, a charge trapping layer, a tunneling layer and a channel layer, the channel layer extending into the semiconductor layer, and the bottom surface of the blocking layer, the bottom surface of the charge trapping layer and the bottom surface of the tunneling layer being flush with the bottom surface of the isolation layer, the bottom surfaces of the channel layers in the plurality of storage structures having a height difference, and the semiconductor layer directly covering the surface of the isolation layer away from the stack structure.

13. The three-dimensional memory as recited in claim 12, further comprising: further comprising: a dummy channel structure penetrating through the stack structure and the isolation layer, and the bottom surface of the dummy channel structure being flush with the bottom surface of the isolation layer.

14. The three-dimensional memory as recited in claim 13, further comprising: the dummy channel structure further comprising: a first air gap, the bottom surface of the first air gap being below the top surface of the isolation layer, and the top surface of the first air gap being below the top surface of the stack structure.

15. The three-dimensional memory as recited in claim 12, further comprising: further comprising: a gate line slot filling layer penetrating through the stack structure and the isolation layer, and the bottom surface of the gate line slot filling layer being flush with the bottom surface of the isolation layer.

16. The three-dimensional memory as recited in claim 15, further comprising: the gate line slot filling layer further comprising: a second air gap, the bottom surface of the second air gap being below the top surface of the isolation layer, and the top surface of the second air gap being below the top surface of the stack structure.

Images