Hemt device, wafer, packaged device, and electronic device

Abstract

The application is suitable for the technical field of semiconductors, and provides a HEMT device, a wafer, a packaged device and an electronic device. The HEMT device comprises a substrate, a nitride epitaxial layer, a gate structure layer, a field plate layer, a first drain electrode, a second drain electrode and a first insulating medium layer. The gate structure layer comprises a first semiconductor layer. The first insulating medium layer covers a second surface and part of a first surface of the gate structure layer. The thickness of the first insulating medium layer is less than the thickness of the first semiconductor layer. The field plate layer comprises a first gate field plate (GFP) and a first GFP extension metal. The first GFP covers part of the first surface of the gate structure layer, and a second surface and part of the first surface of the first insulating medium layer. The first GFP extension metal is symmetrically distributed on both sides of the first GFP and covers part of the first surface of the first insulating medium layer. The channel electric field can be optimized while bidirectional turn-off is achieved. The cell size of the HEMT device can be further reduced, the channel resistance of the device can be reduced, and the on-resistance of the HEMT device can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a HEMT device, wafer, packaging device and electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, gallium nitride (GaN) material, with its wider bandgap, higher breakdown field strength, and higher electron mobility, is gradually replacing silicon (Si) material, which has reached its physical limits, becoming a new material for manufacturing semiconductor devices in the field of power semiconductor technology, and has great application prospects in the field of power integrated circuits (PIC). Meanwhile, such as Figure 1 As shown, normally-off gallium nitride high electron mobility transistor (HEMT) devices made of GaN material have no parasitic PN diodes. In the event of bidirectional overvoltage or bidirectional overcurrent, normally-off gallium nitride HEMT devices can effectively protect the circuit itself.

[0003] However, for the normally-off gallium nitride (HEMT) devices mentioned above, as the voltage specifications of applications decrease and the size of HEMT devices continues to shrink, the gate length of HEMT devices shortens. This leads to an increase in the electric field strength in the channel below the gate at the same voltage. Furthermore, HEMT devices lack parasitic PN diodes at the junction, making the short-channel effect caused by drain-induced barrier lowering (DIBL) more pronounced compared to metal-oxide-semiconductor (MOS) devices made of Si. This results in a sharp decrease in the breakdown voltage of HEMT devices. Therefore, in low- and medium-voltage applications, to suppress the short-channel effect of HEMT devices, the gate length cannot be shortened proportionally with the device size reduction. This is necessary to ensure that HEMT devices meet the short-channel limit and breakdown voltage requirements.

[0004] Therefore, due to the aforementioned short-channel effect, in order to meet a certain withstand voltage, as the size of HEMT devices continues to shrink, the ratio of the gate length to the cell feature size length of HEMT devices will continue to increase, leading to an increase in HEMT channel resistance. This, in turn, affects the on-resistance of normally-off gallium nitride HEMT devices and thus impacts their power consumption. Summary of the Invention

[0005] This application provides a HEMT device, wafer, packaged device, and electronic device to reduce the on-resistance of existing HEMT devices and reduce the power loss of circuits fabricated from HEMT devices while meeting certain withstand voltage requirements.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] In a first aspect, a HEMT device is provided, comprising: a substrate, a nitride epitaxial layer, a gate structure layer, a field plate layer, a first drain electrode, a second drain electrode, and a first insulating dielectric layer;

[0008] The nitride epitaxial layer is disposed on the substrate, the gate structure layer, the first drain electrode, the second drain electrode and the first insulating dielectric layer are disposed on the first surface of the nitride epitaxial layer, the first surface of the nitride epitaxial layer is the surface of the nitride epitaxial layer away from the substrate, and the first drain electrode and the second drain electrode are symmetrically distributed on both sides of the gate structure layer.

[0009] The gate structure layer includes: a first semiconductor layer, wherein the first semiconductor layer is formed of a p-type nitride;

[0010] The first insulating dielectric layer covers the second surface and part of the first surface of the gate structure layer. The first surface of the gate structure layer is the surface of the gate structure layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the gate structure layer intersects with the first surface of the gate structure layer. The thickness of the first insulating dielectric layer is less than the thickness of the first semiconductor layer.

[0011] The field plate layer includes: a first gate field plate GFP and a first GFP extended metal. The first GFP covers a portion of the first surface of the gate structure layer, as well as the second surface and a portion of the first surface of the first insulating dielectric layer. The first GFP extended metal is symmetrically distributed on both sides of the first GFP and covers a portion of the first surface of the first insulating dielectric layer. The first surface of the first insulating dielectric layer is the surface of the first insulating dielectric layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the first insulating dielectric layer intersects with the first surface of the first insulating dielectric layer.

[0012] The HEMT device achieves bidirectional turn-off by symmetrically arranging the first and second drain electrodes. The gate field plate composed of the first GFP and the first GFP extended metal improves the channel electric field distribution and suppresses the short-channel effect. This allows the HEMT device to further reduce the gate length while meeting the breakdown voltage requirements, thereby reducing the channel resistance and cell size of the HEMT device, and further reducing the on-resistance and power consumption of the HEMT device.

[0013] In a first possible implementation of the first aspect, the first GFP is connected to the first GFP extension metal, and the area of ​​the field plate layer in contact with the second surface of the first insulating dielectric layer is smaller than the area of ​​the second surface of the gate structure layer in contact with the first insulating dielectric layer.

[0014] By changing the connection method between the first GFP and the first GFP extended metal, the area of ​​the gate field plate composed of the first GFP and the first GFP extended metal is reduced, thereby reducing the gate capacitance and gate charge of the HEMT device, and thus improving the high-frequency characteristics of the HEMT device.

[0015] In a second possible implementation of the first aspect, the first GFP is arranged with the first GFP extended metal spacer.

[0016] By arranging the first GFP and the first GFP extended metal at intervals, the edge electric field of the first semiconductor layer can be further optimized while reducing the gate capacitance and gate charge of the HEMT device, thereby improving the breakdown characteristics of the HEMT device.

[0017] In a third possible implementation of the first aspect, the HEMT device further includes: a second insulating dielectric layer;

[0018] The second insulating dielectric layer covers the first and second surfaces of the first GFP, the first surface of the first GFP extended metal, and the first surface of the first insulating dielectric layer. The first surface of the first GFP is the surface of the first GFP that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the first GFP intersects with the first surface of the first GFP. The first surface of the first GFP extended metal is the surface of the first GFP extended metal that is away from the substrate and parallel to the first surface of the nitride epitaxial layer.

[0019] The field plate layer further includes: a second GFP and a second GFP extended metal;

[0020] The second GFP covers the second surface and part of the first surface of the second insulating dielectric layer, the second GFP extended metal covers part of the first surface of the second insulating dielectric layer, the second GFP extended metal is symmetrically distributed on both sides of the second GFP, the first surface of the second insulating dielectric layer is the surface of the second insulating dielectric layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer, and the second surface of the second insulating dielectric layer intersects with the first surface of the second insulating dielectric layer.

[0021] The second insulating dielectric layer is provided with a first etching window, and the second GFP is electrically connected to the first GFP through the first etching window.

[0022] By adding a second insulating dielectric layer, a second GFP, and a second GFP extended metal to the first GFP and the first GFP extended metal, the second GFP and the second GFP extended metal can form an inverted U-shaped gate field plate structure. Combined with the inverted U-shaped composite gate field plate structure formed by the first GFP and the first GFP extended metal, the channel electric field distribution and the electric field distribution at the edge of the gate field plate of the HEMT device can be further improved, the short-channel effect can be suppressed, and thus the breakdown voltage of the HEMT device can be improved.

[0023] Based on any of the above possible implementations of the first aspect, in the fourth possible implementation of the first aspect, the gate structure layer further includes: gate metal;

[0024] The gate metal covers the first surface of the first semiconductor layer, and the first surface of the first semiconductor layer is the surface of the first semiconductor layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer;

[0025] The first insulating dielectric layer is provided with a second etching window, and the first GFP is electrically connected to the gate metal through the second etching window.

[0026] By using gate metal as an etching baffle for the gate structure layer, a gate-first self-alignment process can be achieved, which helps to improve the uniformity and accuracy of the etched image.

[0027] Based on the fourth possible implementation of the first aspect described above, in the fifth possible implementation of the first aspect, the gate structure layer further includes: a second semiconductor layer;

[0028] The second semiconductor layer is located on the first surface of the first semiconductor layer, and the projected area of ​​the second semiconductor layer on the nitride epitaxial layer is smaller than the projected area of ​​the first semiconductor layer on the nitride epitaxial layer.

[0029] The gate metal covers a portion of the first surface of the first semiconductor layer, as well as the first and second surfaces of the second semiconductor layer. The first surface of the second semiconductor layer is the surface of the second semiconductor layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the second semiconductor layer intersects with the first surface of the second semiconductor layer.

[0030] By combining the inverted T-shaped gate structure layer and the inverted U-shaped gate field plate extending from the first GFP to both sides, the electric field distribution at the edge of the gate structure layer can be improved, the short-channel effect can be suppressed, and the HEMT device can meet the breakdown voltage requirements. At the same time, the inverted T-shaped gate structure layer can make the HEMT device have a higher concentration of two-dimensional electron gas (2DEG) and a lower channel resistance at the same gate voltage when it is turned on, thereby reducing the on-resistance of the HEMT device.

[0031] Based on the fifth possible implementation of the first aspect described above, in the sixth possible implementation of the first aspect, the gate structure layer further includes: an etch barrier layer;

[0032] The etching barrier layer is located on the first surface of the first semiconductor layer, and the projected area of ​​the etching barrier layer on the nitride epitaxial layer is equal to the projected area of ​​the first semiconductor layer on the nitride epitaxial layer.

[0033] The second semiconductor layer is located on the first surface of the etch barrier layer, and the first surface of the etch barrier layer is the surface of the etch barrier layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer;

[0034] The gate metal covers a portion of the first surface of the etch barrier layer, as well as the first and second surfaces of the second semiconductor layer.

[0035] By inserting an intercalation layer with a higher aluminum (Al) content between different p-type semiconductor layers as an etching termination layer, the difficulty of process implementation can be reduced and the accuracy of etching thickness control can be improved.

[0036] Based on the fifth or sixth possible implementation of the first aspect, in the seventh possible implementation of the first aspect, the centerline of the projection of the second semiconductor layer onto the nitride epitaxial layer coincides with the centerline of the projection of the first semiconductor layer onto the nitride epitaxial layer.

[0037] Based on the fifth, sixth, or seventh possible implementation of the first aspect, in the eighth possible implementation of the first aspect, the gate structure layer further includes: a third insulating dielectric layer;

[0038] The third insulating dielectric layer covers a portion of the first surface of the first semiconductor layer or a portion of the first surface of the etching barrier layer, and covers the second surface and a portion of the first surface of the second semiconductor layer;

[0039] The gate metal covers a portion of the first surface of the second semiconductor layer, as well as the first and second surfaces of the third insulating dielectric layer. The first surface of the third insulating dielectric layer is the surface of the third insulating dielectric layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the third insulating dielectric layer intersects with the first surface of the third insulating dielectric layer.

[0040] Compared to the HEMT devices shown in the fifth and sixth possible embodiments, by providing a third insulating dielectric layer, which isolates a portion of the first semiconductor layer and a portion of the second semiconductor layer from the gate metal, the increase in gate leakage caused by the thinner first semiconductor layer can be reduced.

[0041] Based on the fourth possible implementation of the first aspect described above, in the ninth possible implementation of the first aspect, the HEMT device further includes: a fourth insulating dielectric layer;

[0042] The fourth insulating dielectric layer covers a portion of the first surface of the nitride epitaxial layer, and the fourth insulating dielectric layer is distributed on both sides of the gate structure layer and is spaced apart from the gate structure layer;

[0043] The first insulating dielectric layer covers a portion of the first surface of the fourth insulating dielectric layer, the nitride epitaxial layer, and the first and second surfaces of the gate structure layer;

[0044] The first GFP is extended metallized with the first GFP;

[0045] The GFP extended metal, the first insulating dielectric layer located on the first surface of the nitride epitaxial layer, and the nitride epitaxial layer together form a metal-insulator-semiconductor (MIS) gate structure, and the MIS gate structure and the gate structure layer form a composite gate structure.

[0046] Compared with the aforementioned possible methods, by using a first semiconductor layer and a gate metal to form a first gate structure layer, and combining it with a MIS gate structure to form a composite gate structure, the electric field distribution at the edge of the gate structure layer can be improved and the short-channel effect can be suppressed under the combined effect of the composite gate structure and the inverted U-shaped gate field plate formed by the first GFP and the first GFP extended metal extending from the GFP to both sides. This enables the HEMT device to meet the breakdown voltage requirements. At the same time, the composite gate structure can enable the HEMT device to have a higher concentration of 2DEG in the channel under the same gate voltage when it is turned on, thereby reducing the on-resistance of the HEMT device.

[0047] Based on the ninth possible implementation of the first aspect described above, in the tenth possible implementation of the first aspect, the nitride epitaxial layer includes: a barrier layer;

[0048] The gate structure layer, the first insulating dielectric layer, and the fourth insulating dielectric layer are all located on the side of the barrier layer away from the substrate;

[0049] The thickness of the barrier layer at the MIS gate structure is less than the thickness of the barrier layer in other regions besides the MIS gate structure.

[0050] Compared to the HEMT device in the ninth possible implementation, forming a recessed gate by etching part of the barrier layer on both sides of the first gate structure layer can partially deplete the two-dimensional electron gas at the heterojunction below the recessed gate, further improving the channel electric field distribution and increasing the breakdown voltage.

[0051] Based on any of the above possible implementations of the first aspect, in the eleventh possible implementation of the first aspect, the substrate is generated from a heteroepitaxial substrate or a homoepitaxial substrate, wherein the heteroepitaxial substrate is made of silicon, sapphire or silicon carbide, and the homoepitaxial substrate is made of gallium nitride.

[0052] By using different substrates, the quality of the epitaxial layers grown on the substrate can be optimized, thereby improving the performance of HEMT devices.

[0053] Based on any of the above possible implementations of the first aspect, in the twelfth possible implementation of the first aspect, the nitride epitaxial layer includes: a nucleation layer disposed on the substrate, a buffer layer disposed on the nucleation layer, a channel layer disposed on the buffer layer, and a barrier layer disposed on the channel layer;

[0054] The nucleation layer is formed from aluminum nitride, the buffer layer is formed from aluminum gallium nitride or gallium nitride, the channel layer is formed from undoped gallium nitride, and the barrier layer is formed from aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride.

[0055] By using different materials to generate multiple epitaxial layers such as nucleation layers, buffer layers, channel layers, and barrier layers, the quality of each epitaxial layer can be optimized, thereby improving the performance of HEMT devices.

[0056] Based on any of the above possible implementations of the first aspect, in the thirteenth possible implementation of the first aspect, the first semiconductor layer, the second semiconductor layer, or the etch barrier layer is formed from gallium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride, or indium aluminum gallium nitride.

[0057] By using different materials to generate the first semiconductor layer, the second semiconductor layer, or the etch barrier layer, the bandgap of the first semiconductor layer, the second semiconductor layer, or the etch barrier layer can be increased, thereby increasing the Schottky barrier height between the metal and the semiconductor, reducing the carrier transition probability between the gate metal and the second semiconductor layer, or between the gate metal and the first semiconductor layer, reducing the gate leakage current of the HEMT device, and improving the withstand voltage capability of the gate semiconductor structure.

[0058] In a second aspect, a composite HEMT device is provided, comprising: a main HEMT device and a common-source HEMT device, wherein the main HEMT device is any of the HEMT devices described in the first aspect;

[0059] The common-source HEMT device includes: a substrate, a nitride epitaxial layer, a first clamped drain, a second clamped drain, a clamped source, a first clamped gate, and a second clamped gate;

[0060] The first drain electrode of the main HEMT device is electrically connected to the first clamp drain of the common-source HEMT device, the second drain electrode of the main HEMT device is electrically connected to the second clamp drain of the common-source HEMT device, and the field plate layer of the main HEMT device is electrically connected to the first clamp gate, the second clamp gate, and the clamp source of the common-source HEMT device.

[0061] By using a GaN HEMT device with symmetrical drain as the main HEMT device and a common-source HEMT device as the gate voltage clamping device for the main HEMT device, gate overvoltage protection is provided for the HEMT device.

[0062] In a first possible implementation of the second aspect, the first clamping gate, the second clamping gate, and the clamping source adopt a recessed gate structure;

[0063] The first clamping gate, the second clamping gate, the clamping source, the first clamping drain, and the second clamping drain together form a common source structure. The first clamping gate and the second clamping gate are symmetrically distributed on both sides of the clamping source, and the first clamping drain and the second clamping drain are symmetrically distributed on both sides of the clamping source.

[0064] Based on any of the above possible implementations of the second aspect, in the second possible implementation of the second aspect, the nitride epitaxial layer includes: a nucleation layer epitaxial on the substrate, a buffer layer epitaxial on the nucleation layer, a channel layer epitaxial on the buffer layer, and a barrier layer disposed on the channel layer.

[0065] The common-source HEMT device further includes: a fifth insulating dielectric layer and a sixth insulating dielectric layer, wherein the fifth insulating dielectric layer covers the first surface of the barrier layer other than the first clamped drain, the second clamped drain, the first clamped gate, the second clamped gate and the clamped source, and the sixth insulating dielectric layer covers the first surface and the second surface of the nitride epitaxial layer located at the first clamped gate and the second clamped gate;

[0066] The thickness of the barrier layer located at the first clamping gate and the second clamping gate is less than the thickness of the barrier layer in other regions.

[0067] By etching the fifth insulating dielectric layer and the barrier layer, and filling the gate dielectric, a concave-gate GaN MIS-HEMT device is formed, giving the HEMT device a higher threshold voltage. As a common-source clamped HEMT device, a single common-source HEMT device can effectively clamp a gate voltage of 5 volts (V) or higher. Furthermore, by adjusting the thickness of the barrier layer and the gate dielectric in the first and second concave gates, the clamping voltage between the gate and the first drain, or between the gate and the second drain, of the main HEMT device can be effectively adjusted to meet different clamping requirements. The purpose of symmetrically distributing the first and second clamping drains on both sides of the clamping source is to give the HEMT device a gate voltage clamping characteristic that is substantially symmetrical at both ends.

[0068] Thirdly, a wafer is provided that includes a HEMT device as described in either the first or second aspect.

[0069] Fourthly, a packaging device is provided, the packaging device comprising a HEMT device as described in either the first or second aspect.

[0070] By adding the HEMT device described in either the first or second aspect to the packaged device, the conduction loss of the device can be further reduced, based on the fact that the packaged switching device has bidirectional blocking function.

[0071] Fifthly, an electronic device is provided, the electronic device comprising a HEMT device as described in either the first or second aspect.

[0072] By adding the HEMT device described in either the first or second aspect to the electronic device, the circuit conduction loss of the electronic device can be further reduced and the charging efficiency can be improved, in addition to providing bidirectional overvoltage or bidirectional overcurrent protection for the electronic device.

[0073] A sixth aspect provides an electronic device comprising: a charging integrated circuit, a wired charging interface, and at least one HEMT device as described in either the first or second aspect, wherein the at least one HEMT device comprises: a first HEMT device;

[0074] The gate of the first HEMT device is connected to the first control terminal of the charging integrated circuit, the first drain electrode of the first HEMT device is connected to the wired charging interface, and the second drain electrode of the first HEMT device is connected to the input terminal of the charging integrated circuit.

[0075] The output terminal of the charging integrated circuit is connected to the battery.

[0076] By adding the HEMT device described in either the first or second aspect to the electronic device, during the wired charging process, not only can bidirectional overvoltage or bidirectional overcurrent protection be provided for the wired charging link, but the conduction loss of the wired charging link can also be further reduced, thereby improving charging efficiency.

[0077] In a first possible implementation of the sixth aspect, the electronic device further includes: a wireless receiving integrated circuit, a wireless charging coil, and at least one of the HEMT devices further includes: a second HEMT device;

[0078] The gate of the second HEMT device is connected to the second control terminal of the charging integrated circuit, the first drain electrode of the second HEMT device is connected to the wireless charging coil through the wireless receiving integrated circuit, and the second drain electrode of the second HEMT device is connected to the input terminal of the charging integrated circuit.

[0079] By adding the HEMT device described in either the first or second aspect to the electronic device, during the wireless charging process, not only can bidirectional overvoltage or bidirectional overcurrent protection be provided for the wireless charging link, but the conduction loss of the wireless charging link can also be further reduced, thereby improving charging efficiency. Attached Figure Description

[0080] Figure 1 This is a cross-sectional schematic diagram of a normally-off gallium nitride HEMT device in the prior art;

[0081] Figure 2 This is a cross-sectional schematic diagram of a Si MOS device in the prior art;

[0082] Figure 3A This is a cross-sectional schematic diagram of a HEMT device made of GaN material in related technologies;

[0083] Figure 3BThis is an equivalent circuit diagram of a HEMT device made of GaN material in related technologies;

[0084] Figure 4 This is a schematic diagram of the system architecture involved in a HEMT device provided in an embodiment of this application;

[0085] Figure 5A This is a schematic diagram of a packaged HEMT device according to an embodiment of this application;

[0086] Figure 5B This is a schematic diagram of the surface ball arrangement of a packaged HEMT device according to an embodiment of this application;

[0087] Figure 6A This is a cross-sectional schematic diagram of a HEMT device provided in an embodiment of this application;

[0088] Figure 6B This is a top view schematic diagram of a HEMT device provided in an embodiment of this application;

[0089] Figure 6C This is a process flow diagram of a HEMT device fabrication provided in an embodiment of this application;

[0090] Figure 6D This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0091] Figure 6E This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0092] Figure 6F This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0093] Figure 6G This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0094] Figure 6H This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0095] Figure 6I This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0096] Figure 6J This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0097] Figure 6KThis is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0098] Figure 6L This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0099] Figure 6M This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0100] Figure 6N This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0101] Figure 6O This is a schematic diagram of the structure of a HEMT device during the manufacturing process provided in an embodiment of this application;

[0102] Figure 6P This is a schematic diagram of a simulation structure of an HEMT device provided in an embodiment of this application;

[0103] Figure 6Q This is a simulation curve of the breakdown voltage from the first drain electrode to the second drain electrode of a HEMT device provided in an embodiment of this application;

[0104] Figure 6R This is a simulation curve of the breakdown voltage from the second drain electrode to the first drain electrode of a HEMT device provided in an embodiment of this application;

[0105] Figure 6S This is a simulation curve of the threshold voltage of a HEMT device provided in an embodiment of this application;

[0106] Figure 6T This is a simulation curve of the output characteristics of a HEMT device provided in an embodiment of this application;

[0107] Figure 7A This is a three-dimensional schematic diagram of another HEMT device provided in the embodiments of this application;

[0108] Figure 7B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0109] Figure 8A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0110] Figure 8B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0111] Figure 8CThis is a three-dimensional schematic diagram of another HEMT device provided in the embodiments of this application;

[0112] Figure 9A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0113] Figure 9B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0114] Figure 9C This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0115] Figure 9D This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0116] Figure 9E This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0117] Figure 10A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0118] Figure 10B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0119] Figure 10C This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0120] Figure 10D This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0121] Figure 10E This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0122] Figure 11A This is a three-dimensional schematic diagram of another HEMT device provided in the embodiments of this application;

[0123] Figure 11B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0124] Figure 12A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0125] Figure 12B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0126] Figure 12C This is a three-dimensional schematic diagram of another HEMT device provided in the embodiments of this application;

[0127] Figure 13A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0128] Figure 13B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0129] Figure 13C This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0130] Figure 13D This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0131] Figure 13E This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0132] Figure 14A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0133] Figure 14B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application;

[0134] Figure 14C This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0135] Figure 14D This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0136] Figure 14E This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0137] Figure 14F This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0138] Figure 14G This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0139] Figure 14H This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0140] Figure 14I This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0141] Figure 14J This is a schematic diagram of another HEMT device simulation structure provided in the embodiments of this application;

[0142] Figure 14K This is a simulation curve of the breakdown voltage from the first drain electrode to the second drain electrode of another HEMT device provided in the embodiments of this application;

[0143] Figure 14L This is a simulation curve of the breakdown voltage from the second drain electrode to the first drain electrode of another HEMT device provided in the embodiments of this application;

[0144] Figure 14M This is a simulation curve of the threshold voltage of another HEMT device provided in the embodiments of this application;

[0145] Figure 14N This is a simulation curve of the output characteristics of another HEMT device provided in the embodiments of this application;

[0146] Figure 14O This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0147] Figure 14P This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0148] Figure 14Q This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0149] Figure 14R This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0150] Figure 14S This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0151] Figure 15A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0152] Figure 15B This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0153] Figure 15C This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0154] Figure 15DThis is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0155] Figure 16A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0156] Figure 16B This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0157] Figure 16C This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0158] Figure 16D This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0159] Figure 16E This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0160] Figure 16F This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0161] Figure 16G This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0162] Figure 16H This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0163] Figure 16I This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0164] Figure 16J This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0165] Figure 17A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application;

[0166] Figure 17B This is a schematic diagram of the structure of a HEMT device during the manufacturing of another HEMT device according to an embodiment of this application;

[0167] Figure 18 This is an equivalent circuit diagram of a composite HEMT device provided in an embodiment of this application;

[0168] Figure 19A This is a cross-sectional schematic diagram of a common-source HEMT device provided in an embodiment of this application;

[0169] Figure 19B This is a top view schematic diagram of a composite HEMT device composed of gate-clamped common-source HEMT devices provided in the embodiments of this application;

[0170] Figure 19C This is a process flow diagram of a common-source HEMT device provided in an embodiment of this application;

[0171] Figure 19D This is a schematic diagram of the structure of a composite HEMT device with gate clamp common-source HEMT device provided in the embodiments of this application;

[0172] Figure 19E This is a schematic diagram of the structure of a composite HEMT device with gate clamp common-source HEMT device provided in the embodiments of this application;

[0173] Figure 19F This is a schematic diagram of the structure of a composite HEMT device with gate clamp common-source HEMT device provided in the embodiments of this application;

[0174] Figure 19G This is a schematic diagram of the structure of a composite HEMT device with gate clamp common-source HEMT device provided in the embodiments of this application;

[0175] Figure 19H This is a schematic diagram of the structure of a composite HEMT device with gate clamp common-source HEMT device provided in the embodiments of this application;

[0176] Figure 19I This is a schematic diagram of a common-source HEMT device simulation structure provided in an embodiment of this application;

[0177] Figure 19J This is a simulation curve of the breakdown voltage from the first clamped drain to the second clamped drain of a common-source HEMT device provided in an embodiment of this application;

[0178] Figure 19K This is a simulation curve of the breakdown voltage from the second clamp drain to the first clamp drain of a common-source HEMT device provided in an embodiment of this application;

[0179] Figure 19L This is a simulation curve of the clamping voltage from the first clamping drain to the second clamping drain of a common-source HEMT device provided in this application embodiment;

[0180] Figure 19M This is a simulation curve of the clamping voltage from the second clamp drain to the first clamp drain of a common-source HEMT device provided in this application embodiment. Detailed Implementation

[0181] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known semiconductor devices and circuits have been omitted so as not to obscure the description of this application with unnecessary detail.

[0182] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “the,” “the,” and “the” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise.

[0183] First, the principle of the bidirectional switching device involved in the embodiments of this application will be introduced. The bidirectional switching device is a power switching device, and the two directions of the bidirectional switching device, from source to drain and from drain to source, have similar turn-off functions. Existing bidirectional switching devices are mainly composed of MOS devices (hereinafter referred to as Si MOS devices) made of Si material.

[0184] The following explanation uses a Si MOS device as an example to illustrate bidirectional switching devices. (See also...) Figure 2 , Figure 2 This is a cross-sectional schematic diagram of a Si MOS device in the prior art. From bottom to top, the device includes: a p-type substrate layer, a p-type epitaxial layer, a p-type well region, and an n-type drift region. A recessed gate structure is disposed in the n-type drift region, and the gate is in contact with the p-type well region. This p-type well region can serve as the channel of the Si MOS device. Furthermore, drains 1 and 2, which are buried within the n-type drift region, are disposed on the upper surface of the n-type drift region. Drains 1 and 2 can be symmetrically distributed on both sides of the gate.

[0185] In this configuration, the p-type substrate can be grounded, the gate is the control port of the Si MOS device, drain 1 can be the input or output port of the Si MOS device, and drain 2 can be the output or input port of the Si MOS device.

[0186] When the gate of the Si MOS device is high, the channel of the Si MOS device is turned on, and current can flow from drain 1 to drain 2 through the channel, or vice versa. When the gate of the Si MOS device is low, the channel of the Si MOS device is pinched off, and drain 1 and drain 2 form a symmetrical drift region structure. Drain 1 and drain 2 can form an NPN common anode back-to-back diode with the surrounding n-type drift region and p-type channel, thereby achieving bidirectional high voltage withstand capability.

[0187] It should be noted that with the continuous development of semiconductor technology, the on-resistance of bidirectional switching devices fabricated from Si material has reached the physical limit of Si, making it difficult to further reduce the on-resistance. Therefore, it is necessary to seek new materials to replace traditional Si semiconductor materials in order to further reduce the on-resistance of bidirectional switching devices.

[0188] Based on the above problems, related technologies have proposed the following... Figure 3A The bidirectional HEMT device (hereinafter referred to as HEMT device) fabricated from GaN material is shown, as follows: Figure 3A As shown, the gate G, the first input / output electrode D1, and the second input / output electrode D2 of the HEMT device are disposed on the GaN semiconductor layer. The first input / output electrode D1 and the second input / output electrode D2 can be distributed asymmetrically or substantially symmetrically on both sides of the gate G. The gate G is covered with a gate field plate (GFP), which extends horizontally to form a T-shaped gate metal.

[0189] Moreover, see Figure 3B , Figure 3B An equivalent circuit diagram of a HEMT device with gate protection is shown. The HEMT device may also include a first diode Diode 1 and a second diode Diode 2, which are coupled between the first input / output electrode D1 and GFP, and between the second input / output electrode D2 and GFP, respectively.

[0190] The first diode, Diode 1, and the second diode, Diode 2, can be PN diodes or MOS gate HEMT devices, and are used to provide overvoltage protection for the gate G.

[0191] However, compared to bidirectional switching devices made of Si material, HEMT devices do not have a space charge region formed by a PN junction in the channel. This makes the short-channel phenomenon caused by DIBL in HEMT devices more pronounced than in devices made of Si material, resulting in a sharp decrease in the breakdown voltage of HEMT devices.

[0192] In low- and medium-voltage applications, if the gate length of the HEMT device is relatively short, such as Figure 3A The T-type GFP in the HEMT device shown cannot effectively modulate the electric field distribution of the 2DEG in the heterojunction of the HEMT device, making the HEMT device susceptible to short-channel effects, leading to channel punch-through. Figure 3A The HEMT device shown cannot simultaneously meet the requirements of both the withstand voltage (e.g., 40V) and the lower on-resistance of HEMT devices.

[0193] It should be noted that in low- and medium-voltage applications, the on-resistance of HEMT devices is much greater than their theoretical limit, and their advantage over the theoretical limit of Si devices is no longer significant. One of the main limiting factors is the channel resistance of HEMT devices. For example, in low- and medium-voltage applications, in order to adjust the channel electric field distribution and suppress the short-channel effect of HEMT devices, the gate length of the HEMT device needs to meet the short-channel limit requirement. The gate length cannot be shortened proportionally with the shrinkage of HEMT device size, causing the proportion of the gate length to the cell feature size to continuously increase. This leads to an increase in the channel resistance of the HEMT device, thereby affecting its on-resistance and impacting the power consumption of circuits composed of HEMT devices. Consequently, the on-resistance advantage of HEMT devices in low- and medium-voltage applications is no longer significant.

[0194] Therefore, in low-voltage applications, while ensuring that the bidirectional switching device meets a certain withstand voltage, it is also necessary to further reduce the channel resistance of the HEMT device, thereby reducing the on-resistance of the HEMT device and reducing the power loss of the HEMT device.

[0195] The following section uses normally-off HEMT devices as an example to introduce the application scenarios of bidirectional switching devices.

[0196] Figure 4 This is a schematic diagram of a system architecture involved in a HEMT device provided in an embodiment of this application. It is intended as an example and not a limitation. See also Figure 4 The system architecture may include: battery 401, battery protection MOSFET 402, charging integrated circuit (IC) 403, overvoltage protection switch 404, transfer switch 405, universal serial bus (USB) Type C interface 406, wireless receiver IC 407, and wireless charging coil 408.

[0197] Both the overvoltage protection switch 404 and the changeover switch 405 can be constructed from the HEMT device provided in this embodiment. In the overvoltage protection switch 404, the first drain electrode D1 of the HEMT device is connected to the USB Type-C interface 406, the second drain electrode D2 of the HEMT device is connected to the input terminal (IN) of the charging IC 403, and the gate G of the HEMT device is connected to the first overvoltage protection port (OVPG1) of the charging IC 403.

[0198] Furthermore, the first drain electrode D1 of the HEMT device in the changeover switch 405 is connected to the output terminal of the wireless receiver IC 407, the second drain electrode D2 of the HEMT device is also connected to the input terminal (IN) of the charging IC 403, and the gate G of the HEMT device is connected to the second overvoltage protection port (OVPG2) of the charging IC 403.

[0199] Additionally, the output (OUT) of the charging IC 403 can be connected to the battery 401 via the battery protection MOSFET 402, and the input of the wireless receiver IC 407 can be connected to the output of the wireless charging coil 408. It should be noted that the system architecture of the aforementioned HEMT device may or may not include the battery protection MOSFET 402; this application embodiment does not limit this. If the system architecture does not include the battery protection MOSFET 402, then the output (OUT) of the charging IC 403 can be connected to the battery 401. The following description uses a system architecture including the battery protection MOSFET 402 as an example.

[0200] The above system architecture includes a USB Type-C interface 406 for wired charging, as well as a wireless receiver IC 407 and a wireless charging coil 408 for wireless charging. Therefore, during the charging process of the battery 401, either wired charging or wireless charging can be used.

[0201] During wired charging, the first overvoltage protection port (OVPG1) of the charging IC 403 can output a high level. The gate G of the HEMT device in the overvoltage protection switch 404 can receive the high-level signal, which turns on the HEMT device in the overvoltage protection switch 404, so that the battery 401 can be charged through the USB Type C interface 406.

[0202] Furthermore, the second overvoltage protection port (OVPG2) of the charging IC403 can output a low level. The gate G of the HEMT device in the changeover switch 405 can receive this low-level signal, causing the HEMT device in the changeover switch 405 to turn off. This can prevent the charging current flowing through the overvoltage protection switch 404 from flowing back into the changeover switch 405 and the wireless receiver IC407.

[0203] When a voltage surge occurs at the USB Type C interface 406, the first overvoltage protection port (OVPG1) of the charging IC 403 can output a low level. The gate G of the HEMT device in the overvoltage protection switch 404 can then turn off the HEMT device based on this low level, thus preventing the surge voltage from damaging the charging IC 403.

[0204] During the wireless charging process, the second overvoltage protection port (OVPG2) of the charging IC403 can output a high level. The gate G of the HEMT device in the changeover switch 405 can receive the high-level signal, which turns on the HEMT device in the changeover switch 405. Thus, the battery 401 can be charged through the wireless receiver IC407 and the wireless charging coil 408.

[0205] Furthermore, the first overvoltage protection port (OVPG1) of the charging IC 403 can output a low level. The gate G of the HEMT device in the overvoltage protection switch 404 can receive this low-level signal, causing the HEMT device in the overvoltage protection switch 404 to turn off. This can prevent the charging current flowing through the changeover switch 405 from flowing back into the overvoltage protection switch 404 and the USB Type C interface 406.

[0206] It should be noted that, in practical applications, to reduce charging link losses and ensure charging efficiency, the on-resistance of the bidirectional HEMT switching devices used to drive the overvoltage protection switch 404 and the changeover switch 405 is typically required to be extremely low. Additionally, a certain withstand voltage is required between the first drain electrode and the gate, and between the second drain electrode and the gate, to ensure that the HEMT device does not suffer from device breakdown, thus preventing reliability issues.

[0207] Furthermore, the above system architecture can be applied to charging scenarios for handheld electronic devices. For example, it can be used in scenarios where mobile phones or tablets are charged. This application embodiment does not limit the application scenarios of the above system architecture. Further, the HEMT device provided in this application embodiment can also be used in system architectures for charging energy products or wireless switch products, such as in scenarios where terminal adapters are charged. This application embodiment also does not limit the system architecture and scenarios for the application of the HEMT device.

[0208] In practical applications, HEMT devices can be packaged using wafer-level chip packaging (WLCSP) technology to obtain packaged HEMT devices. Correspondingly, the packaged HEMT devices can be used in the aforementioned system architecture as overvoltage protection switches or transfer switches.

[0209] See Figure 5A and Figure 5B , Figure 5A This is a schematic diagram of a packaged HEMT device according to an embodiment of this application. Figure 5B This is a schematic diagram of the surface-mount ball arrangement of a packaged HEMT device. (Example:) Figure 5A As shown, the packaged HEMT device, from bottom to top, may include: a back coating 501, a semiconductor layer 502 containing device feature structures, and surface balls 503 disposed on the opposite side of the semiconductor layer 502 and the back coating 501. The surface balls 503 can be connected to the gate, the first drain electrode, or the second drain electrode of the HEMT device through the under-bump metallization (UBM) layer in the semiconductor layer 502 and each interconnect metal layer, respectively.

[0210] For example, the height of the packaged HEMT device can be approximately 0.5 mm, with the back coating 501 being approximately 0.04 mm thick, the semiconductor layer 502 approximately 0.25 mm thick, and the surface-mount balls 503 approximately 0.2 mm high. The height of the packaged HEMT device is only half that of existing plastic-encapsulated devices. Furthermore, the thermal resistance of the packaged HEMT device is approximately 50 degrees Celsius per watt (°C / W), and its heat dissipation performance is superior to that of plastic-encapsulated devices of the same size.

[0211] Moreover, see Figure 5B , Figure 5B The diagram shows a 2mm*2mm arrangement of 25 balls. The surface-mounted balls 503 are arranged in a 5*5 pattern. By configuring the distribution of the surface-mounted balls 503, the parasitic resistance between the back-end interconnect metal and the HEMT device can be reduced. Specifically, from left to right, the first column can consist entirely of surface-mounted balls 503 (D1) corresponding to the first drain electrode of the HEMT device; the second column can consist entirely of surface-mounted balls 503 (D2) corresponding to the second drain electrode of the HEMT device; the third column retains only the first and fifth rows of surface-mounted balls 503. The first row of the third column can be surface-mounted balls 503 (G) corresponding to the gate electrode of the HEMT device; the fifth row of the third column can be surface-mounted balls 503 (Sub) corresponding to the substrate electrode of the HEMT device. Similar to the first and second columns, the fourth column can consist entirely of surface-mounted balls 503 (D1) corresponding to the first drain electrode of the HEMT device; and the fifth column can consist entirely of surface-mounted balls 503 (D2) corresponding to the second drain electrode of the HEMT device.

[0212] In addition, the semiconductor layer 502 is provided with a HEMT device composed of multiple device feature structures. The semiconductor layer 502 may include: a substrate, a gallium nitride epitaxial layer, a first drain electrode of the HEMT device, a second drain electrode of the HEMT device, a gate structure layer of the HEMT device, a substrate electrode of the HEMT device, an insulating passivation layer, an interconnect metal layer, an intermediate dielectric layer, and a UBM, etc. The substrate, gallium nitride epitaxial layer, and the first drain electrode, second drain electrode, gate structure layer, and substrate electrode of the HEMT device are used to form the HEMT device feature structure; the insulating passivation layer is used to passivate the surface of the barrier layer of the HEMT device and to form electrical insulation between the first drain electrode, second drain electrode, gate structure layer, and substrate electrode of the HEMT device; the interconnect metal layer is used to connect the various electrodes of the HEMT device, the UBM, and the surface ball 503; the UBM is used to house the surface ball 503.

[0213] Furthermore, the semiconductor layer 502 may be provided with a large number of periodically arranged cell structures of HEMT devices with feature sizes on the order of micrometers. Each cell structure may include a gate, a first drain electrode, and a second drain electrode. The gate, first drain electrode, and second drain electrode of each HEMT device can be connected to the UBM through an interconnect metal layer, thereby being connected to the surface ball 503 through the UBM.

[0214] The following describes the HEMT device proposed in the embodiments of this application. The HEMT device may include a field plate layer, a gate structure layer, and an insulating dielectric layer. Figure 6A , Figure 7A , Figure 8A and Figure 9A This illustrates a HEMT device with modifications to the field plate layer. Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A This illustrates a HEMT device with modifications to the gate structure layer within the metal layer. Figure 16A and Figure 17A The HEMT device with a modified insulating dielectric layer is shown.

[0215] For example Figure 3A The HEMT device shown in this application provides a further reduction in on-resistance while ensuring bidirectional blocking and withstand voltage specifications. See [link to relevant documentation]. Figure 6A and Figure 6B , Figure 6A This is a cross-sectional schematic diagram of a HEMT device provided in an embodiment of this application. Figure 6B This is a top view schematic diagram of a HEMT device provided in an embodiment of this application, as shown below. Figure 6A As shown, the HEMT device may include, from bottom to top: a substrate 601, a nucleation layer 602 epitaxially formed on the substrate 601, a buffer layer 603 epitaxially formed on the nucleation layer 602, a channel layer 604 epitaxially formed on the buffer layer 603, and a barrier layer 605 epitaxially formed on the channel layer 604.

[0216] The substrate 601 can be formed from heteroepitaxial materials such as Si, sapphire, or silicon carbide (SiC), or from GaN homoepitaxial substrate materials; the nucleation layer 602 can be formed from aluminum nitride (AlN); the buffer layer 603 can be formed from high-resistivity GaN or from aluminum gallium nitride (AlGaN); the channel layer 604 can be formed from undoped GaN; and the barrier layer 605 can be formed from AlGaN or from aluminum nitride such as indium aluminum nitride (InAlN), so that the barrier layer 605 can form a heterojunction with the channel layer 604.

[0217] Moreover, such as Figure 6A The nucleation layer 602, buffer layer 603, channel layer 604, and barrier layer 605 of the HEMT device shown can form a nitride epitaxial layer of the HEMT device. The nitride epitaxial layer can be a nitride epitaxial layer formed from group III to V nitrides.

[0218] In addition, a gate structure layer, a first insulating dielectric layer 607 and a field plate layer are provided on the barrier layer 605.

[0219] The gate structure layer may include: a first semiconductor layer 606, and the first semiconductor layer 606 is as follows: Figure 6A The cross-sectional shape shown in the diagram can be rectangular, isosceles trapezoidal, or other regular shapes; this embodiment does not limit this. Furthermore, the thickness of the first insulating dielectric layer 607 is less than the thickness of the first semiconductor layer 606.

[0220] Furthermore, the field plate layer may include a first GFP608 and a first GFP extended metal 609, which can form an inverted U-shaped gate field plate structure extending from the first GFP608 to both sides. Additionally, the first GFP608 and the first semiconductor layer 606 can use an ohmic contact or a Schottky contact; this application embodiment does not limit this.

[0221] It should be noted that the first surface of the nitride epitaxial layer can be the surface of the nitride epitaxial layer away from the substrate. For example, the first surface of the nitride epitaxial layer can be the first surface of the barrier layer 605, that is, the surface of the barrier layer 605 away from the substrate 601.

[0222] The first surface of the gate structure layer can be a surface of the gate structure layer that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer, and the second surface of the gate structure layer intersects with the first surface of the gate structure layer. For example, the first surface of the gate structure layer can be a surface of the first semiconductor layer 606 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605, and the second surface of the gate structure layer can be a surface where the first semiconductor layer 606 and the first surface of the barrier layer 605 intersect.

[0223] The first surface of the first insulating dielectric layer 607 is a surface of the first insulating dielectric layer 607 that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer, and the second surface of the first insulating dielectric layer 607 intersects with the first surface of the first insulating dielectric layer 607. For example, the first surface of the first insulating dielectric layer 607 can be a surface of the first insulating dielectric layer 607 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605, and the second surface of the first insulating dielectric layer 607 can be the surface where the first insulating dielectric layer 607 intersects with the first surface of the barrier layer 605.

[0224] Specifically, the first semiconductor layer 606 and the first insulating dielectric layer 607 are both disposed on the first surface of the nitride epitaxial layer. The first insulating dielectric layer 607 is distributed on both sides of the first semiconductor layer 606, and the first insulating dielectric layer 607 distributed on both sides of the first semiconductor layer 606 also covers the second surface of the first semiconductor layer 606 and extends towards the first surface of the first semiconductor layer 606, covering a portion of the first surface of the first semiconductor layer 606.

[0225] Additionally, the first GFP608 also covers a portion of the first surface of the first semiconductor layer 606 and is in contact with the first insulating dielectric layer 607 located on the first surface of the first semiconductor layer 606. The first GFP608 also covers the second surface of the first insulating dielectric layer 607 to form an inverted U-shaped structure. The first GFP extension metal 609 is distributed on both sides of the first GFP608 and covers the first surface of the first insulating dielectric layer 607.

[0226] It should be noted that the first semiconductor layer 606 can be formed from p-type nitrides, such as GaN, AlGaN, indium gallium nitride (InGaN), InAlN, or indium aluminum gallium nitride (InAlGaN), etc. This application does not limit this specific type. For example, the first semiconductor layer 606 can be formed from Al... x Ga 1-x N is generated, where 0 ≤ x ≤ 1. Furthermore, the doping concentration of the first semiconductor layer 606 can be 1*10⁻⁶. 17 ~1*10 20 cm -3That is, the first semiconductor layer 606 can be doped with 10 to the power of 17 to 10 to the power of 20 particles per cubic centimeter. The doping particles can be particles such as magnesium (Mg), zinc (Zn), calcium (Ca), or carbon (C). In addition, the first insulating dielectric layer 607 can be formed of materials such as silicon nitride (SiN) for surface passivation and metal isolation.

[0227] In addition, the HEMT device may also include a first drain electrode 610 and a second drain electrode 611 symmetrically distributed on both sides of the gate structure layer. Both the first drain electrode 610 and the second drain electrode 611 may be composed of materials such as titanium (Ti), titanium nitride (TiN), Al, or tantalum (Ta). Figure 6A The first drain electrode 610 and the second drain electrode 611 can penetrate the barrier layer 605 and the first insulating dielectric layer 608 and contact the channel layer 604. However, in practical applications, the first drain electrode 610 and the second drain electrode 611 can also only penetrate the first insulating dielectric layer 608 but not penetrate the barrier layer 605. This application does not limit this.

[0228] Moreover, in practical applications, due to limitations in process precision, the first drain electrode 610 and the second drain electrode 611 may be symmetrically distributed on both sides of the gate structure layer, or they may not be completely symmetrically distributed on both sides of the gate structure layer. That is, the first drain electrode 610 and the second drain electrode 611 can be basically symmetrically distributed on both sides of the gate structure layer to achieve the functions of bidirectional conduction and bidirectional blocking.

[0229] Further, see Figure 6B A first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, and a first GFP extended metal 609 are disposed on the barrier layer 605. The first GFP 608 surrounds the first insulating dielectric layer 607 located on the first and second surfaces of the first semiconductor layer 606, and the first GFP extended metal 609 extends to both sides of the first GFP 608, forming an inverted U-shaped gate field plate symmetrically extending from the first GFP 608 to both sides, composed of the first GFP 608 and the first GFP extended metal 609. Moreover, the first GFP 608 can contact the first surface of the first semiconductor layer 606 as a gate metal.

[0230] In addition, a first drain electrode 610 and a second drain electrode 611 are symmetrically distributed on both sides of the first semiconductor layer 606 on the barrier layer 605. The region where the first drain electrode 610 and the second drain electrode 611 are located can serve as an active region ohmic contact. Here, the active region is the collective term for the source region, channel region and drain region of the MOS transistor.

[0231] The aforementioned HEMT devices can be fabricated using traditional wafer fabrication techniques. That is, the epitaxial structure of the HEMT device can be prepared first, and then the device structure of the HEMT device can be fabricated on the prepared epitaxial structure to obtain the desired result. Figures 6A to 6B The HEMT device shown.

[0232] In the process of fabricating HEMT devices, see [link / reference]. Figure 6C HEMT devices can be fabricated using a feasible back-gate process, wherein steps 1 to 6 of the fabrication process can be performed using an epitaxial process to generate the various epitaxial layers of the HEMT device, and steps 7 to 10 can be performed using an etching technique to etch part of the epitaxial layers, thereby forming the HEMT device.

[0233] Specifically, step 1, see Figure 6D Select substrate 601; Step 2, see Figure 6E , can Figure 6D A nucleation layer 602 is formed on the substrate 601 shown; Step 3, see Figure 6F , can Figure 6E A buffer layer 603 is generated on the nucleation layer 602 shown; Step 4, see Figure 6G , can Figure 6F A channel layer 604 is formed on the buffer layer 603 shown; Step 5, see Figure 6H , can Figure 6G A barrier layer 605 is formed on the channel layer 604 shown; Step 6, see Figure 6I In such Figure 6H A semiconductor layer is formed on the barrier layer 605 shown.

[0234] Subsequently, deposition and etching techniques can be used to etch and deposit the epitaxial layer to obtain the first insulating dielectric layer 607, the first GFP 608, the first GFP extended metal 609, the first drain electrode 610, and the second drain electrode 611.

[0235] Specifically, step 7, see 6J, for... Figure 6I The semiconductor layer shown is etched to obtain the first semiconductor layer 606 formed after etching; Step 8, see Figure 6K ,exist Figure 6J Metal is deposited in the active region shown to form the first drain electrode 610 and the second drain electrode 611; Step 9, see Figure 6L In such Figure 6K A first insulating dielectric layer 607 is deposited on the first surface of the barrier layer 605, and on the first and second surfaces of the first semiconductor layer 606. A portion of the first insulating dielectric layer 607 on the first surface of the first semiconductor layer 606 is etched to form an etching window W; Step 10, see... Figure 6M , Figure 6N and Figure 6O In such Figure 6L Metal is deposited on the first surface of the first insulating dielectric layer 607 and the first and second surfaces of the first semiconductor layer 606, as shown, to obtain... Figure 6M The metal layer shown is applied according to a pre-set pattern. Figure 6M The metal layer shown is etched to form a shape like... Figure 6N and Figure 6O The first GFP608 and the first GFP extended metal 609 shown form an inverted U-shaped gate field plate extending to both sides of the gate structure layer.

[0236] To further verify the effectiveness of the HEMT device proposed in the embodiments of this application, simulation software can be used to simulate the HEMT device proposed in the embodiments of this application, and it can be determined that the HEMT device proposed in this application has improved in terms of withstand voltage characteristics.

[0237] During the simulation, the HEMT device can be configured according to the dimensions shown in Table 1. The reference numerals in Table 1 can be found in [reference needed]. Figure 6P , Figure 6P The diagram shows the labels corresponding to each structure in the HEMT device, and Table 1 shows the dimensions corresponding to each label. (See also...) Figure 6P As shown in Table 1, the thickness 101 of the substrate 601 can be 10 micrometers (μm); the thickness 102 of the buffer layer 603 can be 2 μm; the thickness 103 of the channel layer 604 can be 30 nanometers (nm); the thickness 104 of the barrier layer 605 can be 16 nm, the barrier layer 605 can be formed of AlGaN material, and the Al composition ratio can be 18%; the thickness 105 of the first insulating dielectric layer 608 can be 40 nm.

[0238] Furthermore, for the gate structure layer, the length 121 of the gate structure layer can be 0.6 μm; for the first semiconductor layer 606 in the gate structure layer, the thickness 106 of the first semiconductor layer 606 can be 100 nm, and the doping concentration can be 3*10 17 cm -3 .

[0239] In addition, for the entire HEMT device, the size of the lateral cell 100 of the HEMT device can be 1.6 μm; the lengths 111 and 112 of the first drain electrode 610 and the second drain electrode 611 can both be 0.2 μm; the length 141 of the inverted U-shaped gate field plate formed by the first GFP 608 and the first GFP extension metal 609 extending symmetrically from the gate structure layer can be 1 μm; the distance 131 between the boundary of the gate structure layer and the boundary of the first drain electrode 610 can be 0.4 μm; if the first drain electrode 610 and the second drain electrode 611 are symmetrically distributed on both sides of the gate structure layer, the distance 132 between the boundary of the gate structure layer and the boundary of the second drain electrode 611 can also be 0.4 μm.

[0240] Table 1

[0241] label Structure name Parameter value label Structure Name (Unit) Parameter value 100 Lateral cell size 1.6μm 111 First drain electrode length 0.2μm 101 Substrate thickness 10μm 112 Second drain electrode length 0.2μm 102 Buffer layer thickness 2μm 121 Gate structure layer length 0.6μm 103 Channel layer thickness 30nm 131 First grid spacing 0.4μm 104 Barrier layer thickness 16nm 132 Second grid spacing 0.4μm 105 Thickness of the first insulating dielectric layer 40nm 141 Grid plate length 1μm 106 Thickness of the first semiconductor layer 100nm

[0242] It should be noted that in simulation experiments, the buffer layer and the nucleation layer can be treated as the same epitaxial layer, in which case the nucleation layer 602 is not required, and only the buffer layer 603 needs to be set for simulation. Therefore, Table 1 and Figure 6P The dimensions of the nucleation layer 602 are not included. Furthermore, the ohmic contact resistance of the first drain electrode 610 and the second drain electrode 611 is not considered during the simulation of the HEMT device. In addition, in practical applications, the dimensions of the HEMT device described above can be adjusted according to the performance requirements of the HEMT device; this application does not limit the dimensions of the HEMT device.

[0243] First, the breakdown voltage of the drain electrode is simulated. With the potentials of substrate 601, gate, gate field plate, and the second drain electrode 611 all at low levels, the potential of the first drain electrode 610 is gradually increased from 0V. During this increase, the current magnitude of the first drain electrode 610 can be gradually read. If the current magnitude of the first drain electrode 610 abruptly increases to 10μA / mm (microamps per millimeter), it can be determined that the first drain electrode 610 has broken down, and this current potential magnitude can be used as the breakdown voltage from the first drain electrode 610 to the second drain electrode 611. (See also...) Figure 6Q The figure shows the curve of the current of the first drain electrode 610 changing as the potential of the first drain electrode 610 increases. When the current of the first drain electrode 610 suddenly rises to 10μA / mm, the potential of the first drain electrode 610 reaches 52V. Therefore, the breakdown voltage from the first drain electrode 610 to the second drain electrode 611 is 52V.

[0244] Similarly, the breakdown voltage from the second drain electrode 611 to the first drain electrode 610 is simulated in the manner described above, referring to... Figure 6RTherefore, it can be determined that the breakdown voltage from the second drain electrode 611 to the first drain electrode 610 is also 52V.

[0245] Next, the switching characteristics of the HEMT device can be simulated. With the substrate 601 and the second drain electrode 611 both at low levels, and the first drain electrode 610 fixed at 0.1V, the gate potential is gradually increased from 0V. During this increase, the current at the first drain electrode 610 can be read incrementally. If the current at the first drain electrode 610 abruptly increases to 1mA / mm, the HEMT device is confirmed to be turned on, and this gate potential can be used as the threshold voltage of the HEMT device. (See also...) Figure 6S The figure shows the curve of the current of the first drain electrode 610 changing as the gate potential increases. When the current of the first drain electrode 610 rises to 1 mA / mm, the gate potential reaches 2V, and the threshold voltage of the HEMT device can be determined to be 2V.

[0246] Finally, the output characteristic curves of the HEMT device can be simulated. With the potentials of the substrate 601 and the second drain electrode 611 both at low levels, and the gate potential fixed at 5V, the potential of the first drain electrode 610 is gradually increased from 0V. During this increase, the current magnitude of the first drain electrode 610 can be read incrementally. (See also...) Figure 6T If the potential of the first drain electrode 610 reaches 0.5V, the current of the first drain electrode 610 is read, and the on-resistance from the first drain electrode 610 to the second drain electrode 611 is calculated according to the formula R = V / I, where R is the on-resistance, V is the potential of the first drain electrode 610, and I is the current of the first drain electrode 610. Combined with the cell size of the HEMT device being 1.6μm, the characteristic resistance per unit area of ​​the HEMT device can be determined to be 5.2 milliohms per square millimeter (mΩ*mm). 2 ).

[0247] And adopting such Figure 3A The HEMT device shown has a characteristic resistance of 5.2 mΩ*mm for the same cell size. 2 However, the breakdown voltage between the second drain electrode and the first drain electrode of the HEMT device is approximately 30V. The breakdown voltage between the second drain electrode and the first drain electrode of the HEMT device proposed in this application is increased to 52V. The breakdown characteristics of the HEMT device proposed in this application are significantly higher than those of the previous embodiment. Figure 3A The HEMT device shown is a prior art device.

[0248] Alternatively, adopt such as Figure 3ATo achieve a 50V breakdown characteristic in the HEMT device shown, as indicated... Figure 3A The cell size of the HEMT device shown needs to be further increased, resulting in a characteristic resistance per unit area of ​​the HEMT device that is much greater than the 5.2 mΩ*mm² of the HEMT device proposed in the embodiment of this application. 2 .

[0249] In summary, the HEMT device proposed in this application employs a single semiconductor layer gate structure layer, with symmetrically arranged first and second drain electrodes on both sides of the gate structure layer. Furthermore, a first insulating dielectric layer covers the first surface of the nitride epitaxial layer of the HEMT device, as well as a portion of the first and second surfaces of the gate semiconductor structure. A first GFP and a first GFP extended metal are also covered on a portion of the first and second surfaces of the first insulating dielectric layer. The symmetrically arranged first and second drain electrodes enable bidirectional turn-off of the HEMT device. The gate field plate composed of the first GFP and the first GFP extended metal improves the channel electric field distribution and suppresses short-channel effects. This allows the HEMT device to further reduce the gate length while meeting breakdown voltage requirements, thereby reducing the channel resistance and cell size of the HEMT device, and consequently reducing the on-resistance and power consumption of the HEMT device.

[0250] Moreover, by using a back-gate process, the first and second drain electrodes, which are ohmic contacts located in the active region, are formed before the field plate layer. This avoids the damage caused by the high-temperature annealing process during the formation of the first and second drain electrodes to the contact between the metal and semiconductor forming the field plate layer.

[0251] It should be noted that, in accordance with Figures 6C to 6O During the fabrication of HEMT devices, the pattern pre-set in step 10 can be adjusted to obtain, as shown below. Figure 7A and Figure 7B The HEMT device shown, Figure 7A This is a three-dimensional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 7B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device also includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, and a second drain electrode 611.

[0252] Among them, the cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application is similar to... Figure 6A similar.

[0253] and Figure 6A and Figure 6B The HEMT device shown is different from the one described above. See also Figure 7A and Figure 7B ,right Figure 7A The first GFP608, covered by regions A, B, C, and D shown in the diagram, was etched. That is, the first GFP608 only covered a portion of the first surface and a portion of the second surface of the first insulating dielectric layer 607. The area of ​​the first GFP608 in contact with the second surface of the first insulating dielectric layer 607 is smaller than the area of ​​the second surface of the gate structure layer in contact with the first insulating dielectric layer 607, which is also smaller than the area of ​​the second surface of the first semiconductor layer 606 in contact with the first insulating dielectric layer 607. By changing the connection method between the first GFP608 and the first GFP extension metal 609, the area of ​​the gate field plate formed by the first GFP608 and the first GFP extension metal 609 is reduced, thereby reducing the gate capacitance and gate charge of the HEMT device, and thus improving the high-frequency characteristics of the HEMT device.

[0254] Additionally, see Figure 7A and Figure 7B The first GFP extension metal 609 also covers a portion of the first surface of the first insulating dielectric layer 607. Moreover, the first GFP 608 can be connected to the GFP extension metal 609 symmetrically distributed on both sides of the first semiconductor layer 606, thereby forming an inverted U-shaped gate field plate that extends symmetrically from the first GFP 608 to both sides.

[0255] like Figure 7A and Figure 7B The rest of the HEMT device shown is related to... Figure 6A and Figure 6B The HEMT device shown is similar and will not be described in detail here.

[0256] Preparation such as Figure 7A The process of the HEMT device shown is similar to that of... Figure 6C Preparation shown Figure 6A and Figure 6B The process for the HEMT device shown is similar. However, in step 10, the pre-set pattern can be adjusted; see [link to relevant documentation]. Figure 7A The first GFP 608 of the HEMT device does not completely cover the first and second surfaces of the first insulating dielectric layer 607, and the first GFP extended metal 609 also does not completely cover the first surface of the first insulating dielectric layer 607. That is, during the etching process of the metal layer, the first GFP extension metal 609 does not completely cover the first surface of the first insulating dielectric layer 607. Figure 7A Regions A, B, C, and D, indicated by the dashed lines, were also etched, which altered the structure of the gate field plate composed of the first GFP608 and the first GFP extended metal 609.

[0257] For example, targeting Figure 6M , Figure 6N and Figure 6O The corresponding fabrication steps involve depositing metal layers on the first and second surfaces of the first insulating dielectric layer 607 and the first surface of the first semiconductor layer 606, and etching the deposited metal layers according to a pre-set pattern. Specifically, this involves etching the metal layers near the first drain electrode 610 and the second drain electrode 611. Figure 7A The area where the metal layer, indicated by the dashed line, is located is etched to form a first GFP608 and a first GFP extension metal 609, which serve as the gate electrode and an inverted U-shaped gate field plate that extends symmetrically from the first GFP608 to both sides.

[0258] It should be noted that in actual processes, the areas where the metal layer is etched may also include other areas besides areas A to D, and this application embodiment does not limit this.

[0259] and Figure 6A and Figure 6B Similar to the HEMT device shown, in accordance with Figures 6C to 6O During the fabrication of HEMT devices, step 10 can be further adjusted using different pre-set patterns to obtain, for example... Figure 8A He Ru Figure 8B The HEMT device shown, Figure 8A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 8B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, and a second drain electrode 611.

[0260] However, with Figure 6A and Figure 6B The HEMT device shown is different from the one described above. See also Figure 8C , Figure 8C This is a three-dimensional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 8C The first GFP608 in regions A and B shown was etched. That is, the first GFP extension metal 609 covered a portion of the first surface of the first insulating dielectric layer 607, with the first GFP608 and the first GFP extension metal 609 arranged alternately. Figure 7A and Figure 7BCompared to the HEMT device shown, by arranging the first GFP608 and the first GFP609 extended metal at intervals, the gate capacitance and gate charge of the HEMT device can be reduced, while the edge electric field of the first semiconductor 606 can be further optimized, thereby improving the breakdown characteristics of the HEMT device.

[0261] like Figure 8A and Figure 8B The rest of the HEMT device shown is related to... Figure 6A and Figure 6B The HEMT device shown is similar and will not be described in detail here.

[0262] Preparation such as Figure 8A ,like Figure 8B He Ru Figure 8C The process of the HEMT device shown is similar to that of... Figure 6C The preparation shown is as follows Figure 6A He Ru Figure 6B The process for the HEMT device shown is similar. However, in step 10, the pre-set pattern can be adjusted again; see [link to relevant documentation]. Figure 8A and Figure 8B The first GFP extension metal 609 on both sides of the gate structure layer and the GFP608 covering the gate structure layer are arranged alternately, that is, the first GFP extension metal 609 and the first GFP608 do not contact each other.

[0263] For example, preparing such Figure 8A He Ru Figure 8B The process of steps 1 to 9 in the HEMT device shown is similar to... Figures 6C to 6L The corresponding preparation process is similar and will not be described in detail here.

[0264] However, regarding step 10, a metal layer can be deposited on the upper surface of the first insulating dielectric layer 607 and the first semiconductor layer 606, and the deposited metal layer can be etched according to the adjusted pattern. The first GFP extended metal 609 does not cover the first surface of the first insulating dielectric layer 607 near the gate structure layer. That is, during the etching process of the metal layer, the first GFP extended metal 609 does not cover the first surface of the first insulating dielectric layer 607 near the gate structure layer. Figure 8C Regions A and B, indicated by the dashed lines, were etched, which altered the structure of the gate field plate composed of the first GFP608 and the first GFP extended metal 609.

[0265] Besides adjusting the 10th step of the process to obtain different HEMT devices, in accordance with... Figures 6C to 6O In the fabrication of HEMT devices, additional process steps can be added after step 10 to obtain, for example... Figure 9A He Ru Figure 9BThe HEMT device shown, by adding a second insulating dielectric layer, a second GFP, and a second GFP extended metal to the first GFP 608 and the first GFP extended metal 609, can form an inverted U-shaped gate field plate structure. Combined with the inverted U-shaped composite gate field plate structure formed by the first GFP 608 and the first GFP extended metal 609, the channel electric field distribution and the electric field distribution at the edge of the gate field plate of the HEMT device can be further improved, the short-channel effect can be suppressed, and thus the breakdown voltage of the HEMT device can be improved.

[0266] Figure 9A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 9B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, and a second drain electrode 611.

[0267] Moreover, with Figure 6A and Figure 6B The HEMT device shown differs from the one shown in that it further includes: a second insulating dielectric layer 901, a second GFP 902, and a second GFP extended metal 903.

[0268] See Figure 9A The first insulating dielectric layer 901 is covered on the first surface of the first insulating dielectric layer 607, the first and second surfaces of the first GFP 608, and the first surface of the first GFP extension metal 609. The second GFP 902 and the second GFP extension metal 903 are covered on the first and second surfaces of the second insulating dielectric layer 901. The second GFP extension metal 903 is symmetrically distributed on both sides of the second GFP 603.

[0269] The first GFP608, the first GFP extended metal 609, the second GFP902, and the second GFP extended metal 903 constitute the field plate layer.

[0270] Furthermore, the first surface of the first GFP608 is a surface of the first GFP608 that is away from the substrate and parallel to the first surface of the nitride epitaxial layer; the second surface of the first GFP608 intersects with the first surface of the first GFP608; and the first surface of the first GFP extension metal 609 is a surface of the first GFP extension metal 609 that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. For example, the first surface of the first GFP608 can be a surface of the first GFP608 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605; and the first surface of the first GFP extension metal 609 can be a surface of the first GFP extension metal 609 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605.

[0271] The first surface of the second insulating dielectric layer 903 is a surface of the second insulating dielectric layer 903 that is away from the substrate and parallel to the first surface of the nitride epitaxial layer, and the second surface of the second insulating dielectric layer 903 intersects with the first surface of the second insulating dielectric layer 903. For example, the first surface of the second insulating dielectric layer 903 can be a surface of the second insulating dielectric layer 903 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605.

[0272] Additionally, see Figure 9B An etching window W is provided on the second insulating dielectric layer 901 so that the second GFP 902 can be electrically connected to the first GFP 608 through the etching window W. Furthermore, the projection of the etching window W onto the barrier layer 605 can be located within the projection of the first GFP 608 onto the barrier layer 605. Of course, the projection of the etching window W onto the barrier layer 605 can also be located at other positions, and this embodiment does not limit this.

[0273] Specifically, the second insulating dielectric layer 901 covers a portion of the first surface of the first insulating dielectric layer 607, the first and second surfaces of the first GFP 608, and the first surface of the first GFP extension metal 609. The second GFP 902 covers the first and second surfaces of the second insulating dielectric layer 901 and is electrically connected to the first GFP 608 through an etched window W. The second GFP extension metal 903 covers a portion of the first surface of the second insulating dielectric layer 901 and is distributed on both sides of the second GFP 902. The second GFP extension metal 903 may or may not be connected to the second GFP 902; this embodiment does not limit this aspect.

[0274] like Figure 9A and Figure 9B The rest of the HEMT device shown is related to... Figure 6A and Figure 6B The HEMT device shown is similar and will not be described in detail here.

[0275] Preparation such as Figure 9A He Ru Figure 9B The process of the HEMT device shown is similar to that of... Figure 6C The preparation shown is as follows Figure 6A He Ru Figure 6B The process is similar for the HEMT device shown. However, in cases such as Figure 6C After the preparation process shown is completed, the preparation process may also include steps 11 and 12.

[0276] Specifically, preparation such as Figure 9A and Figure 9B The process of steps 1 to 10 in the HEMT device shown is similar to... Figures 6C to 6O The corresponding preparation process is similar and will not be repeated here. However, steps 11 and 12 can be described as follows:

[0277] Step 11, see Figure 9C A second insulating dielectric layer 901 is deposited on a portion of the first surface of the first insulating dielectric layer 607, the first and second surfaces of the first GFP 608, and the first surface of the first GFP extended metal 609, and the second insulating dielectric layer 901 is etched to form an etching window W.

[0278] Step 12, see Figure 9D In such Figure 9C Metal is deposited on the second surface and part of the first surface of the second insulating dielectric layer 901, and the deposited metal is etched according to a preset pattern to obtain an inverted U-shaped second GFP902 and a second GFP extension metal 903 extending from the second GFP902 to both sides. The second GFP902 is brought into contact with the first GFP608 through the etching window W of the second insulating dielectric layer 901 to obtain a hybrid gate field plate (HGFP) structure composed of the first GFP608, the first GFP extension metal 609, the second GFP902 and the second GFP extension metal 903.

[0279] It should be noted that in practical applications, due to limitations in process precision, if a certain level of process precision is achieved, see [reference needed]. Figure 9E HEMT devices may not include the first GFP extension metal 609, thereby further improving the channel electric field distribution and the electric field distribution at the edge of the gate field plate of the HEMT device.

[0280] based on Figure 6A , Figure 7A , Figure 8A and Figure 9A The HEMT device described above, in this application embodiment, proposes another HEMT device that can further reduce on-resistance while ensuring bidirectional blocking and withstand voltage specifications. See [link to relevant documentation]. Figure 10A and Figure 10B , Figure 10A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 10B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application, as shown below. Figure 10A As shown, the HEMT device may include: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, and a second drain electrode 611.

[0281] Moreover, with Figure 6A , Figure 7A , Figure 8A and Figure 9A Unlike the HEMT device shown, this HEMT device also includes a gate metal 1001. The first semiconductor layer 606 and the gate metal 1001 together form the gate structure layer.

[0282] See Figure 10A A gate metal 1001 is added between the first semiconductor layer 606 and the first insulating dielectric layer 607. The gate metal 1001 covers the first surface of the first semiconductor layer 606. The gate metal 1001 and the first semiconductor layer 606 can be connected by an ohmic contact or a Schottky contact; this embodiment does not limit the choice. The first insulating dielectric layer 607 no longer covers the first surface of the first semiconductor layer 606, but instead covers the first surface of the gate metal 1001.

[0283] Specifically, the first surface of the first semiconductor layer 606 is the surface of the first semiconductor layer 606 that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer, and the first surface of the gate metal 1001 is the surface of the gate metal 1001 that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer. For example, the first surface of the first semiconductor layer 606 can be the surface of the first semiconductor layer 606 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605, and the first surface of the gate metal 1001 can be the surface of the gate metal 1001 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605.

[0284] Moreover, see Figure 10B An etched window W is provided on the first insulating dielectric layer 607 so that the first GFP 608 can be electrically connected to the gate metal 1001 through the etched window W. Furthermore, the projection of the etched window W onto the barrier layer 605 can be located within the projection of the gate metal 1001 onto the barrier layer 605. Of course, the projection of the etched window W onto the barrier layer 605 can also be located at other positions, and this embodiment does not limit this.

[0285] For example, see Figure 10B The first insulating dielectric layer 607 can be etched to obtain an etched window W. Then, a first GFP 608 and a first GFP extension metal 609 are covered on the first and second surfaces of the first insulating dielectric layer 607. The first GFP 608 can then contact the gate metal 1001 through the etched window W, thereby achieving metal interconnection. If the first GFP 608 and the first GFP extension metal 609 are connected, the first GFP extension metal 609 is also metal interconnected with the gate metal 1001.

[0286] like Figure 10A and Figure 10B The rest of the HEMT device shown is related to... Figure 6A and Figure 6B The HEMT device shown is similar and will not be described in detail here.

[0287] The aforementioned HEMT devices can be fabricated using traditional wafer fabrication techniques. That is, the epitaxial structure of the HEMT device can be prepared first, and then the device structure of the HEMT device can be fabricated on the prepared epitaxial structure to obtain the desired result. Figures 10A to 10B The HEMT device shown.

[0288] Specifically, in the process of fabricating HEMT devices, HEMT devices can be manufactured using a feasible gate-first process. In step 1 to step 6 of this process, epitaxial processes can be used to generate the various epitaxial layers of the HEMT device, and in step 7 to step 9, etching techniques can be used to etch part of the epitaxial layers to form the HEMT device.

[0289] Steps 1 to 6 in the embodiments of this application can be found in [reference needed]. Figures 6D to 6I The steps shown will not be repeated here.

[0290] After growing the semiconductor layer on the barrier layer 605, step 7 can be performed, see [link to relevant documentation]. Figure 10C Metal is deposited on the semiconductor layer, and the deposited metal is etched according to a pre-set pattern to obtain gate metal 1001. The semiconductor layer is then etched using the gate metal 1001 as a mask to form the first semiconductor layer 606.

[0291] Step 8, see Figure 10DA first insulating dielectric layer 607 is deposited on the first surface of the barrier layer 605, the first surface of the gate metal 1001, and the second surface of the first semiconductor layer 606. A portion of the first insulating dielectric layer 607 on the first surface of the gate metal 1001 is etched to form an etching window W1. At the same time, the first insulating dielectric layer 607 on the ohmic contact portion of the active region on both sides of the first semiconductor layer 606 is etched to form a first drain window W2 and a second drain window W3.

[0292] Step 9, see Figure 10E In such Figure 10D Metal is deposited on the first and second surfaces of the first insulating dielectric layer 607, and the deposited metal is etched according to a pre-set pattern to form a first drain electrode 610 and a second drain electrode 611 in the active region. A first GFP 608 is formed on the first and second surfaces of the gate structure layer, and a first GFP extension metal 609 is formed on a portion of the first surface of the first insulating dielectric layer 607. The first GFP 608 is then brought into contact with the gate metal 1001 through the etching window W of the gate region.

[0293] In summary, the HEMT device proposed in this application, by providing a symmetrically arranged first drain electrode and a second drain electrode on both sides of the gate structure layer, and by covering the first and second surfaces of the gate structure layer of the HEMT device with a first insulating dielectric layer, a first GFP, and a first GFP extended metal, can achieve bidirectional turn-off of the HEMT device through the symmetrically arranged first drain electrode and the second drain electrode. Furthermore, the gate field plate composed of the first GFP and the first GFP extended metal improves the channel electric field distribution and suppresses the short-channel effect, allowing the HEMT device to further reduce the gate length while meeting the breakdown voltage requirements, thereby reducing the channel resistance and cell size of the HEMT device, and thus reducing the on-resistance of the HEMT device.

[0294] Moreover, with Figure 6A Compared to the embodiments shown, the HEMT device proposed in this application uses gate metal as an etching baffle for the gate structure layer to achieve a gate-first self-alignment process, which helps to improve the uniformity and accuracy of the etching image.

[0295] It should be noted that, in accordance with Figures 10C to 10E During the fabrication of HEMT devices, the pattern preset in step 9 can be adjusted to obtain, as shown below. Figure 11A He Ru Figure 11B The HEMT device shown, Figure 11A This is a three-dimensional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 11BThis is a top view schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, a second drain electrode 611, and a gate metal 1001.

[0296] Among them, a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application is similar to... Figure 10A similar.

[0297] However, with Figure 10A and Figure 10B The HEMT device shown is different from the one described above. See also Figure 11A ,right Figure 11A The first GFP608 in regions A, B, C and D shown in the figure was etched, which will not be described in detail here.

[0298] Preparation such as Figure 11A He Ru Figure 11B The process of fabricating the HEMT device shown is similar to that of preparing it. Figure 10A He Ru Figure 10B The process for the HEMT device shown is similar. However, in step 9, the pre-set pattern can be adjusted; see [link to relevant documentation]. Figure 11A A metal layer can be deposited on the first and second surfaces of the first insulating dielectric layer 607, and the deposited metal layer can be etched according to the adjusted pattern to form the first drain electrode 610 and the second drain electrode 611 in the active region. Furthermore, during the etching process of the metal layer, [the following text appears to be incomplete and requires further context: "...the first drain electrode 610 and the second drain electrode 611 can be formed in the active region."] Figure 11B Regions A, B, C, and D, indicated by the dashed lines, were also etched, altering the structure of the gate field plate composed of the first GFP608 and the first GFP extended metal 609. This resulted in the formation of an inverted U-shaped first GFP608 and first GFP extended metal 609, and was achieved through... Figure 11B The etched window W of the gate region shown in the figure makes the first GFP608 contact with the gate metal 1001.

[0299] By changing the connection method of the first GFP608 and the first GFP extended metal 609, the area of ​​the gate field plate composed of the first GFP608 and the first GFP extended metal 609 is reduced, thereby reducing the gate capacitance and gate charge of the HEMT device, which can improve the high-frequency characteristics of the HEMT device and reduce switching losses.

[0300] and Figure 10A and Figure 10B Similar to the HEMT device shown, in accordance with Figures 10C to 10EDuring the fabrication of HEMT devices, the pattern preset in step 9 can be adjusted to obtain, as shown below. Figure 12A He Ru Figure 12B The HEMT device shown, Figure 12A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 12B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, a second drain electrode 611, and a gate metal 1001.

[0301] However, with Figure 10A and Figure 10B The HEMT device shown is different from the one described above. See also Figure 12C ,right Figure 12C The first GFP608 in regions A and B shown in the figure was etched, which will not be described in detail here.

[0302] Preparation such as Figure 12A He Ru Figure 12B The process of fabricating the HEMT device shown is similar to that of preparing it. Figure 10A He Ru Figure 10B The process for the HEMT device shown is similar. However, when performing step 9, the pre-set pattern can be adjusted again, see [link to relevant documentation]. Figure 12A , Figure 12B and Figure 12C Metal can be deposited on the first and second surfaces of the first insulating dielectric layer 1208, and the deposited metal can be etched according to the adjusted pattern to form the first drain electrode 610 and the second drain electrode 611 in the active region. Furthermore, during the etching process of the metal layer, [the following text appears to be incomplete and requires further context: "...the first surface and the second surface can be etched according to the adjusted pattern, thereby forming the first drain electrode 610 and the second drain electrode 611 in the active region."] Figure 12C Regions A and B, indicated by the dashed lines, were also etched, which changed the structure of the gate field plate composed of the first GFP608 and the first GFP extension metal 609, forming an inverted U-shaped first GFP608 and first GFP extension metal 609, and the first GFP608 came into contact with the gate metal 1001 through the etching window of the gate region.

[0303] By changing the connection mode of the first GFP608 and the first GFP extension metal 609, and Figure 11A and Figure 11B Compared to the HEMT device shown, by arranging the first GFP608 and the first GFP extended metal 609 at intervals, the gate capacitance and gate charge of the HEMT device can be reduced, while the edge electric field of the first semiconductor layer 606 can be further optimized, thereby improving the breakdown characteristics of the HEMT device.

[0304] Besides adjusting the 9th step of the process to obtain different HEMT devices, in accordance with... Figures 10C to 10E During the fabrication of HEMT devices, the process after step 6 can be adjusted to obtain results such as... Figure 13A He Ru Figure 13B The HEMT device shown, by adding a second insulating dielectric layer, a second GFP, and a second GFP extended metal to the first GFP608 and the first GFP extended metal 609, allows the second GFP and the second GFP extended metal to form an inverted U-shaped gate field plate structure. Combined with the inverted U-shaped composite gate field plate structure composed of the first GFP608 and the first GFP extended metal 609, the channel electric field distribution and the electric field distribution at the edge of the gate field plate of the HEMT device can be further improved, and the short-channel effect can be suppressed, thereby improving the breakdown voltage of the HEMT device.

[0305] Figure 13A This is a cross-sectional schematic diagram of another HEMT device provided in an embodiment of this application. Figure 13B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, a second drain electrode 611, and a gate metal 1001.

[0306] Moreover, with Figure 10A and Figure 10B Unlike the HEMT device shown, this HEMT device also includes: a second insulating dielectric layer 1301, a second GFP 1302, and a second GFP extension metal 1303. The first GFP 608, the first GFP extension metal 609, the second GFP 1302, and the second GFP extension metal 1303 can collectively form a field plate layer.

[0307] See Figure 13A The second insulating dielectric layer 1301 covers a portion of the first surface of the first insulating dielectric layer 607, the first and second surfaces of the first GFP 608, and the first surface of the first GFP extension metal 609. Furthermore, the first and second surfaces of the second insulating dielectric layer 1301 are covered by a second GFP 1302 and a second GFP extension metal 1303, with the second GFP extension metal 1303 symmetrically distributed on both sides of the second GFP 1302.

[0308] Specifically, the second insulating dielectric layer 1301 covers the first surface of the first insulating dielectric layer 607, the first and second surfaces of the first GFP 608, and the first surface of the first GFP extension metal 609. The second GFP 1302 covers the second surface and part of the first surface of the second insulating dielectric layer 1301, and is electrically connected to the first GFP 608 through an etched window W. The second GFP 1302 covers part of the first and second surfaces of the second insulating dielectric layer 1301. The second GFP extension metal 1303 covers part of the first surface of the second insulating dielectric layer 1301 and is distributed on both sides of the second GFP 1302. The second GFP extension metal 1303 may or may not be connected to the second GFP 1302; this embodiment does not limit this.

[0309] The first and second surfaces of the first GFP608, the first surface of the first GFP-extended metal 609, and the first and second surfaces of the second insulating dielectric layer 1301 can be referred to... Figure 9A and Figure 9B The corresponding descriptions will not be repeated here.

[0310] Moreover, see Figure 13B An etching window W is provided on the second insulating dielectric layer 1301 so that the second GFP1302 can be electrically connected to the first GFP608 through the etching window W. Furthermore, the projection of the etching window W onto the barrier layer 605 lies within the projection of the first GFP608 onto the barrier layer 605. Of course, the projection of the etching window W onto the barrier layer 605 can also be located at other positions, and this embodiment does not limit this.

[0311] like Figure 13A and Figure 13B The rest of the HEMT device shown is related to... Figure 10A and Figure 10B The HEMT device shown is similar and will not be described in detail here.

[0312] Preparation such as Figure 13A He Ru Figure 13B The process of fabricating the HEMT device shown is similar to that of preparing it. Figure 10A He Ru Figure 10B The process for the HEMT device shown is similar, however, step 9 in the fabrication process can be adjusted, and steps 10 and 11 can also be included.

[0313] Specifically, see Figures 13C to 13E This demonstrates the preparation of, as Figure 13A He Ru Figure 13B The process of fabricating a HEMT device is shown, where steps 1 to 8 correspond to the fabrication process, and the fabrication... Figure 10A He Ru Figure 10BThe fabrication process of the HEMT device shown is similar and will not be described in detail here.

[0314] Step 9, see Figure 13C Metal is deposited on the first and second surfaces of the first insulating dielectric layer 607, and the deposited metal is etched according to a pre-set pattern to form a first GFP608 and a first GFP extension metal 609 above the gate structure layer. The first GFP608 is made to contact the gate metal 1001 through the etching window of the first insulating dielectric layer 607 at the gate structure layer.

[0315] Step 10, see Figure 13D A second insulating dielectric layer 1301 is deposited on the first surface of the first insulating dielectric layer 607, the first and second surfaces of the first GFP 608, and the first surface of the first GFP extended metal 609, and the second insulating dielectric layer 1301 is etched to form an etching window W.

[0316] Step 11, see Figure 13E In such Figure 13D Metal layers are deposited on the second surface and part of the first surface of the second insulating dielectric layer 1301, and the deposited metal layers are etched according to a preset pattern to form a first drain electrode 610 and a second drain electrode 611 in the active region. At the same time, an inverted U-shaped second GFP 1302 and a second GFP extension metal 1303 extending from the second GFP 1302 to both sides are obtained. The first GFP 608 is contacted through the etching window W of the second insulating dielectric layer 1301 to obtain a composite gate field plate structure composed of the first GFP 608, the first GFP extension metal 609, the second GFP 1302 and the second GFP extension metal 1303.

[0317] based on Figure 10A , Figure 11A , Figure 12A and Figure 13A The HEMT device described above, in this application embodiment, proposes another HEMT device that can further reduce on-resistance while meeting bidirectional blocking and withstand voltage specifications. See [link to relevant documentation]. Figure 14A and Figure 14B , Figure 14A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application. Figure 14B This is a top view schematic diagram of another HEMT device provided in the embodiments of this application, as shown below. Figure 14AAs shown, the HEMT device may include: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, a second drain electrode 611, and a gate metal 1001.

[0318] Moreover, with Figure 10A , Figure 11A , Figure 12A and Figure 13A Unlike the HEMT device shown, this HEMT device also includes an etch barrier layer 1401 and a second semiconductor layer 1402.

[0319] The gate structure layer comprises a first semiconductor layer 606, an etch stop layer 1401, a second semiconductor layer 1402, and a gate metal 1001. Furthermore, the projected area of ​​the etch stop layer 1401 on the nitride epitaxial layer is equal to the projected area of ​​the first semiconductor layer 606 on the nitride epitaxial layer. That is, the first semiconductor layer 606 and the etch stop layer 1401 have the same pattern size, and the first semiconductor layer 606 is larger than the second semiconductor layer 1402.

[0320] See Figure 14A In the HEMT device, an etch stop layer 1401 and a second semiconductor layer 1402 are incorporated between the first semiconductor layer 606 and the gate metal 1001. The etch stop layer 1401 covers the first surface of the first semiconductor layer 606. The second semiconductor layer 1402 covers the first surface of the etch stop layer 1401. The gate metal 1001 covers a portion of the first surface of the etch stop layer 1401 and the first and second surfaces of the second semiconductor layer 1402.

[0321] Wherein, the first surface of the second semiconductor layer 1402 is the surface of the second semiconductor layer 1402 that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer, the second surface of the second semiconductor layer 1402 intersects with the first surface of the second semiconductor layer 1402, and the first surface of the etch barrier layer 1401 is the surface of the etch barrier layer 1401 that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer.

[0322] For example, the first surface of the second semiconductor layer 1402 can be a surface of the second semiconductor layer 1402 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605, and the first surface of the etching barrier layer 1401 can be a surface of the etching barrier layer 1401 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605.

[0323] Moreover, the second semiconductor layer 1402 is disposed in the middle region of the first semiconductor layer 606, that is, the midline of the projection of the second semiconductor layer 1402 on the nitride epitaxial layer is substantially coincident with the midline of the projection of the first semiconductor layer 606 on the nitride epitaxial layer. And referring to Figure 14A , the length of the first semiconductor layer 606 in the left-right direction is greater than the length of the second semiconductor layer 1402 in the left-right direction.

[0324] In addition, the shape of the second semiconductor layer 1402 in the cross-sectional view as shown in Figure 14A can be a rectangle, an isosceles trapezoid, or other regular shapes. The embodiments of the present application do not limit this. In addition, an ohmic contact or a Schottky contact can be adopted between the gate metal 1001 and the second semiconductor layer 1402.

[0325] It should be noted that the second semiconductor layer 1402 can be formed by p-type nitride to form a p-type semiconductor layer. For example, the second semiconductor layer 1402 can be formed by p-type doped nitrides such as GaN, AlGaN, InGaN, InAlN, or InAlGaN. The etch stop layer 1401 can be formed by nitrides containing an Al component, such as AlGaN, InAlN, or InAlGaN.

[0326] For example, the second semiconductor layer 1402 can be formed by Al y Ga 1-y N, where 0 ≤ y ≤ 1. Moreover, the doping concentration of the second semiconductor layer 606 can be 1×10 17 ~1×10 20 cm -3 , where the doping particles can be particles such as Mg, Zn, Ca, or C. The etch stop layer 1401 can be formed by Al z Ga 1-z N, where 0 ≤ y < z ≤ 1. Moreover, the doping type of the etch stop layer 1401 can be p-type doping, n-type doping, or unintentional doping, etc. The embodiments of the present application do not limit the doping type and doping concentration of the etch stop layer 1401.

[0327] Further, if the second semiconductor layer 1402 is also formed by a nitride containing an Al component, the Al component content of the etch stop layer 1401 is higher than the Al component content of the second semiconductor layer 1402 to obtain a high etch selectivity between the second semiconductor layer 1402 and the etch stop layer 1401 and improve the etch accuracy. Similarly, if the first semiconductor layer 606 is also formed by a nitride containing an Al component, the Al component content of the first semiconductor layer 606 is lower than the Al component content of the barrier layer 605 to obtain a high etch selectivity between the first semiconductor layer 606 and the barrier layer 605 and improve the etch accuracy.

[0328] It should be noted that, in the embodiments of this application, the gate structure layer may only include the first semiconductor layer 606, the second semiconductor layer 1402, and the gate metal 1001, without including the etch stop layer 1401. That is, the gate structure layer may be composed of the first semiconductor layer 606, the second semiconductor layer 1402 disposed on the first surface of the first semiconductor layer 606, and the gate metal 1001 disposed on a portion of the first surface of the first semiconductor layer 606 and the first and second surfaces of the second semiconductor layer. Figure 14A and Figure 14B Only HEMT devices with gate structures including etch barrier layer 1401 are shown.

[0329] like Figure 14A and Figure 14B The rest of the HEMT device shown is related to... Figure 10A and Figure 10B The HEMT device shown is similar and will not be described in detail here.

[0330] The aforementioned HEMT devices can be fabricated using traditional wafer fabrication techniques. That is, the epitaxial structure of the HEMT device can be prepared first, and then the device structure of the HEMT device can be fabricated on the prepared epitaxial structure to obtain the desired result. Figures 14A to 14B The HEMT device shown.

[0331] Specifically, in the process of fabricating HEMT devices, HEMT devices can be manufactured through the following feasible fabrication scheme. Steps 1 to 8 of this fabrication scheme can be used to generate the various epitaxial layers of the HEMT device using epitaxial processes. Steps 9 to 13 can be used to etch part of the epitaxial layers using deposition and etching techniques, thereby forming the HEMT device.

[0332] Steps 1 to 6 in the embodiments of this application are related to... Figures 6C to 6I The steps shown are similar and will not be repeated here.

[0333] After obtaining the semiconductor layer through epitaxial growth, step 7 can be performed, see [link to previous steps]. Figure 14C An etch barrier layer 1401 is formed on the semiconductor layer.

[0334] Step 8, see Figure 14D In such Figure 14C A semiconductor layer is then formed on the etch barrier layer 1401 shown.

[0335] Subsequently, deposition and etching techniques can be used to etch and deposit the epitaxial layer to obtain gate metal 1001, first insulating dielectric layer 607, first drain electrode 610, second drain electrode 611, first GFP 608 and first GFP extension metal 609.

[0336] Specifically, step 9, see Figure 14E Dry etching can be used, with the etching of the barrier layer 1401 as the etching termination point. Figure 14D The semiconductor layer located on the first surface of the etch barrier layer 1401 shown in the figure is etched to obtain the following: Figure 14E The second semiconductor layer 1402 is shown.

[0337] Step 10, see Figure 14F In such Figure 14E Metal layers are deposited on the first surface of the etch barrier layer 1401 and the first and second surfaces of the second semiconductor layer 1402, as shown. The deposited metal layers are then etched according to a pre-set pattern to obtain the desired result. Figure 14F The gate metal 1001 is shown.

[0338] Step 11, see Figure 14G The gate metal 1001 can be used as a mask to etch the etch barrier layer 1401 and the semiconductor layer located on the first surface of the barrier layer 605, to obtain the following: Figure 14G The diagram shows a gate structure layer comprising a first semiconductor layer 606, an etch stop layer 1401, a second semiconductor layer 1402, and a gate metal 1001.

[0339] Step 12, see Figure 14H In such Figure 14G An insulating dielectric is deposited on the first surface of the barrier layer 1405, the first surface of the gate structure layer, and the second surface of the gate structure layer to obtain a first insulating dielectric layer 607. Etching is performed in the region of the active region ohmic contact and part of the gate structure layer to form an etching window W.

[0340] Step 13, see Figure 14I In such Figure 14G Metal is deposited at the etch window of the active region ohmic contact of the first insulating dielectric layer 607 to form the first drain electrode 610 and the second drain electrode 611. At the same time, metal is deposited on the first surface and the second surface of the first insulating dielectric layer 607 to form an inverted U-shaped first GFP 608 and a first GFP extension metal 609 extending from the first GFP 608 to both sides. The first GFP 608 is made to contact the gate metal 1001 through the etch window W of the gate region.

[0341] To further verify the effectiveness of the HEMT device proposed in the embodiments of this application, simulation software can be used to simulate the HEMT device proposed in the embodiments of this application, and it can be determined that the HEMT device proposed in this application has improved in terms of withstand voltage characteristics.

[0342] During the simulation, the HEMT device can be configured according to the dimensions shown in Table 2. The reference numerals in Table 2 can be found in [reference needed]. Figure 14J , Figure 14J The diagram shows the labels corresponding to each structure in the HEMT device, and Table 2 shows the dimensions corresponding to each label. (See also...) Figure 14J According to Table 2, the thickness 101 of the substrate 601 can be 10 μm; the thickness 102 of the buffer layer 603 can be 2 μm; the thickness 103 of the channel layer 604 can be 30 nm; the thickness 104 of the barrier layer 605 can be 16 nm, and the barrier layer 605 is formed of AlGaN material, with an Al composition ratio of 18%; the thickness 105 of the first insulating dielectric layer 607 can be 40 nm, and the first insulating dielectric layer 607 can be formed of SiN.

[0343] Furthermore, for the first semiconductor layer 606 and the second semiconductor layer 1402 in the gate structure layer, the length 121 of the gate structure layer can be 0.7 μm; the thickness 106 of the first semiconductor layer 606 can be 40 nm, and the doping concentration can be 3*10⁻⁶. 17 cm -3 The first extension length 122 of the first semiconductor layer 606 can be 0.2 μm; the second extension length 123 of the first semiconductor layer 606 can also be 0.2 μm; the thickness 107 of the second semiconductor layer 1402 can be 60 nm, and the doping concentration can be 3*10⁻⁶. 17 cm -3 The length 124 of the second semiconductor layer 1402 can be 0.3 μm.

[0344] In addition, for the entire HEMT device, the size of the lateral cell 100 of the HEMT device can be 1.6 μm; the lengths 111 and 112 of the first drain electrode 610 and the second drain electrode 611 can both be 0.2 μm; the length 141 of the gate field plate composed of GFP608 and GFP extended metal 609 can be 1 μm; the distance 131 between the boundary of the gate structure layer and the boundary of the first drain electrode 610 can be 0.35 μm; if the first drain electrode 610 and the second drain electrode 611 are symmetrically distributed on both sides of the gate structure layer, the distance 132 between the boundary of the gate structure layer and the boundary of the second drain electrode 611 can also be 0.35 μm.

[0345] Table 2

[0346]

[0347]

[0348] It should be noted that in simulation experiments, the buffer layer and the nucleation layer can be treated as the same epitaxial layer, in which case the nucleation layer is not required, and only the buffer layer needs to be set for simulation. Therefore, Table 2 and Figure 14J The dimensions of the nucleation layer 602 are not included. Furthermore, the ohmic contact resistance of the first drain electrode 610 and the second drain electrode 611 is not considered during the simulation of the HEMT device. The etch barrier layer 1401 is also simplified as the first semiconductor layer 606. In practical applications, the dimensions of the HEMT device described above can be adjusted according to the performance requirements of the HEMT device; this application does not limit the dimensions of the HEMT device.

[0349] First, the breakdown voltage of the drain electrode can be simulated. With the substrate potential, gate potential, gate field plate potential, and the potential of the second drain electrode all at low levels, the potential of the first drain electrode 610 is gradually increased from 0V. During the increase, the current magnitude of the first drain electrode 610 can be read step by step. If the current magnitude of the first drain electrode 610 suddenly changes to 10μA / mm, it can be determined that the first drain electrode 610 has broken down, and the potential magnitude of the first drain electrode 610 at this point can be used as the breakdown voltage from the first drain electrode 610 to the second drain electrode 611. See [link to relevant documentation] Figure 14K The curve of the current of the first drain electrode 610 changing as the potential of the first drain electrode 610 increases is shown. When the current of the first drain electrode 610 suddenly rises to 10μA / mm, the potential of the first drain electrode 610 reaches 50V. Therefore, the breakdown voltage from the first drain electrode 610 to the second drain electrode 611 is 50V.

[0350] Similarly, the breakdown voltage from the second drain electrode 611 to the first drain electrode 610 can be simulated in the same manner as described above, referring to... Figure 14L Therefore, it can be determined that the breakdown voltage from the second drain electrode 611 to the first drain electrode 610 is also 50V.

[0351] Next, the switching characteristics of the HEMT device were simulated. With the substrate and second drain electrode potentials both low, and the first drain electrode potential fixed at 0.1V, the gate potential was gradually increased from 0V. During this increase, the current at the first drain electrode 610 was gradually read. If the current at the first drain electrode 610 increased to 1mA / mm, the HEMT device was considered to be turned on, and this gate potential could be used as the threshold voltage of the HEMT device. (See also...) Figure 14M The figure shows the curve of the current of the first drain electrode 610 changing as the gate potential increases. When the current of the first drain electrode 610 rises to 1 mA / mm, the gate potential reaches 1.8V, and the threshold voltage of the HEMT device can be determined to be 1.8V.

[0352] Finally, the output characteristic curve of the HEMT device was simulated. With the substrate potential and the potential of the second drain electrode both at low levels, and the gate potential fixed at 5V, the potential of the first drain electrode 610 was gradually increased from 0V. During the increase of the potential, the current of the first drain electrode 610 could be read step by step. See [link / reference] Figure 14N If the potential of the first drain electrode 610 reaches 0.5V, the current of the first drain electrode 610 is read, and the on-resistance from the first drain electrode 610 to the second drain electrode 611 is calculated according to the formula R = V / I, where R is the on-resistance, V is the potential of the first drain electrode 610, and I is the current of the first drain electrode 610. Combined with the cell size of the HEMT device being 1.6μm, the characteristic resistance per unit area of ​​the HEMT device can be determined to be 4mΩ*mm. 2 ,and Figure 6A The HEMT device shown has a characteristic resistance per unit area of ​​5.2 mΩ*mm. 2 In comparison, the characteristic resistance per unit area of ​​the HEMT device in this application embodiment is reduced to 4mΩ*mm. 2 The characteristic resistance per unit area was reduced by 23%, resulting in further optimization.

[0353] It should be noted that, in accordance with Figures 14C to 14I During the fabrication of HEMT devices, step 10 can be adjusted to obtain, as shown below. Figure 15A The HEMT device shown, Figure 15A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, a second drain electrode 611, a gate metal 1001, an etch stop layer 1401, and a second semiconductor layer 1402.

[0354] Moreover, with Figure 14A Unlike the HEMT device shown, this HEMT device also includes a third insulating dielectric layer 1501. The first semiconductor layer 606, the etch stop layer 1401, the second semiconductor layer 1402, the gate metal 1001, and the third insulating dielectric layer 1501 constitute the gate structure layer.

[0355] See Figure 15AThe third insulating dielectric layer 1501 covers a portion of the first surface of the etch barrier layer 1401, and the second surface and a portion of the first surface of the second semiconductor layer 1402. By providing the third insulating dielectric layer 1501, a portion of the first semiconductor layer 606 and a portion of the second semiconductor layer 1402 are isolated from the gate metal 1001, thereby reducing the increase in gate leakage current caused by the thinner first semiconductor layer 606. Furthermore, the gate metal 1001 no longer covers the first surface of the first semiconductor layer 606 and the second surface of the second semiconductor layer 1402, but instead covers a portion of the first surface of the second semiconductor layer 1402, as well as the first and second surfaces of the third insulating dielectric layer 1501.

[0356] The first surface of the third insulating dielectric layer 1501 is the surface of the third insulating dielectric layer 1501 that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer, and the second surface of the third insulating dielectric layer 1501 intersects with the first surface of the third insulating dielectric layer 1501. For example, the first surface of the third insulating dielectric layer 1501 can be the surface of the third insulating dielectric layer 1501 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605.

[0357] like Figure 15A The rest of the HEMT device shown is related to... Figure 14A and Figure 14B The HEMT device shown is similar and will not be described in detail here.

[0358] In addition, in this embodiment of the application, the gate structure layer may only include the first semiconductor layer 606 and the second semiconductor layer 1402, without the etch barrier layer 1401. That is, the gate structure layer may be composed of the first semiconductor layer 606, the second semiconductor layer 1402 disposed on the first surface of the first semiconductor layer 606, the third insulating dielectric layer 1501 disposed on the first surface of the first semiconductor layer 606 and on the second surface and part of the first surface of the second semiconductor layer 1402, and the gate metal 1001 disposed on part of the first surface of the second semiconductor layer 1402 and on the first and second surfaces of the third insulating dielectric layer 1501. Figure 15A Only HEMT devices with gate structure layers including etch stop layer 1401 are shown.

[0359] Preparation such as Figure 15A The process of fabricating the HEMT device shown is similar to that of preparing it. Figure 14A He Ru Figure 14B The process for the HEMT device shown is similar, namely steps 1 to 9 and step 13 in the embodiments of this application, which can be found in [reference needed]. Figures 14C to 14E as well as Figure 14IThe steps shown will not be repeated here. However, during the execution of steps 10 to 12, a third insulating dielectric layer 1501 can be first covered on the second semiconductor layer 1402 after dry etching, and then the third insulating dielectric layer 1501 can be etched. After that, gate metal 1001, first insulating dielectric layer 607, first GFP 608 and first GFP extension metal 609 can be deposited on the etched third insulating dielectric layer 1501.

[0360] Specifically, see Figures 15B to 15D This demonstrates the preparation of, as Figure 15A The process of steps 10 to 12 in the HEMT device shown:

[0361] Step 10, see Figure 15B An insulating dielectric is deposited on the first surface of the etch barrier layer 1401 and the first and second surfaces of the second semiconductor layer 1402, and the deposited insulating dielectric is etched according to a pre-set pattern to form an etch window W, resulting in... Figure 15B The third insulating dielectric layer 1501 is shown.

[0362] Step 11, see Figure 15C In such Figure 15B Metal layers are deposited on the first and second surfaces of the third insulating dielectric layer 1501 and a portion of the first surface of the second semiconductor layer 1402, as shown. The deposited metal layers are then etched according to a pre-defined pattern to obtain the desired result. Figure 15C The gate metal 1001 is shown.

[0363] Step 12, see Figure 15D The gate metal 1001 can be used as a mask to etch the third insulating dielectric layer 1501, the etch stop layer 1401, and the semiconductor layer, to obtain the following: Figure 15D The gate structure layer shown is covered with gate metal 1001.

[0364] in addition, Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A The field plate layer and insulating dielectric layer in the HEMT device shown can be applied to Figure 14A and Figure 15A The field plate layer and insulating dielectric layer in the middle make it possible to... Figure 14A and Figure 15A The HEMT devices shown have different gate field plate structures, which can further reduce the channel on-resistance and reduce the on-resistance of the HEMT devices while meeting the breakdown voltage requirements.

[0365] Specifically, see Figure 14O , Figure 14O Is it like this? Figure 14A The HEMT device shown and such Figure 6A The cross-sectional view of the HEMT device after assembly is shown below. Figure 14O As shown, the combined HEMT device includes only the first GFP 608 and the first GFP extended metal 609, but no longer includes the gate metal 1001. The first GFP 608 covers the first and second surfaces of the second semiconductor layer 1402, a portion of the first surface of the etch stop layer 1401, and the edge of the first insulating dielectric layer 607. Furthermore, the top view of the combined HEMT device is similar to... Figure 6B Similarly, I will not go into details here.

[0366] In addition, such as Figure 14A The HEMT device shown and such Figure 7A The cross-sectional view and top view of the HEMT device after assembly shown are respectively compared with... Figure 14O and Figure 7B Similarly, I will not go into details here.

[0367] See Figure 14P , Figure 14P Is it like this? Figure 14A The HEMT device shown and such Figure 8A The cross-sectional view of the HEMT device after assembly is shown below. Figure 14P As shown, the combined HEMT device includes only a first GFP608 and a first GFP extension metal 609, and the first GFP608 and the first GFP extension metal 609 are not connected. The first GFP extension metal 609 is symmetrically distributed on both sides of the first GFP608. Other than... Figure 14O The HEMT device shown is similar and will not be described again here. Furthermore, the top view of the assembled HEMT device is similar to... Figure 8B Similarly, I will not go into details here.

[0368] See Figure 14Q , Figure 14Q Is it like this? Figure 14A The HEMT device shown and such Figure 9A The cross-sectional view of the HEMT device after assembly is shown below. Figure 14QAs shown, the combined HEMT device includes: a first insulating dielectric layer 607, a second insulating dielectric layer 901, a second GFP 902, and a second GFP extended metal 903, but no longer includes the first GFP extended metal 609 and the gate metal 1001. The first insulating dielectric layer 607 serves as the gate dielectric. The first insulating dielectric layer 607 is located on the first surface of the barrier layer 605 and covers the second surface of the first semiconductor layer 606, as well as the edge and part of the first surface of the etch stop layer 1401. The first GFP 608 covers the first and second surfaces of the second semiconductor layer 1402, part of the first surface of the etch stop layer 1401, the edge of the first insulating dielectric layer 607, and the second surface of the first insulating dielectric layer 607. The second surface of the first insulating dielectric layer 607 intersects with the first surface of the first insulating dielectric layer 607. The second insulating dielectric layer 901, the second GFP 902, and the second GFP extended metal 903 can be referenced... Figure 9A The corresponding descriptions will not be repeated here. Furthermore, the top view of the combined HEMT device is... Figure 9B Similarly, I will not go into details here.

[0369] In addition, such as Figure 14A The HEMT device shown and such Figure 10A and Figure 11A The cross-sectional view and top view of the HEMT device after assembly shown are respectively compared with... Figure 10B and Figure 11B Similarly, I will not go into details here.

[0370] See Figure 14R , Figure 14R Is it like this? Figure 14A The HEMT device shown and such Figure 12A The cross-sectional view of the HEMT device after assembly is shown below. Figure 14R As shown, in the combined HEMT device, the first GFP608 and the first GFP extension metal 609 are not connected, and the first GFP extension metal 609 is symmetrically distributed on both sides of the first GFP608.

[0371] See Figure 14S , Figure 14S Is it like this? Figure 14A The HEMT device shown and such Figure 13A The cross-sectional view of the HEMT device after assembly is shown below. Figure 14S As shown, the combined HEMT device also includes: a second insulating dielectric layer 1301, a second GFP 1302, and a second GFP extension metal 1303. The second insulating dielectric layer 1301, the second GFP 1302, and the second GFP extension metal 1303 can be referenced... Figure 13A The corresponding descriptions will not be repeated here.

[0372] akin, Figure 15A respectively with Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A The cross-sectional view of the combined HEMT device is shown below. Figures 140 to 14S Similarly, I will not go into details here.

[0373] In conclusion, with Figure 6A Compared to the illustrated embodiments, the HEMT device proposed in this application has a first drain electrode and a second drain electrode symmetrically arranged on both sides of the gate structure layer. A first insulating dielectric layer, a first GFP, and a first GFP extended metal are covered on the first surface of the gate structure layer of the HEMT device. Furthermore, an etch barrier layer can be inserted between the first semiconductor layer and the second semiconductor layer of the gate structure layer. The symmetrically arranged first drain electrode and second drain electrode can achieve bidirectional turn-off of the HEMT device. Under the combined effect of the inverted T-shaped gate structure layer and the inverted U-shaped gate field plate extending from both sides of the first GFP, the electric field distribution at the edge of the gate structure layer can be improved, the short-channel effect can be suppressed, and the HEMT device can meet the breakdown voltage requirements. At the same time, the inverted T-shaped gate structure layer can make the HEMT device have a higher concentration of 2DEG and a lower channel resistance at the channel under the same gate voltage, thereby reducing the on-resistance of the HEMT device.

[0374] Furthermore, an intercalation layer with a higher Al composition can be inserted between different p-type semiconductor layers as an etch termination layer, thereby reducing the difficulty of process implementation and improving the accuracy of etch thickness control.

[0375] In addition, regarding Figure 15A The HEMT device shown in the figure, by providing a third insulating dielectric layer, isolates part of the first semiconductor layer and part of the second semiconductor layer from the gate metal, thereby reducing the increase in gate leakage caused by the thinner first semiconductor layer.

[0376] based on Figure 10A , Figure 11A , Figure 12A and Figure 13A The HEMT device described above, in this application embodiment, proposes another HEMT device that can further reduce on-resistance while ensuring bidirectional blocking and withstand voltage specifications. See [link to relevant documentation]. Figure 16A , Figure 16A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application, as shown below. Figure 16AAs shown, the HEMT device may include: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, a second drain electrode 611, and a gate metal 1001. The first insulating dielectric layer 607 serves as the dielectric layer, and the first GFP 608 is connected to the first GFP extension metal 609.

[0377] Moreover, with Figure 10A , Figure 11A , Figure 12A and Figure 13A The HEMT device shown is different in that it further includes a fourth insulating dielectric layer 1601, and the thickness of the first insulating dielectric layer 607 is less than or equal to the thickness of the fourth insulating dielectric layer 1601.

[0378] See Figure 16A The fourth insulating dielectric layer 1601 is not in contact with the first semiconductor layer 606 and the gate metal 1001. Furthermore, in the HEMT device, the first insulating dielectric layer 607 serves as the gate dielectric, covering the fourth insulating dielectric layer 1601, the first and second surfaces of the gate structure layer, and a portion of the first surface of the nitride epitaxial layer. The fourth insulating dielectric layer 1601 can be formed from materials such as SiN and Al2O3; this embodiment does not limit its composition.

[0379] Specifically, the fourth insulating dielectric layer 1601 covers a portion of the first surface of the barrier layer 605, is distributed on both sides of the first semiconductor layer 606, and does not contact the first semiconductor layer 606; that is, the fourth insulating dielectric layer 1601 and the gate structure layer are arranged alternately. The first insulating dielectric layer 607 covers a portion of the first surface of the barrier layer 605, the fourth insulating dielectric layer 1601, and the first and second surfaces of the gate structure layer.

[0380] like Figure 16A The rest of the HEMT device shown is related to... Figure 10A and Figure 10B The HEMT device shown is similar and will not be described in detail here.

[0381] Additionally, it should be noted that the first GFP extended metal 609 covers the first insulating dielectric layer 607 located on the first surface of the barrier layer 605, and extends along the edge of the fourth insulating dielectric layer 1601 toward the first surface of the fourth insulating dielectric layer 1601, covering the first surface of the fourth insulating dielectric layer 1601. Thus, the first insulating dielectric layer 607, the first GFP extended metal 609, and the barrier layer 1605 located on the first surface of the barrier layer 605 can form a metal-insulator-semiconductor (MIS) gate structure.

[0382] The first surface of the fourth insulating dielectric layer 1601 is the surface of the fourth insulating dielectric layer 1601 that is away from the substrate 601 and parallel to the first surface of the nitride epitaxial layer, and the second surface of the fourth insulating dielectric layer 1601 intersects with the first surface of the fourth insulating dielectric layer 1601. For example, the first surface of the fourth insulating dielectric layer 1601 can be the surface of the fourth insulating dielectric layer 1601 that is away from the substrate 601 and parallel to the first surface of the barrier layer 605.

[0383] Therefore, in addition to the original first gate structure layer A composed of the first semiconductor layer 606 and the gate metal 1001, the HEMT device may also include two MIS gate structures. For example, one of the MIS gate structures can be used as the second gate structure B, and the other MIS gate structure can be used as the third gate structure C. The second gate structure B and the third gate structure C are distributed on both sides of the first gate structure layer A. Then, the HEMT device may include a composite gate structure composed of the first gate structure layer A, the second gate structure B, and the third gate structure C.

[0384] The aforementioned HEMT devices can be fabricated using traditional wafer fabrication techniques. That is, the epitaxial structure of the HEMT device can be prepared first, and then the device structure of the HEMT device can be fabricated on the prepared epitaxial structure to obtain the desired result. Figure 16A The HEMT device shown.

[0385] Specifically, in the process of fabricating HEMT devices, HEMT devices can be manufactured through the following feasible fabrication scheme. Steps 1 to 6 of this fabrication scheme can be used to generate the various epitaxial layers of the HEMT device using an epitaxial process, and steps 7 to 10 can be used to etch part of the epitaxial layers using an etching technique, thereby forming the HEMT device.

[0386] Steps 1 to 6 in the embodiments of this application can be found in [reference needed]. Figures 6D to 6I The steps shown will not be repeated here.

[0387] After generating the first semiconductor layer 606, step 7 can be performed, see [link to step 7]. Figure 16BA metal layer is deposited on the first semiconductor layer 606, and the deposited metal layer is etched according to a pre-set pattern to obtain gate metal 1001. Then, using gate metal 1001 as a mask, the semiconductor layer on the barrier layer 605 is etched to obtain... Figure 16B The first semiconductor layer 606 and the gate metal 1001 shown form the first gate structure layer A.

[0388] Step 8, see Figure 16C In such Figure 16B A fourth insulating dielectric layer 1601 is deposited on the first surface of the barrier layer 605, the second surface of the first semiconductor layer 606, and the first surface of the gate metal 1001. A portion of the fourth insulating dielectric layer 1601 on the first surface of the gate metal 1001 and the second surface of the first semiconductor layer 606 is removed by etching, and composite gate windows (W1 and W2) are formed on both sides of the first semiconductor layer 606.

[0389] Step 9, see Figure 16D In such Figure 16C The first surface of the fourth insulating dielectric layer 1601, the first surface of the barrier layer 605, the second surface of the first semiconductor layer 606, and a portion of the first surface and edge of the gate metal 1001 are shown to have a first insulating dielectric layer 607 deposited.

[0390] Step 10, see Figure 16E In such Figure 16D Metal is deposited in the etching window of the active region to form a first drain electrode 610 and a second drain electrode 611. A first insulating dielectric layer 607 is partially etched above the gate metal 1001 to form a gate etching window. An inverted U-shaped gate field plate composed of a first GFP 608 and a first GFP extension metal 609 is formed above the first gate structure A and the composite gate window, extending to both sides from the first GFP 608, so that the first GFP 608 contacts the gate metal 1001 through the gate etching window.

[0391] It should be noted that, in accordance with Figures 16B to 16E During the fabrication of HEMT devices, step 8 of the process can be adjusted to obtain, as shown below. Figure 17A The HEMT device shown, Figure 17A This is a cross-sectional schematic diagram of another HEMT device provided in the embodiments of this application. The HEMT device includes: a substrate 601, a nucleation layer 602, a buffer layer 603, a channel layer 604, a barrier layer 605, a first semiconductor layer 606, a first insulating dielectric layer 607, a first GFP 608, a first GFP extension metal 609, a first drain electrode 610, a second drain electrode 611, a gate metal 1001, and a fourth insulating dielectric layer 1601.

[0392] Among them, such as Figure 17AThe HEMT device shown is similar to... Figure 16A The devices shown are similar and will not be described in detail here.

[0393] Preparation such as Figure 17A The process of fabricating the HEMT device shown is similar to that of preparing it. Figure 16A The process for the HEMT device shown is similar. However, when performing step 8, after the fourth insulating dielectric layer 1601 has been etched to obtain the composite gate window formed by the barrier layer 605, the barrier layer 605 can be further shallowly etched to form a concave gate structure.

[0394] Preparation such as Figure 17A The processes in steps 1 to 7 and steps 9 to 10 of the HEMT device shown are similar to... Figure 16B , Figure 16D and Figure 16E The preparation process is similar to that described above, and will not be repeated here.

[0395] For the preparation steps corresponding to step 8, please refer to [link / reference]. Figure 17B First, a fourth insulating dielectric layer 1601 can be deposited on the first surface of the barrier layer 605 and the first and second surfaces of the gate structure layer. Then, a portion of the fourth insulating dielectric layer 1601 on the first surface of the gate metal 1001 and the second surface of the first semiconductor layer 606 can be etched to remove part of the fourth insulating dielectric layer 1601, forming a composite gate window. Simultaneously, after etching the portion of the fourth insulating dielectric layer 1601 on the second surface of the first semiconductor layer 606 near the gate structure layer, further etching can be performed... Figure 17B The barrier layer 605 shown is shallowly etched so that the depth of the recessed gate in the barrier layer 605 meets a preset condition, or the thickness of the etched barrier layer 605 meets a preset condition. For example, the depth of the recessed gate can be 3 to 5 nm, and the thickness of the etched barrier layer 605 can be 10 to 15 nm.

[0396] in addition, Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A The field plate layer and insulating dielectric layer in the HEMT device shown can be applied to Figure 16A and Figure 17A The field plate layer and insulating dielectric layer in the middle make it possible to... Figure 16A and Figure 17A The HEMT devices shown have different gate field plate structures, which can further reduce the channel on-resistance and reduce the on-resistance of the HEMT devices while meeting the breakdown voltage requirements.

[0397] Specifically, see Figure 16F , Figure 16F Is it like this? Figure 16A The HEMT device shown and such Figure 6A The cross-sectional view of the HEMT device after assembly is shown below. Figure 16F As shown, the combined HEMT device includes a first GFP 608 and a first GFP extended metal 609, but no longer includes the gate metal 1001, and the first GFP 608 is in contact with a portion of the first surface of the first semiconductor layer 606. Furthermore, the top view of the combined HEMT device is... Figure 6B Similarly, I will not go into details here.

[0398] like Figure 16A The HEMT device shown and such Figure 7A The cross-sectional view and top view of the HEMT device after assembly are shown. Figure 16F and Figure 7B Similarly, I will not go into details here.

[0399] See Figure 16G , Figure 16G Is it like this? Figure 16A The HEMT device shown and such Figure 8A The cross-sectional view of the HEMT device after assembly is shown below. Figure 16G As shown, the combined HEMT device includes a first GFP608 and a first GFP extension metal 609, with the first GFP extension metal 609 symmetrically distributed on both sides of the first GFP608. The first GFP extension metal 609 may include at least two spaced-apart portions, such as... Figure 16G As shown, the first GFP extension metal 609 may include a first portion connected to the first GFP 608, and may also include a second portion spaced apart from the first portion. Furthermore, the top view of the combined HEMT device is... Figure 8B Similarly, I will not go into details here.

[0400] See Figure 16H , Figure 16H Is it like this? Figure 16A The HEMT device shown and such Figure 9A The cross-sectional view of the HEMT device after assembly is shown below. Figure 16HAs shown, the combined HEMT device may further include: a second insulating dielectric layer 901, a second GFP 902, and a second GFP extended metal 903, but no longer includes the gate metal 1001. The second insulating dielectric layer 901 covers the first and second surfaces of the gate structure layer, as well as the first surface of the first insulating dielectric layer 607. Furthermore, the first GFP 608 is in contact with a portion of the first surface of the first semiconductor layer 606. Additionally, the second GFP 902 covers the second surface and a portion of the first surface of the second insulating dielectric layer 901 and is electrically connected to the first GFP 608. Moreover, the top view of the combined HEMT device is... Figure 9B Similarly, I will not go into details here.

[0401] In addition, such as Figure 16A The HEMT device shown and such Figure 10A and Figure 11A The cross-sectional view and top view of the HEMT device after assembly shown are respectively compared with... Figure 10A and Figure 11B Similarly, I will not go into details here.

[0402] See Figure 16I , Figure 16I Is it like this? Figure 16A The HEMT device shown and such Figure 12A The cross-sectional view of the HEMT device after assembly is shown below. Figure 16I As shown, in the combined HEMT device, the first GFP608 and the first GFP extension metal 609 are not connected, and the first GFP extension metal 609 is symmetrically distributed on both sides of the first GFP608. The first GFP extension metal 609 may include at least two parts spaced apart, such as... Figure 16G As shown, the first GFP extension metal 609 may include a first portion connected to the first GFP 608, and may also include a second portion spaced apart from the first portion.

[0403] See Figure 16J , Figure 16J Is it like this? Figure 16A The HEMT device shown and such Figure 13A The cross-sectional view of the HEMT device after assembly is shown below. Figure 16J As shown, the combined HEMT device also includes: a second insulating dielectric layer 1301, a second GFP 1302, and a second GFP extension metal 1303. The second insulating dielectric layer 1301, the second GFP 1302, and the second GFP extension metal 1303 can be referenced... Figure 13A The corresponding descriptions will not be repeated here.

[0404] akin, Figure 17A respectively with Figure 6A, Figure 7B , Figure 8A , Figure 9A , Figure 10A , Figure 11B , Figure 12A and Figure 13A The cross-sectional view of the combined HEMT device is shown below. Figures 16F to 16J Similarly, I will not go into details here.

[0405] In conclusion, with Figure 6A Compared to the illustrated implementation examples, the HEMT device proposed in this application uses a first semiconductor layer to form a first gate structure, and combines it with a MIS gate structure to form a composite gate structure. A first drain electrode and a second drain electrode are symmetrically arranged on both sides of the gate. The symmetrical arrangement of the first drain electrode and the second drain electrode enables bidirectional turn-off of the HEMT device. Furthermore, under the combined effect of the composite gate structure and the inverted U-shaped symmetrical extended field plate structure composed of the first GFP and the first GFP extended metal, the electric field distribution at the edge of the gate structure layer can be improved, the short-channel effect can be suppressed, and the HEMT device can meet the breakdown voltage requirements. At the same time, through the composite gate structure, the HEMT device has a higher concentration of 2DEG in the channel under the same gate voltage, thereby reducing the on-resistance of the HEMT device.

[0406] It should be noted that, for Figure 17A The HEMT device shown forms a recessed gate by etching part of the barrier layer on both sides of the first gate structure. This can partially deplete the two-dimensional electron gas at the heterojunction below the recessed gate, further improving the channel electric field distribution and increasing the breakdown voltage.

[0407] Regarding the aforementioned HEMT devices, this application proposes a symmetrical drain GaN HEMT device with gate voltage clamping between the gate and drain, wherein the clamping device is a common-source GaN HEMT device. See [link to relevant documentation] Figure 18 , Figure 18 This is an equivalent circuit diagram of a HEMT device provided in an embodiment of this application, such as... Figure 18 As shown, the HEMT device may include: a main HEMT device and a common-source HEMT device, wherein the main HEMT device can be... Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A The HEMT device shown will not be described in detail here.

[0408] Common-source HEMT devices have a higher threshold voltage than master HEMT devices. When the master HEMT device is off, the common-source HEMT device is also off, resulting in a combined device being off. When the master HEMT device is active, the common-source HEMT remains off, without affecting the gate-drain electrical characteristics of the master HEMT device. When the gate voltage of the master HEMT device exceeds the normal operating voltage, i.e., exceeds the threshold voltage of the common-source HEMT, the common-source HEMT turns on and discharges current, preventing the gate voltage of the master HEMT device from rising further, thus providing gate voltage clamping protection.

[0409] See Figure 19A , Figure 19A This is a cross-sectional schematic diagram of one type of common-source HEMT device, as shown above. Figure 19A As shown, the common-source HEMT device may include, from bottom to top: a substrate 1901, a nucleation layer 1902 epitaxially formed on the substrate 1901, a buffer layer 1903 epitaxially formed on the nucleation layer 1901, a channel layer 1904 epitaxially formed on the buffer layer 1903, a barrier layer 1905 epitaxially formed on the channel layer 1904, and a fifth insulating dielectric layer 1906 epitaxially formed on the barrier layer 1905.

[0410] The substrate 1901 can be formed from Si, sapphire, or SiC heteroepitaxial materials, or from GaN homoepitaxial substrate materials, etc.; the fifth insulating dielectric layer 1906 can be formed from SiN or other materials, used for surface passivation and metal isolation; the nucleation layer 1902, buffer layer 1903, channel layer 1904, and barrier layer 1905 can form a nitride epitaxial layer, which is connected to... Figure 6A The nitride epitaxial layer of the corresponding HEMT device is similar, and will not be described in detail here.

[0411] Furthermore, the common-source HEMT device may also include: a first recessed gate A and a second recessed gate B formed by etching through the fifth insulating dielectric layer 1906 and continuing to etch the barrier layer 1905, and a sixth insulating dielectric layer 1907 covering the fifth insulating dielectric layer 1906, the first recessed gate A and the second recessed gate B. The sixth insulating dielectric layer 1907 serves as the gate dielectric for the first recessed gate A and the second recessed gate B and may be formed from materials such as SiN or Al2O3.

[0412] It should be noted that in practical applications, the first recessed gate A and the second recessed gate B may only penetrate the fifth insulating dielectric layer 608, but not the barrier layer 1905. This application embodiment does not limit this.

[0413] Corresponding to the first recessed gate A and the second recessed gate B, the first clamping gate 1908 and the first clamping gate 1909 can be deposited in both the first recessed gate A and the second recessed gate B using active region ohmic metal or gate metal deposition processes. The first recessed gate A, the sixth insulating dielectric layer 1907, and the first clamping gate 1908 form the first recessed gate structure C, and the second recessed gate B, the sixth insulating dielectric layer 1907, and the second clamping gate 1908 form the second recessed gate structure D.

[0414] Furthermore, a clamping source 1910 is disposed between the first clamping gate 1908 and the first clamping gate 1909. A first clamping drain 1911 and a second clamping drain 1912 are disposed substantially symmetrically on both sides of the first clamping gate 1908, the first clamping gate 1909, and the clamping source 1910. The clamping source 1910 serves as the common source of the first clamping gate 1908 and the first clamping gate 1909, and as the common source of the first clamping drain 1911 and the second clamping drain 1912, thus forming a common source structure. The clamping source 1910 can be electrically connected to both the first clamping gate 1908 and the first clamping gate 1909.

[0415] In addition, the clamping source 1910, the first clamping drain 1911, and the second clamping drain 1912 of the common-source HEMT device can penetrate the fifth insulating dielectric layer 1906 and the barrier layer 1905 and contact the channel layer 1904. However, in practical applications, the clamping source 1910, the first clamping drain 1911, and the second clamping drain 1912 can also penetrate only the fifth insulating dielectric layer 1906 but not the barrier layer 1905. This application does not limit this.

[0416] The first clamping gate 1908, the first clamping gate 1909, the clamping source 1910, the first clamping drain 1911, and the second clamping drain 1912 can all be composed of materials such as Ti, TiN, Al, or Ta. This application embodiment does not limit this.

[0417] It should be noted that the first clamping drain 1911 and the second clamping drain 1912 can be distributed substantially symmetrically on both sides of the clamping source 1910 to achieve similar breakdown voltages from the clamping source 1910 to the first clamping drain 1911 and from the clamping source 1910 to the second clamping drain 1912. Furthermore, the first clamping gate 1908 and the first clamping gate 1909 can be distributed substantially symmetrically on both sides of the clamping source 1910 to achieve substantially consistent clamping voltages for the first recessed gate structure C and the second recessed gate structure D.

[0418] Furthermore, Figure 19B This is a simplified top view of a composite HEMT device, specifically a simplified top view of a composite HEMT device with gate clamping. Figure 19BThe left side is a top view of the main HEMT device. Figure 19B The diagram on the right is a top view of a common-source HEMT device.

[0419] Since the main HEMT device is illustrated using the HEMT device shown in Figure 10A as an example, the top view of the main HEMT device will not be described again.

[0420] See Figure 19B Within the barrier layer 1905, a first clamping gate 1908 and a first clamping gate 1909 are deposited through active region metal deposition. A clamping source 1910 is disposed between the first clamping gate 1908 and the first clamping gate 1909 within the barrier layer 1905. For example, the clamping source 1910 can be disposed in the middle region between the first clamping gate 1908 and the first clamping gate 1909. A first clamping drain 1911 and a second clamping drain 1912 are disposed on both sides of the clamping source 1910 in a basically symmetrical manner. The distance between the first clamping drain 1911 and the clamping source 1910 is greater than or equal to the distance between the first clamping gate 1908 and the clamping source 1910, and the distance between the second clamping drain 1912 and the clamping source 1910 is greater than or equal to the distance between the first clamping gate 1909 and the clamping source 1910, thereby forming a common source structure.

[0421] Furthermore, the first drain electrode 610 of the main HEMT device is electrically connected to the first clamp drain 1911 of the common-source HEMT device through the first metal 1913, the second drain electrode 611 of the main HEMT device is electrically connected to the second clamp drain 1912 of the common-source HEMT device through the second metal 1914, and the gate metal 612 of the main HEMT device and the first GFP608 extending symmetrically on both sides of the inverted U-shape are electrically connected to the first clamp gate 1908, the first clamp gate 1909 and the clamp source 1910 of the common-source HEMT device through the third metal 1915.

[0422] The aforementioned common-source HEMT device can be fabricated together with the main HEMT device using traditional wafer fabrication techniques. That is, the common-source HEMT device can be fabricated simultaneously with the main HEMT device using appropriate process steps. The following... Figure 10A The HEMT device shown is the master HEMT device, illustrating the process flow for jointly fabricating a symmetrical drain master HEMT device and a common-source HEMT device.

[0423] Specifically, in the preparation process, see Figure 19C The following feasible fabrication scheme can be used, in which steps 1 to 6 can be generated by epitaxial process to generate each epitaxial layer, and steps 7 to 11 can be used by etching technology to etch part of the epitaxial layer, thereby forming a symmetrical drain GaN HEMT device with gate voltage clamp between the gate and drain.

[0424] Steps 1 to 6 in the embodiments of this application are related to... Figures 10C to 10E The steps shown are similar and will not be repeated here.

[0425] After the first semiconductor layer 606 is obtained through epitaxial growth, step 7 can be performed, see [link to relevant documentation]. Figure 19D Metal is deposited on the surface of the first semiconductor layer 606, and the gate metal 1001 of the main HEMT device is formed by etching. The first semiconductor layer 606 is etched using the gate metal 1001 as a mask to form the gate structure layer of the main HEMT device.

[0426] Step 8, see Figure 19E In such Figure 19D A fifth insulating dielectric layer 607 (1906) is deposited on the first and second surfaces of the gate structure layer shown, and the fifth insulating dielectric layer 607 (1906) is etched to form the recessed gate window of the common-source HEMT device.

[0427] Step 9, see Figure 19F Continue etching Figure 19E The barrier layer 605 (1905) at the recessed gate window shown forms the first recessed gate A and the second recessed gate B, and deposits the sixth insulating dielectric layer 1907.

[0428] Step 10, see Figure 19G Continue etching the fifth insulating dielectric layer 607 (1906) and the sixth insulating dielectric layer 1907 to form the first drain window, the second drain window and the etched window of the main HEMT device, and the first clamped drain window 1911, the second clamped drain window 1912 and the first clamped source window 1910 of the common source HEMT device.

[0429] Step 11, see Figure 19H Through an active region metal deposition process, the first drain electrode 610, the second drain electrode 611, the first GFP 608 and the first GFP extension metal 609 of the main HEMT device, and the first clamped drain 1911, the second clamped drain 1912, the first clamped gate 1908, the first clamped gate 1909 and the clamped source 1910 of the common source HEMT device are formed.

[0430] To further verify the effectiveness of the symmetrical drain GaNHEMT device with gate voltage clamping between the gate and drain proposed in the embodiments of this application, the common-source HEMT device proposed in the embodiments of this application can be simulated using simulation software.

[0431] During the simulation, the common-source HEMT devices can be configured according to the dimensions shown in Table 3. The reference numerals in Table 3 can be found in [reference needed]. Figure 19I , Figure 19IThe diagram shows the labels corresponding to each structure in the common-source HEMT device, and Table 3 shows the dimensions corresponding to each label. (See also...) Figure 19I As shown in Table 3, the thickness 101 of the substrate 1901 can be 10 μm; the thickness 102 of the buffer layer 1903 can be 2 μm; the thickness 103 of the channel layer 1904 can be 30 nm; the thickness 104 of the barrier layer 1905 can be 16 nm, and the barrier layer 1905 is formed from AlGaN material with an Al composition ratio of 18%; the thickness 105 of the fifth insulating dielectric layer 1906 can be 40 nm; the thickness 107 of the sixth insulating dielectric layer 1907 can be 20 nm, and both the fifth insulating dielectric layer 1906 and the sixth insulating dielectric layer 1907 can be formed from SiN.

[0432] Furthermore, for the entire common-source HEMT device, the size of the lateral cell 100 of the common-source HEMT device can be 4.4 μm; the lengths 121 of the first clamping gate 1908 and 122 of the first clamping gate 1909 can both be 0.5 μm; the lengths 113 of the clamping source 1910, 111 of the first clamping drain 1911, and 112 of the second clamping drain 1912 can both be 0.2 μm; the distance 131 between the boundary of the first clamping gate 1908 and the boundary of the first clamping drain 1911 is... The dimensions can be 1 μm; the distance 132 between the boundary of the first clamping gate 1909 and the boundary of the second clamping drain 1912 can be 1 μm; the distance 141 between the boundary of the first clamping gate 1908 and the boundary of the clamping source 1910 can be 0.5 μm; the distance 142 between the boundary of the first clamping gate 1909 and the boundary of the clamping source 1910 can be 0.5 μm; the dimensions of the left gate field plate length 151 and the right gate field plate length 152 of the common source structure can both be 0.2 μm.

[0433] Table 3

[0434]

[0435]

[0436] It should be noted that in simulation experiments, the buffer layer and the nucleation layer can be treated as the same epitaxial layer, in which case the nucleation layer is not required, and only the buffer layer needs to be set for simulation. Therefore, Table 3 and Figure 19I None of the dimensions include the size corresponding to the nucleation layer. Moreover, in practical applications, the dimensions of the aforementioned common-source HEMT devices can be adjusted according to the performance requirements of the common-source HEMT devices. The embodiments of this application do not limit the size of the common-source HEMT devices.

[0437] First, the breakdown voltage of the drain electrode is simulated. With the potentials of the first clamping gate 1908, the first clamping gate 1909, the clamping source 1910, and the second clamping drain 1912 all at low levels, the potential of the first clamping drain 1911 is gradually increased from 0V. During this increase, the current magnitude of the first clamping drain 1911 can be read incrementally. (See...) Figure 19J The curve showing the change of the current of the first clamp drain 1911 as the potential of the first clamp drain 1911 increases indicates that the breakdown voltage from the first clamp drain 1911 to the second clamp drain 1912 is much greater than 50V, which meets the reverse breakdown withstand voltage between the gate and drain of the main HEMT device.

[0438] Similarly, the breakdown voltage from the second clamp drain 1912 to the first clamp drain 1911 can be simulated in the same manner as described above, referring to... Figure 19K It can be determined that the breakdown voltage from the second clamp drain 1912 to the first clamp drain 1911 is also much greater than 50V, which meets the reverse breakdown withstand voltage between the gate and drain of the main HEMT device.

[0439] Next, the gate voltage clamping curve of the common-source HEMT device was simulated. With the potential of the second clamping drain 1912 low and the potential of the first clamping drain 1911 fixed at 0.1V, the potentials of the first clamping gate 1908, the first clamping gate 1909, and the clamping source 1910 were gradually increased from 0V. During this increase, the current magnitude of the first drain electrode of the main HEMT device could be gradually read. If the current magnitude of the first drain electrode of the main HEMT device increased to 10μA / mm, the potential from the first drain electrode to the gate of the main HEMT device at this point could be used as the clamping voltage from the first clamping drain 1911 to the second clamping drain 1912. (See also...) Figure 19L The curve shows the change of the current of the first drain electrode as the potential from the first drain electrode to the gate increases. When the current of the first drain electrode rises to 10 μA / mm and the potential from the first drain electrode to the gate reaches 5.5V, it can be determined that the clamping voltage from the first clamp drain 1911 to the second clamp drain 1912 is 5.5V, which meets the clamping voltage requirement between the gate and the first drain electrode of the main HEMT device.

[0440] Similarly, the clamping voltage from the second clamping drain 1912 to the first clamping drain 1911 can be simulated in the same manner as described above, referring to... Figure 19M It can be determined that the clamping voltage from the second clamp drain 1912 to the first clamp drain 1911 is 5.5V.

[0441] In summary, the HEMT device proposed in this application uses a GaN HEMT device with symmetrical drain as the main HEMT device and a common-source HEMT device as the gate voltage clamping device of the main HEMT device. By using the common-source HEMT device as the gate voltage clamping device, the HEMT device has a gate voltage clamping characteristic that is basically symmetrical at both ends.

[0442] Furthermore, by etching the fifth insulating dielectric layer and the barrier layer and filling the gate dielectric, a concave-gate GaN MIS-HEMT device is formed, resulting in a higher threshold voltage for the HEMT device. As a common-source clamped HEMT device, this allows a single common-source HEMT device to effectively clamp a gate voltage above 5V. Additionally, by adjusting the thickness of the barrier layer retained in the first and second concave gates, and the thickness of the sixth insulating dielectric layer (gate dielectric 1907), the clamping voltage between the gate and the first drain, or between the gate and the second drain, of the main HEMT device can be effectively adjusted to meet different clamping requirements.

[0443] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0444] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0445] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0446] In the embodiments provided in this application, it should be understood that the disclosed HEMT device and the method for manufacturing the HEMT device can be implemented in other ways.

[0447] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0448] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A HEMT device, characterized in that, include: Substrate, nitride epitaxial layer, gate structure layer, field plate layer, first drain electrode, second drain electrode and first insulating dielectric layer; The nitride epitaxial layer is disposed on the substrate, and the gate structure layer, the first drain electrode, the second drain electrode and the first insulating dielectric layer are disposed on the first surface of the nitride epitaxial layer. The first surface of the nitride epitaxial layer is the surface of the nitride epitaxial layer away from the substrate, and the first drain electrode and the second drain electrode are symmetrically distributed on both sides of the gate structure layer. The gate structure layer includes: a first semiconductor layer, wherein the first semiconductor layer is formed of a p-type nitride; The first insulating dielectric layer covers the second surface and part of the first surface of the gate structure layer. The first surface of the gate structure layer is the surface of the gate structure layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the gate structure layer intersects with the first surface of the gate structure layer. The thickness of the first insulating dielectric layer is less than the thickness of the first semiconductor layer. The field plate layer includes: a first gate field plate GFP and a first GFP extended metal. The first GFP covers a portion of the first surface of the gate structure layer, as well as the second surface and a portion of the first surface of the first insulating dielectric layer. The first GFP extended metal is symmetrically distributed on both sides of the first GFP and covers a portion of the first surface of the first insulating dielectric layer. The first surface of the first insulating dielectric layer is the surface of the first insulating dielectric layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the first insulating dielectric layer intersects with the first surface of the first insulating dielectric layer.

2. The HEMT device according to claim 1, characterized in that, The first GFP is connected to the first GFP extended metal, and the area of ​​the field plate layer in contact with the second surface of the first insulating dielectric layer is smaller than the area of ​​the second surface of the gate structure layer in contact with the first insulating dielectric layer.

3. The HEMT device according to claim 1, characterized in that, The first GFP and the first GFP extended metal spacer are arranged.

4. The HEMT device according to claim 1, characterized in that, The HEMT device further includes: a second insulating dielectric layer; The second insulating dielectric layer covers the first and second surfaces of the first GFP, the first surface of the first GFP extended metal, and the first surface of the first insulating dielectric layer. The first surface of the first GFP is the surface of the first GFP that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the first GFP intersects with the first surface of the first GFP. The first surface of the first GFP extended metal is the surface of the first GFP extended metal that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The field plate layer further includes: a second GFP and a second GFP extended metal; The second GFP covers the second surface and part of the first surface of the second insulating dielectric layer, the second GFP extended metal covers part of the first surface of the second insulating dielectric layer, the second GFP extended metal is symmetrically distributed on both sides of the second GFP, the first surface of the second insulating dielectric layer is the surface of the second insulating dielectric layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer, and the second surface of the second insulating dielectric layer intersects with the first surface of the second insulating dielectric layer. The second insulating dielectric layer is provided with a first etching window, and the second GFP is electrically connected to the first GFP through the first etching window.

5. The HEMT device according to any one of claims 1 to 4, characterized in that, The gate structure layer further includes: gate metal; The gate metal covers the first surface of the first semiconductor layer, and the first surface of the first semiconductor layer is the surface of the first semiconductor layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer; The first insulating dielectric layer is provided with a second etching window, and the first GFP is electrically connected to the gate metal through the second etching window.

6. The HEMT device according to claim 5, characterized in that, The gate structure layer further includes: a second semiconductor layer; The second semiconductor layer is located on the first surface of the first semiconductor layer, and the projected area of ​​the second semiconductor layer on the nitride epitaxial layer is smaller than the projected area of ​​the first semiconductor layer on the nitride epitaxial layer. The gate metal covers a portion of the first surface of the first semiconductor layer, as well as the first and second surfaces of the second semiconductor layer. The first surface of the second semiconductor layer is the surface of the second semiconductor layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the second semiconductor layer intersects with the first surface of the second semiconductor layer.

7. The HEMT device according to claim 6, characterized in that, The gate structure layer further includes: an etch barrier layer; The etching barrier layer is located on the first surface of the first semiconductor layer, and the projected area of ​​the etching barrier layer on the nitride epitaxial layer is equal to the projected area of ​​the first semiconductor layer on the nitride epitaxial layer. The second semiconductor layer is located on the first surface of the etch barrier layer, and the first surface of the etch barrier layer is the surface of the etch barrier layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer; The gate metal covers a portion of the first surface of the etch barrier layer, as well as the first and second surfaces of the second semiconductor layer.

8. The HEMT device according to claim 6, characterized in that, The centerline of the projection of the second semiconductor layer onto the nitride epitaxial layer coincides with the centerline of the projection of the first semiconductor layer onto the nitride epitaxial layer.

9. The HEMT device according to claim 6, characterized in that, The gate structure layer further includes: a third insulating dielectric layer; The third insulating dielectric layer covers a portion of the first surface of the first semiconductor layer or a portion of the first surface of the etching barrier layer, and covers the second surface and a portion of the first surface of the second semiconductor layer; The gate metal covers a portion of the first surface of the second semiconductor layer, as well as the first and second surfaces of the third insulating dielectric layer. The first surface of the third insulating dielectric layer is the surface of the third insulating dielectric layer that is away from the substrate and parallel to the first surface of the nitride epitaxial layer. The second surface of the third insulating dielectric layer intersects with the first surface of the third insulating dielectric layer.

10. The HEMT device according to claim 5, characterized in that, The HEMT device further includes: a fourth insulating dielectric layer; The fourth insulating dielectric layer covers a portion of the first surface of the nitride epitaxial layer, and the fourth insulating dielectric layer is distributed on both sides of the gate structure layer and is spaced apart from the gate structure layer; The first insulating dielectric layer covers a portion of the first surface of the fourth insulating dielectric layer, the nitride epitaxial layer, and the first and second surfaces of the gate structure layer; The first GFP is extended metallized with the first GFP; The first GFP extended metal, the first insulating dielectric layer located on the first surface of the nitride epitaxial layer, and the nitride epitaxial layer together form a metal-insulator-semiconductor (MIS) gate structure, and the MIS gate structure and the gate structure layer form a composite gate structure.

11. The HEMT device according to claim 10, characterized in that, The nitride epitaxial layer includes: a barrier layer; The gate structure layer, the first insulating dielectric layer, and the fourth insulating dielectric layer are all located on the side of the barrier layer away from the substrate; The thickness of the barrier layer at the MIS gate structure is less than the thickness of the barrier layer in other regions besides the MIS gate structure.

12. The HEMT device according to any one of claims 1 to 4, characterized in that, The substrate is formed from a heteroepitaxial substrate or a homoepitaxial substrate, wherein the heteroepitaxial substrate is made of silicon, sapphire or silicon carbide, and the homoepitaxial substrate is made of gallium nitride.

13. The HEMT device according to any one of claims 1 to 4, characterized in that, The nitride epitaxial layer includes: a nucleation layer disposed on the substrate, a buffer layer disposed on the nucleation layer, a channel layer disposed on the buffer layer, and a barrier layer disposed on the channel layer; The nucleation layer is formed from aluminum nitride, the buffer layer is formed from aluminum gallium nitride or gallium nitride, the channel layer is formed from undoped gallium nitride, and the barrier layer is formed from aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride.

14. The HEMT device according to any one of claims 1 to 4, characterized in that, The first semiconductor layer, the second semiconductor layer, or the etch barrier layer are formed from gallium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride, or indium aluminum gallium nitride.

15. A composite HEMT device, characterized in that, include: The main HEMT device and the common-source HEMT device, wherein the main HEMT device is any one of the HEMT devices described in claims 1 to 14; The common-source HEMT device includes: a substrate, a nitride epitaxial layer, a first clamped drain, a second clamped drain, a clamped source, a first clamped gate, and a second clamped gate; The first drain electrode of the main HEMT device is electrically connected to the first clamp drain of the common-source HEMT device, the second drain electrode of the main HEMT device is electrically connected to the second clamp drain of the common-source HEMT device, and the field plate layer of the main HEMT device is electrically connected to the first clamp gate, the second clamp gate, and the clamp source of the common-source HEMT device.

16. The composite HEMT device according to claim 15, characterized in that, The common-source HEMT device adopts a concave gate structure; The first clamping gate, the second clamping gate, the clamping source, the first clamping drain, and the second clamping drain together form a common source structure. The first clamping gate and the second clamping gate are symmetrically distributed on both sides of the clamping source, and the first clamping drain and the second clamping drain are symmetrically distributed on both sides of the clamping source.

17. The composite HEMT device according to claim 15 or 16, characterized in that, The nitride epitaxial layer includes: a nucleation layer epitaxially formed on the substrate, a buffer layer epitaxially formed on the nucleation layer, a channel layer epitaxially formed on the buffer layer, and a barrier layer disposed on the channel layer. The common-source HEMT device further includes: a fifth insulating dielectric layer and a sixth insulating dielectric layer, wherein the fifth insulating dielectric layer covers the first surface of the barrier layer other than the first clamped drain, the second clamped drain, the first clamped gate, the second clamped gate and the clamped source, and the sixth insulating dielectric layer covers the first surface and the second surface of the nitride epitaxial layer located at the first clamped gate and the second clamped gate; The thickness of the barrier layer located at the first clamping gate and the second clamping gate is less than the thickness of the barrier layer in other regions.

18. A wafer, characterized in that, The wafer includes a HEMT device as described in any one of claims 1 to 17.

19. A packaged device, characterized in that, The packaged device includes the HEMT device as described in any one of claims 1 to 17.

20. An electronic device, characterized in that, The electronic device includes the HEMT device as described in any one of claims 1 to 17.

21. An electronic device, characterized in that, The electronic device includes: a charging integrated circuit, a wired charging interface, and at least one HEMT device as described in any one of claims 1 to 17, wherein at least one HEMT device includes: a first HEMT device; The gate of the first HEMT device is connected to the first control terminal of the charging integrated circuit, the first drain electrode of the first HEMT device is connected to the wired charging interface, and the second drain electrode of the first HEMT device is connected to the input terminal of the charging integrated circuit. The output terminal of the charging integrated circuit is connected to the battery.

22. The electronic device according to claim 21, characterized in that, The electronic device further includes: a wireless receiver integrated circuit and a wireless charging coil; at least one of the HEMT devices further includes: a second HEMT device. The gate of the second HEMT device is connected to the second control terminal of the charging integrated circuit, the first drain electrode of the second HEMT device is connected to the wireless charging coil through the wireless receiving integrated circuit, and the second drain electrode of the second HEMT device is connected to the input terminal of the charging integrated circuit.

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