Entity layer circuitry for multi-wire interface

Abstract

The application discloses an entity layer circuit, which specifically comprises N signal connection pads, four or six signal entity medium additional sublayers, and M shielding connection pads. The M shielding connection pads comprise a first shielding connection pad coupled to the four signal entity medium additional sublayer or first to third shielding connection pads coupled to the six signal entity medium additional sublayer. The first shielding connection pad is located between a second signal connection pad and a third signal connection pad among the signal connection pads; the second shielding connection pad is located between the third signal connection pad and a fourth signal connection pad among the signal connection pads; the third shielding connection pad is located between the fourth signal connection pad and a fifth signal connection pad among the signal connection pads, and M and N are positive integers.

Description

[0001] This invention is a divisional application of application number 201810799479.8 filed on July 19, 2018, entitled "Physical Layer Circuit for Multi-line Interface". Technical Field

[0002] This invention relates to multi-line data interfaces, and more particularly to physical layer circuits and physical media add-on sublayers applicable to different physical layer modes of multi-line data interfaces. Background Technology

[0003] Mobile devices such as smartphones contain various components for different purposes, such as application processors, displays, and CMOS image sensors. These components need to be interconnected through physical interfaces. For example, an application processor can provide frame data to the display through an interface to present visual content. Alternatively, a CMOS image sensor can provide sensed image data to the application processor through an interface to output photos or videos.

[0004] The MIPI specification, developed by the Mobile Industry Processor Interface (MIPI) Alliance, is widely used for inter-component signal communication and data transmission in the aforementioned mobile devices. MIPI D-PHY is one of the MIPI specifications. In the MIPI D-PHY interface, communication is achieved through one clock channel and one to four data channels. Each data channel contains differential signal pairs. The clock channel is used to transmit differential clock signals, while each data channel is used to transmit differential data signals.

[0005] To meet the high-speed transmission requirements of specific data (such as image data), the MIPI Alliance developed and defined the MIPI C-PHY specification. In the MIPI C-PHY interface, communication is achieved through three signal lines. Each signal line transmits a three-valued signal, which can be converted into a binary logic signal. A key feature of MIPI C-PHY is the embedding of a clock signal within the data signal; the receiving end executes clock and data responses while receiving the data signal.

[0006] While the MIPI C-PHY interface can effectively achieve high-speed signal communication and provide high throughput, it is not necessary for all components and requirements in mobile devices. Therefore, it would be highly desirable for manufacturers to provide functional blocks and / or integrated circuits that are compatible with both MIPI D-PHY and MIPI C-PHY specifications. Thus, it is necessary to provide integrated circuits or semiconductor devices that support both MIPI D-PHY and MIPI C-PHY specifications. Summary of the Invention

[0007] One object of this invention is to provide physical layer circuitry and multi-signal physical media add-on sublayers suitable for different physical layer modes of multi-wire interfaces. The physical layer circuitry and physical media add-on sublayers proposed in this invention are designed with the signal characteristic differences between different physical layer modes, such as MIPI D-PHY and MIPI C-PHY, in mind. This enables a combined physical layer (combo PHY) device that can seamlessly connect to either MIPI D-PHY-based or MIPI C-PHY-based devices.

[0008] Embodiments of the present invention provide a physical layer circuit comprising: N signal pads, including at least four signal pads; a four-signal physical medium additional sublayer coupled to the four signal pads; and M shielding pads, including at least one first shielding pad coupled to the four-signal physical medium additional sublayer. The first shielding pad is located between a second signal pad and a third signal pad among the four signal pads, and M and N are positive integers.

[0009] An embodiment of the present invention provides a physical layer circuit comprising: N signal pads, including at least six signal pads; a six-signal physical medium additional sublayer coupled to the six signal pads; and M shielding pads, including at least one first shielding pad, one second shielding pad, and one third shielding pad, respectively coupled to the six-signal physical medium additional sublayer. The first shielding pad is located between a second signal pad and a third signal pad among the six signal pads; the second shielding pad is located between a third signal pad and a fourth signal pad among the six signal pads; and the third shielding pad is located between a fourth signal pad and a fifth signal pad among the six signal pads, where M and N are positive integers.

[0010] Embodiments of the present invention provide a physical layer circuit comprising: N signal pads, including at least four signal pads; and a four-signal physical medium sublayer coupled to the four signal pads. The four-signal physical medium sublayer further comprises a four-signal termination circuit. The four-signal termination circuit comprises: four adjustable resistive elements, each respectively coupled to one of the four signal pads; a wire coupled between one end of a first adjustable resistive element and one end of a second adjustable resistive element; a first switch selectively coupled between one end of the second adjustable resistive element and one end of a third adjustable resistive element; and a second switch selectively coupled between the end of the third adjustable resistive element and one end of a fourth adjustable resistive element. The first switch is controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal.

[0011] An embodiment of the present invention provides a physical layer circuit, the physical layer circuit comprising: N signal pads, including at least six signal pads; and a six-signal physical medium additional sublayer coupled to the six signal pads. The six-signal physical medium additional sublayer comprises: a six-signal termination circuit coupled to the six signal pads. The six-signal termination circuit includes: six adjustable resistive elements, each coupled to one of the six signal pads; a first wire coupled between one end of a first adjustable resistive element and one end of a second adjustable resistive element; a second wire coupled between one end of a fifth adjustable resistive element and one end of a sixth adjustable resistive element; a first switch selectively coupled between the end of the second adjustable resistive element and one end of a third adjustable resistive element; a second switch selectively coupled between the end of the third adjustable resistive element and one end of a fourth adjustable resistive element; and a third switch selectively coupled between the end of the fourth adjustable resistive element and the end of the fifth adjustable resistive element. The first and third switches are controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal. Attached Figure Description

[0012] Figure 1 This invention relates to a PHY circuit comprising a four-signal PMA that supports both dual-channel and three-channel PHY modes.

[0013] Figure 2 This invention describes how to reduce the number of deserializers in a PMA (Programmable Array Analyzer).

[0014] Figure 3 This invention provides a PHY circuit comprising a six-signal PMA that supports both dual-channel and triple-channel PHY modes.

[0015] Figure 4 This invention illustrates how clock signals are used to process data signals at different stages in an embodiment of the invention.

[0016] Figure 5 This is a signal pad arrangement for a PHY circuit containing a four-signal PMA in an embodiment of the present invention.

[0017] Figure 6 This is a signal pad arrangement for a PHY circuit containing a six-signal PMA in an embodiment of the present invention.

[0018] Figure 7 and Figure 8 This refers to a signal pad arrangement that includes electrostatic discharge protection and pad shielding.

[0019] Figures 9A-9C This is a terminal circuit applicable to both dual-channel and triple-channel PHY modes in the prior art.

[0020] Figures 10A-10D This is a terminal circuit applicable to a four-signal PMA in an embodiment of the present invention.

[0021] Figures 11A-11D This is a terminal circuit applicable to a six-signal PMA in an embodiment of the present invention.

[0022] Figure 12 This is a CDR circuit in a receiver used for three-wire communication connections in one embodiment of the present invention.

[0023] Figure 13 This is a signal timing diagram for a CDR circuit with a duty cycle correction circuit.

[0024] Figure 14 A detailed circuit diagram of one embodiment of a duty cycle correction circuit.

[0025] Figure 15 and Figure 16 explain Figure 14 The signal timing diagram for the operation of the duty cycle correction circuit.

[0026] Figure 17 A detailed circuit diagram of another embodiment of the duty cycle correction circuit.

[0027] Figure 18 explain Figure 17 The signal timing diagram for the operation of the duty cycle correction circuit.

[0028] Figure 19In another embodiment of the present invention, a CDR circuit is used in a receiver for a three-wire communication connection.

[0029] Figure 20 explain Figure 19 The signal timing diagram for the operation of the delay correction circuit.

[0030] Attached icon number

[0031] 800, 900, 110, 210, 411, 412 Entity Media Additional Sublayer

[0032] 600 terminal circuit

[0033] 811-813, 911-916 Differential Amplifier

[0034] 821, 822, 1110, 1112, 921, 923, 925 S / H circuits

[0035] 823, 1111, 922, 924, 1010, 1200 CDR circuits

[0036] Deserializers 831, 832, 833, 1120, 931-935, 1020

[0037] 840, 1130, 941, 942, 1030 buffers

[0038] 845, 1035, 943, 944 Symbol Decoder

[0039] Data processing units 850, 1040, 951, and 952

[0040] 100, 200, 300, 400 physical layer circuits

[0041] 320, 322, 420, 422 ESD protection circuits

[0042] 330 and 430 entity coding sub-layers

[0043] 500, 600, 700 terminal circuits

[0044] Delay units 1210-1223 and 2011-2013

[0045] XOR gates 1221-1223, 2021-2023, 2091-2092

[0046] 1231-1233, 2031-2033 latches

[0047] 1240, 2040 OR gate

[0048] 1250, 1500, 1800 duty cycle correction circuit

[0049] 1260, 2060 Alignment Delay Units

[0050] Sampling units 1281-1282 and 2081-2082

[0051] Frequency dividers 1271-1272 and 2071-2072

[0052] 1511-1512 Selector

[0053] 1520 TDC

[0054] 1530, 1820 digital control logic

[0055] 1540, 1830 NAND gates

[0056] 1550, 1840 Programmable Delay Lines

[0057] 1810 comparator

[0058] 2000 Delay Adjustment Unit Detailed Implementation

[0059] Numerous specific details are described below to provide the reader with a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate how the invention can be implemented in the absence of one or more specific details, or by utilizing other methods, elements, or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the core concepts of the invention.

[0060] The phrase "in one embodiment" in this specification means that a particular feature, structure, or characteristic described in that embodiment may be included in at least one embodiment of the invention. Therefore, the phrase "in one embodiment" appearing throughout this specification does not necessarily mean the same embodiment. Furthermore, the aforementioned particular features, structures, or characteristics may be combined in any suitable form in one or more embodiments.

[0061] This invention primarily provides a four-signal physical medium attachment sublayer (PMA) and / or a six-signal PMA in the physical layer circuit (PHY) of the receiver for communication with PHY specifications that conform to the MIPI C-PHY standard or other types using three signal lines to form a channel (hereinafter referred to as three-wire lane PHY), and with PHY specifications that conform to the MIPI C-PHY standard or other types using two signal lines to form a channel (hereinafter referred to as two-wire lane PHY). In embodiments of this invention, the four-signal PMA and six-signal PMA can be implemented in the form of intellectual property (IP) cores, IP blocks, or functional blocks to improve design productivity and make the development of highly complex integrated circuits easier to manage.

[0062] Both the four-signal PMA and the six-signal PMA of this invention can be configured to operate in either MIPI D-PHY mode (or other types of two-wire channel PHY mode) or MIPI C-PHY mode (or other types of three-wire channel PHY mode). For each of them, the four-signal PMA can provide two "two-wire" channels or one "three-wire" channel for a communication connection, while the six-signal PMA can provide three "two-wire" channels or two "three-wire" channels for a communication connection.

[0063] Due to the signal characteristics of these different PHY modes, different signal processing procedures / hardware resources are required to process signals conforming to different PHY specifications. As described below, this invention provides pad arrangements, termination circuits, deserialization structures, and clock and data recovery circuits for four-signal and six-signal PMAs.

[0064] Invention as a whole

[0065] Please refer to Figure 1 This is a schematic diagram of a portion of a PHY circuit according to an embodiment of the present invention. As shown, the PHY circuit includes a four-signal PMA 800 and four signal pads DOP_TOA, DON_TOB, D1P_TOC, and D1N, as well as a four-signal termination circuit 600. Signal pads DOP_TOA, DON_TOB, D1P_TOC, and D1N are respectively coupled to differential amplifiers 811-813 in the four-signal PMA 800. The four-signal termination circuit 600 is also respectively coupled to signal pads DOP_TOA, DON_TOB, D1P_TOC, and D1N. Therefore, differential amplifiers 811-813 are respectively coupled to the termination circuit 600.

[0066] Typically, the four-signal PMA 800 in this embodiment supports two-wire channel PHY modes (e.g., MIPI D-PHY) and three-wire channel PHY modes (e.g., MIPI C-PHY). When the four-signal PMA 800 is configured in MIPI D-PHY mode and operates in MIPI D-PHY mode for MIPI D-PHY communication connections, it can support two two-wire channels. Signal pads DOP_TOA and DON_TOB are connected to the first two-wire channel, while signal pads D1P_TOC and D1N are connected to the second two-wire channel. Alternatively, when the four-signal PMA 800 is set to MIPI C-PHY mode and operates in MIPI C-PHY mode for MIPI C-PHY communication connections, signal pads DOP_TOA, DON_TOB, and D1P_TOC are connected to a three-wire channel.

[0067] In the MIPI D-PHY mode / signal wiring configuration, signal pads D0P_T0A and D0N_T0B are coupled to differential amplifier 811, and differential amplifier 811 outputs a differential signal D0 based on the difference between the signals on signal pads D0P_T0A and D0N_T0B. Signal pads D1P_T0C and D1N are coupled to differential amplifier 813 via a switch, and differential amplifier 813 outputs a differential signal D1 based on the difference between the signals on signal pads D1P_T0C and D1N. Furthermore, a first signal processing block is coupled to differential amplifier 811. This first signal processing block is used to process the differential signal D0 when the four-signal PMA 800 operates in MIPI D-PHY mode. A third signal processing block is coupled to differential amplifier 811. This third signal processing block is used to process the differential signal D1 when the four-signal PMA 800 operates in MIPI D-PHY mode.

[0068] In one embodiment, the first signal processing block includes at least a sample and hold (S / H) circuit 821. The S / H circuit 821 generates a sequence data signal D0[1:0] and a clock signal D0_CK based on the differential signal D0. The third signal processing block includes at least an S / H circuit 823, and the S / H circuit 823 generates a sequence data signal D1[1:0] and a clock signal D1_CK based on the differential signal D1.

[0069] In one embodiment, the first signal processing block may further include a 2-to-8 deserializer 831 coupled to an S / H circuit 821. The S / H circuit 821 outputs data signals D0[1:0] and clock signals D0_CK to the 2-to-8 deserializer 831. The 2-to-8 deserializer 831 deserializes them to generate multiple parallel data signals D0[7:0] and clock signals D0_BCK. The third signal processing block may further include a 2-to-8 deserializer 833 coupled to an S / H circuit 823. The S / H circuit 823 outputs data signals D1[1:0] and clock signals D1_CK to the 2-to-8 deserializer 833. The 2-to-8 deserializer 833 deserializes them to generate multiple parallel data signals D1[7:0] and clock signals D1_BCK.

[0070] In the MIPI C-PHY mode / signal wiring configuration, signal pads D0P_TOA, D0N_TOB, and D1P_TOC are coupled to differential amplifiers 811-813. Differential amplifier 811 outputs a differential signal TOAB based on the difference between the signals on signal pads D0P_TOA and D0N_TOB. Differential amplifier 812 outputs a differential signal TOCA based on the difference between the signals on signal pads D1P_TOC and D0P_TOA. Differential amplifier 813 outputs a differential signal TOBC based on the difference between the signals on signal pads D0P_TOB and D1P_TOC. Differential amplifiers 811-813 are coupled to a second signal processing block. When the four-signal PMA800 operates in MIPI C-PHY mode, this second signal processing block processes the differential signals TOAB, TOBC, and TOCA.

[0071] In one embodiment, the second signal processing block includes at least a C-PHY clock and data recovery (CDR) circuit 822, and the C-PHY CDR circuit 822 generates a set of sequence data signals TOAB[1:0], TOBC[1:0] and TOCA[1:0] and a corresponding clock signal TO_CK based on the differential signals TOAB, TOBC and TOCA.

[0072] In one embodiment, the second signal processing block includes at least a 2-to-8 deserializer 832 coupled to the C-PHY CDR circuit 822. The C-PHY CDR circuit 822 outputs signals TOAB[1:0], TOBC[1:0], TOCA[1:0], and TO_CK to the 2-to-8 deserializer 832. The 2-to-8 deserializer 832 performs a deserialization operation on the signals TOAB[1:0], TOBC[1:0], and TOCA[1:0] according to the clock signal TOCK, thereby generating a set of parallel data signals TOAB[7:0], TOBC[7:0], TOCA[7:0], and the corresponding clock signal TO_BCK.

[0073] The 2-to-8 deserializer 832 is further coupled to the 8-to-7 first-in, first-out buffer (FIFO) 840, and the 8-to-7 FIFO 840 converts the 8-bit metadata signals TOAB[7:0], TOBC[7:0], and TOCA[7:0] into 7-bit lengths. The 8-to-7 FIFO 840 is coupled to the 7-symbol decoding unit 845. The 7-symbol decoding unit 845 is used to decode the data signals read from the 8-to-7 FIFO 840, thereby generating data symbols. The 7-symbol decoding unit 845 is coupled to the data processing unit 850. The data processing unit 850 is used to process the data symbols output by the 7-symbol decoding unit 845. The data processing unit 850 may include a 7-symbol to 16-bit demapper for demapping each 7 symbols received from the 7-symbol decoding unit 845 into a 16-bit metadata word.

[0074] Furthermore, the 8-7 FIFOs 840, the 7-symbol decoding unit 845, and the data processing unit 850 together serve as the C-PHY decoding processor 860 in the four-signal PMA 800. Moreover, the order of the 8-7 FIFOs and the 7-symbol decoding unit in the four-signal PMA 800 is interchangeable. According to different embodiments of the invention, the symbol decoding unit may be positioned before the FIFO (see the applicant's U.S. Patent Application No. 15 / 956,709, which discloses an architecture where the symbol decoding unit precedes the FIFO).

[0075] Since the four-signal PMA 800 may not operate simultaneously in MIPI D-PHY and MIPI C-PHY modes, the number of 2 to 8 deserializers configured in the four-signal PMA 800 can be reduced. Please refer to [reference needed]. Figure 2To further understand, when operating in MIPI D-PHY mode, S / H circuits 1110 and 1112 can share the same 2-to-8 deserializer 1120, and the 2-to-8 deserializer 1120 deserializes the data signals D0[1:0] and D1[1:0] according to the clock signals D0_CK and D1_CK, respectively. On the other hand, when operating in MIPI C-PHY mode, C-PHY CDR circuit 1111 only requires one 2-to-8 deserializer 1120, and the 2-to-8 deserializer 1120 deserializes the data signals T0AB[1:0], T0BC[1:0], and T0CA[1:0] according to the clock signal T0_CK. Figure 1 Compared to the three separate deserializers 831-833 required for the four-signal PMA 800, this implementation significantly improves circuit area utilization efficiency.

[0076] Figure 3 This is another embodiment of the present invention that supports MIPI D-PHY and MIPI C-PHY communication connections. As shown in the figure, Figure 3 The PHY circuit includes a six-signal PMA 900, signals D0P_T0A, D0N_T0B, D1P_T0C, D1N_T1A, D2P_T1B, and D2N_T1C, and a six-signal termination circuit 700. Signal pads D0P_T0A, D0N_T0B, D1P_T0C, D1N_T1A, D2P_T1B, and D2N_T1C are respectively coupled to differential amplifiers 911-916 of the six-signal PMA 900. The six-signal termination circuit 700 is also respectively coupled to signal pads D0P_T0A, D0N_T0B, D1P_T0C, D1N_T1A, D2P_T1B, and D2N_T1C. Therefore, differential amplifiers 911-916 are respectively coupled to the six-signal termination circuit 700.

[0077] When the six-signal PMA 900 is set to MIPI D-PHY mode and operates in MIPI D-PHY mode in a MIPI D-PHY-based communication cable, signal pads D0P_T0A and D0N_T0B are connected to the first two-wire channel in the MIPI D-PHY communication cable, signal pads D1P_T0C and D1N_T1A are connected to the second two-wire channel in the MIPI D-PHY communication cable, and pads D2P_T1C and D2N_T1C are connected to the third two-wire channel in the MIPI D-PHY communication cable. Alternatively, when the six-signal PMA 900 is set to MIPI C-PHY mode and operates in MIPI C-PHY mode in a MIPI C-PHY-based communication cable, signal pads D0P_T0A, D0N_T0B, and D1P_T0C are connected to the first three-wire channel in the MIPI C-PHY communication cable, and signal pads D1N_T1A, D2P_T1B, and D2N_T1C are connected to the second three-wire channel in the MIPI C-PHY communication cable.

[0078] In MIPI D-PHY mode / communication connection, signal pads D0P_T0A and D0N_T0B are coupled to differential amplifier 911, and differential amplifier 911 outputs a differential signal D0 based on the difference between the signals on signal pads D0P_T0A and D0N_T0B. Signal pads D1P_T0C and D1N_T1A are coupled to differential amplifier 913 via a switch, and differential amplifier 913 outputs a differential signal D1 based on the difference between the signals on signal pads D1P_T0C and D1N_T1A. Signal pads D2P_T1B and D2N_T1C are coupled to differential amplifier 916 via a switch, and differential amplifier 916 outputs a differential signal D2 based on the difference between the signals on signal pads D2P_T1B and D2N_T1C. Furthermore, the first signal processing block is coupled to the differential amplifier 911, and when the six-signal PMA 900 operates in MIPI D-PHY mode, the first signal processing block is used to process the differential signal D0. The third signal processing block is coupled to the differential amplifier 913, and when the six-signal PMA 900 operates in MIPI D-PHY mode, the third signal processing block is used to process the differential signal D1. The fifth signal processing block is coupled to the differential amplifier 916, and when the six-signal PMA 900 operates in MIPI D-PHY mode, the fifth signal processing block is used to process the differential signal D2.

[0079] In one embodiment, the first signal processing block includes at least an S / H circuit 921. The S / H circuit 921 generates a sequence data signal D0[1:0] and a clock signal D0_CK based on signal D0. The third signal processing block includes at least an S / H circuit 923, and the S / H circuit 923 generates a sequence data signal D1[1:0] and a clock signal D1_CK based on signal D1. The fifth signal processing block includes at least an S / H circuit 925, and the S / H circuit 925 generates a sequence data signal D2[1:0] and a clock signal D2_CK based on signal D2.

[0080] In one embodiment, the first signal processing block may further include 2 to 8 deserializers 931 coupled to the S / H circuit 921. The S / H circuit 921 outputs data signals D0[1:0] and clock signals D0_CK to the 2 to 8 deserializers 931. The 2 to 8 deserializers 931 deserialize these signals to generate multiple parallel data signals D0[7:0] and clock signals D0_BCK. The third signal processing block may further include 2 to 8 deserializers 933 coupled to the S / H circuit 923. The S / H circuit 923 outputs data signals D1[1:0] and clock signals D1_CK to the 2 to 8 deserializers 933. The 2 to 8 deserializers 933 deserialize these signals to generate multiple parallel data signals D1[7:0] and clock signals D1_BCK. The fifth signal processing block may further include 2 to 8 deserializers 935 coupled to the S / H circuit 925. The S / H circuit 925 outputs data signals D2[1:0] and clock signals D2_CK to a 2-to-8 deserializer 935. The 2-to-8 deserializer 935 performs a deserialization operation on these signals to generate multiple parallel data signals D2[7:0] and clock signals D2_BCK.

[0081] In MIPI C-PHY mode / communication connection, signal pads D0P_T0A and D0N_T0B are coupled to differential amplifier 911, and differential amplifier 911 outputs a differential signal TOAB based on the difference between the signals on signal pads D0P_T0A and D0N_T0B. Signal pads D0P_T0A and D1P_T0C are coupled to differential amplifier 912, and differential amplifier 912 outputs a differential signal TOCA based on the difference between the signals on signal pads D0P_T0A and D1P_T0C. Signal pads D1P_T0C and D0N_T0B are coupled to differential amplifier 913 via a switch, and differential amplifier 913 outputs a differential signal TOBC based on the difference between the signals on signal pads D1P_T0C and D0N_T0B. Signal pads D1N_T1A and D2P_T1B are coupled to differential amplifier 914, which outputs a differential signal T1AB based on the difference between the signals on signal pads D1N_T1A and D2P_T1B. Signal pads D1N_T1A and D2N_T1C are coupled to differential amplifier 915, which outputs a differential signal T1CA based on the difference between the signals on signal pads D1N_T1A and D2N_T1C. Signal pads D2P_T1B and D2N_T1C are coupled to differential amplifier 916 via a switch, which outputs a differential signal T1BC based on the difference between the signals on signal pads D2P_T1B and D2N_T1C.

[0082] Differential amplifiers 911-913 are also coupled to a second signal processing block. When the six-signal PMA 900 is set to MIPI C-PHY mode, the second signal processing block processes the differential signals T0AB, T0BC, and T0CA. Differential amplifiers 914-916 are also coupled to a fourth signal processing block. When the six-signal PMA 900 is set to MIPI C-PHY mode, the fourth signal processing block processes the differential signals T1AB, T1BC, and T1CA.

[0083] In one embodiment, the second signal processing block includes at least a C-PHY CDR circuit 922, and the C-PHY CDR circuit 922 generates a set of sequence data signals TOAB[1:0], TOBC[1:0], and TOCA[1:0] and a corresponding clock signal T0_CK based on signals TOAB, TOBC, and TOCA. The fourth signal processing block includes at least a C-PHY CDR circuit 924, and generates a set of sequence data signals T1AB[1:0], T1BC[1:0], and T1CA[1:0] and a corresponding clock signal T1_CK based on signals T1AB, T1BC, and T1CA.

[0084] In one embodiment, the second signal processing block may further include 2 to 8 deserializers 932 coupled to a C-PHYCDR circuit 922. The C-PHYCDR circuit 922 outputs signals TOAB[1:0], TOBC[1:0], TOCA[1:0], and TO_CK to the 2 to 8 deserializers 932. The 2 to 8 deserializers 932 deserialize signals TOAB[1:0], TOBC[1:0], and TOCA[1:0] according to the clock signal TOCK, thereby generating a set of parallel data signals TOAB[7:0], TOBC[7:0], TOCA[7:0], and the corresponding clock signal TO_BCK. The fourth signal processing block may further include 2 to 8 deserializers 934 coupled to a C-PHYCDR circuit 924. The C-PHY CDR circuit 924 outputs signals T1AB[1:0], T1BC[1:0], T1CA[1:0], and T1_CK to a 2-to-8 deserializer 934. The 2-to-8 deserializer 934 performs deserialization operations on signals T1AB[1:0], T1BC[1:0], and T1CA[1:0] based on the clock signal T1CK, thereby generating a set of parallel data signals T1AB[7:0], T1BC[7:0], T1CA[7:0], and the corresponding clock signal T1_BCK.

[0085] In one embodiment, the 2-to-8 deserializer 932 is further coupled to the 8-to-7 FIFO 941, and the 8-to-7 FIFO 941 converts the 8-bit metadata signals TOAB[7:0], TOBC[7:0], and TOCA[7:0] into 7-bit lengths. The 8-to-7 FIFO 941 is coupled to a 7-symbol decoding unit 943. The 7-symbol decoding unit 943 is used to decode the data signals read from the 8-to-7 FIFO 941, thereby generating data symbols. The 7-symbol decoding unit 943 is coupled to a data processing unit 951. The data processing unit 951 is used to process the data symbols output by the 7-symbol decoding unit 943. The data processing unit 951 may include a 7-symbol to 16-bit demapper for demapping every 7 symbols received from the 7-symbol decoding unit 943 into 16-bit metadata words. Furthermore, the 8 to 7 FIFOs 941, the 7 symbol decoding unit 943, and the data processing unit 951 together function as the C-PHY decoding processor 960 in the six-signal PMA 900. Moreover, the order of the FIFOs and symbol decoding units in the six-signal PMA of the present invention is interchangeable. According to various embodiments of the present invention, the symbol decoding unit may also be located before the FIFO (see the applicant's U.S. Patent Application No. 15 / 956,709, which discloses an architecture where the symbol decoding unit precedes the FIFO).

[0086] The 2-to-8 deserializer 934 is further coupled to the 8-to-7 FIFO 942. The 8-to-7 FIFO 942 converts the 8-bit data signals T1AB[7:0], T1BC[7:0], and T1CA[7:0] into 7-bit lengths. The 8-to-7 FIFO 942 is coupled to the 7-symbol decoding unit 944. The 7-symbol decoding unit 944 is used to decode the data signals read from the 8-to-7 FIFO 942, thereby generating data symbols. The 7-symbol decoding unit 944 is coupled to the data processing unit 952. The data processing unit 952 is used to process the data symbols output by the 7-symbol decoding unit 944. The data processing unit 952 may include a 7-symbol to 16-bit demapper for demapping every 7 symbols received from the 7-symbol decoding unit 944 into 16-bit data words. In addition, the 8 to 7 FIFOs 942, the 7 symbol decoding unit 944, and the data processing unit 952 together serve as another C-PHY decoding processor 970 in the six-signal PMA 900.

[0087] As mentioned above, to improve circuit area utilization efficiency, it is possible to... Figure 2 The embodiments shown generally combine 2 to 8 deserializers 931-933, and may also combine 2 to 8 deserializers 934 and 935.

[0088] Figure 4 This section describes how to utilize clock signals to process data signals at different stages. As shown in the figure, deserializers 2 to 8 1020 deserialize data signals AB[1:0], BC[1:0], and CA[1:0] according to the clock signal TCK, where the frequency of the clock signal TCK is half the symbol rate of the communication connection. FIFOs 8 to 7 1030 convert the 8-bit metadata signals AB[7:0], BC[7:0], and CA[7:0] into 7-bit data words according to the clock signal BCK, where the frequency of the clock signal BCK is 1 / 8 of the symbol rate. The 7-symbol decoding unit 1035 decodes the data signals read from FIFOs 8 to 7 1030 to generate symbols according to the clock signal SCK. The data processing unit 1040 is coupled to the 7-symbol decoding unit 1035 and is used to process the symbols output from the 7-symbol decoding unit 1035. The data processing unit 1040 may include a 7-to-16-bit demapper configured to demap every 7 symbols received from the 7-symbol decoding unit 1035 into a 16-bit data word based on a clock signal SCK, wherein the frequency of the clock signal SCK is 1 / 7 of the symbol rate.

[0089] Please note, Figure 1 and Figure 3The data width of any specific bit width mentioned in the embodiments is intended for illustrative purposes and not for limitation. Those skilled in the art should understand how to select different data width bits to configure the various components, such as the deserializer, FIFO, and symbol decoding unit in four-signal and six-signal PMAs, depending on different application and design requirements.

[0090] Pad arrangement

[0091] from Figure 1 and Figure 3 The signals transmitted by the PHY circuit in a device can be subject to interference, such as crosstalk between signal transmission lines. Therefore, shielding techniques are commonly used in various designs to mitigate interference. To address these issues, this invention provides an innovative pad arrangement that uses and distributes pads more rationally and effectively, thereby shielding against interference.

[0092] Figure 5 According to an embodiment of the present invention, the pad arrangement can be used in a PHY circuit containing a four-signal PMA. As shown, the PHY circuit 100 includes a four-signal PMA 110 and signal pads DOP_TOA, DON_TOB, CKP_TOC, and CKN_XXX for connection to other integrated circuits / devices, which are coupled to the four-signal PMA 110 via any possible type of conductor. A shielding pad SH is coupled to ground or power supply voltage and is used to shield the signal pads DOP_TOA and DON_TOB to prevent interference with the signal pads CKP_TOC and CKN_XXX.

[0093] The four-signal PMA 110 can be configured in either a two-wire channel PHY mode (e.g., MIPI D-PHY) or a three-wire channel PHY mode (e.g., MIPI C-PHY). In the two-wire channel PHY mode, signal pads DOP_TOA and DON_TOB form a data channel, while signal pads CKP_TOC and CKN_XXX serve as clock channels. The signal PMA 110 transmits / receives a pair of data signals via signal pads DOP_TOA and DON_TOB, and a pair of clock signals via signal pads CKP_TOC and CKN_XXX. In the three-wire channel mode, the three signal pads form a channel. For example, signal pads DOP_TOA, DON_TOB, and CKP_TOC form a channel, and signal pad CKN_XXX may not be used.

[0094] Please note that in various embodiments of the present invention, Figure 5The pad arrangement shown can be further applied to PHY circuits comprising N signal pads and M shielding pads, where N and M are positive integers. In such an embodiment, the N signal pads include at least four signal pads, and the M shielding pads include at least one shielding pad. The at least four signal pads and the at least one shielding pad can be arranged in a manner similar to... Figure 5 The pad arrangement shown is illustrated.

[0095] Figure 6 According to an embodiment of the present invention, the pad arrangement can be used in a PHY circuit containing a six-signal PMA. As shown, the PHY circuit 200 includes a six-signal PMA 210 and signal pads DOP_T0A, DON_T0B, CKP_T0C, CKN_T1A, D1P_T1B, and D1N_T1C for connection to another integrated circuit / device. Shielding pads SH0, SH1, and SH2 are coupled to ground or power supply voltage and are used to protect certain signal pads from interference by other signal pads.

[0096] The six-signal PMA 210 can be configured for either a two-wire channel PHY mode or a three-wire channel PHY mode. In the two-wire channel PHY mode, signal pads D0P_T0A and D0N_T0B, as well as D1P_T1B and D1N_T1C, form a data channel, while signal pads CKP_T0C and CKN_XXX form a clock channel. The six-signal PMA 210 transmits / receives data signal pairs through signal pads D0P_T0A and D0N_T0B, as well as D1P_T1B and D1N_T1C, and transmits / receives a clock signal pair through signal pads CKP_T0C and CKN_T1A. In the three-wire channel PHY mode, the three pads form one channel. For example, signal pads D0P_T0A, D0N_T0B, and CKP_T0C form a three-wire channel, while signal pads CKN_T1A, D1P_T0B, and D1N_T1C form another three-wire channel.

[0097] Please note that in various embodiments of the present invention, Figure 6 The pad arrangement shown can be further applied to PHY circuits comprising N signal pads and M shielding pads, where N and M are positive integers. In such an embodiment, the N signal pads comprise at least six signal pads, and the M shielding pads comprise at least three shielding pads. The at least six signal pads and the at least three shielding pads can be arranged in a manner similar to... Figure 6 The pad arrangement shown is illustrated.

[0098] Please refer to Figure 7 and Figure 8These figures illustrate the pad arrangement for electrostatic discharge (ESD) protection and pad shielding. Figure 7 A pad arrangement according to an embodiment of the present invention is shown, which can be used in a PHY circuit including a six-signal PMA. As shown, the PHY circuit 300 includes a six-signal PMA 210, a Physical Encoding Sublayer (PCS) 330, ESD protection circuits 320 and 322, and signal pads DOP_T0A, DON_T0B, CKP_T0C, CKN_T1A, D1P_T1B, and D1N_T1C for connection to another integrated circuit / device. Shielding pads SH0 and SH4 are used to couple the ESD protection circuits 320 and 322 to ground to provide electromagnetic shielding. Additionally, shielding pads SH1, SH2, and SH3 are coupled to ground or power supply voltage and are used to shield certain signal pads from interference from other signal pads.

[0099] Figure 8 According to an embodiment of the present invention, the pad arrangement can be used in a PHY circuit comprising a combination of a six-signal PMA and a four-signal PMA. As shown, the PHY circuit 400 includes a six-signal PMA 411, a four-signal PMA 412, a PCS 430, and ESD protection circuits 420 and 422. The six-signal PMA 411 is connected to another integrated circuit / device via signal pads DOP_T0A, DON_T0B, CKP_T0C, CKN_T1A, D1P_T1B, and D1N_T1C. The four-signal PMA 412 is connected to another integrated circuit / device via signal pads DOP_T0A, DON_T0B, CKP_T0C, and CKN_XXX. Shielding pads SH0 and SH6 are used to couple the ESD protection circuits 420 and 422 to ground to provide electromagnetic shielding. Additionally, shielding pads SH1, SH2, SH3, SH4, and SH5 are coupled to ground or power supply voltage and are used to shield certain signal pads from interference from other signal pads.

[0100] Terminal circuit

[0101] As described above, both the four-signal PMA and the six-signal PMA of the present invention can be configured to operate in either a two-channel PHY mode or a three-channel PHY mode. Therefore, there is a need to provide a termination circuit suitable for the signal characteristics of different PHY modes.

[0102] Figure 9A The diagram illustrates the prior art termination circuits applicable to both two-wire channel PHY mode and three-wire channel PHY mode. By controlling... Figure 9A The switch in the terminal circuit 500. For example... Figure 9A As shown, the terminal circuit 500 can be switched to the first configuration to adapt to Figure 9B The dual-channel configuration is shown. Alternatively, switch to the second configuration to suit your needs. Figure 9C The diagram shows a three-wire channel. The MIPI standard requires that the equivalent decoupling capacitor in a three-wire channel be greater than that in a two-wire channel. Therefore, the capacitance value of each decoupling capacitive element C1, C2, and C3 will be 1X (where "X" represents a unit capacitance value). However, this implementation will lead to... Figure 9C The three-channel configuration shown exhibits capacitor redundancy (i.e., capacitive element C2). To overcome the capacitor redundancy in the termination circuit 500 in the three-channel configuration, this invention provides an innovative architecture for improving the termination circuit.

[0103] Figure 10A A four-signal termination circuit 600 according to an embodiment of the present invention is shown, which can be used in a PHY circuit including a four-signal PMA. The termination circuit 600 includes adjustable resistive elements R1-R4, switches S61-S62, and decoupling capacitive elements C1-C3 (each capacitive element C1-C2 has a capacitance value of 0.5X, while capacitive element C3 has a capacitance value of 1X). In this embodiment, each adjustable resistive element R1-R4 can be coupled to a signal pad of a PHY circuit including a four-signal PMA (e.g., a four-signal PMA 800). Note that according to various embodiments of the present invention, the adjustable resistive elements R1-R4 can be replaced with other types of electrical impedance elements.

[0104] Please also refer to Figure 1 and Figure 10A When the four-signal PMA 800 is operating in dual-channel PHY mode, each pair of signal pads forms a channel. A pair of differential signals can be sent / received via signal pads D0P_TOA and D0N_TOB, while another pair of clock signals can be sent / received via signal pads D1P_TOC and D1N. At this time, switch S62 is on and switch S61 is off (e.g., ...). Figure 10B (As shown). Therefore, the equivalent decoupling capacitance value obtained at signal pads D0P_T0A and D0N_T0B is (0.5+0.5)X, and the decoupling capacitance value obtained at pads D1P_T0C and D1N is 1X. Furthermore, when the four-signal PMA 800 is operating in three-wire channel PHY mode, switch S61 is on and switch S62 is off (…). Figure 10C (As shown). Therefore, an equivalent decoupling capacitance of (0.5 + 0.5 + 1)X is obtained at signal pads D0P_T0A, D0N_T0B, and D1P_T0C. Furthermore, as... Figure 10D As shown, in another embodiment, decoupling capacitive elements C1 and C2 can be combined into a larger decoupling capacitive element CN with a capacitance value of (0.5 + 0.5).

[0105] Figure 11A A six-signal termination circuit 700 according to an embodiment of the present invention is shown, which can be used in a PHY circuit including a six-signal PMA. The six-signal termination circuit 700 includes adjustable resistive elements R1-R6, switches S61-S63, and decoupling capacitive elements C1-C6 (each capacitive element has a capacitance value of 0.5X). In this embodiment, each adjustable resistive element R1-R6 can be coupled to a signal pad of a PHY circuit including a six-signal PMA (e.g., a six-signal PMA 900). Note that according to various embodiments of the present invention, the adjustable resistive elements R1-R6 can be replaced with other types of impedance elements.

[0106] Please also refer to Figure 3 and Figure 11A When the six-signal PMA 900 operates in dual-channel PHY mode, it can transmit / receive a pair of data signals on signal pads D0P_T0A and D0N_T0B, a pair of data signals on signal pads D1P_T0C and D1N_T1A, and a pair of clock signals on signal pads D2P_T1B and D2N_T1C. Alternatively, when the six-signal PMA 900 operates in three-channel PHY mode, it can provide two three-channels. For example, one set of three-wire signals can be transmitted on signal pads D0P_T0A, D0N_T0B, and signal pad D1P_T0A, and another set of three-wire signals can be transmitted on signal pads D1N_T1A, D2P_T1B, and D2P_T1C.

[0107] When the six-signal PMA 900 is set to operate in dual-channel PHY mode, switch S62 is turned on while switches S61 and S63 are not turned on (e.g., Figure 11B (As shown). Therefore, decoupling capacitors with capacitance values ​​equivalent to (0.5 + 0.5)X are formed at signal pads D0P_T0A and D0N_T0B, signal pads D1P_T0C and D1N_T1A, and signal pads D2P_T1B and D2N_T1C, respectively. Furthermore, when the six-signal PMA 900 is configured to operate in three-wire channel PHY mode, switches S61 and 63 are turned on while switch S62 is not turned on (e.g., ...). Figure 11C(As shown). Therefore, decoupling capacitors with capacitance values ​​equivalent to (0.5 + 0.5 + 0.5)X are formed at signal pads D0P_T0A, D0N_T0B, and D1P_T0C, and signal pads D1N_T1A, D2P_T1B, and D2N_T1C, respectively. Furthermore, as... Figure 11D As shown, in one possible embodiment, decoupling capacitive elements C1 and C2 can be implemented with a larger decoupling capacitive element CN1 having a capacitance value of (0.5 + 0.5) × 1000. Alternatively, in another possible embodiment, decoupling capacitive elements C5 and C6 can also be implemented with a larger decoupling capacitive element CN2 having a capacitance value of (0.5 + 0.5) × 1000.

[0108] Compared to termination circuit 500, the four-signal termination circuit 600 and the six-signal termination circuit 700 do not have capacitor redundancy when switching to a three-wire channel configuration. Furthermore, another advantage of the termination circuits 600 and 700 of the present invention is the number of switches. Since the termination circuits 600 and 700 require fewer switches than the termination circuit 500, signal loss can be reduced.

[0109] Clock and Data Reply

[0110] In the MIPI C-PHY specification, the clock signal is embedded in the data signal. Therefore, the PHY circuit in the receiver needs to recover the clock signal from the received data signal.

[0111] According to one embodiment of the present invention, Figure 12 A CDR circuit is shown in a receiver suitable for MIPI C-PHY (or other three-wire channel PHY standards) communication connections. As shown, the CDR circuit 1200 has three input terminals for receiving signals AB, BC, and CA generated by a differential amplifier. The differential amplifier can be... Figure 1 The differential amplifiers 811-813 shown in the embodiments, or Figure 3 The differential amplifiers 911-916 shown in the embodiments receive differential signals on three signal pads / wires, namely signal pads DOP_TOA, DON_TOB, and DIP_TOC, and convert them into differential signals AB, BC, and CA (i.e., Figure 1 or Figure 3 In T0AB[1:0], T0BC[1:0] and T0CA[1:0]).

[0112] Three signals AB, BC, and CA are input to delay units 1210, 1211, and 1212, generating delayed versions AB_D, BC_D, and CA_D of signals AB, BC, and CA, respectively. Then, exclusive OR (XOR) gates 1221, 1222, and 1223 perform XOR operations on signals AB and AB_D, BC and BC_D, and CA and CA_D, respectively. Accordingly, XOR gates 1221, 1222, and 1223 generate XOR output signals AB_X, BC_X, and CA_X. Due to the XOR operation, the signal transitions in signals AB, BC, and CA will result in pulses in the XOR output signals AB_X, BC_X, and CA_X. Then, the XOR output signals AB_X, BC_X, and CA_X are sent to latches 1231, 1232, and 1233, providing a clock signal for latches 1231, 1232, and 1233 to latch a high logic level signal. Additionally, latches 1231, 1232, and 1233 can be reset via the reset control signal RSTB. Therefore, the rising edges of the latched output signals AB_EDGE, BC_EDGE, and CA_EDGE are triggered by the XOR output signals AB_X, BC_X, and CA_X, respectively, while the falling edges of the latched output signals AB_EDGE, BC_EDGE, and CA_EDGE are triggered by the reset control signal RSTB.

[0113] Then, the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE are sent to the OR gate 1240, which performs an OR operation on the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE to generate the clock signal RCK. The clock signal RCK can be processed by frequency dividers 1271 and 1272 with different divisors (i.e., 2 and 7) to generate clock signals for different purposes. The clock signal TCK generated by frequency divider 1271 is provided to sampling units 1281 and 1282 to sample signals AB_S, BC_S, and CA_S for performing a deserialization operation (where signals AB_S, BC_S, and CA_S can be output by delaying the delayed signals AB_D, BC_D, and CA_D through the aligned delay unit 1260). Furthermore, the clock signal SCK generated by frequency divider 1272 is provided to, for example, the data processing unit 850 (…). Figure 1 (Chinese), 951-952 Figure 3 Medium) and 1040( Figure 4 (Medium) and other circuits perform data processing operations.

[0114] On the other hand, the generated clock signal RCK is further sent to the duty cycle correction circuit 1250, thereby generating a reset control signal RSTB. The duty cycle correction circuit 1250 is used to correct the clock signal RCK to achieve a 50% (or approximately 50%) duty cycle for the clock signal RCK. The duty cycle correction circuit 1250 achieves a 50% duty cycle by generating the reset control signal RSTB to correct the clock signal RCK.

[0115] As described above, the clock signal RCK is generated by performing an OR operation on the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE. Therefore, adjusting the duty cycles of the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE (by resetting these signals) can substantially change the duty cycle of the clock signal RCK.

[0116] The timing diagram of the duty cycle correction circuit 1250 processing the clock signal RCK is as follows: Figure 13 As shown. When the pulses of signals AB_X, BC_X, and CA_X follow the signal transitions of signals AB, BC, and CA, the pulses of signals AB_X, BC_X, and CA_X are indicated by dashed lines to reflect this situation. The pulses of signals AB_X, BC_X, and CA_X will trigger latches 1231, 1232, and 1233 to transition the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE to a high logic level. Moreover, when the reset control signal RSTB is asserted, latches 1231, 1232, and 1233 are reset, which causes the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE to transition to a low logic level. It should be understood that the timing of the pulses of the reset control signal RSTB can determine the duty cycle of the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE, thereby determining the duty cycle of the clock signal RCK.

[0117] According to various embodiments of the present invention, the duty cycle correction circuit can have different detailed circuitry. Please refer to... Figure 14The figure shows a detailed circuit diagram of an embodiment of the duty cycle correction circuit 1250. As shown, the duty cycle correction circuit 1500 has a time-to-digital converter (TDC) 1520. The TDC 1520 is used to measure the time difference between adjacent edges of signals AB_EDGE, BC_EDGE, and CA_EDGE, and accordingly convert the measured time difference into a digital (TDC) result. Selectors 1511 and 1512 are used to select two signals from signals AB_EDGE, BC_EDGE, and CA_EDGE for measurement by the TDC 1520. The TDC result is averaged by digital control circuit logic 1530, and the digital control logic 1530 outputs a delay control signal to control the delay line 1550 based on half of the averaged TDC result. The delay line 1550 is used to delay the clock signal RCK, and the NAND gate 1540 is used to perform a NAND operation on the clock signal RCK and its delayed version, thereby generating a reset control signal RSTB. When the time difference between signals AB_EDGE, BC_EDGE, and CA_EDGE is long, the duty cycle of the clock signal RCK will be longer, and vice versa. Therefore, the TDC result will reflect this, allowing the digital control logic 1530 to find the appropriate delay amount for the delay line, thereby adjusting the timing of the reset control signal RSTB so that the clock signal RCK has a duty cycle of approximately 50%. Note that the NAND gate 1540 can be replaced by another type of logic gate or combination of logic gates, as long as they provide the same result.

[0118] Please refer to Figure 15 and Figure 16 To better understand how the duty cycle correction circuit 1500 actually handles the repeated input pattern “+x→-y→+z→-x→+y→-z→+x” representing symbol 3333333 and the repeated input pattern “+x→-z→+y→-x→+z→-y→+x” representing symbol 1111111.

[0119] Figure 17 A detailed circuit diagram of another embodiment of the duty cycle correction circuit 1250 of the present invention is shown. The duty cycle correction circuit 1800 includes a low-pass RC filter comprising a resistive element R and a capacitive element C, used to filter the clock signal RCK. The low-pass RC filter generates a filtered signal Vduty. A comparator 1810 compares the signal Vduty with a predetermined signal VDD / 2 to produce a comparison result UP. Digital control logic 1820 controls a delay line 1840 based on the comparison result UP. Through the low-pass RC filter, the duty cycle of the clock signal RCK is reflected and represented as the voltage level of the signal Vduty. Please refer to... Figure 18As shown in the figure, if comparator 1810 detects that the voltage level of signal Vduty is lower than the predetermined signal VDD / 2, it means that the duty cycle of clock signal RCK is less than 50%. Therefore, the output signal UP of comparator 1810 remains at a high logic level "1". Based on the output signal UP, digital control logic 1820 generates a delay control signal to adjust the delay time of delay line 1840. Once comparator 1810 detects that the voltage level of signal Vduty is equal to the predetermined signal VDD / 2, it indicates that the duty cycle of clock signal RCK is 50%. Therefore, the output signal UP of comparator 1810 becomes a low logic level "0". Therefore, based on the comparison result UP, digital control logic 1820 controls delay line 1840 to generate an appropriate delay (such as increasing or decreasing the delay until the comparison result UP shows no difference) to generate a reset control signal RSTB to correct the clock signal RCK, thereby achieving a 50% duty cycle.

[0120] Figure 19 This is a schematic diagram of the CDR circuit in a receiver used for MIPI C-PHY (or other three-channel PHY standard) communication connections in another embodiment of the present invention. Figure 19 The CDR circuit in Figure 12 The CDR circuits shown share common features and components. However, the main differences between them are... Figure 19 In this embodiment, a delay adjustment unit 2000 is used instead of a duty cycle correction circuit 1200 to generate a reset control signal. The delay adjustment unit 2000 generates a reset control signal RSTB based on an adjustable delay time and a clock signal RCK.

[0121] As mentioned above, the clock signal RCK transitions to a high logic level and begins a new cycle at the rising edges of signals AB_X, BC_X, and CA_X. However, as Figure 20As shown in the circle, if the period of signal BC_edge is too long, the rising edges of signals AB_X and CA_X will be masked. This is caused by an incorrect timing of the reset control signal RSTB. The incorrect timing of the reset control signal RSTB resets signal BC_edge too slowly, thus masking the rising edges of signals AB_X and CA_X. To prevent the rising edges of signals AB_X, BC_X, and CA_X from being masked, the delay adjustment unit 2000 adjusts the reset control signal RSTB according to the sampling results AB_O[0], BC_O[0], and CA_O[0] and the sampling results AB_O[1], BC_O[1], and CA_O[1]. Specifically, the delay adjustment unit 2000 detects the XOR output signal XOR[0] of XOR gate 2091 and the XOR output signal XOR[1] of XOR gate 2092. XOR gate 2091 performs an XOR operation on the sampling results AB_O[0], BC_O[0], and CA_O[0]. The sampling results AB_O[0], BC_O[0], and CA_O[0] are generated by sampling unit 2081 sampling signals AB_S, BC_S, and CA_S according to the clock signal TCK. XOR gate 2092 performs XOR operation on the sampling results AB_O[1], BC_O[1], and CA_O[1]. The sampling results AB_O[1], BC_O[1], and CA_O[1] are generated by sampling unit 2082 sampling signals AB_S, BC_S, and CA_S according to the inverted version of the clock signal TCK.

[0122] The delay adjustment circuit 2000 will start with an initial delay, which ensures Figure 19 The entire CDR circuit can operate normally. Then, the delay timing of the reset control signal RSTB is slowly increased by the circuit of the delay adjustment circuit 2000. Once an incorrect timing is caused, it will be reflected as a signal transition in the XOR output signal XOR[0] and / or the XOR output signal XOR[1]. Once the delay adjustment unit 2000 detects the signal transition of the XOR output signal XOR[0] and / or the XOR output signal XOR[1], it sets the adjustable delay time to half of the incorrect timing. As a result, the reset control signal RSTB will reset the latches 2031-2033 earlier than the incorrect timing, which makes the falling edges of the signals AB_EDGE, BC_EDGE and CA_EDGE appear earlier without shielding the next signal edge. Therefore, the clock signal RCK can reach nearly 50% of the duty cycle. For example, as Figure 20In the circular section, if the reset control signal RSTB resets latches 2031-2033 earlier than before, the falling edge of the latch output signal BC_edge will appear earlier. As a result, the XOR output signals AB_X and CA_X will not be masked by the latch output signal BC_edge, and the clock signal RCK can appropriately follow the rising edges of signals AB_X and CA_X.

[0123] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An entity layer circuit, characterized by, The entity layer circuit includes: four signal pads; a four-signal entity medium additional sub-layer coupled to the four signal pads; and a shield pad coupled to the four-signal entity medium additional sub-layer; wherein the shield pad is located between a second signal pad and a third signal pad of the four signal pads; when the four-signal entity medium additional sub-layer operates in a first entity layer mode, every two signal pads of the four signal pads are arranged as a same channel, and when the four-signal entity medium additional sub-layer operates in a second entity layer mode, three signal pads of the four signal pads are arranged as a same channel.

2. An entity layer circuit, characterized by The entity layer circuit includes: six signal pads; a six-signal entity medium additional sub-layer coupled to the six signal pads; and three shield pads including a first shield pad, a second shield pad, and a third shield pad, respectively coupled to the six-signal entity medium additional sub-layer; wherein the first shield pad is located between a second signal pad and a third signal pad of the six signal pads; the second shield pad is located between the third signal pad and a fourth signal pad of the six signal pads; the third shield pad is located between the fourth signal pad and a fifth signal pad of the six signal pads; when the six-signal entity medium additional sub-layer operates in a first entity layer mode, every two signal pads of the six signal pads are arranged as a same channel, and when the six-signal entity medium additional sub-layer operates in a second entity layer mode, every three signal pads of the six signal pads are arranged as a same channel.

3. An entity layer circuit, characterized by The entity layer circuit includes: four signal pads; a four-signal entity medium additional sub-layer coupled to the four signal pads, including: a four-signal termination circuit coupled to the four signal pads, including: four adjustable resistive elements, each coupled to one of the four signal pads; a wire coupled between an end point of a first adjustable resistive element and an end point of a second adjustable resistive element; a first switch selectively coupled between the end point of the second adjustable resistive element and an end point of a third adjustable resistive element; and a second switch selectively coupled between the end point of the third adjustable resistive element and an end point of a fourth adjustable resistive element; wherein the first switch is controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal.

4. An entity layer circuit, characterized by The entity layer circuit includes: six signal pads; a six-signal entity medium additional sub-layer coupled to the six signal pads, including: a six-signal termination circuit coupled to the six signal pads, including: six adjustable resistive elements, each coupled to one of the six signal pads; a first wire coupled between an end point of a first adjustable resistive element and an end point of a second adjustable resistive element; a first switch selectively coupled between the end point of the second adjustable resistive element and an end point of a third adjustable resistive element; and a second switch selectively coupled between the end point of the third adjustable resistive element and an end point of a fourth adjustable resistive element; wherein the first switch is controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal. a second wire coupled between an end point of a fifth adjustable resistive element and an end point of a sixth adjustable resistive element; a first switch selectively coupled between the end point of the second adjustable resistive element and an end point of a third adjustable resistive element; and a second switch selectively coupled between the end point of the third adjustable resistive element and an end point of a fourth adjustable resistive element; a third switch selectively coupled between the end point of the fourth adjustable resistive element and the end point of the fifth adjustable resistive element; wherein the first and third switches are controlled by a switch control signal and the second switch is controlled by an inverted version of the switch control signal.

Images