Phase interpolation device and its clock signal selector

Abstract

This invention provides a phase interpolation device and a clock signal selector that can avoid generating false signals during clock signal switching operations. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to the selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. Specifically, when the selector changes from selecting a first clock signal as the selected clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point based on the transition point of the lagging phase of the first clock signal and the second clock signal, and generates the selection signal according to the set time point.

Description

Technical Field

[0001] This invention relates to a phase interpolation device and a clock signal selector thereof, and particularly to a device that prevents the generation of unwanted glitch signals when the clock signal is switched. Background Technology

[0002] Please refer to Figure 1 , Figure 1 The diagram illustrates a waveform of a clock signal switching operation in a known technological field. In this field, for example, in the technology of phase interpolation devices, it is often necessary to switch between clock signals with different phases. Figure 1 In the process, when the selected clock signal MXCLK is selected, it needs to be selected by the clock signal CLK. <0> Switch to clock signal CLK <1> At that time, in the publicly known technical field, the clock signal CLK is often used. <0> The transition point T1 is used as the set time point for executing the clock signal switching action. Under these conditions, in the prior art, due to the transient effect of the selector executing the clock signal switching action, a portion of the clock signal CLK may be affected between time points T1 and T2. <0> The selector generates a false signal GS on the selected clock signal MXCLK, which may cause abnormal operation of the phase interpolation device. Summary of the Invention

[0003] The present invention relates to a phase interpolation device and its clock signal selector, which can avoid generating false signals during clock signal switching.

[0004] According to an embodiment of the present invention, a clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals of different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. Specifically, when the selector changes from selecting a first clock signal as the selected clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point based on the transition point of the lagging phase of the first clock signal and the second clock signal, and generates the selection signal based on the set time point.

[0005] According to an embodiment of the present invention, the phase interpolation device includes an N-stage selector, a selection signal generator, and an interpolation operation circuit. Each of the N-stage selectors receives multiple clock signals with different phases. Each N-stage selector receives N selection signals and generates N-stage selected clock signals with different phases based on the N selection signals, where N is an integer greater than 1. The phase of the i-th stage selected clock signal leads the phase of the (i+1)-th stage selected clock signal, where i is a positive integer less than N. The selection signal generator generates N selection signals, wherein the selection signal generator generates the i-th stage selection signal based on the (i+M)-th stage selected clock signal, where M is greater than or equal to 1. The interpolation operation circuit performs interpolation operations on two of the N-stage selected clock signals to generate an output clock signal.

[0006] Based on the above, the clock signal selector of the present invention sets the timing point for performing the clock signal switching action according to the transition point of the phase lagging one of the first clock signal and the second clock signal during the execution of the signal switching action. In this way, it prevents false signals from occurring during the clock signal switching action due to the incomplete transition of the first clock signal and the second clock signal, and avoids the phenomenon of the phase interpolation device activating. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1 The waveform diagram shown is a waveform diagram of a clock signal switching action performed in the prior art.

[0009] Figure 2 A schematic diagram of a clock signal selector according to an embodiment of the present invention is shown;

[0010] Figure 3A , 3B The diagram shows the operating waveform of the clock signal selector according to an embodiment of the present invention.

[0011] Figure 4 A schematic diagram of a phase interpolation device according to another embodiment of the present invention is shown;

[0012] Figures 5A to 5C The diagram shows the operating waveform of the phase interpolation device according to an embodiment of the present invention.

[0013] Figure 6 A schematic diagram of a phase interpolation device according to another embodiment of the present invention is shown.

[0014] Explanation of icon numbers

[0015] 200: Clock signal selector;

[0016] 210, 411~413, 611~613: Selectors;

[0017] 220: Select signal generator;

[0018] 400, 600: Phase interpolation device;

[0019] 420, 620: Select signal generator;

[0020] 430, 630: Interpolation operation circuit;

[0021] CLK <0> ~CLK <3> Clock signal;

[0022] GS: False signal;

[0023] M1~M3, MXCLK: Select clock signal;

[0024] MXCLK selects the clock signal;

[0025] OUT: Output clock signal;

[0026] S1, S2, SEL: Selection signals;

[0027] T1~T5: Time points;

[0028] V1, V2, V3: Voltage values. Detailed Implementation

[0029] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0030] Please refer to Figure 2 , Figure 2This diagram illustrates a clock signal selector according to an embodiment of the present invention. The clock signal selector 200 includes a selector 210 and a selection signal generator 220. The selector 210 receives multiple clock signals CLK of different phases. <0> and CLK <1> The selector 210 selects the clock signal CLK according to the selection signal S1. <0> and CLK <1> One of them is used to generate the selected clock signal MXCLK. The selection signal generator 220 is coupled to the selector 210 and is used to generate the selection signal S1. In this embodiment, when the selector 210 selects the clock signal CLK... <0> To change the selection of clock signal MXCLK to selection of clock signal CLK. <1> When the clock signal MXCLK is selected, or when selector 210 selects the clock signal CLK. <1> To change the selection of clock signal MXCLK to selection of clock signal CLK. <0> When the clock signal MXCLK is selected, the selection signal generator 220 can select the clock signal CLK. <0> and clock signal CLK <1> The transition point of the phase lagging component is used to generate a set time point, and a selection signal S1 is generated based on the set time point.

[0031] In this embodiment, the clock signal CLK <0> The phase can lead the clock signal CLK. <1> The phase. Please refer to the implementation details simultaneously. Figure 3A , 3B The diagram shows the operating waveform of a clock signal selector according to an embodiment of the present invention. Figure 3A In the process, when the clock signal selector 200 wants to select the clock signal MXCLK, it is determined by the clock signal CLK. <0> Switch to clock signal CLK <1> In time (phase advance mode), the selection signal generator 220 can select the clock signal CLK. <0> The set time point is the time point after a delay from the transition point (time point T2), for example, the time point after the clock signal CLK. <1> The transition point is used as the set time point. In this embodiment, the selection signal generator 220 can use the clock signal CLK that lags behind in phase as the set time point. <1> The time point T3 when the voltage transitions to a high value is used as the set time point. The selection signal generator 220 sets the selection signal S1 to a first voltage value V1 before the set time point (time point T3) and a second voltage value V2 after the set time point (time point T3). The selector 210 can select the clock signal CLK before the set time point (time point T3) based on the selection signal S1 which is the first voltage value V1. <0> This generates the selected clock signal MXCLK, and after the set time point (time point T3), selects the clock signal CLK based on the selection signal S1, which is the second voltage value V2. <1> To generate the selected clock signal MXCLK.

[0032] It can be observed here that at the set time point when the voltage value of the selection signal S1 changes, the clock signal CLK... <0> and CLK <1> All voltages have transitioned to stable values. Therefore, the clock signal CLK is executed at the set time point. <0> and CLK <1> The switching action between clock signals can prevent the selected clock signal MXCLK from generating false signals.

[0033] exist Figure 3B In the clock signal selector 200, when the clock signal selector 200 is in phase back mode, the clock signal selector 200 causes the selected clock signal MXCLK to be selected by the clock signal CLK. <1> Switch to clock signal CLK <0> At that time, the selection signal generator 220 can select the clock signal CLK. <1> The transition point (time point T4) is used as the set time point. The selection signal generator 220 sets the selection signal S1 to a second voltage value V2 before the set time point (time point T4) and a first voltage value V1 after the set time point (time point T4). The selector 210 can select the clock signal CLK before the set time point (time point T4) based on the selection signal S1 which has the second voltage value V2. <1> This generates the selected clock signal MXCLK, and after the set time point (time point T4), selects the clock signal CLK based on the selection signal S1, which is the first voltage value V1. <0> To generate the selected clock signal MXCLK.

[0034] Here we can see that, similarly, at the set time point when the selection signal S1 undergoes a voltage value change, the clock signal CLK... <0> and CLK <1> All voltages have transitioned to stable values. Therefore, the clock signal CLK is executed at the set time point. <0> and CLK <1> The switching action between clock signals can prevent the selected clock signal MXCLK from generating false signals.

[0035] In another embodiment of this invention, the selection signal generator 220 may not set the set time point to time point T4, but may instead select a clock signal CLK that is relatively lagging in phase. <1> The set time point is a time point (e.g., time point T5) after a delay from the transition point (time point T4). This also prevents the selected clock signal MXCLK from generating false signals.

[0036] Incidentally, the first voltage value V1 and the second voltage value V2 can be different logic values. Furthermore, while the first voltage value V1 and the second voltage value V2 are not identical, the magnitude relationship between them is not fixed. In other embodiments of the present invention, the first voltage value V1 may also be greater than the second voltage value V2.

[0037] Furthermore, in this embodiment of the invention, the selector 210 can also receive three or more clock signals. The selector 210 can switch between two of the multiple clock signals and generate a selected clock signal MXCLK. The selection signal generator 220 can generate a set time point based on the transition point of the lagging phase of the selected first clock signal and the second clock signal, and generate a selection signal S1. The selector 210 can then select the first clock signal and the second clock signal based on the selection signal S1 to generate MXCLK. In this implementation, the selector 210 can perform the clock signal selection operation based on multiple voltage values ​​of the selection signal S1 corresponding to the multiple clock signals. Furthermore, the selection signal S1 can also be implemented digitally; that is, the selection signal S1 can be a digital signal with multiple bits. The selection signal S1 can have multiple logic values ​​to correspond to the multiple clock signals respectively.

[0038] Furthermore, the selector 210 in this embodiment can be implemented using a multiplexer circuit well known to those skilled in the art, without any particular specific requirement. The selection signal generator 220 can be implemented using digital circuitry; for example, the selection signal generator 220 can be configured with a flip-flop (e.g., a D-type flip-flop) to generate the clock signal CLK. <0> CLK <1> The transition point is detected, and a selection signal is generated based on the detection result.

[0039] Please refer to the following: Figure 4 , Figure 4 A schematic diagram of a phase interpolation device according to another embodiment of the present invention is shown. The phase interpolation device 400 includes multi-stage selectors 411-413, a selection signal generator 420, and an interpolation operation circuit 430. Each of the selectors 411-413 receives a clock signal CLK. <0> ~CLK <3> Among them, the clock signal CLK <0> ~CLK <3> They have a phase difference in sequence. The clock signal CLK of the first stage... <0> The phase of the second stage clock signal CLK is ahead of the phase of the second stage clock signal. <1> The second-stage clock signal CLK <1> The phase of the signal leads the third-stage clock signal CLK. <2> The third-level clock signal CLK <2> Its phase leads the fourth stage clock signal CLK. <3> Selectors 411 to 413 receive selection signals S1, S2, and S3 respectively, and generate selection clock signals M1 to M3 respectively.

[0040] Selection signal generator 420 is used to generate selection signals S1 and S2. Specifically, selection signal generator 420 generates the first-level selection signal S1 based on the second-level selection clock signal M2, and generates the second-level selection signal S2 based on the third-level selection clock signal M3. Notably, the third-level (last-level) selector 413 generates the third-level selection clock signal M3 based on the previous-level (second-level) selection signal S2.

[0041] The selected clock signals M1 and M2 generated by selectors 411 and 412 respectively can be provided to the interpolation circuit 430. The interpolation circuit 430 is used to perform interpolation operations on the selected clock signals M1 and M2 to generate the output clock signal OUT.

[0042] Incidentally, the interpolation circuit 430 of this embodiment can be implemented using any clock signal interpolation circuit known to those skilled in the art, without any particular limitation. Furthermore, the number of selectors 411-413 and the clock signal CLK in this embodiment... <0> ~CLK <3> The quantities of selectors 411-413 and clock signal CLK are merely for illustrative purposes and are not intended to limit the scope of the invention. Designers can change the number of selectors 411-413 and clock signal CLK according to actual needs. <0> ~CLK <3> There is no fixed limit to the quantity.

[0043] Please refer to the following for details regarding the movements. Figure 4 , Figures 5A to 5C ,in Figures 5A to 5C The diagram shows the operating waveforms of the phase interpolation device according to an embodiment of the present invention. Figure 5A as well as Figure 5B In phase-forward mode, selectors 411-413 in phase interpolation device 500 select clock signal CLK respectively. <0> CLK <1> CLK <2> Instead of using the selected clock signals M1 to M3 respectively, they are changed to use the selected clock signal CLK respectively. <1> CLK <2> CLK <3> These are respectively used as the selected clock signals M1 to M3. At this time, in Figure 5AIn this context, for selector 411, selection signal generator 420 can generate selection signal S1 based on the selection clock signal M2 generated by selector 412. This is because the selection clock signal M2 generated by selector 412 is equal to the clock signal CLK. <1> Therefore, the clock signal CLK can be set by selecting the signal generator 420. <1> The transition point (time point T3) is set as the set time point, and a selection signal S1 is generated based on this set time point. Specifically, the selection signal generator 420 can set the selection signal S1 to a first voltage value V1 before time point T3, and to a second voltage value V2 after time point T3. In this way, before time point T3, the selector 411 can select the clock signal CK based on the selection signal S1 with the first voltage value V1. <0> To select clock signal M1, and after time point T3, select clock signal CK based on selection signal S1 for the second voltage value V2. <1> Select clock signal M1.

[0044] On the other hand, Figure 5B In this context, for selector 412, selection signal generator 420 can generate selection signal S2 based on the selection clock signal M3 generated by selector 413. This is because the selection clock signal M3 generated by selector 413 is equal to the clock signal CLK at this time. <2> Therefore, the clock signal CLK can be set by selecting the signal generator 420. <2> The transition point (time point T4) is the set time point, and the selection signal S2 is generated based on this set time point. Specifically, the selection signal generator 420 can set the selection signal S2 to the third voltage value V3 before time point T4, and to the fourth voltage value V4 after time point T4. In this way, before time point T4, the selector 412 can select the clock signal CK based on the selection signal S2 with the third voltage value V3. <1> To select clock signal M2, and after time point T4, select clock signal CK based on selection signal S2 for the fourth voltage value V4. <2> Select clock signal M2.

[0045] The first voltage value V1 to the fourth voltage value V4 mentioned above can also be implemented by different first logic values ​​to the fourth logic values.

[0046] In addition, Figure 5CIn phase back-off mode, selectors 411-413 in phase interpolation device 400 select clock signal CLK respectively. <1> CLK <2> CLK <3> Instead of using the selected clock signals M1 to M3 respectively, they are changed to use the selected clock signal CLK respectively. <0> CLK <1> CLK <2> These are respectively used as selection clock signals M1 to M3. Specifically, for selector 411, selection signal generator 420 can generate selection signal S1 based on the selection clock signal M2 generated by selector 412. This is because the selection clock signal M2 generated by selector 412 is equal to the clock signal CLK. <2> Therefore, the clock signal CLK can be set by selecting the signal generator 420. <2> The transition point (time point T4) is set as the set time point, and the selection signal S1 is generated based on this set time point. Specifically, the selection signal generator 420 can set the selection signal S1 to the second voltage value V2 before time point T4, and set the selection signal S1 to the first voltage value V1 after time point T4. In this way, before time point T4, the selector 411 can select the clock signal CK based on the selection signal S1 with the second voltage value V2. <1> To select clock signal M1, and after time point T4, select clock signal CK based on selection signal S1 for the first voltage value V1. <0> Select clock signal M1.

[0047] In the above explanation, the clock signal CLK <0> ~CLK <3> The switching actions are all performed when the clock signal changes state and is maintained at a stable voltage value. Therefore, during the switching action, the selected clock signal will not generate false signals.

[0048] Please refer to the following: Figure 6 , Figure 6 A schematic diagram of a phase interpolation device according to another embodiment of the present invention is shown. The phase interpolation device 600 includes multiple selectors 611-613, a selection signal generator 620, and an interpolation operation circuit 630. Each of the selectors 611-613 receives a clock signal CLK with a different phase. <0> ~CLK <3> The first-stage clock signal CLK <0> The phase of the second stage clock signal CLK is ahead of the phase of the second stage clock signal. <1> The second-stage clock signal CLK <1> The phase of the signal leads the third-stage clock signal CLK. <2> The third-level clock signal CLK <2> Its phase leads the fourth stage clock signal CLK. <3> Selectors 611 to 613 generate selected clock signals M1 to M3 respectively, among which selected clock signals M1 and M2 are transmitted to interpolation circuit 630. Interpolation circuit 630 can perform interpolation operation on selected clock signals M1 and M2 and generate output clock signal OUT.

[0049] and Figure 4The implementations differ, but selectors 611-613 receive the same selection signal SEL. The selection signal generator 620 generates the signal based on the selected clock signal M3, which has the longest delayed phase among the selected clock signals M1-M3. In other words, selectors 611-613 perform the switching action between clock signals after a sufficiently long delay, effectively preventing the generation of false signals.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock signal selector, characterized in that, include: A selector receives multiple clock signals of different phases, and the selector selects one of the multiple clock signals according to a selection signal to generate a selected clock signal; as well as A selection signal generator, coupled to the selector, generates the selection signal. When the selector changes from selecting the first clock signal as the selected clock signal to selecting the second clock signal as the selected clock signal, the selection signal generator generates a set time point based on the transition point of the phase lagging one of the first clock signal and the second clock signal, and generates the selection signal based on the set time point.

2. The clock signal selector according to claim 1, characterized in that, The phase of the first clock signal leads that of the second clock signal.

3. The clock signal selector according to claim 2, characterized in that, The selection signal generator sets the transition point of the second clock signal to the set time point, sets the selection signal to a first voltage value before the set time point, and sets the selection signal to a second voltage value after the set time point; when the selection signal is the first voltage value, the selector selects the first clock signal as the selected clock signal, and when the selection signal is the second voltage value, the selector selects the second clock signal as the selected clock signal.

4. The clock signal selector according to claim 1, characterized in that, The phase of the first clock signal lags behind that of the second clock signal.

5. The clock signal selector according to claim 4, characterized in that, The selection signal generator sets a time point after a delay of the transition point of the first clock signal as the set time point. Before the set time point, the selection signal generator sets the selection signal to a first voltage value, and after the set time point, the selection signal generator sets the selection signal to a second voltage value. The selector selects the first clock signal as the selected clock signal when the selection signal is the first voltage value, and selects the second clock signal as the selected clock signal when the selection signal is the second voltage value.

6. A phase interpolation device, characterized in that, include: An N-stage selector, each of which receives multiple clock signals with different phases, receives N selection signals respectively, and generates N-stage selected clock signals with different phases according to the N selection signals respectively, where N is an integer greater than 1, and the phase of the i-th selected clock signal leads the phase of the (i+1)-th selected clock signal, where i is a positive integer less than N; A selection signal generator is used to generate the N selection signals, wherein the selection signal generator generates the selection signal of the i-th level according to the selection clock signal of the (i+M)-th level, where M is greater than or equal to 1; as well as The interpolation circuit performs interpolation operations on two of the N selected clock signals to generate an output clock signal.

7. The phase interpolation device according to claim 6, characterized in that, The Nth stage selector generates the Nth stage selected clock signal based on the selection signal of the (N-1)th stage.

8. The phase interpolation device according to claim 6, characterized in that, The selection signal generator generates a set time point based on the transition point of the selected clock signal of the (i+M)th stage, sets the selection signal of the i-th stage to a first voltage value before the set time point, and sets the selection signal of the i-th stage to a second voltage value after the set time point.

9. The phase interpolation device according to claim 6, characterized in that, The selection signal generator generates a set time point based on a delay time of the transition point of the selected clock signal of the (i+M)th stage, sets the selection signal of the i-th stage to a first voltage value before the set time point, and sets the selection signal of the i-th stage to a second voltage value after the set time point.

10. The phase interpolation device according to claim 8 or 9, characterized in that, The i-th stage selector selects a first clock signal to generate an i-th stage selected clock signal when the i-th stage selection signal is the first voltage value, and the i-th stage selector selects a second clock signal to generate an i-th stage selected clock signal when the i-th stage selection signal is the second voltage value. In phase-forward mode, the phase of the first clock signal leads the phase of the second clock signal, and in phase-backward mode, the phase of the first clock signal lags the phase of the second clock signal.

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