Photosensitive device

Abstract

A photosensitive device includes a substrate, a plurality of transmission lines, a plurality of signal lines, a first photosensitive unit and a second photosensitive unit. The transmission line extends along a first direction. The signal line extends along a second direction. The second direction is interlaced with the first direction. The first photosensitive unit and the second photosensitive unit are connected to the transmission line and the signal line. The first photosensitive unit and the second photosensitive unit each include a control circuit and a photosensitive element electrically connected to the control circuit. The photosensitive element of the second photosensitive unit is located in the first direction of the photosensitive element of the first photosensitive unit. The photosensitive element of the first photosensitive unit overlaps with at least one of the corresponding signal lines connected to the second photosensitive unit.

Description

Technical Field

[0001] The invention relates to a photosensitive device. Background Art

[0002] In recent years, with the development of optoelectronic technology, the application of photosensitive devices has become more and more extensive, and the sensing ability and sensing quality of photosensitive devices have also been improved. For photosensitive devices used to sense X-rays, due to their convenience and good image quality, their application and development in medical treatment are quite active. In order to achieve better sensing quality and even sense dynamic images, the photosensitive elements in the photosensitive devices are required to have a high light receiving area. Generally speaking, photosensitive elements and control circuits for controlling the photosensitive elements are provided in the photosensitive devices, and these control circuits limit the area of ​​the photosensitive elements. Therefore, there is still room for improvement in high-performance photosensitive devices. Summary of the invention

[0003] The object of the present invention is to provide a photosensitive device, wherein the photosensitive element has the advantage of a large light receiving area.

[0004] At least one embodiment of the present invention provides a photosensitive device. The photosensitive device includes a substrate, a plurality of transmission lines, a plurality of signal lines, a first photosensitive unit, and a second photosensitive unit. The transmission lines and the signal lines are located on the substrate. The transmission lines extend along a first direction. The signal lines extend along a second direction. The second direction is interlaced with the first direction. The first photosensitive unit and the second photosensitive unit are located on the substrate and are connected to the transmission lines and the signal lines. The first photosensitive unit and the second photosensitive unit each include a control circuit and a photosensitive element. The photosensitive element is electrically connected to the control circuit and includes a first electrode, a photosensitive layer, and a second electrode stacked in sequence. The photosensitive element of the second photosensitive unit is located in the first direction of the photosensitive element of the first photosensitive unit. The first electrode, the photosensitive layer, and the second electrode of the photosensitive element of the first photosensitive unit overlap at least one of the corresponding signal lines connected to the second photosensitive unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a schematic top view of a photosensitive device according to an embodiment of the present invention.

[0006] Figure 1B yes Figure 1A A schematic top view of a control circuit of a photosensitive device.

[0007] Figure 2 yes Figure 1A Schematic cross-sectional view of line a-a'.

[0008] Figure 3 yes Figure 1B A circuit diagram of a control circuit of a photosensitive device.

[0009] Figure 4Ais a schematic top view of a photosensitive device according to an embodiment of the present invention.

[0010] Figure 4B yes Figure 4A A schematic top view of a control circuit of a photosensitive device.

[0011] The reference numerals are as follows:

[0012] 1,2: Photosensitive device

[0013] 10,10a: first photosensitive unit

[0014] 20,20a: second photosensitive unit

[0015] 100:Substrate

[0016] 110h: Through hole

[0017] 110: first insulating layer

[0018] a-a': line

[0019] BE: First electrode

[0020] BP1: First buffer layer

[0021] BP2: Second buffer layer

[0022] BP3: The third buffer layer

[0023] CH: Channel Layer

[0024] CL1, CL2, CL3: Connection structure

[0025] CR: Channel area

[0026] D1: First direction

[0027] D2: Second direction

[0028] D3: Third direction

[0029] E1: First source / drain

[0030] E2: Second source / drain

[0031] G: Gate

[0032] GV, GV1, GV2: Groove

[0033] HL1: First transmission line

[0034] HL2: Second transmission line

[0035] HL3: Third Transmission Line

[0036] L1, L2, L3, L4: Length

[0037] LD: Photosensitive element

[0038] LD1,LD1': left side

[0039] LD2,LD2': right side

[0040] LD3, LD3': lower side

[0041] LD4, LD4': upper side

[0042] LD': Dashed line

[0043] M1: first conductive pattern layer

[0044] M2: second conductive pattern layer

[0045] M3: The third conductive pattern layer

[0046] M4: fourth conductive pattern layer

[0047] PL1: First flat layer

[0048] PL1h: First conductive hole

[0049] PL2h: Second conductive hole

[0050] PL2: Second flat layer

[0051] PL3: Third flat layer

[0052] SDR: Source / Drain Region

[0053] SML: Semiconductor Patterning Layer

[0054] SR: Photosensitive layer

[0055] T1: The first active element

[0056] T2: Second active element

[0057] T3: The third active element

[0058] T4: The fourth active element

[0059] T5: The fifth active element

[0060] TE: Second electrode

[0061] VL1: First signal line

[0062] VL2: Second signal line

[0063] VL3: The third signal line

[0064] VL4: The fourth signal line

[0065] VL5: The fifth signal line

[0066] VL6: Sixth signal line

[0067] X1,X2,Y1,Y2: distance DETAILED DESCRIPTION

[0068] Figure 1A is a schematic top view of a photosensitive device according to an embodiment of the present invention. Figure 1B yes Figure 1A For the convenience of explanation, Figure 1A and Figure 1B The substrate and insulating layer of the photosensitive device are omitted. Figure 2 yes Figure 1A Schematic cross-sectional view of line a-a'.

[0069] Please refer to Figure 1A and Figure 2 The photosensitive device 1 includes a substrate 100, a plurality of transmission lines, a plurality of signal lines, a first photosensitive unit 10, and a second photosensitive unit 20. The transmission lines, the signal lines, the first photosensitive unit 10, and the second photosensitive unit 20 are located on the substrate 100. The first photosensitive unit 10 and the second photosensitive unit 20 are connected to the transmission lines and the signal lines. The second photosensitive unit 20 is located in the first direction D1 of the first photosensitive unit 10.

[0070] In the present embodiment, the signal line includes a first signal line VL1, a second signal line VL2, a third signal line VL3, a fourth signal line VL4, a fifth signal line VL5 and a sixth signal line VL6, and the transmission line includes a first transmission line HL1, a second transmission line HL2 and a third transmission line HL3. The first transmission line HL1, the second transmission line HL2 and the third transmission line HL3 extend along a first direction D1, and the first signal line VL1, the second signal line VL2, the third signal line VL3, the fourth signal line VL4, the fifth signal line VL5 and the sixth signal line VL6 extend along a second direction D2, and the first direction D1 is interlaced with the second direction D2.

[0071] The first photosensitive unit 10 and the second photosensitive unit 20 each include a control circuit CC and a photosensitive element LD. For the convenience of describing the control circuit CC of the first photosensitive unit 10 and the control circuit CC of the second photosensitive unit 20, Figure 1B The semiconductor pattern layer SML, the first conductive pattern layer M1 and the second conductive pattern layer M2 are shown, and other film layers are omitted. Figure 1B In the diagram, the same film layers are represented by the same fill pattern.

[0072] Please refer to Figure 1B and Figure 2, the semiconductor pattern layer SML is located on the substrate 100. In this embodiment, the semiconductor pattern layer SML is directly formed on the substrate 100, but the present invention is not limited thereto. In other embodiments, another buffer layer is sandwiched between the semiconductor pattern layer SML and the substrate 100.

[0073] In this embodiment, the semiconductor pattern layer SML includes a plurality of channel layers CH connected to or separated from each other. The position and number of the channel layers CH can be adjusted according to actual needs.

[0074] In some embodiments, the material of the substrate 100 may be glass, quartz, organic polymer, or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. If the substrate impurities are to be blocked from affecting the device characteristics, one or more insulating layers are covered on the substrate 100. In some embodiments, the material of the semiconductor pattern layer SML may be amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials.

[0075] The first conductive pattern layer M1 is located on the substrate 100. In the present embodiment, a gate insulating layer 102 is sandwiched between the first conductive pattern layer M1 and the substrate 100 and between the first conductive pattern layer M1 and the semiconductor pattern layer SML. The gate insulating layer 102 has the same pattern as the first conductive pattern layer M1, for example, but the present invention is not limited thereto. In other embodiments, the gate insulating layer 102 covers the entire surface of the substrate 100 except for the positions where the conductive holes (for example, the conductive holes corresponding to the source / drain) are provided.

[0076] In the present embodiment, the first conductive pattern layer M1 includes a plurality of gates G and a connection structure CL1. The gate G at least partially overlaps the corresponding channel layer CH. In the present embodiment, each channel layer CH includes at least one channel region CR and a plurality of source / drain regions SDR, and the doping concentration of the source / drain region SDR is different from the doping concentration of the channel region CR. For example, the doping concentration of the source / drain region SDR is greater than the doping concentration of the channel region CR. The gate G overlaps the channel region CR of the channel layer CH.

[0077] In some embodiments, the material of the first conductive pattern layer M1 may be metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials.

[0078] The first insulating layer 110 is located on the first conductive pattern layer M1. The first insulating layer 110 has a plurality of through holes overlapping a portion of the semiconductor pattern layer SML and a plurality of through holes overlapping a portion of the first conductive pattern layer M1. In some embodiments, the first insulating layer 110 may also be referred to as an interlayer insulating layer.

[0079] The second conductive pattern layer M2 is located on the first insulating layer 110. In the present embodiment, the second conductive pattern layer M2 includes a plurality of first source / drain electrodes E1, a plurality of second source / drain electrodes E2, and a plurality of signal lines extending along the second direction D2. The signal lines include a first signal line VL1, a second signal line VL2, a third signal line VL3, a fourth signal line VL4, a fifth signal line VL5, and a sixth signal line VL6. The first source / drain electrode E1 and the second source / drain electrode E2 are located between the corresponding first transmission line VL1 and the second transmission line VL2. The second conductive pattern layer M2 is filled in the through hole of the first insulating layer 110 to form a conductive hole 110h, and the second conductive pattern layer M2 is electrically connected to the semiconductor pattern layer SML and the first conductive pattern layer M1 through the conductive hole 110h.

[0080] In some embodiments, the material of the second conductive pattern layer M2 may be metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials.

[0081] In the present embodiment, the semiconductor pattern layer SML, the first conductive pattern layer M1 and the second conductive pattern layer M2 constitute a plurality of control circuits CC, wherein each control circuit CC includes a first active element T1, a second active element T2, a third active element T3, a fourth active element T4 and a fifth active element T5. The first active element T1, the second active element T2, the third active element T3, the fourth active element T4 and the fifth active element T5 each include a gate G, a channel layer CH, a first source / drain E1 and a second source / drain E2.

[0082] Figure 3 yes Figure 1B Please also refer to the circuit diagram of the control circuit of the photosensitive device. Figure 3 and Figure 1B, the gate G of the first active element T1 is electrically connected to the first signal line VL1, wherein the first signal line VL1 is used to receive the first scan signal SL1, for example. The first source / drain E1 of the first active element T1 is electrically connected to the third signal line VL3, wherein the third signal line VL3 is used to receive the reference signal Vref, for example. In the present embodiment, the first source / drain E1 of the first active element T1 is electrically connected to the connection structure CL1, and is electrically connected to the third signal line VL3 through the connection structure CL1, wherein the connection structure CL1 crosses the second signal line VL2.

[0083] The gate G of the second active element T2 is electrically connected to the second source / drain E2 of the first active element T1. The first source / drain E1 of the second active element T2 is electrically connected to the first electrode BE of the photosensitive element LD (please also refer to Figure 1A , Figure 1B and Figure 2 ).

[0084] The gate G of the third active element T3 crosses the second signal line VL2 and the third signal line VL3, and is electrically connected to the fourth signal line VL4, wherein the fourth signal line VL4 is used to receive the read signal Read, for example. The first source / drain E1 of the third active element T3 is electrically connected to the second source / drain E2 of the second active element T2. For example, the first source / drain E1 of the third active element T3 is connected to the second source / drain E2 of the second active element T2. The second source / drain E2 of the third active element T3 is electrically connected to the third transmission line HL3 (please refer to Figure 1A and Figure 1B ), wherein the third transmission line HL3 is electrically connected to the current-to-voltage circuit ICV (please refer to Figure 3 In some embodiments, the current-to-voltage circuit ICV includes an amplifier OP and a capacitor C2 and a switch CLR connected in parallel with the amplifier OP, but the present invention is not limited thereto.

[0085] The gate G of the fourth active element T4 crosses the second signal line VL2 to the fifth signal line VL5 and is electrically connected to the sixth signal line VL6, wherein the sixth signal line VL6 is used to receive the third scan signal SL3. The first source / drain E1 of the fourth active element T4 is electrically connected to the first electrode BE of the photosensitive element LD (please refer to Figure 1A and Figure 1B The second source / drain E2 of the fourth active device T4 is electrically connected to the second signal line VL2, wherein the second signal line VL2 is used to receive the voltage signal VSS, for example.

[0086] The gate G of the fifth active element T5 crosses the second signal line VL2 to the fourth signal line VL4 and is electrically connected to the fifth signal line VL5, wherein the fifth signal line VL5 is used to receive the second scanning signal SL2. The first source / drain E1 of the fifth active element T5 is electrically connected to the first electrode BE of the photosensitive element LD (see Figure 1A and Figure 1B The second source / drain E2 of the fifth active element T5 is electrically connected to the second transmission line HL2 (please refer to Figure 1A and Figure 1B ), wherein the second transmission line HL2 is electrically connected to the current source I (please refer to Figure 3 ).

[0087] In this embodiment, the gate G of the second active element T2 and the second source / drain E2 of the first active element T1 are electrically connected to point S, the first source / drain E1 of the second active element T2, the first source / drain E1 of the fourth active element T4 and the first source / drain E1 of the fifth active element T5 are electrically connected to point A, and a capacitor C1 is provided between point S and point A.

[0088] Figure 1A , Figure 1B and Figure 3 The circuit layout of a control circuit CC is illustrated, but the purpose is not to limit the circuit layout of the control circuit CC of the present invention. The circuit layout of the control circuit CC of the present invention can be adjusted according to actual needs. For example, the number and position of active components in the control circuit CC can be adjusted according to actual needs.

[0089] Please refer to Figure 1A and Figure 2 , the first planar layer PL1 is located on the control circuit CC. For example, the first planar layer PL1 is located on the second conductive pattern layer M2 and the first insulating layer 110. In some embodiments, a first buffer layer BP1 is further included between the first planar layer PL1 and the second conductive pattern layer M2 and between the first planar layer PL1 and the first insulating layer 110, but the present invention is not limited thereto. In some embodiments, the thickness of the first planar layer PL1 is, for example, 0 micrometers to 5 micrometers. The first planar layer PL1 has a plurality of through holes that overlap a portion of the second conductive pattern layer M2.

[0090] The third conductive pattern layer M3 is located on the first planar layer PL1 and is filled into the through holes of the first planar layer PL1 to form a plurality of first conductive holes PL1h.

[0091] In the present embodiment, the third conductive pattern layer M3 includes a plurality of first electrodes BE, a connection structure CL2, and a connection structure CL3. The first source / drain E1 of the second active element T2, the first source / drain E1 of the fourth active element T4, and the first source / drain E1 of the fifth active element T5 are electrically connected to the first electrode BE. Specifically, the first electrode BE is electrically connected to the first source / drain E1 of the second active element T2, the first source / drain E1 of the fourth active element T4, and the first source / drain E1 of the fifth active element T5 through a first conductive hole PL1h penetrating the first flat layer PL1. The connection structure CL2 is electrically connected to the second source / drain E2 of the fifth active element T5 through a first conductive hole PL1h penetrating the first flat layer PL1. The connection structure CL3 is electrically connected to the second source / drain E2 of the third active element T3 through a first conductive hole PL1h penetrating the first flat layer PL1.

[0092] In some embodiments, the material of the third conductive pattern layer M3 may be metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials.

[0093] A plurality of photosensitive layers SR are located on the first electrode BE. For example, the photosensitive layer SR is directly formed on the first electrode BE. In some embodiments, the photosensitive layer SR includes a semiconductor stack layer, for example, a stack layer including a P-type semiconductor, an intrinsic semiconductor, and an N-type semiconductor. In other embodiments, the material of the photosensitive layer SR includes a silicon-rich silicon oxide layer, a silicon-rich silicon nitride layer, a silicon-rich silicon oxynitride layer, a silicon-rich silicon carbide layer, a silicon-rich silicon carbon oxide layer, a hydrogenated silicon-rich silicon oxide layer, a hydrogenated silicon-rich silicon nitride layer, a hydrogenated silicon-rich silicon carbide layer, hydrogenated amorphous silicon, hydrogenated microcrystalline silicon, hydrogenated polycrystalline silicon, or a combination thereof.

[0094] A plurality of second electrodes TE are located on the photosensitive layer SR. For example, the second electrode TE is formed directly on the photosensitive layer SR. In the present embodiment, the second electrode TE has a similar projection shape to the photosensitive layer SR, and the second electrode TE and the photosensitive layer SR can be defined by the same or different patterning processes (etching processes). When the second electrode TE and the photosensitive layer SR are defined by the same patterning process, the sidewalls of the second electrode TE and the photosensitive layer SR are aligned, thereby saving the number of photomasks required for the patterning process, but the present invention is not limited thereto. In other embodiments, the second electrode TE is not aligned with the sidewalls of the photosensitive layer SR.

[0095] In some embodiments, the second electrode TE includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or a stacked layer of at least two thereof.

[0096] In this embodiment, a plurality of first electrodes BE, a plurality of photosensitive layers SR and a plurality of second electrodes TE constitute a plurality of photosensitive elements LD. In this embodiment, each photosensitive element LD includes a first electrode BE, a photosensitive layer SR and a second electrode TE stacked in sequence.

[0097] In the present embodiment, the first photosensitive unit 10 and the second photosensitive unit 20 each include a photosensitive element LD and a control circuit CC, the photosensitive element LD of the second photosensitive unit 20 is located in the first direction D1 of the photosensitive element LD of the first photosensitive unit 10, and the photosensitive element LD of the first photosensitive unit 10 is separated from the photosensitive element LD of the second photosensitive unit 20. The photosensitive element LD is electrically connected to the control circuit CC, and the first flat layer PL1 is located between the control circuit CC and the photosensitive element LD. In some embodiments, a plurality of first conductive holes PL1h penetrating the first flat layer PL1 are provided in the first flat layer PL1, and the photosensitive layer SR of the photosensitive element LD and the second electrode TE do not overlap the first conductive holes PL1h. In the present embodiment, the photosensitive layer SR of the photosensitive element LD includes a groove GV. For example, the groove GV of the photosensitive element LD of the second photosensitive unit 20 is located on the side of the photosensitive element LD of the second photosensitive unit 20 close to the first photosensitive unit 10.

[0098] In some embodiments, the first flat layer PL1 is prone to surface unevenness at a position close to the first conductive hole PL1h. Therefore, in order to avoid the poor yield of the photosensitive element LD due to unevenness, the photosensitive layer SR is arranged away from the position of the first conductive hole PL1h. In other words, the groove GV of the photosensitive layer SR is arranged corresponding to the first conductive hole PL1h. In this embodiment, the groove GV overlaps with part of the active elements in the control circuit CC (for example, including part of the second active element T2, part of the third active element T3, and part of the fifth active element T5). In addition, in this embodiment, the second electrode TE also has a groove similar to the groove GV of the photosensitive layer SR, and the position of the groove of the second electrode TE corresponds to the position of the groove GV of the photosensitive layer SR. The first electrode BE also has a groove similar to the groove GV. However, in order to allow the first electrode BE to be electrically connected to the control circuit CC, the first electrode BE needs to overlap one of the first conductive holes PL1h, resulting in the groove shape of the first electrode BE being slightly different from the groove GV of the photosensitive layer SR.

[0099] If the photosensitive element in each photosensitive unit only overlaps the signal line connected to itself, but does not overlap the signal line connected to the adjacent photosensitive unit, the position of the photosensitive element (such as the position of the first electrode, the photosensitive layer or the second electrode) is Figure 1AAs shown by the dotted line LD'. In the present embodiment, by making the photosensitive element LD in each photosensitive unit close to other adjacent photosensitive units, the photosensitive element LD has a larger light-collecting area. For example, in some embodiments, the left side LD1 of the photosensitive element LD is offset to the right (towards the first direction D1) by a distance X1 compared to the position of the left side LD1' of the dotted line LD', and the right side LD2 of the photosensitive element LD is offset to the right (towards the first direction D1) by a distance X2 compared to the position of the right side LD2' of the dotted line LD'. The length L1 of the left side LD1 and the left side LD1' in the second direction D2 is less than the length L2 of the right side LD2 and the right side LD2' in the second direction D2, and therefore, the area of ​​the photosensitive element LD is larger than the area defined by the dotted line LD'. In some embodiments, the distance X1 and the distance X2 are between 0 microns and 100 microns.

[0100] In this embodiment, the first electrode BE, the photosensitive layer SR and the second electrode TE of the photosensitive element LD of the first photosensitive unit 10 overlap with at least one of the corresponding signal lines connected to the second photosensitive unit 20 (for example, the first signal line VL1 connected to the second photosensitive unit 20) in the third direction D3 perpendicular to the substrate 100. Thus, the photosensitive element LD has a larger light receiving area.

[0101] The second flat layer PL2 is located on the photosensitive element LD. For example, the second flat layer PL2 is located on the third conductive pattern layer M3 and the second electrode TE. In some embodiments, a second buffer layer BP2 is further included between the second flat layer PL2 and the second electrode TE and between the second flat layer PL2 and the third conductive pattern layer M3, but the present invention is not limited thereto. In some embodiments, the thickness of the second flat layer PL2 is, for example, 0 microns to 5 microns. The second flat layer PL2 has a plurality of through holes that overlap the third conductive pattern layer M3 and the second electrode TE.

[0102] The fourth conductive pattern layer M4 is located on the second flat layer PL2. The fourth conductive pattern layer M4 fills the through hole of the second flat layer PL2 to form a plurality of second conductive holes PL2h. In the present embodiment, the fourth conductive pattern layer M4 includes a first transmission line HL1, a second transmission line HL2, and a third transmission line HL3. The first transmission line HL1 is electrically connected to the second electrode TE of the photosensitive element LD through the second conductive hole PL2h. The second transmission line HL2 is electrically connected to the connection structure CL2 through the second conductive hole PL2h, and is electrically connected to the second source / drain E2 of the fifth active element T5 through the connection structure CL2. The third transmission line HL3 is electrically connected to the connection structure CL3 through the second conductive hole PL2h, and is electrically connected to the second source / drain E2 of the third active element T3 through the connection structure CL3.

[0103] In this embodiment, the control circuit CC of the first photosensitive unit 10 and the control circuit CC of the second photosensitive unit 20 are electrically connected to the same first transmission line HL1 , the same second transmission line HL2 , and the same third transmission line HL3 .

[0104] The third planar layer PL3 is located on the fourth conductive pattern layer M4 and the second planar layer PL2. In some embodiments, a third buffer layer BP3 is further included between the third planar layer PL3 and the fourth conductive pattern layer M4 and between the third planar layer PL3 and the second planar layer PL2, but the invention is not limited thereto.

[0105] Figure 4A is a schematic top view of a photosensitive device according to an embodiment of the present invention. Figure 4B yes Figure 4A For the convenience of explanation, Figure 4A and Figure 4B The substrate and insulating layer of the photosensitive device are omitted.

[0106] exist Figure 4A In the embodiment, the first photosensitive unit 10a and the second photosensitive unit 20a each include a control circuit CC and a photosensitive element LD. To facilitate the description of the control circuit CC of the first photosensitive unit 10a and the control circuit CC of the second photosensitive unit 20a, Figure 4B The semiconductor pattern layer SML, the first conductive pattern layer M1 and the second conductive pattern layer M2 are shown, and other film layers are omitted. Figure 4B In the diagram, the same film layers are represented by the same fill pattern.

[0107] Please refer to Figure 4A and Figure 4B , the photosensitive device 2 includes a substrate (not shown), a plurality of transmission lines, a plurality of signal lines, a first photosensitive unit 10a and a second photosensitive unit 20a. The transmission lines, the signal lines, the first photosensitive unit 10a and the second photosensitive unit 20a are located on the substrate. The first photosensitive unit 10a and the second photosensitive unit 20a are connected to the transmission lines and the signal lines. The second photosensitive unit 20a is located in the first direction D1 of the first photosensitive unit 10a.

[0108] In the present embodiment, the semiconductor pattern layer SML includes a plurality of channel layers CH connected to or separated from each other, the first conductive pattern layer M1 includes a plurality of gates G connected to or separated from each other, the second conductive pattern layer M2 includes a plurality of first source / drain electrodes E1, a plurality of second source / drain electrodes E2, and a first transmission line HL1 and a second transmission line HL2 extending along a first direction D1, the third conductive pattern layer M3 includes a plurality of first electrodes BE, a connection structure CL2, a connection structure CL3, and a connection structure CL4, and the fourth conductive pattern layer M4 includes a first signal line VL1, a second signal line VL2, a third signal line VL3, and a fourth signal line VL4 extending along a second direction D2.

[0109] In this embodiment, the semiconductor pattern layer SML, the first conductive pattern layer M1 and the second conductive pattern layer M2 constitute a plurality of control circuits CC, wherein each control circuit CC includes a first active element T1, a second active element T2 and a third active element T3. The first active element T1, the second active element T2 and the third active element T3 each include a gate G, a channel layer CH, a first source / drain E1 and a second source / drain E2.

[0110] The gate G of the first active device T1 is electrically connected to the first transmission line HL1. The first source / drain E1 of the first active device T1 is electrically connected to the first signal line VL1. For example, the first source / drain E1 of the first active device T1 is electrically connected to the first signal line VL1 through the connection structure CL2.

[0111] The gate G of the second active element T2 is electrically connected to the second transmission line HL2. The first source / drain E1 of the second active element T2 is electrically connected to the first electrode BE of the photosensitive element LD. The second source / drain E2 of the second active element T2 is electrically connected to the second signal line VL2. For example, the second source / drain E2 of the second active element T2 is electrically connected to the second signal line VL2 through the connection structure CL3.

[0112] The gate G of the third active element T3 is electrically connected to the first source / drain E1 of the second active element T2, and the first source / drain E1 of the third active element T3 is electrically connected to the second source / drain E2 of the first active element T1. The second source / drain E2 of the third active element T3 is electrically connected to the fourth signal line VL4. For example, the second source / drain E2 of the third active element T3 is electrically connected to the fourth signal line VL4 through the connection structure CL4.

[0113] The second electrode TE of the light sensing element LD is electrically connected to the third signal line VL3 .

[0114] In the present embodiment, each control circuit CC is electrically connected to the first signal line VL1, the second signal line VL2, the third signal line VL3 and the fourth signal line VL4, and each control circuit CC is electrically connected to the first transmission line HL1 and the second transmission line HL2. In the present embodiment, the control circuit CC of the first photosensitive unit 10a and the control circuit CC of the second photosensitive unit 20a are electrically connected to the same first transmission line HL1 and the same second transmission line HL2.

[0115] In this embodiment, the first photosensitive unit 10a and the second photosensitive unit 20a each include a photosensitive element LD and a control circuit CC. The photosensitive element LD of the second photosensitive unit 20a is located in the first direction D1 of the photosensitive element LD of the first photosensitive unit 10a, and the photosensitive element LD of the first photosensitive unit 10a is separated from the photosensitive element LD of the second photosensitive unit 20a. The photosensitive element LD is electrically connected to the control circuit CC, and the first planar layer (see Figure 2 ) is located between the control circuit CC and the photosensitive element LD. In some embodiments, a plurality of first conductive holes PL1h penetrating the first flat layer are provided in the first flat layer, and the photosensitive layer SR of the photosensitive element LD and the second electrode TE do not overlap the first conductive holes PL1h. In this embodiment, the photosensitive layer SR of the photosensitive element LD of the second photosensitive unit 20a includes a groove GV, wherein the groove GV is located on a side of the photosensitive element LD of the second photosensitive unit 20a close to the first photosensitive unit 10a.

[0116] In some embodiments, the first flat layer is prone to surface unevenness at the location of the first conductive hole PL1h. Therefore, in order to improve the yield of the photosensitive element LD, the photosensitive layer SR needs to be set as far away from the location of the first conductive hole PL1h as possible. In this embodiment, grooves GV1 and GV2 are respectively provided on both sides of the photosensitive layer SR. Through the provision of the grooves GV1 and GV2, the photosensitive layer SR only overlaps with one first conductive hole PL1h connected to the photosensitive element LD, and does not overlap with other first conductive holes PL1h that are not connected to the photosensitive element LD. In this embodiment, the first electrode BE and the second electrode TE both have grooves GV1 and GV2 similar to those of the photosensitive layer SR.

[0117] If the photosensitive element in each photosensitive unit only overlaps the signal line connected to itself, but does not overlap the signal line connected to the adjacent photosensitive unit, the position of the photosensitive element (such as the position of the first electrode, the photosensitive layer or the second electrode) is Figure 4AAs shown by the dotted line LD'. In the present embodiment, by making the photosensitive element in each photosensitive unit close to other adjacent photosensitive units, the photosensitive element LD has a larger light-collecting area. For example, in some embodiments, the lower side LD3 of the photosensitive element LD is offset upward (toward the first direction D1) by a distance Y1 compared to the position of the lower side LD3' of the dotted line LD', and the upper side LD4 of the photosensitive element LD is offset upward (toward the first direction D1) by a distance Y2 compared to the position of the upper side LD4' of the dotted line LD'. The length L3 of the lower side LD3 and the lower side LD3' in the second direction D2 is less than the length L4 of the upper side LD4 and the upper side LD4' in the second direction D2, and therefore, the area of ​​the photosensitive element LD is larger than the area defined by the dotted line LD'. In some embodiments, the distance Y1 and the distance Y2 are between 0 microns and 100 microns.

[0118] In this embodiment, the first electrode BE, the photosensitive layer SR and the second electrode TE of the photosensitive element LD of the first photosensitive unit 10a overlap with at least one of the corresponding signal lines connected to the second photosensitive unit 20a (for example, the first signal line VL1 connected to the second photosensitive unit 20a) in the direction perpendicular to the substrate 100. Thus, the photosensitive element LD has a larger light receiving area.

Claims

1. A photosensitive device, comprising: a substrate; A plurality of transmission lines are located on the substrate and extend along a first direction; A plurality of signal lines are located on the substrate and extend along a second direction, wherein the second direction intersects with the first direction; and A first photosensitive unit and a second photosensitive unit are located on the substrate and connected to the plurality of transmission lines and the plurality of signal lines, and the first photosensitive unit and the second photosensitive unit each include: a control circuit; and A photosensitive element is electrically connected to the control circuit and includes a first electrode, a photosensitive layer and a second electrode stacked in sequence, wherein: The photosensitive element of the second photosensitive unit is located in the first direction of the photosensitive element of the first photosensitive unit, and the first electrode, the photosensitive layer and the second electrode of the photosensitive element of the first photosensitive unit overlap at least one of the corresponding plurality of signal lines connecting the second photosensitive unit. 2 . The photosensitive device as claimed in claim 1 , wherein the photosensitive element of the first photosensitive unit is separated from the photosensitive element of the second photosensitive unit.

3. The photosensitive device as described in claim 1, wherein each of the control circuits is electrically connected to a first signal line, a second signal line, a third signal line, a fourth signal line, a fifth signal line and a sixth signal line among the plurality of signal lines, each of the control circuits is electrically connected to a first transmission line, a second transmission line and a third transmission line among the plurality of transmission lines, and the first electrode, the photosensitive layer and the second electrode of the photosensitive element of the first photosensitive unit overlap on the first signal line connecting the second photosensitive unit. 4 . The photosensitive device as claimed in claim 3 , wherein the control circuit of the first photosensitive unit and the control circuit of the second photosensitive unit are electrically connected to the same first transmission line, the same second transmission line and the same third transmission line.

5. The photosensitive device as claimed in claim 3, wherein each of the control circuits comprises: a first active element, wherein a gate of the first active element is electrically connected to the first signal line, and a first source / drain of the first active element is electrically connected to the third signal line; a second active element, wherein a gate of the second active element is electrically connected to a second source / drain of the first active element, and a first source / drain of the second active element is electrically connected to the first electrode of the photosensitive element; a third active element, wherein a gate of the third active element is electrically connected to the fourth signal line, a first source / drain of the third active element is electrically connected to a second source / drain of the second active element, and a second source / drain of the third active element is electrically connected to the third transmission line; a fourth active element, wherein a gate of the fourth active element is electrically connected to the sixth signal line, a first source / drain of the fourth active element is electrically connected to the first electrode of the photosensitive element, and a second source / drain of the fourth active element is electrically connected to the second signal line; as well as A fifth active element, wherein the gate of the fifth active element is electrically connected to the fifth signal line, the first source / drain of the fifth active element is electrically connected to the first electrode of the photosensitive element, and the second source / drain of the fifth active element is electrically connected to the second transmission line. 6 . The photosensitive device as claimed in claim 1 , wherein the photosensitive layer of the photosensitive element of the second photosensitive unit comprises a groove, wherein the groove is located at a side of the photosensitive element of the second photosensitive unit close to the first photosensitive unit. 7 . The photosensitive device as claimed in claim 6 , wherein the groove overlaps a portion of active components in the control circuit of the second photosensitive unit.

8. The photosensitive device according to claim 6, further comprising: A first flat layer is located between the control circuit and the photosensitive element, wherein the first flat layer is provided with a plurality of first conductive holes penetrating the first flat layer, and the photosensitive layer of the photosensitive element and the second electrode do not overlap the plurality of first conductive holes.

9. A photosensitive device as described in claim 1, wherein each of the control circuits is electrically connected to a first signal line, a second signal line, a third signal line and a fourth signal line among the plurality of signal lines, each of the control circuits is electrically connected to a first transmission line and a second transmission line among the plurality of transmission lines, and the first electrode, the photosensitive layer and the second electrode of the first photosensitive unit overlap on the first signal line connecting the second photosensitive unit. 10 . The photosensitive device as claimed in claim 9 , wherein the control circuit of the first photosensitive unit and the control circuit of the second photosensitive unit are electrically connected to the same first transmission line and the same second transmission line.

11. The photosensitive device as claimed in claim 9, wherein each of the control circuits comprises: a first active device, wherein a gate of the first active device is electrically connected to the first transmission line, and a first source / drain of the first active device is electrically connected to the first signal line; a second active element, wherein a gate of the second active element is electrically connected to the second transmission line, a first source / drain of the second active element is electrically connected to the first electrode of the photosensitive element, and a second source / drain of the second active element is electrically connected to the second signal line; as well as a third active element, wherein the gate of the third active element is electrically connected to the first source / drain of the second active element, the first source / drain of the third active element is electrically connected to the second source / drain of the first active element, and the second source / drain of the third active element is electrically connected to the fourth signal line.

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