Programmable circuit, integrated circuit and electronic device
By designing a programmable circuit containing multiple collaborative working modules, the problem of insufficient UI and single DDR mode in the existing circuit in DQS signal offset processing is solved, real-time monitoring of DQS signals and support of multi-DDR modes is realized.
Patent Information
- Application Number
- CN202210197430.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-01
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2042-03-01
AI Technical Summary
When existing circuits solve the DQS signal offset, DQS_gate has only half a UI, and cannot monitor the DQS signal offset in real time and correct it in real time, resulting in a single code error and DDR mode.
A programmable circuit is designed, including a signal conversion module, a signal configuration module, a first enable signal generation module, a DDR configuration module, a phase monitoring module and a phase adjustment module. Through the coordinated work of these modules, phase monitoring and real-time adjustment of the DQS signal are realized, the UI of the DQS gate is expanded, and a variety of DDR modes are supported.
Real-time monitoring and correction of DQS signal offset is realized, DQ data errors are avoided, and three DDR modes are supported: DDR3, DDR4 1tCK and DDR4 2tCK.
Smart Images
Figure CN114637647B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a programmable circuit, an integrated circuit and an electronic device. Background Art
[0002] In DDR (Double Data Rate, double data rate synchronous dynamic random access memory) memory, DDR3 / 4 (third and fourth generation DDR) DQS signal will be in high impedance state when switching between reading and writing. Therefore, it is necessary to generate a DQS_gate (DQS window) through DDR PHY (port physical layer) to avoid the high impedance state of the DQS signal and prevent bit errors when DDR3 / 4 reads data.
[0003] DDR PHY (port physical layer) uses an adjustable delay internal signal rxena (enable signal) to sample the read-returned DQS signal, returns a bit signal sample, adjusts the delay of rxena through the DQS Gate training algorithm, and then determines the position of the first rising edge of the read-returned DQS signal by judging the continuous sample values, and then determines the width of DQS_gate in combination with the read burst length. DDR PHY (port physical layer) can obtain the effective window of DQS through this feedback adjustment mechanism, and after the circuit obtains the effective DQS_gate, DDRPHY (port physical layer) needs to monitor the DQS jitter or CLK jitter caused by the change of VT in real time. The gate position obtained by DQS Gate training may no longer be in the optimal position, so DDR PHY (port physical layer) needs to have the ability to dynamically adjust DQS Gate.
[0004] However, according to the current technical solution, the DQS_gate obtained is only half a UI (1 UI corresponds to the time interval of half a clock cycle). Therefore, when the DQS signal offset is greater than 0.5 UI, the solution will not be able to correctly remove the high-impedance state of DQS, resulting in errors in DQS sampling DQ data. In addition, the solution cannot set the DDR mode of the system and lacks the real-time monitoring and correction function of the DQS signal offset.
[0005] like Figure 1 This is a UI effect diagram for DDR4 MEM particles based on the existing method. It can be seen from the figure that the DQS_gate at position A or position B is only half a UI, which leads to the need for the circuit to frequently adjust the DQS gate position due to DQS jitter when the temperature changes and the voltage fluctuates. This process will waste system bandwidth and even cause unrecoverable bit errors in the system. DDR4 particles can be set to 1 or 2 cycles, but the existing circuit can only support one of the modes. Summary of the invention
[0006] The purpose of the present invention is to provide a programmable circuit, an integrated circuit and an electronic device to solve the problem that the DQS_gate of the existing circuit has only half a UI when solving the DQS signal offset, and the DQS signal offset cannot be monitored and corrected in real time, further solving the technical problem of the single DDR mode of the circuit.
[0007] The technical solution of the present invention is as follows:
[0008] A programmable circuit is provided, comprising:
[0009] A signal conversion module, used for converting a parallel signal input from an external circuit into a serial signal and outputting the serial signal to the signal configuration module;
[0010] A signal configuration module, configured to receive the serial signal output by the signal conversion module and the second clock frequency signal input by the external circuit, shift the phase of the serial signal output by the signal conversion module by 0 degree or 360 degrees, and output the serial signal after the phase shift to the first enable signal generation module;
[0011] A first enable signal generating module, used for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to the DDR configuration module and the phase monitoring module;
[0012] a DDR configuration module, configured to receive the first enable signal and the DQS signal input by the external circuit to generate a second enable signal; and to set the DDR mode of the programmable circuit according to the first gating signal input by the external circuit, the second gating signal input by the external circuit, and the ddr4_mode signal input by the external circuit to the phase monitoring module;
[0013] A phase monitoring module, used to monitor the phase of the DQS signal and output the monitoring result to the external circuit;
[0014] A phase adjustment module is used to adjust the phase of the first enable signal generated by the first enable signal generation module according to the monitoring result input by the external circuit.
[0015] In some embodiments, the programmable circuit further includes a first AND gate, a second AND gate, an OR gate, and a divider by two;
[0016] The first input end of the first AND gate receives the global reset signal input by the external circuit, and is respectively connected to the reset ends of the signal conversion module, the signal configuration module, the first enable signal generation module, the phase monitoring module and the phase adjustment module, the second input end of the first AND gate receives the local reset signal input by the external circuit, and the output end of the first AND gate is connected to the reset end of the DDR configuration module and the binary divider;
[0017] A first input end of the second AND gate receives a DQS signal input by the external circuit, a second input end of the second AND gate receives a second enable signal output by the DDR configuration module, and an output end of the second AND gate outputs a logic AND signal of the DQS signal and the second enable signal to the DDR configuration module, wherein the logic AND signal is a DQS_gating signal;
[0018] The first input end of the OR gate receives the DQS phase direction signal input by the external circuit, the second input end of the OR gate receives the second enable signal output by the DDR configuration module, the second input end of the OR gate is low level triggered, and the output end of the OR gate outputs a logic OR signal to the binary divider;
[0019] The input end of the binary frequency divider receives the logic OR signal outputted by the output end of the OR gate, and the output end of the binary frequency divider outputs a binary frequency-divided signal of the DQS phase direction signal to the DDR configuration module.
[0020] In some embodiments, the programmable circuit further comprises:
[0021] A Gray code to hot code module, used for converting the Gray code input from the external circuit into a hot code and outputting the hot code to the delay chain module;
[0022] A delay chain module comprises a first delay chain region and a second delay chain region, wherein the first delay chain region is used to receive a DQS_gating signal and a delay chain enable signal output by the second AND gate; the second delay chain region is used to receive a logic OR signal output by the OR gate and the delay chain enable signal; and the delay chain module is used to cause a 45-degree phase shift between the DQS signal and the DQ signal.
[0023] In some embodiments, the parallel signal is a four-bit DQS_gate_ctrl signal; the signal conversion module further includes:
[0024] A first rate mode, in which a clock frequency of the first clock clk_slow of the signal conversion module is the same as a clock frequency of the second clock clk_fast, and the serial signal is a DQS_gate_ctrl signal using only one bit;
[0025] a second rate mode, in which a ratio of a clock frequency of the first clock clk_slow and a clock frequency of the second clock clk_fast of the signal conversion module is 1:2, and the serial signal is a two-bit DQS_gate_ctrl signal;
[0026] a third rate mode, in which a ratio of a clock frequency of the first clock clk_slow to a clock frequency of the second clock clk_fast of the signal conversion module is 1:4, and the serial signal is a four-bit DQS_gate_ctrl signal;
[0027] The clock frequency of the first clock and the clock frequency of the second clock are input from the external circuit.
[0028] In some embodiments, the DDR configuration module is used to set the DDR mode of the programmable circuit according to the first gating signal input by the external circuit, the second gating signal input by the external circuit, and the ddr4_mode signal input by the external circuit to the phase monitoring module; including:
[0029] Set the DDR3 mode, in which the first gating signal is 0, the second gating signal is 0, and the ddr4_mode signal is 0;
[0030] Set the DDR4 1tCK mode, in which the first gating signal is 0, the second gating signal is 1, and the ddr4_mode signal is 0;
[0031] Setting a DDR4 2tCK mode, wherein in the DDR4 2tCK mode, the first gating signal is 1 and the second gating signal is 1;
[0032] The ddr4_mode signal is input to the phase monitoring module via the external circuit.
[0033] In some embodiments, the phase monitoring module is used to monitor the phase of the DQS signal input by the external circuit; including:
[0034] Receiving four clock frequency signals inputted by the external circuit, wherein the phases of the four clock frequency signals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively;
[0035] receiving a first enable signal output by the first enable signal generating module, and monitoring a position of a phase of the DQS signal input by the external circuit relative to the DQS_gating signal according to the DQS signal input by the external circuit and the first enable signal output by the first enable signal generating module;
[0036] The phase of the DQS signal is shifted to the left relative to the DQS_gating signal, and the output end of the phase monitoring module outputs 0111 or 1111;
[0037] The phase of the DQS signal is shifted to the right relative to the DQS_gating signal, and the output end of the phase monitoring module outputs 0000 or 0001;
[0038] The phase of the DQS signal is not offset relative to the DQS_gating signal, and the output terminal of the phase monitoring module outputs 0011.
[0039] In some embodiments, the phase monitoring module outputs the monitoring result to the external circuit; including:
[0040] The phase monitoring module receives the read_clk_ctrl[2:0] signal input by the external circuit;
[0041] The external circuit receives the output value of the output terminal of the phase monitoring module;
[0042] The external circuit adjusts the read_clk_ctrl[2:0] signal according to the output value of the output end of the phase monitoring module; the output end of the phase monitoring module outputs 0111 or 1111, and the value of the read_clk_ctrl[2:0] signal increases; the output end of the phase monitoring module outputs 0001 or 0000, and the value of the read_clk_ctrl[2:0] signal decreases.
[0043] In some embodiments, the phase adjustment module is used to adjust the phase of the first enable signal generated by the first enable signal generation module according to the monitoring result input by the external circuit; including:
[0044] Receive a read_clk_ctrl[2:0] signal input from the external circuit;
[0045] Receive the clock frequency signal input by the external circuit and increase the phase number of the clock frequency signal through the four-clock to eight-clock region of the phase adjustment module, the phases of the clock frequency signal input by the external circuit are 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively, and the phases of the clock frequency signal after the four-clock to eight-clock region of the phase adjustment module are 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees respectively;
[0046] According to the value of the read_clk_ctrl[2:0] signal, the phase of the first enable signal generated by the first enable signal generating module is increased by 45 degrees or decreased by 45 degrees. The value of the read_clk_ctrl[2:0] signal increases, the phase of the DQS_gating signal increases by 45 degrees, the value of the read_clk_ctrl[2:0] signal decreases, and the phase of the DQS_gating signal decreases by 45 degrees.
[0047] Another technical solution of the present invention is as follows:
[0048] An integrated circuit is provided, comprising any programmable circuit described above.
[0049] Another technical solution of the present invention is as follows:
[0050] An electronic device is provided, comprising a device body and the above-mentioned integrated circuit arranged in the device body.
[0051] Beneficial effects of the present invention:
[0052] The programmable circuit, integrated circuit and electronic device provided by the present invention, through the above technical solution,
[0053] The UI of the DQS gate is expanded, and the offset status of the DQS signal is monitored in real time for real-time correction, avoiding DQ data errors caused by DQS sampling. The DDR configuration module also implements the configuration of three DDR modes: DDR3, DDR4 1tCK, and DDR4 2tCK. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0055] Figure 1 The UI effect diagram of the MEM particles for DDR4 is the background technology of this application;
[0056] Figure 2 A circuit connection diagram of an embodiment of the present application;
[0057] Figure 3 This is the effect diagram of the DDR3 mode of the embodiment of the present application
[0058] Figure 4 This is the effect diagram of the DDR4 1tCK mode of the embodiment of this application
[0059] Figure 5 This is the effect diagram of the DDR4 2tCK mode of the embodiment of this application
[0060] Figure 6 A schematic diagram of an integrated circuit structure provided in an embodiment of the present application;
[0061] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0062] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present application. It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0063] It should be noted that in the description of the embodiments, prefixes and suffixes such as "module", "first", "second", etc. are used to facilitate the description of the present application and have no specific meanings in themselves; and the "connection" described in this embodiment refers to an electrical connection, which can be a direct connection relationship or an indirect connection relationship.
[0064] Figure 2 is a circuit connection diagram of an embodiment of the present application, such as Figure 2 As shown, the programmable circuit 100 of the embodiment of the present application includes a signal conversion module (Parallel to series), a signal configuration module, a first enable signal generation module, a DDR configuration module, a phase monitoring module, a phase adjustment module, a Gray code to hot code module, a delay chain module, and also includes a first AND gate connected to the reset end of each module, and a second AND gate and an OR gate connected to the DDR configuration module and the delay chain module respectively. Specifically:
[0065] The signal conversion module (Parallel to series) of the embodiment of the present application converts the parallel signal input from the external circuit into a serial signal, and outputs it to the signal configuration module connected to the signal conversion module through the gate_ser port of the signal conversion module. The DQS_gate_ctrl[3:0] signal is a four-bit DQS_gating signal control code. The external circuit of the embodiment of the present application refers to the external control circuit connected to the programmable circuit of the present application, which is not explained in detail in the embodiment of the present application.
[0066] As an implementation mode of this embodiment, the external circuit selects the rate mode of the signal conversion module. In the corresponding rate mode, the clock frequency and the DQS_gate_ctrl[3:0] signal input to the signal conversion module by the external circuit have different states, wherein the rate mode of the signal conversion module includes:
[0067] In the first rate mode full_rate mode (full rate), the clock frequency of the first clock clk_slow of the signal conversion module is the same as the clock frequency of the second clock clk_fast. At this time, the serial signal of the signal conversion module is a DQS_gate_ctrl[0] signal using only one bit;
[0068] In the second rate mode half_rate mode (half rate), the ratio of the clock frequency of the first clock clk_slow of the signal conversion module to the clock frequency of the second clock clk_fast is 1:2, and the serial signal of the signal conversion module is a two-bit DQS_gate_ctrl[2:0] signal;
[0069] In the third rate mode quad_rate mode (quarter rate), the ratio of the clock frequency of the first clock clk_slow to the clock frequency of the second clock clk_fast of the signal conversion module is 1:4. At this time, the serial signal of the signal conversion module uses a four-bit DQS_gate_ctrl[3:0] signal.
[0070] The signal configuration module of the embodiment of the present application is used to receive the serial signal output by the signal conversion module and the second clock frequency signal input by the external circuit, and shift the phase of the serial signal input by the signal conversion module by 0 degree or 360 degrees, wherein, if the shift_phase_360 signal is triggered, the phase of the serial signal input by the signal conversion module is shifted by 360 degrees, and if the signal is not triggered, the phase is not shifted; and then output the serial signal after the phase shift to the first enable signal (read_ena signal) generation module;
[0071] The first enable signal (read_ena signal) generating module of the embodiment of the present application is used to receive the serial signal after phase shift, and output it to the phase monitoring module and the DDR configuration module;
[0072] The first enable signal (read_ena signal) generating module further receives an output signal of the phase adjustment module, and adjusts the phase of the generated first enable signal (read_ena signal) according to the signal, and the phase is adjusted no more than 45 degrees each time.
[0073] The DDR configuration module of the embodiment of the present application is used to receive the first enable signal read_ena signal input by the first enable signal (read_ena signal) generation module to generate a second enable signal DQS_ena signal; and is used to set the DDR mode of the programmable circuit according to the first gate control signal gate_high signal input by the external circuit, the second gate control signal gate_latch signal input by the external circuit, and the ddr4_mode signal input by the external circuit to the phase monitoring module, wherein the DDR mode includes DDR3 mode, DDR4 1tCK mode, and DDR4 2tCK mode;
[0074] Specifically, Figure 3 As shown in the effect diagram of DDR3 mode, in DDR3 mode, the first gate signal gate_high of the DDR configuration module is 0, the second gate signal gate_latch is 0, and the ddr4_mode signal of the phase monitoring module is 0. At this time, the maximum left and right offset of the DQS signal in the circuit is 1 UI, and the high impedance state of DQS can be correctly removed, which greatly increases the robustness of the DDR3 system.
[0075] like Figure 4 The effect diagram of DDR4 1tCK mode. In DDR4 1tCK mode, the first gate signal gate_high of the DDR configuration module is 0, the second gate signal gate_latch is 1, and the ddr4_mode signal of the phase monitoring module is 0. At this time, the DQS signal in the circuit is offset by 1 UI at most, and the high impedance state of DQS can be correctly removed, reducing the error rate of DDR4 system 1tCK mode.
[0076] like Figure 5 As shown in the effect diagram of DDR4 2tCK mode, in DDR4 2tCK mode, the first gating signal gate_high signal of the DDR configuration module is 1, and the second gating signal gate_latch signal is 1. At this time, the DQS signal in the circuit is offset by 2 UI to the left and right at most, and the high impedance state of DQS can be correctly removed, reducing the error rate of DDR4 system 2tCK mode.
[0077] The phase monitoring module of the embodiment of the present application monitors the phase of the DQS signal input from the external circuit and outputs the dqs_sample_sync[3:0] signal. The phase monitoring module also receives four clock frequency signals input from the external circuit, wherein the phases of the four clock frequency signals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. The phase monitoring module receives the first enable signal read_ena signal output by the first enable signal (read_ena signal) generation module, and monitors the position of the phase of the DQS signal input from the external circuit relative to the DQS_gating signal according to the DQS signal input from the external circuit and the first enable signal read_ena signal output by the first enable signal (read_ena signal) generation module, wherein the first enable signal read_ena signal generates the DQS_ena signal through the DDR configuration module, and the DQS_ena signal and the DQS signal are logically ANDed to generate the DQS_gating signal, so the position of the phase of the DQS signal relative to the DQS_gating signal can be determined according to the readena signal and the DQS signal;
[0078] Specifically, when the phase of the DQS signal is shifted to the left relative to the DQS_gating signal, the output terminal dqs_sample_sync[3:0] signal of the phase monitoring module outputs 0111 or 1111;
[0079] When the phase of the DQS signal shifts to the right relative to the DQS_gating signal, the dqs_sample_sync[3:0] signal at the output of the phase monitoring module outputs 0000 or 0001;
[0080] When the phase of the DQS signal is not offset relative to the DQS_gating signal, the dqs_sample_sync[3:0] signal at the output of the phase monitoring module outputs 0011;
[0081] The phase monitoring module of the embodiment of the present application further receives a read_clk_ctrl[2:0] signal input by an external circuit; the external circuit receives an output value of an output terminal of the phase monitoring module, and adjusts the read_clk_ctrl[2:0] signal according to the output value of the output terminal of the phase monitoring module; wherein, when the output terminal of the phase monitoring module outputs 0111 or 1111, the value of the read_clk_ctrl[2:0] signal increases; when the output terminal of the phase monitoring module outputs 0001 or 0000, the value of the read_clk_ctrl[2:0] signal decreases;
[0082] As an implementation of this embodiment, the phase monitoring module also includes an external circuit input DDR4_mode signal, which together with the DDR configuration module of this application configures the DDR mode of this application.
[0083] The phase adjustment module of the embodiment of the present application is used to adjust the phase of the first enable signal read_ena signal according to the value of the monitoring result read_clk_ctrl[2:0] signal input by the external circuit.
[0084] The phase adjustment module of the embodiment of the present application receives the read_clk_ctrl[2:0] signal input by the external circuit, and receives the clock frequency signal input by the external circuit, and increases the phase number of the clock frequency signal through the "4to8clk" module (four clocks to eight clocks region) of the DQS_gating phase correction module, and the phases of the clock frequency signal input by the external circuit are 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively, and the phases of the clock frequency signal after the four clocks to eight clocks region of the DQS_gating phase correction module are 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees respectively;
[0085] Then, according to the value of the read_clk_ctrl[2:0] signal, the phase of the first enable signal read_ena signal is increased or decreased by 45 degrees, the value of the read_clk_ctrl[2:0] signal increases, the phase of the DQS_gating signal increases by 45 degrees, the value of the read_clk_ctrl[2:0] signal decreases, and the phase of the DQS_gating signal decreases by 45 degrees.
[0086] The Gray code to hot code module of the embodiment of the present application converts the Gray code input from the external circuit into hot code and outputs it to the delay chain module;
[0087] The delay chain module of the embodiment of the present application includes a first delay chain area and a second delay chain area. The first delay chain area is used to receive the DQS_gating signal and the delay chain enable signal output by the second AND gate to generate a DQS delay signal (DQS del); the second delay chain area is used to receive the logical OR signal and the delay chain enable signal output by the OR gate to generate a DQS phase direction delay signal (DQSb del signal); the delay chain module is used to cause the DQS signal and the DQ signal to have a 45-degree phase offset.
[0088] The first input end of the first AND gate of the embodiment of the present application receives a global reset signal input by an external circuit, and is respectively connected to the reset ends of the signal conversion module, the signal configuration module, the first enable signal (read_ena signal) generation module, the phase monitoring module, and the phase adjustment module. The second input end of the first AND gate receives a local reset signal input by an external circuit, and the output end of the first AND gate is connected to the reset end of the DDR configuration module and the binary divider;
[0089] In the embodiment of the present application, the first input end of the second AND gate receives the DQS signal input by the external circuit, the second input end of the second AND gate receives the second enable signal DQS_ena signal output by the DDR configuration module, and the output end of the second AND gate outputs a logic AND signal, i.e., a DQS_gating signal, to the delay chain module and the DDR configuration module respectively;
[0090] In the embodiment of the present application, the first input end of the OR gate receives the DQS phase direction signal input by the external circuit, the second input end of the OR gate receives the second enable signal DQS_ena signal output by the DDR configuration module, and the second input end of the OR gate is a low level trigger. The output end of the OR gate outputs a logic OR signal to the delay chain module and the divider respectively;
[0091] The input end of the binary frequency divider in the embodiment of the present application receives the logical OR signal output by the output end of the OR gate, and the output end of the binary frequency divider outputs a binary frequency-divided signal of the DQS phase direction signal to the DDR configuration module.
[0092] like Figure 6 As shown, the embodiment of the present application further provides an integrated circuit 200, and the integrated circuit 200 includes a programmable circuit for going up a tree.
[0093] like Figure 7 As shown, an embodiment of the present application further provides an electronic device 300 , which includes a device body 310 and the above-mentioned integrated circuit 200 , wherein the integrated circuit 200 is disposed in the device body 300 .
[0094] The above contents are further detailed descriptions of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as the protection scope of the present invention.
Claims
1. A programmable circuit, characterized in that: include: A signal conversion module, used for converting a parallel signal input from an external circuit into a serial signal and outputting the serial signal to the signal configuration module; A signal configuration module, configured to receive the serial signal output by the signal conversion module and the second clock frequency signal input by the external circuit, shift the phase of the serial signal output by the signal conversion module by 0 degree or 360 degrees, and output the serial signal after the phase shift to the first enable signal generation module; A first enable signal generating module, used for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to the DDR configuration module and the phase monitoring module; a DDR configuration module, configured to receive the first enable signal and the DQS signal input by the external circuit to generate a second enable signal; and to set the DDR mode of the programmable circuit according to the first gating signal input by the external circuit, the second gating signal input by the external circuit, and the ddr4_mode signal input by the external circuit to the phase monitoring module; A phase monitoring module, used to monitor the phase of the DQS signal and output the monitoring result to the external circuit; A phase adjustment module is used to adjust the phase of the first enable signal generated by the first enable signal generation module according to the monitoring result input by the external circuit.
2. The programmable circuit according to claim 1, wherein: The programmable circuit also includes a first AND gate, a second AND gate, an OR gate and a binary frequency divider; The first input end of the first AND gate receives the global reset signal input by the external circuit, and is respectively connected to the reset ends of the signal conversion module, the signal configuration module, the first enable signal generation module, the phase monitoring module and the phase adjustment module, the second input end of the first AND gate receives the local reset signal input by the external circuit, and the output end of the first AND gate is connected to the reset end of the DDR configuration module and the binary divider; A first input end of the second AND gate receives a DQS signal input by the external circuit, a second input end of the second AND gate receives a second enable signal output by the DDR configuration module, and an output end of the second AND gate outputs a logic AND signal of the DQS signal and the second enable signal to the DDR configuration module, wherein the logic AND signal is a DQS_gating signal; The first input end of the OR gate receives the DQS phase direction signal input by the external circuit, the second input end of the OR gate receives the second enable signal output by the DDR configuration module, the second input end of the OR gate is low level triggered, and the output end of the OR gate outputs a logic OR signal to the binary divider; The input end of the binary frequency divider receives the logic OR signal outputted by the output end of the OR gate, and the output end of the binary frequency divider outputs a binary frequency-divided signal of the DQS phase direction signal to the DDR configuration module.
3. The programmable circuit according to claim 2, characterized in that The programmable circuit further comprises: A Gray code to hot code module, used for converting the Gray code input from the external circuit into a hot code and outputting the hot code to the delay chain module; A delay chain module comprises a first delay chain region and a second delay chain region, wherein the first delay chain region is used to receive a DQS_gating signal and a delay chain enable signal output by the second AND gate; the second delay chain region is used to receive a logic OR signal output by the OR gate and the delay chain enable signal; and the delay chain module is used to cause a 45-degree phase shift between the DQS signal and the DQ signal.
4. The programmable circuit according to claim 1, wherein: The parallel signal is a four-bit DQS_gate_ctrl signal; the signal conversion module also includes: A first rate mode, in which a clock frequency of the first clock clk_slow of the signal conversion module is the same as a clock frequency of the second clock clk_fast, and the serial signal is a DQS_gate_ctrl signal using only one bit; a second rate mode, in which a ratio of a clock frequency of the first clock clk_slow and a clock frequency of the second clock clk_fast of the signal conversion module is 1:2, and the serial signal is a two-bit DQS_gate_ctrl signal; a third rate mode, in which a ratio of a clock frequency of the first clock clk_slow to a clock frequency of the second clock clk_fast of the signal conversion module is 1:4, and the serial signal is a four-bit DQS_gate_ctrl signal; The clock frequency of the first clock and the clock frequency of the second clock are input from the external circuit.
5. The programmable circuit according to claim 1, wherein: The DDR configuration module is used to set the DDR mode of the programmable circuit according to the first gating signal input by the external circuit, the second gating signal input by the external circuit and the ddr4_mode signal input by the external circuit to the phase monitoring module; comprising: Set the DDR3 mode, in which the first gating signal is 0, the second gating signal is 0, and the ddr4_mode signal is 0; Set the DDR4 1tCK mode, in which the first gating signal is 0, the second gating signal is 1, and the ddr4_mode signal is 0; Setting a DDR4 2tCK mode, wherein in the DDR4 2tCK mode, the first gating signal is 1 and the second gating signal is 1; The ddr4_mode signal is input to the phase monitoring module via the external circuit.
6. The programmable circuit according to claim 2, wherein: The phase monitoring module is used to monitor the phase of the DQS signal input by the external circuit; including: Receiving four clock frequency signals inputted by the external circuit, wherein the phases of the four clock frequency signals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively; receiving a first enable signal output by the first enable signal generating module, and monitoring a position of a phase of the DQS signal input by the external circuit relative to the DQS_gating signal according to the DQS signal input by the external circuit and the first enable signal output by the first enable signal generating module; The phase of the DQS signal is shifted to the left relative to the DQS_gating signal, and the output end of the phase monitoring module outputs 0111 or 1111; The phase of the DQS signal is shifted to the right relative to the DQS_gating signal, and the output end of the phase monitoring module outputs 0000 or 0001; The phase of the DQS signal is not offset relative to the DQS_gating signal, and the output terminal of the phase monitoring module outputs 0011.
7. The programmable circuit according to claim 6, wherein: The phase monitoring module outputs the monitoring result to the external circuit; comprising: The phase monitoring module receives the read_clk_ctrl[2:0] signal input by the external circuit; The external circuit receives the output value of the output terminal of the phase monitoring module; The external circuit adjusts the read_clk_ctrl[2:0] signal according to the output value of the output end of the phase monitoring module; the output end of the phase monitoring module outputs 0111 or 1111, and the value of the read_clk_ctrl[2:0] signal increases; the output end of the phase monitoring module outputs 0001 or 0000, and the value of the read_clk_ctrl[2:0] signal decreases.
8. The programmable circuit according to claim 7, characterized in that The phase adjustment module is used to adjust the phase of the first enable signal generated by the first enable signal generation module according to the monitoring result input by the external circuit; comprising: Receive a read_clk_ctrl[2:0] signal input from the external circuit; Receive the clock frequency signal input by the external circuit and increase the phase number of the clock frequency signal through the four-clock to eight-clock region of the phase adjustment module, the phases of the clock frequency signal input by the external circuit are 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively, and the phases of the clock frequency signal after the four-clock to eight-clock region of the phase adjustment module are 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees respectively; According to the value of the read_clk_ctrl[2:0] signal, the phase of the first enable signal generated by the first enable signal generating module is increased by 45 degrees or decreased by 45 degrees. The value of the read_clk_ctrl[2:0] signal increases, the phase of the DQS_gating signal increases by 45 degrees, the value of the read_clk_ctrl[2:0] signal decreases, and the phase of the DQS_gating signal decreases by 45 degrees.
9. An integrated circuit, characterized in that: The programmable circuit comprises any one of claims 1 to 8.
10. An electronic device, characterized in that: The device comprises a device body and the integrated circuit according to claim 9 arranged in the device body.
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