A synchronization method for a multi-channel high-speed digital-to-analog conversion module

Abstract

The application discloses a kind of synchronization methods of multi-channel high-speed digital-analog conversion module, comprising: reference clock source generates reference clock;Trigger controller generates trigger signal, trigger signal is used to inform each DAC board to start the digital quantity transmission of new waveform;Master chip PLL is multiplied to preset operating frequency by reference clock, and the feedback path of master chip PLL is removed to DAC board, and the delay of voltage-controlled oscillator output master chip IO's wiring is consistent and position is close;DAC PLL is multiplied to the sampling clock frequency of DAC by reference clock, and the output phase of DAC PLL can be adjusted, to ensure the timing margin when DAC reads digital quantity;Master chip is triggered under trigger signal, and at preset time, the digital quantity of several waveforms to be converted is sent to DAC by isochronous transmission path, and DAC converts digital quantity into analog waveform, realizes that all DAC completes digital quantity to analog quantity conversion at the same time, and realizes the high-precision synchronous conversion of DAC.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital-to-analog conversion synchronous control, and particularly relates to a synchronization method of a multi-channel high-speed digital-to-analog conversion module. BACKGROUND

[0002] In a high-precision measurement and control system, thousands of high-speed digital-to-analog converters (DACs) often work simultaneously to realize parallel output of multi-channel analog signals. Such a system has extremely high requirements for the synchronization of DAC output analog waveforms, and the synchronization needs to meet two core requirements: one is DAC clock synchronization, that is, the digital-to-analog conversion time of different DACs needs to be strictly aligned; the other is control logic data sending synchronization, that is, a master control chip needs to send digital quantities to be converted to all DACs at the same time to ensure that the analog waveforms output by the DACs deviate by less than one sampling period. However, in the prior art, if the sampling clocks of different DACs come from different references or have different transmission path lengths, the clock phase deviation will be caused, and then the conversion time will be misaligned; and the signal transmission delay difference between different positions in a chip or between different chips is large, which may cause the time difference of digital quantities reaching each DAC to exceed one sampling period; the above problems will cause the analog waveforms output by multi-channel DACs to deviate obviously, and thus seriously reduce the overall precision and reliability of the measurement and control system, and therefore a multi-channel DAC synchronization method solving the above problems is urgently needed. SUMMARY

[0003] The application aims to provide a synchronization method of a multi-channel high-speed digital-to-analog conversion module to solve the deficiencies in the prior art, which solves the synchronization problem of a multi-channel high-speed DAC measurement and control system, realizes high-precision synchronous conversion of DACs, can be widely applied to fields such as radar, communication, industrial measurement and control which have extremely high requirements for the synchronization of analog signals, and has significant practical value and promotion prospect.

[0004] One embodiment of the application provides a synchronization method of a multi-channel high-speed digital-to-analog conversion module, which is applied to a measurement and control system containing multiple digital-to-analog converters (DACs), and the structure of the measurement and control system comprises a reference clock source, a trigger controller and at least two DAC boards with consistent structures. Each DAC board is integrated with a master control chip, a DAC, a master control chip PLL and a DAC PLL. The method comprises the following steps:

[0005] The reference clock source generates a reference clock, which is distributed to all DAC boards through reference clock cables with equal lengths to ensure that the reference clocks received by the DAC boards are consistent in phase;

[0006] The trigger controller generates a trigger signal, which is distributed to all DAC boards through trigger signal cables with equal lengths and adjustable lengths, and the trigger signal is used to inform the DAC boards to start sending digital quantities of a new waveform;

[0007] The master chip PLL multiplies the reference clock to a preset operating frequency, and the feedback path of the master chip PLL is moved to the DAC board, and meanwhile, the layout and wiring of the master chip meet the requirements that the two wire delays of the chip IO to the phase detector are consistent and the positions are close to each other; the wire delays of the voltage-controlled oscillator output master chip IO are consistent and the positions are close to each other;

[0008] The DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable to ensure the timing margin when the DAC reads the digital quantity.

[0009] The master chip sends the digital quantity of the to-be-converted waveform to the DAC through the isochronous transmission path at the preset time under the triggering of the trigger signal, and the DAC converts the digital quantity into an analog waveform, so that all the DACs complete the conversion of the digital quantity into the analog quantity at the same time.

[0010] Optionally, the reference clock source provides a clock reference for the measurement and control system to ensure that the clock frequencies of all modules of the measurement and control system are not deviated; wherein the frequency of the reference clock is set to 25MHz.

[0011] Optionally, the master chip PLL multiplies the reference clock into two clocks, wherein the first clock is set to 125MHz clock for the internal logic register of the master chip to work; the second clock is set to 1GHz clock for the master chip to send data to the DAC, and the 1GHz clock adopts single-edge trigger data transmission.

[0012] Optionally, the feedback path of the master chip PLL is arranged outside the master chip and is wired from the DAC board.

[0013] Optionally, at least one parallel-serial conversion shift register is integrated on the master chip, which receives 8-bit parallel digital quantity from the internal logic register at a rate of 125MHz, and then converts the parallel digital quantity into serial digital quantity at a rate of 1GHz and sends it to the DAC.

[0014] Optionally, the trigger controller is provided with a trigger controller PLL, which multiplies the reference clock to the operating frequency of the trigger controller to ensure that the trigger controller stably outputs the trigger signal.

[0015] Optionally, the parameters of the DAC include: sampling rate 1GSPS, resolution 8bit, interface data width 8bit; the DAC is used to receive the serial digital quantity sent by the master chip and convert it into the corresponding analog waveform.

[0016] Optionally, the two lines of the chip IO to the phase detector include: a line of the first master chip IO to the phase detector and a line of the fourth master chip IO to the phase detector; wherein the phases of the first master chip IO and the fourth master chip IO are consistent.

[0017] Optionally, the line of the voltage-controlled oscillator output to the third master chip IO and to the second master chip IO includes: a line of the voltage-controlled oscillator output to the third master chip IO through 8 frequency division and 5 frequency division and a line of the voltage-controlled oscillator output to the second master chip IO through parallel-serial conversion shift register; wherein the phases of the third master chip IO and the second master chip IO are consistent.

[0018] Optionally, the synchronization method ensures that the analog waveform deviation of all DAC outputs is better than one sampling period, and the digital quantities planned to be converted at the same time complete analog waveform conversion at the same time.

[0019] Compared with the prior art, the application is applied to a measurement and control system including multiple digital-to-analog converters (DACs), which comprises a reference clock source, a trigger controller and at least two DAC boards with consistent structures. The reference clock source generates a reference clock, which is distributed to all DAC boards through equal-length reference clock cables to ensure that the phases of the reference clocks received by the DAC boards are consistent. The trigger controller generates a trigger signal, which is distributed to all DAC boards through equal-length and adjustable-length trigger signal cables. The trigger signal is used to inform the DAC boards to start sending digital quantities of a new waveform. The master chip PLL multiplies the reference clock to a preset working frequency, and the feedback path of the master chip PLL is moved to the DAC board. Meanwhile, the layout and wiring of the master chip meet the requirements that the two lines of the chip IO to the phase detector have consistent delay and are close to each other, and the lines of the voltage-controlled oscillator output to the master chip IO have consistent delay and are close to each other. The DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable to ensure the timing margin when the DAC reads the digital quantity. Under the trigger of the trigger signal, the master chip sends a plurality of waveform digital quantities to be converted to the DAC through equal-time transmission paths at a preset time. The DAC converts the digital quantity into an analog waveform to realize the conversion of the digital quantity to the analog quantity at the same time. The application solves the synchronization problem of a multi-channel high-speed DAC measurement and control system and realizes high-precision synchronous conversion of the DAC. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A measurement and control system structure diagram of a digital-to-analog converter (DAC) is provided for the embodiments of the application.

[0021] Figure 2A DAC board and master control chip clock schematic diagram provided for an embodiment of the application;

[0022] Figure 3 A master control chip internal layout and wiring schematic diagram provided for an embodiment of the application;

[0023] Figure 4 A schematic diagram of the relationship between each clock and data provided for an embodiment of the application. DETAILED DESCRIPTION

[0024] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the application and cannot be explained as a limitation of the application.

[0025] The embodiment of the application provides a synchronization method of a multi-channel high-speed digital-to-analog conversion module, which can be applied to electronic equipment, such as a microwave source array, specifically, a phased array antenna, a quantum computer and the like.

[0026] Referring to Figure 1 , Figure 1 A measurement and control system structure schematic diagram of a digital-to-analog converter DAC provided for an embodiment of the application, the measurement and control system structure of the digital-to-analog converter DAC includes a reference clock source, a trigger controller and at least two DAC boards with consistent structures, a master control chip, a DAC, a master control chip PLL and a DAC PLL are integrated on each DAC board, and the method includes that the reference clock source generates a reference clock, which is distributed to all DAC boards through an equal-length reference clock cable, so as to ensure that the reference clocks received by each DAC board are consistent in phase; the trigger controller generates a trigger signal, which is distributed to all DAC boards through an equal-length and length-adjustable trigger signal cable, and the trigger signal is used to inform each DAC board to start sending digital quantity of a new waveform; the master control chip PLL frequency-multiplies the reference clock to a preset working frequency, and a feedback path of the master control chip PLL is moved to the DAC board, and meanwhile, the master control chip layout and wiring meet that the delay of two wiring lines from a chip IO to a phase detector is consistent and the positions are close; the delay of wiring lines from a voltage-controlled oscillator output to a master control chip IO is consistent and the positions are close; the DAC PLL frequency-multiplies the reference clock to a sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable, so as to ensure the timing margin when the DAC reads the digital quantity; under the triggering of the trigger signal, the master control chip sends a plurality of waveform digital quantities to be converted to the DAC through an equal-time transmission path at a preset time, the DAC converts the digital quantity into an analog waveform, and all DACs complete the conversion from digital quantity to analog quantity at the same time.

[0027] The reference clock source provides a clock reference for the measurement and control system to ensure that the clock frequency of each module of the measurement and control system is not deviated. The frequency of the reference clock can be set to 25MHz. The main control chip PLL multiplies the reference clock to two clocks, wherein the first clock is set to 125MHz clock for the internal logic register of the main control chip to work, and the second clock is set to 1GHz clock for the main control chip to send data to the DAC, and the 1GHz clock adopts single-edge trigger data transmission. The feedback path of the main control chip PLL is set outside the main control chip and is wired from the DAC board. At least one parallel-serial conversion shift register is integrated on the main control chip, which receives 8bit parallel digital quantity from the internal logic register at a rate of 125MHz, and then converts the parallel digital quantity to serial digital quantity at a rate of 1GHz and sends it to the DAC. The trigger controller is built-in trigger controller PLL, which multiplies the reference clock to the working frequency of the trigger controller, for ensuring the trigger controller to stably output trigger signal. The parameters of the DAC include: sampling rate 1GSPS, resolution 8bit, interface data width 8bit; the DAC is used to receive the serial digital quantity sent by the main control chip and convert it to the corresponding analog waveform. The two wires from the chip IO to the phase detector include: the wire from the first main control chip IO on the DAC board to the phase detector and the wire from the fourth main control chip IO to the phase detector; wherein the phase of the first main control chip IO is consistent with the phase of the fourth main control chip IO. The wires from the voltage-controlled oscillator output to the third main control chip IO and to the second main control chip IO include: the wire from the voltage-controlled oscillator output to the third main control chip IO through 8 frequency division and 5 frequency division, and the wire from the voltage-controlled oscillator output to the second main control chip IO through parallel-serial conversion shift register; wherein the phase of the third main control chip IO is consistent with the phase of the second main control chip IO. The synchronization method ensures that the deviation of the analog waveform output by all DACs is better than one sampling period, and the digital quantity planned to be converted at the same time is converted into analog waveform at the same time.

[0028] It should be noted that the initial data in the present application is the digital quantity of several waveforms to be sent, and the target signal obtained is the analog waveform corresponding to the digital quantity of the above several waveforms. The effect to be achieved is to ensure that the digital quantity converted at the same time is converted into analog waveform synchronously. It should be noted that the sampling clock phases of all digital-to-analog converters DACs are ensured to be the same, and the digital quantity at the same time is ensured to be sent to the digital-to-analog converter DAC at the same time.

[0029] The reference clock source is the clock reference of the above-mentioned measurement and control system, and the clock of the measurement and control system comes from the clock source, so that the frequency deviation between each part of the whole system is ensured. The main control chip is responsible for sending digital quantity to the DAC at the correct time, the internal main control chip PLL is responsible for frequency multiplication of the clock of the reference clock source to a high enough frequency for the main control chip to work. The DAC digital-to-analog conversion chip is responsible for converting digital quantity into analog quantity. The DAC PLL is responsible for frequency multiplication of the clock of the reference clock source to a high enough frequency to serve as the sampling clock of the DAC. The DAC board provides bearing for the main control chip, the DAC and the DAC PLL, and distributes the clock of the reference clock source to the main control chip and the DAC PLL. The trigger controller is used to send a trigger signal to each DAC board, and the trigger signal is a start signal for starting sending of a digital quantity. The internal trigger controller PLL is responsible for frequency multiplication of the clock of the reference clock source to a high enough frequency for the trigger controller to work.

[0030] It should be noted that the reference clock source generates a reference clock, which is distributed to all DAC boards. The trigger controller generates a trigger signal to all DAC boards for informing the DAC boards to start sending a new round of waveforms. All DAC boards have consistent hardware design. For the convenience of description, it is assumed that the reference clock frequency is 25MHz, the main clock of the main control chip is 125MHz, the single edge of the clock for the main control chip to send data to the DAC is 1GHz, the sampling rate of the DAC is 1GSPS, the resolution is 8bit, and the interface data width is 8bit. Referring to Figure 2 , Figure 2 A DAC board and a main control chip clock schematic diagram provided by the embodiment of the application is shown in the figure. The main control chip accepts a 25MHz reference clock, generates 125MHz and 1GHz clocks by using an internal PLL, and is used for internal logic work and outputting data to the DAC, respectively. There are a plurality of serial-to-parallel shift registers. Each serial-to-parallel shift register receives 8bit parallel data from the internal logic at a rate of 125MHz, and then sends the data to the DAC in series at a rate of 1GHz.

[0031] In order to compensate for the change of the internal delay of the main control chip with process voltage and temperature, the following measures can be taken: first, the feedback path of the main control chip PLL is moved outside the chip, and then the wiring is made from the DAC board; second, some requirements are added to the internal layout of the main control chip, as shown in Figure 3 , Figure 3 An internal layout of the main control chip provided by the embodiment of the application is shown in the figure. The layout requirements are as follows: the purpose of the close position is to reduce the influence of the temperature process voltage difference of different positions of the chip:

[0032] 1. The input wiring from the chip IO to the phase detector, that is, Figure 3 the delay of the two lines from P1 to the phase detector and P4 to the phase detector in the above-mentioned is consistent, and the positions are close;

[0033] 2. The delay of the output of the voltage controlled oscillator through the 8 divider to P3 and the delay of the output of the voltage controlled oscillator through the parallel-serial shift register to P2 are consistent, and the positions are close to each other.

[0034] 3. The delay of the output of the voltage controlled oscillator through the 8 divider to the clock end of the internal logic register is not strictly required, and the delay of the output of the voltage controlled oscillator through the 8 divider to the clock end of the 5 divider register is basically consistent, and the setup time and the hold time are met.

[0035] The above requirements ensure that:

[0036] 1. All P2s of the DAC boards send data to the DACs connected thereto at the same time. The reason is as follows:

[0037] The phases at P1 and P4 are consistent, the delay of P3 to P4 is outside the chip, and therefore the phases of P1 and P3 are consistent. Since the delay of the voltage controlled oscillator to P3 and the delay of the voltage controlled oscillator to P2 are not stable but consistent, that is, the phases of P3 and P2 are consistent. Therefore, the phases of P1 and P2 are consistent, that is, the time when P2 sends data to the DAC is consistent with the edge of P1. Since P1 of different DAC boards comes from the same reference clock source and the cable lengths are consistent, all P2s send data to the DACs connected thereto at the same time.

[0038] Another guarantee factor that the phases of P2 and P3 are consistent is that P3 passes through a series of dividers, and P2 does not pass through a divider, that is, the edge of P3 is necessarily the edge of the 1GHz clock, and the data of P2 is sent at each edge of the 1GHz clock, which ensures that the edge of P3 is necessarily the time when the data of P2 is sent.

[0039] 2. The edges of the 125MHz clock of all DAC boards are also basically aligned, and the reason is as follows:

[0040] P3s of all DAC boards are aligned, and the edges of P3 and the edges of the 125MHz clock cannot differ too much. The 125MHz is not very high frequency, and the timing requirement is not very strict. A little deviation can also be considered as basically aligned.

[0041] It should be noted that the requirements for the trigger controller are similar to the requirements for the master control chip, but can be appropriately relaxed, because the trigger signal is sent by the 125MHz clock, and the timing margin is relatively large. When the measurement and control system is integrated, only the length of the trigger cable needs to be adjusted, so that the DAC board receives the trigger signal and meets the setup time and the hold time.

[0042] The DAC PLL output clock phase can be finely adjusted to meet the setup time and hold time of the data. Since the input reference clock phase of all DAC PLLs is the same (from the same reference clock source and the same cable length), the output of all DAC PLLs can also have the same phase, that is, all DACs sample data at the same time, and after fixed period internal processing, analog waveforms are sent at the same time.

[0043] For example, the reference clock source as the system clock reference can generate a 25MHz reference clock, which is distributed to all DAC boards through equal length cables to ensure that the clock frequency of each module is unbiased; the trigger controller built-in trigger controller PLL is used to multiply the reference clock to its working frequency to generate a trigger signal and start a new round of waveform transmission of the DAC board, which is distributed to all DAC boards through equal length cables with adjustable length to meet the setup time and hold time requirements of the trigger signal. The DAC board is the core bearing unit of multi-channel synchronization, and each DAC board has consistent structure and can integrate the following submodules:

[0044] The master chip is used to send the digital quantity to be converted, i.e., the digital quantity of several waveforms, to the DAC at a preset time under the trigger of the trigger signal;

[0045] The master chip PLL is integrated in the master chip, which multiplies the reference clock to two clocks—125MHz clock for the internal logic register of the master chip, and 1GHz clock for the data transmission of the parallel-to-serial shift register, and the feedback path is moved to the DAC board to compensate for the IO delay of the chip;

[0046] The parallel-to-serial shift register receives 8-bit parallel digital quantity output by the internal logic register at a rate of 125MHz, and converts it to serial digital quantity at a rate of 1GHz and sends it to the DAC;

[0047] The DAC digital-to-analog conversion chip is set to have a sampling rate of 1GSPS, a resolution of 8bit, and an interface data width of 8bit, and is responsible for converting the digital quantity sent by the master chip into an analog waveform;

[0048] The DAC PLL is used to multiply the reference clock to 1GHz, which is the sampling clock of the DAC, and the output phase can be finely adjusted to ensure the timing margin when the DAC reads the digital quantity.

[0049] Based on the above system structure, the synchronization method specifically includes the following steps:

[0050] Step 1: Clock reference unification and transmission path optimization: the reference clock source distributes the 25MHz reference clock to all DAC boards through the equal-length reference clock cable, ensuring that the phases of the reference clocks received by the DAC boards are completely consistent; the trigger controller distributes the trigger signal to all DAC boards through the equal-length trigger signal cable with adjustable length, and adjusts the cable length to make the time of receiving the trigger signal of each DAC board meet the setup time and hold time, ensuring that all DAC boards start data transmission synchronously.

[0051] Step 2: Master chip clock and layout wiring optimization. The feedback path of the master chip PLL is moved from the chip interior to the DAC board to compensate for the transmission delay of the IO port of the master chip; the internal layout and wiring of the master chip meet the following requirements: the delay of the two wires from the chip IO (P1, P4) to the phase detector is consistent, and the physical positions are close; the delay of the wires from the output of the voltage-controlled oscillator to the chip IO (P3) after 8 division and 5 division is consistent with the delay of the wires from the output of the voltage-controlled oscillator to the chip IO (P2) after parallel-serial conversion and shift register, and the physical positions are close; the delay of the wires from the output of the voltage-controlled oscillator to the clock end of the internal logic register after 8 division is basically consistent with the delay of the wires from the output of the voltage-controlled oscillator to the clock end of the 5 division register, and meets the setup time and hold time.

[0052] Step 3: DAC sampling clock phase adjustment. Adjust the output phase of the DAC PLL on each DAC board, and ensure that the sampling clock phases of all DACs are consistent under the premise of equal length of the reference clock cable, to provide the clock basis for synchronous conversion of digital quantities.

[0053] Step 4: Data synchronous transmission and conversion. After the trigger signal is triggered, the internal logic register of the master chip sends 8bit parallel digital quantity to the parallel-serial conversion shift register at a rate of 125MHz; the parallel-serial conversion shift register converts the parallel digital quantity into serial digital quantity at a rate of 1GHz, and sends it to the DAC through the isochronous transmission path; all DACs synchronously read the digital quantity and convert it into an analog waveform under the trigger of the phase-consistent 1GHz sampling clock, realizing the conversion of digital quantity at the same time and completing the conversion of analog waveform at the same time.

[0054] Reference Figure 4 , Figure 4 A schematic diagram of the relationship between each clock and data is provided for the embodiment of the application, which shows the relationship between each clock and data. P2 of all DAC boards is aligned, and the DAC clock of all DAC boards is also aligned, that is, all DACs sample new data at the same time and emit analog waveforms after fixed-period internal processing.

[0055] The synchronization method of the multi-channel high-speed digital-to-analog conversion module has the following beneficial effects compared with the prior art:

[0056] 1. High synchronization accuracy. By referring to the equal length of the clock cable, triggering the equal length of the signal cable, and adjusting the phase of the DAC PLL, the sampling clock phase of all DACs is ensured to be consistent, and the digital quantity is synchronized to the DAC, and the analog waveform deviation is better than one sampling period;

[0057] 2. Strong anti-interference ability. The main control chip PLL feedback path is moved out and the internal layout and wiring are optimized, which compensates for the delay fluctuation caused by process, temperature and voltage changes, and ensures the stability of data transmission;

[0058] 3. Good versatility. All DAC boards use consistent hardware design, which can flexibly expand the number of DACs, and the clock frequency and DAC parameters can be adjusted according to the needs, and the application range is wide;

[0059] 4. High reliability. Through timing margin optimization and adjustable trigger signal length, data reading timing errors are avoided, and the reliability of long-term system operation is improved.

[0060] In an optional embodiment, the synchronization method of the present application is described in detail in combination with specific parameters and timing relationships, so that those skilled in the art can more clearly understand the implementation process of the present application.

[0061] 1. System parameter setting

[0062] In this embodiment, the system core parameters are set as follows:

[0063] Reference clock source output frequency: 25MHz;

[0064] Main control chip PLL output clock: 125MHz (internal logic working clock), 1GHz (data sending clock, single edge trigger);

[0065] DAC parameters: sampling rate 1GSPS, resolution 8bit, interface data width 8bit;

[0066] Parallel-to-serial conversion shift register: 8bit parallel data is received at 125MHz per channel, and serial data is sent at 1GHz;

[0067] DAC board quantity: N pieces (N≥2, adapt to the needs of the measurement and control system).

[0068] 2. Synchronization process specific embodiment

[0069] After the reference clock source is started, a 25MHz reference clock is generated and distributed to N pieces of DAC boards through a same-specification cable with a length error, and each piece of DAC board receives a reference clock with a phase difference; after the trigger controller is started, a built-in PLL thereof multiplies the 25MHz reference clock to 125MHz to generate a trigger signal, which is distributed to N pieces of DAC boards through a same-specification cable with an adjustable length, and the length of the cable is adjusted to make the time difference of receiving the trigger signal by each DAC board meet the requirements of the setup time and the hold time of the trigger signal. After the main control chip on each DAC board receives the 25MHz reference clock, a built-in PLL thereof multiplies the reference clock to 125MHz and 1GHz, the 125MHz clock drives the internal logic register to work, and the internal logic register generates 8bit parallel digital quantity (digital quantity of a plurality of waveforms) to be converted according to the measurement and control requirement; the 1GHz clock drives the parallel-serial conversion shift register to work, and the shift register waits for the trigger signal to start data reception; the internal layout and wiring of the main control chip strictly follow the principle of consistent delay and close position, wherein, the wiring delay difference between P1 to phase detector and P4 to phase detector is less than 0.1ns, and the physical distance is the minimum process distance; the wiring delay difference between the voltage-controlled oscillator to P3 and to P2 is less than 0.1ns, and the physical distance is the minimum process distance; and the wiring length difference between the voltage-controlled oscillator to the internal logic register and to the 5-frequency division register meets the timing requirements.

[0070] When the DAC board receives the trigger signal, the internal logic register immediately sends 8bit parallel digital quantity to the parallel-serial conversion shift register at a rate of 125MHz; after the parallel-serial conversion shift register receives the parallel data, it converts the parallel data to serial data at a rate of 1GHz, and sends the serial data to the input interface of the DAC through the impedance-matched transmission line. The DAC PLL on each DAC board multiplies the 25MHz reference clock to 1GHz, adjusts the phase by fine granularity, aligns the rising edge of the DAC sampling clock with the center of the stable window of the serial data, and ensures the timing margin; under the unified trigger of the 1GHz sampling clock, all DACs synchronously read the serial digital quantity, convert the digital quantity to analog waveform after fixed period processing, realize that the analog waveforms output by N pieces of DAC are generated at the same time, and the waveform deviation is better than 1 sampling period.

[0071] It should be noted that the synchronization method of the multi-channel high-speed digital-to-analog conversion module can also be applied to a quantum chip measurement and control system to perform quantum measurement and control operations.

[0072] The reference clock cables are equal in length, the trigger signal cables are equal in length, the main control chip PLL feedback path is compensated, that is, the feedback path is moved outside the chip to compensate for the chip IO delay, the internal key wire of the main control chip is equal in time, the clock layout and wiring requirements of the main control chip are the same, and the length of the trigger cable can be adjusted, and the DAC PLL output phase can be finely adjusted to ensure that there is sufficient timing margin when the DAC reads digital quantities. The above layout and wiring requirements compensate for the delay of multiple changes, which is an important guarantee for the simultaneous arrival of digital quantities at the DAC, and is an important part of the application.

[0073] Compared with the prior art, the application is applied to a measurement and control system comprising multiple digital-to-analog converters (DACs), including a reference clock source, a trigger controller, and at least two DAC boards with consistent structures. Each DAC board is integrated with a main control chip, a DAC, a main control chip PLL, and a DAC PLL. The reference clock source generates a reference clock, which is distributed to all DAC boards through equal-length reference clock cables to ensure that the reference clock phases received by each DAC board are consistent. The trigger controller generates a trigger signal, which is distributed to all DAC boards through equal-length and adjustable-length trigger signal cables. The trigger signal is used to inform each DAC board to start sending digital quantities of a new waveform. The main control chip PLL multiplies the reference clock to a preset working frequency, and the feedback path of the main control chip PLL is moved to the DAC board. At the same time, the main control chip layout and wiring meet the following requirements: the delays of the two wires from the chip IO to the phase detector are consistent and close in position; the delays of the wires from the voltage-controlled oscillator output to the main control chip IO are consistent and close in position; the DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable to ensure the timing margin when the DAC reads digital quantities; under the trigger of the trigger signal, the main control chip sends several waveform digital quantities to be converted to the DAC through an equal-time transmission path at a preset time. The DAC converts the digital quantities into analog waveforms, realizing the conversion of digital quantities to analog quantities by all DACs at the same time. It solves the synchronization problem of a multi-channel high-speed DAC measurement and control system and realizes high-precision synchronous conversion of the DAC.

[0074] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the action sequence described, because according to the application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the application.

[0075] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0076] In several embodiments provided by the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments described above is merely illustrative, and the division of the units can be changed according to actual needs. For example, the units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0077] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.

[0078] In addition, each functional unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0079] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0080] The embodiments of the present application are described in detail above, and the specific examples are applied to the principles and implementation manners of the present application. The above embodiment descriptions are only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range can be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A synchronization method for a multi-channel high-speed digital-to-analog converter module, characterized in that, A measurement and control system comprising multiple digital-to-analog converters (DACs) is provided. The system structure includes a reference clock source, a trigger controller, and at least two identical DAC boards. Each DAC board integrates a main control chip, a DAC, a main control chip PLL, and a DAC PLL. The method includes: The reference clock source generates a reference clock, which is distributed to all DAC boards through reference clock cables of equal length to ensure that the reference clock received by each DAC board is in phase. The trigger controller generates a trigger signal, which is distributed to all DAC boards through trigger signal cables of equal and adjustable length. The trigger signal is used to notify each DAC board to start sending digital signals of a new waveform. The main control chip PLL multiplies the reference clock to a preset operating frequency, and the feedback path of the main control chip PLL is moved to the DAC board. Simultaneously, the layout and routing of the main control chip satisfy the following: the two traces from the main control chip I / O to the phase detector have consistent delays and are located close to each other; the traces from the voltage-controlled oscillator output to the main control chip I / O have consistent delays and are located close to each other. Specifically, the main control chip PLL multiplies the reference clock into two clock paths: the first path is set to a 125MHz clock for the operation of the main control chip's internal logic registers; the second path is set to a 1GHz clock for the main control chip to send data to the DAC, and the 1GHz clock uses single-edge triggered data transmission. The traces from the voltage-controlled oscillator output to the third main control chip I / O and to the second main control chip I / O include: traces from the voltage-controlled oscillator output to the third main control chip I / O via 8-division and 5-division, and traces from the voltage-controlled oscillator output to the second main control chip I / O via a parallel-to-serial conversion shift register. The third main control chip I / O and the second main control chip I / O are in phase. The DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable to ensure the timing margin when the DAC reads digital data. When triggered by a trigger signal, the main control chip sends several digital waveforms to be converted to the DAC at a preset time through an isochronous transmission path. The DAC converts the digital signals into analog waveforms, so that all the DACs can complete the conversion from digital to analog signals at the same time.

2. The synchronization method according to claim 1, characterized in that, The reference clock source provides a clock reference for the measurement and control system to ensure that the clock frequency of each module of the measurement and control system is without deviation; wherein, the frequency of the reference clock is set to 25MHz.

3. The synchronization method according to claim 2, characterized in that, The feedback path of the main control chip PLL is located outside the main control chip and is routed from the DAC board.

4. The synchronization method according to claim 3, characterized in that, The main control chip integrates at least one parallel-to-serial conversion shift register. The parallel-to-serial conversion shift register receives 8 bits of parallel digital data from an internal logic register at a rate of 125MHz, and then converts the parallel digital data into serial digital data at a rate of 1GHz and sends it to the DAC.

5. The synchronization method according to claim 1, characterized in that, The trigger controller has a built-in trigger controller PLL, which multiplies the reference clock to the operating frequency of the trigger controller to ensure that the trigger controller outputs a stable trigger signal.

6. The synchronization method according to claim 1, characterized in that, The parameters of the DAC include: sampling rate of 1 GSPS, resolution of 8 bits, and interface data width of 8 bits; the DAC is used to receive the serial digital quantity sent by the main control chip and convert it into the corresponding analog waveform.

7. The synchronization method according to claim 1, characterized in that, The two traces from the chip I / O to the phase detector include: the trace from the first main control chip I / O to the phase detector on the DAC board and the trace from the fourth main control chip I / O to the phase detector; wherein, the phases of the first main control chip I / O and the fourth main control chip I / O are consistent.

8. The synchronization method according to any one of claims 1-7, characterized in that, The synchronization method ensures that the analog waveform deviation of all DAC outputs is better than one sampling period, and that the digital quantities planned to be converted at the same time are all converted into analog waveforms at the same time.

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