Programming method of memory, memory and storage system

Abstract

The present application provides a programming method, a memory, and a storage system for a memory, relating to the field of storage technologies. The method includes: in a first pulse stage of programming a selected memory cell, applying a first programming voltage to a selected word line with a first pulse width; in a second pulse stage of programming the selected memory cell, applying a second programming voltage to the selected word line with a second pulse width; wherein, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage. During the programming process, different pulse bandwidths are adopted in different pulse stages, and programming is performed according to the corresponding pulse bandwidth according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth can be adopted to ensure sufficient programming duration; while when the programming voltage is high, a shorter pulse bandwidth is adopted to increase the supplementary potential and reduce the loss caused by programming voltage interference.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and particularly to a programming method for a memory, a memory, and a storage system. Background Art

[0002] A three-dimensional (3D) memory generally includes a plurality of memory strings arranged in an array, and each memory string includes a plurality of memory cells connected in series. When programming a selected memory cell (i.e., writing data), a programming voltage needs to be applied to a selected word line (WL) connected to the selected memory cell, so that electrons in the channel of the selected memory cell tunnel to the floating gate.

[0003] Among them, the programming process is implemented by an Increment Step Pulse Program (ISPP) method, and a programming voltage with a certain pulse width is applied in each pulse stage of the ISPP for programming.

[0004] However, when the pulse width in the pulse stage of the ISPP is large, the programming efficiency will be reduced at a relatively large programming voltage, affecting the programming speed of the memory. Summary of the Invention

[0005] This application provides a programming method for a memory, a memory, and a storage system, which can improve the programming efficiency. The technical solution is as follows:

[0006] On the one hand, a programming method for a memory is provided, and the method includes:

[0007] Applying a first programming voltage to a selected word line with a first pulse width in a first pulse stage;

[0008] Applying a second programming voltage to the selected word line with a second pulse width in a second pulse stage;

[0009] The first pulse stage and the second pulse stage are two pulse stages among a plurality of pulse stages for programming a selected memory cell, the selected memory cell is a memory cell to be programmed, and the selected word line is the word line connected to the selected memory cell;

[0010] The selected memory cell is programmed by an Increment Step Pulse Program method, the first pulse stage is earlier than the second pulse stage in time sequence, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage.

[0011] In an optional embodiment, the plurality of pulse stages are divided into a first programming stage and a second programming stage;

[0012] The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage;

[0013] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

[0014] In an optional embodiment, the first programming stage includes a first number of pulse stages arranged continuously, and the second programming stage includes a second number of pulse stages arranged continuously;

[0015] Or,

[0016] The programming voltage of each pulse stage in the first programming stage is less than the stage voltage threshold, and the programming voltage of each pulse stage in the second programming stage is greater than the stage voltage threshold.

[0017] In an optional embodiment, the magnitude of the pulse width of the pulse stage is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0018] In an optional embodiment, the first programming voltage corresponds to a first initial programming voltage at the initial moment of the first pulse stage, and the first programming voltage corresponds to a first termination programming voltage at the termination moment of the first pulse stage, and the first initial programming voltage is less than the first termination programming voltage;

[0019] The second programming voltage corresponds to a second initial programming voltage at the initial moment of the second pulse stage, and the second programming voltage corresponds to a second termination programming voltage at the termination moment of the second pulse stage, and the second initial programming voltage is less than the second termination programming voltage.

[0020] In an optional embodiment, the difference between the first termination programming voltage and the first initial programming voltage is a first voltage difference;

[0021] The difference between the second termination programming voltage and the second initial programming voltage is a second voltage difference;

[0022] The first voltage difference is greater than the second voltage difference.

[0023] In an optional embodiment, the first programming voltage shows a stepwise increasing trend during the first pulse stage and the second programming voltage shows a stepwise increasing trend during the second pulse stage;

[0024] Or,

[0025] Both the first programming voltage and the second programming voltage show a linear increasing trend during the pulse stage;

[0026] Or,

[0027] The first programming voltage has either a stepped increasing trend or a linear increasing trend in the first pulse stage, and the second programming voltage has the other of the stepped increasing trend or the linear increasing trend in the second pulse stage.

[0028] In an alternative embodiment, the method further includes:

[0029] In a third pulse stage, applying a third programming voltage to the selected word line with a third pulse width;

[0030] wherein the second pulse stage is temporally prior to the third pulse stage, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

[0031] On the other hand, a memory is provided, the memory includes: a storage array unit and a peripheral logic unit, and the peripheral logic unit includes a control circuit;

[0032] The control circuit is configured to apply a first programming voltage to the selected word line with a first pulse width in a first pulse stage; apply a second programming voltage to the selected word line with a second pulse width in a second pulse stage;

[0033] The first pulse stage and the second pulse stage are two of a plurality of pulse stages for programming a selected memory cell, the selected memory cell is a memory cell to be programmed, and the selected word line is a word line connected to the selected memory cell;

[0034] The selected memory cell is programmed by a stepped pulse voltage programming method, the first pulse stage is temporally prior to the second pulse stage, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage.

[0035] In an alternative embodiment, the plurality of pulse stages are divided into a first programming stage and a second programming stage;

[0036] The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage;

[0037] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

[0038] In an alternative embodiment, the first programming phase includes a first number of pulse phases arranged in series, and the second programming phase includes a second number of pulse phases arranged in series;

[0039] Alternatively,

[0040] the programming voltage of each pulse phase in the first programming phase is less than the phase voltage threshold, and the programming voltage of each pulse phase in the second programming phase is greater than the phase voltage threshold.

[0041] In an alternative embodiment, the magnitude of the pulse width of the pulse phase is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0042] In an alternative embodiment, the first programming voltage corresponds to a first initial programming voltage at the initial moment of the first pulse phase, and the first programming voltage corresponds to a first termination programming voltage at the termination moment of the first pulse phase, and the first initial programming voltage is less than the first termination programming voltage;

[0043] the second programming voltage corresponds to a second initial programming voltage at the initial moment of the second pulse phase, and the second programming voltage corresponds to a second termination programming voltage at the termination moment of the second pulse phase, and the second initial programming voltage is less than the second termination programming voltage.

[0044] In an alternative embodiment, the difference between the first termination programming voltage and the first initial programming voltage is a first voltage difference;

[0045] the difference between the second termination programming voltage and the second initial programming voltage is a second voltage difference;

[0046] the first voltage difference is greater than the second voltage difference.

[0047] In an alternative embodiment, the first programming voltage shows a stepwise increasing trend during the first pulse phase and the second programming voltage shows a stepwise increasing trend during the second pulse phase;

[0048] Alternatively,

[0049] both the first programming voltage and the second programming voltage show a linear increasing trend during the pulse phase;

[0050] Alternatively,

[0051] the first programming voltage shows either a stepwise increasing trend or a linear increasing trend during the first pulse phase, and the second programming voltage shows the other of a stepwise increasing trend or a linear increasing trend during the second pulse phase.

[0052] In an alternative embodiment, the control circuit is further configured to apply a third programming voltage to the selected word line with a third pulse width during a third pulse phase;

[0053] wherein, the second pulse phase is temporally prior to the third pulse phase, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

[0054] On the other hand, a storage system is provided, the storage system includes:

[0055] one or more memories as described in the above embodiments, and,

[0056] a memory controller coupled to the memory and configured to control the storage.

[0057] On the other hand, a computer-readable storage medium is provided, in which instructions are stored, and when the instructions run on a control circuit, they implement the programming method of the memory as described in any one of the above embodiments.

[0058] The technical solution provided by this application may include the following beneficial effects:

[0059] During the programming process, different pulse bandwidths are used in different pulse phases, and corresponding pulse bandwidths are used for programming according to the programming voltage of the pulse phase. When the programming voltage is low, a longer pulse bandwidth can be used to ensure sufficient programming duration; while when the programming voltage is high, a shorter pulse bandwidth is used. In the programming environment of the stepped pulse voltage programming method, the programming efficiency of the memory can be improved and the programming speed can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0061] Figure 1 is a schematic structural diagram of a 3D memory provided by an illustrative embodiment of the present application;

[0062] Figure 2 is a schematic diagram of stepped pulse voltage programming provided by an illustrative embodiment of the present application;

[0063] Figure 3 is a flowchart of a programming method of a memory provided by an exemplary embodiment of the present application;

[0064] Figure 4 is a schematic diagram of the application process of the first programming voltage provided based on the Figure 3 illustrated embodiment;

[0065] Figure 5 is a schematic diagram of dividing the programming process into two programming stages provided by an exemplary embodiment of the present application;

[0066] Figure 6 is a schematic diagram of dividing the programming process into three programming stages provided by an exemplary embodiment of the present application;

[0067] Figure 7 is a schematic diagram of determining the pulse width according to the division of programming stages provided by an exemplary embodiment of the present application;

[0068] Figure 8 is a bar schematic diagram of the pulse width provided by an exemplary embodiment of the present application;

[0069] Figure 9 is a flowchart of a programming method of a memory provided by another exemplary embodiment of the present application;

[0070] Figure 10 is a schematic diagram of the linear rise of the programming voltage provided by an exemplary embodiment of the present application;

[0071] Figure 11 is a schematic diagram of the stepped rise of the programming voltage provided by an exemplary embodiment of the present application;

[0072] Figure 12 is a schematic diagram of the structure of a memory provided by an exemplary embodiment of the present application;

[0073] Figure 13 is a schematic diagram of the structure of a storage system provided by an exemplary embodiment of the present application. Detailed implementation manners

[0074] The following further describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0075] The programming method of the memory provided by the embodiment of the present application can be applied to a memory. The memory can be a 3D memory, for example, it can be a 3D NAND flash.

[0076] A three-dimensional (3D) memory is a multi-layer stacked memory. Schematically, the 3D memory is a 3D NAND flash. As Figure 1As shown, a plurality of memory strings 110 included in the 3D memory 100 are arranged in a direction parallel to the bearing surface of the substrate, and a plurality of memory cells 120 in each memory string 110 are arranged in a direction perpendicular to the bearing surface of the substrate. That is, the plurality of memory cells included in the 3D memory are arranged in a three-dimensional array on the substrate to form a memory array (array).

[0077] One end of the memory string 110 is connected to the bit line (Bite Line, BL), and the other end is connected to the source line (Source Line, SL).

[0078] The memory cells in each memory string are also connected to the memory cells in other memory strings through word lines (Word Line, WL). For example, each memory string may include 64 memory cells, then the 3D memory may include 64 word lines WL<63:0>, and each word line is connected to a part of the memory cells located in the same layer (i.e., having the same height relative to the substrate). It should be noted that 64 memory cells are only a specific example, and the application is not limited thereto. In some embodiments, each memory string may include more than 64 memory cells, such as 128, 196, etc. In a 3D memory, the memory cells connected to the same word line are called a memory page (page), and all the memory strings sharing a set of word lines are called a memory block (block).

[0079] The memory string 110 further includes an upper selection transistor connected to the drain of the first memory cell and a lower selection transistor connected to the source of the last memory cell. Among them, the upper selection transistor is also called the top select gate (Top Select Gate, TSG) or the drain select transistor. The lower selection transistor is also called the bottom select gate (Bottom Select Gate, BSG) or the source select transistor.

[0080] The gate of the TSG is connected to the drain select line (Drain Select Line, DSL), the source of the TSG is connected to the drain of the first memory cell, and the drain of the TSG is connected to the bit line.

[0081] The gate of the BSG is connected to the source select line (Source Select Line, SSL), the drain of the BSG is connected to the source of the last memory cell, and the source of the BSG is connected to the source line.

[0082] By Figure 1It can be known that the memory cells in memory string 110 share a group of WLs with the memory cells in other memory strings. Assuming that each memory string includes m + 1 memory cells, the 3D memory can include m + 1 WLs: WL0 to WLm, where m is an integer greater than 1. Among them, each WL is connected to the respective memory cells located in the same layer (i.e., having the same height relative to the bearing surface of the substrate). Or, it can be understood that: the control gates of the respective memory cells located in the same layer, and the gate connection lines between the respective control gates form a WL.

[0083] According to the amount of data that a memory cell can store, the types of memory cells can be classified into single-level cell (SLC), multi-level cell (MLC), trinary-level cell (TLC), and quad-level cell (QLC), etc. Among them, each SLC can store 1 bit of data, each MLC can store 2 bits of data, each TLC can store 3 bits of data, and each QLC can store 4 bits of data. In a 3D memory, the data stored in the respective memory cells located in the same layer can form k memory pages. Among them, k is the number of bits of data that each memory cell can store.

[0084] In the embodiments of the present application, the memory cells in the 3D memory can be floating-gate field-effect transistors or charge trap field-effect transistors and other field-effect transistors capable of storing data. TSG and BSG can be ordinary field-effect transistors, or they can also be field-effect transistors capable of storing data. Among them, the floating-gate field-effect transistor includes a source electrode, a drain electrode, and two gate electrodes. Both of the two gate electrodes are conductors, and one of the two gate electrodes is a control gate (CG), and the other gate electrode is a floating gate (FG), simply referred to as a floating gate. The control gate is used to connect to the word line, and the floating gate is the unit for storing data. The charge trap field-effect transistor includes a source electrode, a drain electrode, a control gate, and a charge trap layer. The charge trap layer is the unit for storing data, and the charge trap layer is made of an insulating material such as silicon nitride. Below, taking the floating-gate field-effect transistor as an example, the data writing principle of the memory cell is introduced.

[0085] When writing data into a memory cell, a programming voltage can be applied to the control gate of the floating-gate field-effect transistor, so that electrons in the channel of the floating-gate field-effect transistor tunnel to the floating gate. By controlling the magnitude of the programming voltage, the number of electrons tunneling to the floating gate can be controlled, and thus the magnitude of the threshold voltage Vth of the floating-gate field-effect transistor can be controlled. Generally, the higher the charge stored in the floating gate, the higher the threshold voltage Vth of the floating-gate field-effect transistor. It can be understood that when the threshold voltage Vth of the floating-gate field-effect transistor is different, the voltage required to be applied to the control gate of the floating-gate field-effect transistor to turn it on is different. Therefore, the magnitude of the threshold voltage Vth of the floating-gate field-effect transistor can reflect the content of the data stored therein.

[0086] It should be understood that in a 3D memory, the channels of the respective memory cells in each memory string can be connected in sequence to form a columnar structure perpendicular to the substrate.

[0087] Currently, the main programming method used in memory programming is the Increment Step Pulse Program (ISPP) method. During the programming process, when applying the programming voltage, the voltage is not applied in one go, but is increased step by step incrementally until the voltage reaches the programming requirement.

[0088] Schematically, please refer to Figure 2 , which shows an ISPP programming schematic diagram provided by an exemplary embodiment of the present application. As Figure 2 shown, during the programming process, first, an initial voltage is applied to the selected word line corresponding to the selected memory cell in the first pulse stage 210, and then it is verified whether the initial voltage reaches the required programming voltage. If not, a voltage step ΔVpp is added to the initial voltage to obtain a second pulse voltage, and the second pulse voltage is applied to the selected word line corresponding to the selected memory cell in the second pulse stage 220, and it is continuously verified whether the second pulse voltage reaches the required programming voltage. The above process is repeated until the pulse voltage applied to the selected word line reaches the required programming voltage, and then the programming stops.

[0089] In the related art, in order to improve the programming speed, usually the pulse width is extended, so as to increase the step size to accelerate the programming. During the ISPP process, the longer the pulse width, the larger the step size (step) between two adjacent pulse stages. For example: if pulse stage 1 corresponds to pulse width 1, then 0.4V is added to the programming voltage of pulse stage 1 as the programming voltage of pulse stage 2, and enter pulse stage 2; if pulse stage 1 corresponds to pulse width 2, and pulse width 2 is greater than pulse width 1, then 0.7V is added to the programming voltage of pulse stage 1 as the programming voltage of pulse stage 2, and enter pulse stage 2.

[0090] However, extending the pulse width will result in margin loss of the read window. Since the pulse duration of the programming voltage pulse in each pulse stage becomes longer, there will be a loss of duration in the process of reaching the required programming voltage.

[0091] Margin loss includes the loss caused by the lower boosting potential of the selected memory cell when the programming voltage is relatively large after extending the pulse width, thus reducing the programming efficiency.

[0092] In the embodiments of the present application, the pulse width of the pulse stage in the above ISPP process is adaptively adjusted, and the pulse width of the previous pulse stage in the ISPP process is controlled to be greater than the pulse width of the subsequent pulse stage in the ISPP process, so as to avoid the margin loss caused by programming interference while increasing the programming rate.

[0093] Figure 3 FIG. is a flowchart of a programming method of a memory provided by an exemplary embodiment of the present application. Taking the application of this method to a 3D memory as an example, as Figure 3 shown, the method includes:

[0094] Step 301, applying a first programming voltage to the selected word line with a first pulse width in a first pulse stage.

[0095] The first pulse stage is one of the multiple pulse stages for programming the selected memory cell.

[0096] Wherein, the selected memory cell is the memory cell to be written with data, and the selected word line is the word line connected to the selected memory cell.

[0097] The first pulse stage is the stage for applying the programming voltage to the memory cell during the programming process. In the first pulse stage, the programming voltage continuously applied to the selected word line is the first programming voltage, and the pulse width is the first pulse width. In some embodiments, the programming voltage is directly increased to the first programming voltage in the first pulse stage, or, in the first pulse stage, the programming voltage is first increased to a first intermediate voltage and then increased from the first intermediate voltage to the first programming voltage. This embodiment does not limit this.

[0098] In the embodiments of the present application, the first pulse width refers to the pulse width corresponding to the applied first programming voltage, that is, the application process of the first intermediate voltage and the voltage increase process are pulses other than the pulse width; or, the first pulse width refers to the pulse width corresponding to the period from the application of the first intermediate voltage until the application of the first programming voltage is completed.

[0099] Schematically, taking the pulse width corresponding to the first programming voltage applied as the first pulse width as an example for illustration, as Figure 4 shown, for the selected word line 400, during the first pulse stage (Loop) of the selected memory cell through the selected word line 400, a first programming voltage is applied to the selected word line 400. Among them, first, a first intermediate voltage is applied to the selected word line 400, and then it is increased to the first programming voltage on the basis of the first intermediate voltage. Among them, the application process corresponding to the first programming voltage corresponds to the first pulse width.

[0100] Among them, the first intermediate voltage is a stage voltage between the starting voltage and the first programming voltage. The value of the first intermediate voltage can be the intermediate value of the starting voltage and the first programming voltage, or can be the voltage value between the starting voltage and the first programming voltage determined according to other optimization principles, or can be any value between the starting voltage and the first programming voltage. This embodiment does not limit this. Among them, the starting voltage can be the pre-charge voltage in the pre-charge stage or the verification voltage in the verification stage.

[0101] Step 302, apply a second programming voltage to the selected word line with a second pulse width in the second pulse stage.

[0102] The first pulse stage and the second pulse stage are two pulse stages among multiple pulse stages for programming the selected memory cell.

[0103] Among them, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage.

[0104] Optionally, the selected memory cell is programmed in a stepped pulse voltage mode ISPP, and the first pulse stage is earlier in time than the second pulse stage.

[0105] The second pulse stage is the stage for applying a programming voltage to the memory cell during the programming process. And in the second pulse stage, the programming voltage continuously applied to the selected word line is the second programming voltage, and the pulse width is the second pulse width. In some embodiments, in the second pulse stage, the programming voltage is directly increased to the second programming voltage, or, in the second pulse stage, first the programming voltage is increased to the second intermediate voltage, and then it is increased from the second intermediate voltage to the second programming voltage. This embodiment does not limit this.

[0106] In the embodiment of the present application, the second pulse width refers to the pulse width corresponding to the second programming voltage applied, that is, the application process of the second intermediate voltage and the process of voltage increase are pulses other than the pulse width; or the second pulse width refers to the pulse width corresponding to the period from the application of the second intermediate voltage until the application of the second programming voltage is completed.

[0107] Among them, the second intermediate voltage is a stage voltage between the starting voltage and the second programming voltage. The value of the second intermediate voltage can be the intermediate value of the starting voltage and the second programming voltage, or the voltage value between the starting voltage and the second programming voltage determined according to other optimization principles, or any value between the starting voltage and the second programming voltage. This embodiment does not limit this.

[0108] In some embodiments, if the first pulse stage is temporally prior to the second pulse stage, then the starting voltage is the verification voltage of the verification stage before the second pulse stage.

[0109] That is to say, in the embodiments of the present application, in the programming stage, there are at least two pulse stages. For the pulse stage with a smaller programming voltage, the pulse width is larger, and for the pulse stage with a larger programming voltage, the pulse width is smaller.

[0110] In some embodiments, during the programming process, the channel of the selected memory string is grounded, and the channel of the deselected memory string is floated. Among them, the selected memory string refers to the memory string to which the selected memory cell belongs, and the other memory strings outside the selected memory string are the deselected memory strings. In this embodiment, the TSG in the selected memory string is turned on, the BSG in the selected memory string is turned off, and the BL connected to the TSG is grounded, so that the channel of the selected memory string is grounded. And, the TSG and BSG in the deselected memory string are both turned off, so that the channel of the deselected memory string is floated. Thus, when programming the selected memory cell through the selected word line, it will not affect the memory cells in the deselected memory string.

[0111] Optionally, while applying the programming voltage V pgm on the selected word line, a turn-on voltage V pass can be applied on the deselected (unselected, unsel) WLs. The turn-on voltage V pass is used to turn on all the deselected memory cells connected to the unsel WL, so as to realize the connection between the selected memory cell and the sel BL. Among them, the deselected memory cells are the memory cells that do not correspond to the programming task.

[0112] It can be understood that the programming voltage V pgm is usually relatively high, so a large voltage difference can be formed between the control gate and the channel of the selected memory cell, and then electrons in the channel can tunnel to the floating gate of the selected memory cell to realize data storage. And, by adjusting the magnitude of the programming voltage V pgm , the number of electrons stored in the floating gate can be adjusted, and then the threshold voltage Vth of the selected memory cell can be adjusted.

[0113] Since the turn-on voltage V pass is usually lower than the programming voltage V pgm, so the voltage difference between the control gate and the channel of the deselected memory cell connected to the unsel WL is relatively small, thereby avoiding the tunneling of electrons in the channel to the floating gate. For the deselected memory cell connected to the sel WL in the deselected memory string, since the channel of the deselected memory string is floating, the voltage difference between the control gate and the channel of the deselected memory cell connected to the sel WL is also relatively small, which can also avoid the tunneling of electrons in the channel to the floating gate. That is, when programming the selected memory cell, the deselected memory cells connected to the unsel WL and the deselected memory cells connected to the sel WL will not be programmed, that is, the programming of the deselected memory cells is suppressed.

[0114] In summary, the method provided by the embodiment of the present application uses different pulse bandwidths in different pulse stages during the programming process, and performs programming according to the corresponding pulse bandwidth according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth can be used to ensure sufficient programming duration and increase the step size in the low programming voltage stage to accelerate programming; when the programming voltage is large, a shorter pulse bandwidth is used, which can improve the programming efficiency of the memory and improve the programming speed in the programming environment of the stepped pulse voltage programming method.

[0115] Optionally, the determination method of the pulse width includes at least one of the following methods:

[0116] First, divide the programming process into programming stages

[0117] That is, divide the programming process of the selected memory cell into at least two programming stages. Each programming stage includes at least one pulse stage, and each programming stage corresponds to a pulse width. That is, the pulse stages in the same programming stage correspond to the same pulse width. Among them, the programming stage includes a first programming stage and a second programming stage.

[0118] Optionally, the programming process is divided into programming stages according to the programming timing. For example: the first n pulse stages in the programming process are divided into the first programming stage, and the (n + 1)-th pulse stage to the (n + m)-th pulse stage are divided into the second programming stage, where n and m are positive integers.

[0119] In this embodiment, the multiple pulse stages are divided into a first programming stage and a second programming stage; the pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage;

[0120] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

[0121] Optionally, the first programming stage and the second programming stage can be two adjacent programming stages, or any two non - adjacent programming stages.

[0122] Among them, the number of pulse stages included in each programming stage can be the same or different.

[0123] Schematically, taking the programming process divided into two programming stages as an example, as Figure 5 shown, in the programming process of the selected storage cell, it is divided into programming stage 510 and programming stage 520. Among them, programming stage 510 includes pulse stages (Loop) 1 to Loopk, that is, a total of k pulse stages, and the pulse stages in this programming stage 510 correspond to pulse bandwidth 1 (pulsewidth_1); programming stage 520 includes Loopk + 1 to Loopk + m, a total of m pulse stages, and the pulse stages in this programming stage 520 correspond to pulse bandwidth 2 (pulse width_2). Among them, k, m, and n are all positive integers.

[0124] Schematically, taking the programming process divided into three programming stages as an example, as Figure 6 shown, in the programming process of the selected storage cell, it is divided into programming stage 610, programming stage 620, and programming stage 630. Among them, programming stage 610 includes pulse stages (Loop) 1 to Loopk, that is, a total of k pulse stages, and the pulse stages in this programming stage 610 correspond to pulse bandwidth 1 (pulse width_1); programming stage 620 includes Loopk + 1 to Loopk + m, a total of m pulse stages, and the pulse stages in this programming stage 620 correspond to pulse bandwidth 2 (pulse width_2); programming stage 630 includes Loopk + m + 1 to Loopk + m + n, a total of n pulse stages, and the pulse stages in this programming stage 630 correspond to pulse bandwidth 3 (pulsewidth_3).

[0125] It should be noted that the above division into two programming stages and three programming stages is only a schematic example. In some embodiments, multiple pulse stages can also be divided into more programming stages, and this embodiment does not limit this.

[0126] Schematically, taking the programming process divided into three programming stages as an example, as Figure 7 shown, the selected storage cell is storage cell n, and its corresponding selected word line is Select WLn. Then, in the programming process, it is divided into three programming stages. Among them, the first programming stage includes Loop710, the second programming stage includes Loop720, and the third programming stage includes Loop730.

[0127] In Loop710, a first programming voltage is applied to Select WLn, and the first programming voltage corresponds to a first pulse width; in Loop720, a second programming voltage is applied to Select WLn, and the second programming voltage corresponds to a second pulse width; in Loop730, a third programming voltage is applied to Select WLn, and the third programming voltage corresponds to a third pulse width. And due to the characteristics of the stepped pulse voltage programming ISPP method, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; while the first pulse width is greater than the second pulse width, and the second pulse width is greater than the third pulse width.

[0128] Among them, Loop710 is one of the pulse stages in the first programming stage, Loop720 is one of the pulse stages in the second programming stage, and Loop730 is one of the pulse stages in the third programming stage. Figure 7 It is only a schematic example.

[0129] The above pulse stages are shown in a bar chart as Figure 8 shown. During the programming process, there are stepped pulse stages 810, 820, and 830. Among them, the pulse stage 810 corresponds to a wider pulse width and a smaller programming voltage; the pulse width of the pulse stage 820 is smaller than that of the pulse stage 810, and the programming voltage of the pulse stage 820 is greater than that of the pulse stage 810; the pulse width of the pulse stage 830 is smaller than that of the pulse stage 820, and the programming voltage of the pulse stage 830 is greater than that of the pulse stage 820.

[0130] Optionally, the above division method of the programming stage includes at least one of the following methods:

[0131] 1.1 Divide multiple pulse stages into programming stages based on the number of steps.

[0132] Among them, the number of steps refers to the number of adjustments of the programming voltage in ISPP. In some embodiments, when the required programming voltage is not reached, the programming voltage is adjusted once between the i-th pulse stage and the (i + 1)-th pulse stage, that is, adjusted once between adjacent two pulse stages, and there is one step between adjacent two pulse stages.

[0133] Then, the first programming stage includes a first number of pulse stages arranged continuously, and the second programming stage includes a second number of pulse stages arranged continuously, where the first number and the second number are the same, or the first number and the second number are different. Taking the case where the first number and the second number are the same as an example, for instance: the first programming stage includes 3 sequentially arranged pulse stages, and the second programming stage includes 3 sequentially arranged pulse stages; taking the case where the first number and the second number are different and the first number and the second number decrease according to the sorting of the programming stages as an example, for instance: the first programming stage includes 4 continuously arranged pulse stages, and the second programming stage includes 3 continuously arranged pulse stages.

[0134] Schematically, every three Loops stepped forward divide a programming stage. For example: stepping from Loop1 to Loop2, and from Loop2 to Loop3, then Loop1, Loop2, and Loop3 are divided into the same programming stage, corresponding to the same pulse width 1, and after Loop3, the pulse width starts to decrease to pulse width 2. Starting from Loop4, it corresponds to pulse width 2. Stepping from Loop3 to Loop4, from Loop4 to Loop5, and from Loop5 to Loop6, then Loop4, Loop5, and Loop6 are divided into the same programming stage, corresponding to the same pulse width 2, and so on.

[0135] 1.2 Divide the programming process into programming stages based on the step size of the programming voltage for stepping.

[0136] Among them, the step size is the adjustment amplitude of the programming voltage between adjacent two pulse stages. For example: during the programming process, the programming voltage difference between adjacent two pulse stages is 1V, then this step size is 1V. Divide the rated programming stage according to this step size.

[0137] Schematically, when the step size is less than 1V, every four pulse stages are divided into a programming stage; when the step size is greater than 1V, every three pulse stages are divided into a programming stage; when the step size is 3V, every two pulse stages are divided into a programming stage.

[0138] For example: the step size of the ISPP programming process is 2V, then Loop1, Loop2, and Loop3 are divided into a programming stage, corresponding to pulse width 1. The step size of the ISPP programming process is 0.7V, and Loop4, Loop5, Loop6, and Loop7 are divided into a programming stage, corresponding to pulse width 2, and so on until the programming voltage reaches the required programming voltage.

[0139] 1.3 Divide the programming process into programming stages based on the stage voltage threshold.

[0140] Among them, the stage voltage threshold is used to define the programming voltage range corresponding to each programming stage.

[0141] Then, in the first programming stage, the programming voltage of each pulse stage is less than the stage voltage threshold, and in the second programming stage, the programming voltage of each pulse stage is greater than the stage voltage threshold.

[0142] Illustratively, if the stage voltage thresholds are set to 2V, 5V, and 8V, then when the programming voltage reaches 2V, the pulse stages with a programming voltage of 2V and within are divided into the same programming stage, corresponding to a pulse width of 1; when the programming voltage reaches 5V, the pulse stages with a programming voltage in the range of 2V to 5V are divided into the same programming stage, corresponding to a pulse width of 2; when the programming voltage reaches 8V, the pulse stages with a programming voltage in the range of 5V to 8V are divided into the same programming stage, corresponding to a pulse width of 3.

[0143] It should be noted that the above division method of the programming stage is only an illustrative example, and the embodiments of the present application do not limit this.

[0144] Second, the magnitude of the pulse width of the pulse stage is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0145] That is, during the programming of ISPP, each Loop uses a different pulse width, and as the programming voltage increases during the ISPP programming process, the pulse width gradually decreases.

[0146] Illustratively, Loop1, Loop2, and Loop3 are three consecutive pulse stages. Among them, Loop1 corresponds to the programming voltage Vpp1, Loop2 corresponds to the programming voltage Vpp2, Loop3 corresponds to the programming voltage Vpp3, the difference between Vpp2 and Vpp1 is ΔVpp1, and the difference between Vpp3 and Vpp2 is ΔVpp2. Then, the pulse width 1 corresponding to Loop1 is greater than the pulse width 2 corresponding to Loop2, and the pulse width 2 corresponding to Loop2 is greater than the pulse width 3 corresponding to Loop3.

[0147] In some embodiments, as the pulse stage changes, the pulse width decreases in a stepwise manner. For example, Loop1 corresponds to the pulse width 1, Loop2 corresponds to the pulse width 2, and Loop3 corresponds to the pulse width 3. Among them, the difference between the pulse width 1 and the pulse width 2 is the preset pulse width difference; the difference between the pulse width 2 and the pulse width 3 is the preset pulse width difference.

[0148] In other embodiments, as the pulse stage changes, the pulse width decreases linearly. For example, Loop1 corresponds to the pulse width 1, Loop2 corresponds to the pulse width 2, and Loop3 corresponds to the pulse width 3. Among them, the pulse width 2 is half of the pulse width 1, and the pulse width 3 is half of the pulse width 2.

[0149] To sum up, the method provided in the embodiment of the present application adopts different pulse bandwidths in different pulse stages during the programming process, and programming is performed using the corresponding pulse bandwidth according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth can be used to ensure sufficient programming time; when the programming voltage is large, a shorter pulse bandwidth is used to increase the boosting potential and reduce the margin loss caused by programming voltage interference.

[0150] The method provided in this embodiment divides the pulse stage in the programming process into different programming stages by dividing the programming stage in the programming process. Different programming stages correspond to different pulse widths, so that the pulse width corresponding to the pulse stage is determined based on the programming stage. The programming stages are divided according to the sequence of the programming process, so that the pulse width in the early stage of the programming process is controlled to be larger, the pulse width in the middle stage is moderate, and the pulse width in the late stage is smaller, thereby improving programming efficiency.

[0151] The method provided in this embodiment determines the negative correlation between the pulse width and the programming voltage during the programming process, and adaptively adjusts the pulse width according to the real-time changes of the programming voltage, thereby applying the programming voltage with a corresponding appropriate pulse width, thereby improving the adaptability between the pulse width and the programming voltage, thereby improving programming efficiency.

[0152] In the method provided in this embodiment, in the first few pulse stages / low programming states of the programming process, the PGM voltage is relatively low, and a relatively long pulse width is used to ensure sufficient programming time. If the pulse width is relatively small, the effective programming efficiency is relatively low, and the number of programming pulses increases, resulting in lower programming efficiency. In the intermediate pulse stages / intermediate programming states, a moderate PGM pulse width is used. In the last few pulse stages / high programming states, programming disturbance is mainly caused by Fowler-Nordheim tunneling (FN). The programming voltage is relatively large, requiring a relatively high channel potential. A relatively short pulse width can be used to increase the boosting potential and reduce the loss caused by PGMdisturb.

[0153] In the embodiment of the present application, the programming process includes at least three pulse stages as an example for explanation. Figure 9 As shown in the above Figure 3 After step 302, the following steps are further included:

[0154] Step 303: In a third pulse phase, a third programming voltage is applied to the selected word line with a third pulse width.

[0155] Among them, taking the ISPP programming method as an example, the second pulse stage is temporally prior to the third pulse stage, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

[0156] I. The programming process is divided into at least three programming stages, including a first programming stage, a second programming stage, and a third programming stage arranged in sequence. The first pulse stage is within the first programming stage, and a first programming voltage is applied to the selected word line; the second pulse stage is within the second programming stage, and a second programming voltage is applied to the selected word line; the third pulse stage is within the third programming stage, and a third programming voltage is applied to the selected word line. The pulse stage in the first programming stage corresponds to a first pulse width, the pulse stage in the second programming stage corresponds to a second pulse width, and the pulse stage in the third programming stage corresponds to a third pulse width.

[0157] Among them, the first pulse width is greater than the second pulse width, and the second pulse width is greater than the third pulse width; the first programming voltage is less than the second programming voltage, and the second programming voltage is less than the third programming voltage.

[0158] II. The first pulse stage, the second pulse stage, and the third pulse stage are three pulse stages in the programming process in order of time from the earliest to the latest. These three pulse stages may be continuous or discontinuous, and the programming voltages applied in the pulse stages increase in sequence with the time sequence. That is, the first programming voltage applied in the first pulse stage is less than the second programming voltage applied in the second pulse stage, and the second programming voltage applied in the second pulse stage is less than the third programming voltage applied in the third pulse stage. Among them, the magnitude of the programming voltage has an inverse correlation with the magnitude of the pulse width, so the first pulse width in the first pulse stage is greater than the second pulse width in the second pulse stage, and the second pulse width in the second pulse stage is greater than the third pulse width in the third pulse stage.

[0159] In summary, the method provided by the embodiment of the present application uses different pulse bandwidths in three pulse stages during the programming process, and performs programming according to the corresponding pulse bandwidth according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth is used to ensure sufficient programming duration; when the programming voltage is high, a shorter pulse bandwidth is used to improve the boosting potential and reduce the margin loss caused by programming voltage interference.

[0160] In an optional embodiment, the first programming voltage and / or the second programming voltage is a programming voltage with a changing trend during the pulse stage.

[0161] That is, the first programming voltage corresponds to a first initial programming voltage at the initial moment of the first pulse stage, and the first programming voltage corresponds to a first termination programming voltage at the termination moment of the first pulse stage, and the first initial programming voltage is less than the first termination programming voltage;

[0162] The second programming voltage corresponds to a second initial programming voltage at the initial moment of the second pulse stage, and the second programming voltage corresponds to a second termination programming voltage at the termination moment of the second pulse stage, and the second initial programming voltage is less than the second termination programming voltage.

[0163] Optionally, the difference between the first termination programming voltage and the first initial programming voltage is a first voltage difference; the difference between the second termination programming voltage and the second initial programming voltage is a second voltage difference; the first voltage difference is greater than the second voltage difference.

[0164] When there is a third programming voltage, the third initial programming voltage of the third programming voltage at the initial moment of the third pulse stage is less than the third termination programming voltage of the third programming voltage at the termination moment of the third pulse stage.

[0165] Optionally, the difference between the third termination programming voltage and the third initial programming voltage is a third voltage difference; the second voltage difference is greater than the third voltage difference.

[0166] Wherein, the change mode of the programming voltage with a changing trend includes at least one of the following modes:

[0167] 1. The first programming voltage and / or the second programming voltage shows a stepwise increasing trend in the pulse stage; that is, the first programming voltage shows a stepwise increasing trend in the first pulse stage, and the second programming voltage shows a stepwise increasing trend in the second pulse stage;

[0168] 2. The first programming voltage and / or the second programming voltage shows a linear increasing trend in the pulse stage; that is, the first programming voltage shows a linear increasing trend in the first pulse stage, and the second programming voltage shows a linear increasing trend in the second pulse stage.

[0169] That is, the first programming voltage shows a stepwise increasing trend in the first pulse stage; or, the first programming voltage shows a linear increasing trend in the first pulse stage.

[0170] The second programming voltage shows a stepwise increasing trend in the second pulse stage; or, the second programming voltage shows a linear increasing trend in the second pulse stage.

[0171] Wherein, the change mode of the first programming voltage is the same as or different from the change mode of the second programming voltage. That is, the first programming voltage shows one of the stepwise increasing trend or the linear increasing trend in the first pulse stage, and the second programming voltage shows the other of the stepwise increasing trend or the linear increasing trend in the second pulse stage.

[0172] In some embodiments, when there is a third programming voltage, the third programming voltage shows a stepwise increasing trend during the third pulse stage; alternatively, the third programming voltage shows a linear increasing trend during the third pulse stage.

[0173] The linear increasing trend and the stepwise increasing trend will be described separately.

[0174] Linear increasing trend:

[0175] Optionally, on the basis of controlling the pulse widths of each pulse stage during the programming process, the programming voltage is in a "triangle peak" shape during one pulse stage, that is, the programming voltage shows an increasing trend during the effective programming process of one pulse stage.

[0176] Optionally, the voltage difference △Vpgm of the rising voltage of the programming voltage during the pulse stage can be controlled separately for different pulse stages. Among them, the voltage difference △Vpgm of the rising voltage is the difference between the maximum voltage and the minimum voltage during the effective programming process of the programming voltage during the pulse stage.

[0177] Illustratively, in the embodiments of the present application, taking the programming process being sequentially divided into three programming stages: the first programming stage, the second programming stage, and the third programming stage as an example for description, the three programming stages are arranged in chronological order. Among them, the first programming stage includes a first pulse stage, and the first programming voltage of the first pulse stage corresponds to the first pulse width; the second programming stage includes a second pulse stage, and the second programming voltage of the second pulse stage corresponds to the second pulse width; the third programming stage includes a third pulse stage, and the third programming voltage of the third pulse stage corresponds to the third pulse width.

[0178] Among them, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, and the second pulse width is greater than the third pulse width.

[0179] In some embodiments, taking the first programming stage as an example for description, the voltage differences of the rising voltages corresponding to each pulse stage within the first programming stage are the same or different. When the voltage differences of the rising voltages corresponding to each pulse stage within the first programming stage are different, the voltage difference of the rising voltage decreases one by one according to the chronological order of the pulse stages; alternatively, the voltage differences of the rising voltages of each pulse stage are reduced in batches within the first programming stage. For example: the first programming stage includes 5 pulse stages. Among them, the voltage differences of the rising voltages corresponding to the first pulse stage and the second pulse stage are 1, the voltage differences of the rising voltages corresponding to the third pulse stage and the fourth pulse stage are 2, and the voltage difference of the rising voltage corresponding to the fifth pulse stage is 3. Among them, the voltage difference 1 is greater than the voltage difference 2, and the voltage difference 2 is greater than the voltage difference 3. The embodiments of the present application do not limit this.

[0180] Illustratively, please refer to Figure 10, which shows a schematic diagram of the linear rise of the programming voltage provided by an exemplary embodiment of the present application. As Figure 10 shown, the programming process is divided into three programming stages, namely the first programming stage 1010, the second programming stage 1020, and the third programming stage 1030.

[0181] Among them, for the first pulse stage in the first programming stage 1010, a first programming voltage with a linearly increasing trend is applied to the selected word line during the first pulse stage. As Figure 10 shown, during the effective programming process in the first pulse stage, the first programming voltage shows a linear rising trend, and the rising trend of the first programming voltage continues over the first pulse bandwidth. Optionally, the effective programming process refers to the part in the first pulse stage except for the intermediate voltage and the transition voltage, and this effective programming process includes the first pulse bandwidth part of the first programming voltage. Among them, the rising voltage difference of the first programming voltage in the first pulse bandwidth part is △Vpgm1.

[0182] For the second pulse stage in the second programming stage 1020, a second programming voltage with a linearly increasing trend is applied to the selected word line during the second pulse stage. As Figure 10 shown, during the effective programming process in the second pulse stage, the second programming voltage shows a linear rising trend, and the rising trend of the second programming voltage continues over the second pulse bandwidth. Optionally, this effective programming process includes the second pulse bandwidth part of the second programming voltage. Among them, the rising voltage difference of the second programming voltage in the second pulse bandwidth part is △Vpgm2.

[0183] For the third pulse stage in the third programming stage 1030, a third programming voltage with a linearly increasing trend is applied to the selected word line during the third pulse stage. As Figure 10 shown, during the effective programming process in the third pulse stage, the third programming voltage shows a linear rising trend, and the rising trend of the third programming voltage continues over the third pulse bandwidth. Optionally, this effective programming process includes the third pulse bandwidth part of the third programming voltage. Among them, the rising voltage difference of the third programming voltage in the third pulse bandwidth part is △Vpgm3.

[0184] Among them, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, the second pulse width is greater than the third pulse width, and △Vpgm1 is greater than △Vpgm2, and △Vpgm2 is greater than △Vpgm3.

[0185] Among them, since the above-mentioned first programming voltage, second programming voltage, and third programming voltage are all programming voltages showing an upward trend, taking the first programming voltage being lower than the second programming voltage as an example for illustration, the first programming voltage being lower than the second programming voltage means that the programming voltage at the start time of the first programming voltage is lower than the programming voltage at the start time of the second programming voltage; or, the programming voltage at the end time of the first programming voltage is lower than the programming voltage at the end time of the second programming voltage; or, the programming voltage at the start time of the first programming voltage is lower than the programming voltage at the end time of the second programming voltage; or, the programming voltage at the end time of the first programming voltage is lower than the programming voltage at the start time of the second programming voltage. This embodiment does not limit this.

[0186] It should be noted that in the above embodiment, taking the first programming voltage, second programming voltage, and third programming voltage all showing a linear upward trend as an example for illustration, in some embodiments, there may be a programming voltage that remains stable among the first programming voltage, second programming voltage, and third programming voltage; or there may be a programming voltage showing a gradient upward trend among the first programming voltage, second programming voltage, and third programming voltage. This application embodiment does not limit this.

[0187] In addition, in the above embodiment, taking the rising form of the three programming voltages and the pressure difference relationship between the three programming voltages as an example for illustration, in this embodiment, the pressure difference of the above programming voltage decreases with the decrease of the pulse width, and it can also be realized among more pulse stages with the same or different pulse widths.

[0188] To sum up, in the first few pulse stages / low programming states during the programming process, the PGM voltage is relatively low, and a relatively long pulse width is used to ensure sufficient programming time. However, in the case of a relatively low PGM voltage, the programming efficiency is relatively low. If a relatively high programming voltage is used, it will cause over-programming (Overpgm). Therefore, the programming voltage gradually increases in a pulse stage, greatly improving the effective programming rate on the basis of ensuring no Overpgm;

[0189] In the intermediate pulse stage / intermediate programming state, a moderate PGM pulse width is used, and △Vpgm2 < △Vpgm1;

[0190] In the last few pulse stages / high programming states, the programming voltage is relatively large. When the programming voltage shows an upward trend, it will further increase the boosting potential, thereby reducing the margin loss caused by programming interference. Among them, △Vpgm3 < △Vpgm2, otherwise over-programming will occur and cause margin loss.

[0191] Stepwise increasing trend:

[0192] Based on controlling the pulse widths of each pulse stage during the programming process, the programming voltage is in a "step" shape during a pulse stage, that is, the programming voltage rises in a step-by-step manner during the effective programming process of a pulse stage.

[0193] Optionally, the programming voltage rises in two steps during a pulse stage, that is, the programming voltage first reaches the programming voltage at the initial moment during a pulse stage, and then after a certain time, it rises to the programming voltage at the termination moment until the pulse width is reached; or, the programming voltage rises in multiple steps more than two steps during a pulse stage. First, the programming voltage reaches the programming voltage at the initial moment during a pulse stage, and then every certain time, the current programming voltage is raised to a certain value until the programming voltage at the termination moment is reached, and finally the pulse width is reached.

[0194] Optionally, the voltage difference △Vpgm of the rising voltage of the programming voltage during the pulse stage can be controlled separately for different pulse stages. Among them, the voltage difference △Vpgm of the rising voltage is the difference between the maximum voltage and the minimum voltage during the effective programming process of the programming voltage in the pulse stage.

[0195] Schematically, in the embodiments of the present application, taking the programming process being sequentially divided into three programming stages: the first programming stage, the second programming stage, and the third programming stage as an example for illustration. The three programming stages are arranged in sequence. Among them, the first programming stage includes a first pulse stage, and the first programming voltage of the first pulse stage corresponds to the first pulse width; the second programming stage includes a second pulse stage, and the second programming voltage of the second pulse stage corresponds to the second pulse width; the third programming stage includes a third pulse stage, and the third programming voltage of the third pulse stage corresponds to the third pulse width.

[0196] Among them, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, and the second pulse width is greater than the third pulse width.

[0197] In some embodiments, taking the first programming stage as an example for illustration, the voltage differences of the rising voltages corresponding to each pulse stage within the first programming stage are the same or different. When the voltage differences of the rising voltages corresponding to each pulse stage within the first programming stage are different, the voltage difference of the rising voltage decreases one by one according to the sequential sorting of the pulse stages; or, the voltage differences of the rising voltages of each pulse stage are reduced in batches within the first programming stage. For example, the first programming stage includes 5 pulse stages. Among them, the voltage differences of the rising voltages corresponding to the first pulse stage and the second pulse stage are 1, the voltage differences of the rising voltages corresponding to the third pulse stage and the fourth pulse stage are 2, and the voltage difference of the rising voltage corresponding to the fifth pulse stage is 3. Among them, the voltage difference 1 is greater than the voltage difference 2, and the voltage difference 2 is greater than the voltage difference 3. The embodiments of the present application do not limit this.

[0198] Schematic. Please refer to Figure 11 , which shows a schematic diagram of the linear increase of the programming voltage provided by an exemplary embodiment of the present application. Among them, taking the two-step increase method as an example, the stepped increasing trend is schematically shown. As Figure 11 shown, the programming process is divided into three programming stages, namely the first programming stage 1110, the second programming stage 1120, and the third programming stage 1130.

[0199] Among them, for the first pulse stage in the first programming stage 1110, a first programming voltage with a two-step gradient increasing trend is applied to the selected word line during the first pulse stage. As Figure 11 shown, during the effective programming process in the first pulse stage, the first programming voltage first reaches a first initial voltage value, and then, within a certain duration, such as: half of the first pulse bandwidth or close to half of the first pulse bandwidth, it rises from the initial voltage value to the first boosting voltage value and is applied until the first pulse bandwidth is reached. Optionally, the effective programming process refers to the part except the intermediate voltage and the transition voltage within the first pulse stage, and this effective programming process includes the first pulse bandwidth part of the first programming voltage. Among them, the rising voltage difference of the first programming voltage in the first pulse bandwidth part is △Vpgm1.

[0200] For the second pulse stage in the second programming stage 1120, a second programming voltage with a two-step gradient increasing trend is applied to the selected word line during the second pulse stage. As Figure 11 shown, during the effective programming process in the second pulse stage, the second programming voltage first reaches a second initial voltage value, and then, within a certain duration, such as: half of the second pulse bandwidth or close to half of the second pulse bandwidth, it rises from the initial voltage value to the second boosting voltage value and is applied until the second pulse bandwidth is reached. Optionally, the effective programming process refers to the part except the intermediate voltage and the transition voltage within the second pulse stage, and this effective programming process includes the second pulse bandwidth part of the second programming voltage. Among them, the rising voltage difference of the second programming voltage in the second pulse bandwidth part is △Vpgm2.

[0201] For the third pulse stage in the third programming stage 1130, a third programming voltage with a two-step gradient increasing trend is applied to the selected word line during the third pulse stage. As Figure 11As shown, during the effective programming process in the third pulse stage, the third programming voltage first reaches a third initial voltage value, and then, within a certain duration, such as half of the third pulse bandwidth or close to half of the third pulse bandwidth, it is increased from the initial voltage value to the third increased voltage value and applied until the third pulse bandwidth is reached. Optionally, the effective programming process refers to the part in the third pulse stage other than the intermediate voltage and the transition voltage, and this effective programming process includes the third pulse bandwidth part of the third programming voltage. Among them, the rising voltage difference of the third programming voltage in the third pulse bandwidth part is ΔVpgm3.

[0202] Among them, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, the second pulse width is greater than the third pulse width, and ΔVpgm1 is greater than ΔVpgm2, and ΔVpgm2 is greater than ΔVpgm3.

[0203] Among them, since the above-mentioned first programming voltage, second programming voltage, and third programming voltage are all programming voltages with an upward trend, taking the first programming voltage being lower than the second programming voltage as an example for illustration, the first programming voltage being lower than the second programming voltage means that the programming voltage at the starting moment of the first programming voltage is lower than the programming voltage at the starting moment of the second programming voltage; or, the programming voltage at the ending moment of the first programming voltage is lower than the programming voltage at the ending moment of the second programming voltage; or, the programming voltage at the starting moment of the first programming voltage is lower than the programming voltage at the ending moment of the second programming voltage; or, the programming voltage at the ending moment of the first programming voltage is lower than the programming voltage at the starting moment of the second programming voltage; or, when the first programming voltage and the second programming voltage are realized as three-step or multi-step rising voltages, the intermediate step programming voltage of the first programming voltage is lower than the intermediate step programming voltage of the second programming voltage, for example: the second step programming voltage in the first programming voltage is lower than the second step programming voltage in the second programming voltage. This embodiment does not limit this.

[0204] It should be noted that in the above-mentioned embodiments, taking the first programming voltage, the second programming voltage, and the third programming voltage all having a stepped upward trend as an example for illustration, in some embodiments, there may be a programming voltage that remains stable among the first programming voltage, the second programming voltage, and the third programming voltage; or there may be a programming voltage with a linear upward trend among the first programming voltage, the second programming voltage, and the third programming voltage. This application embodiment does not limit this.

[0205] In addition, in the above-mentioned embodiments, taking the rising forms of the three programming voltages and the voltage difference relationship between the three programming voltages as an example for illustration, in this embodiment, the voltage difference of the above-mentioned programming voltage decreases with the decrease of the pulse width, and it can also be realized among more pulse stages with the same or different pulse widths.

[0206] In summary, during the first few pulse stages / low programming state of the programming process, the PGM voltage is relatively low, and a relatively long pulse width is used to ensure sufficient programming time. However, when the PGM voltage is relatively low, the programming efficiency is relatively low. If a relatively high programming voltage is used, it will cause over-programming (Overpgm). Therefore, the programming voltage is stepped up in a single pulse stage, which greatly improves the effective programming rate on the basis of ensuring no Overpgm.

[0207] During the middle pulse stage / middle programming state, a moderate PGM pulse width is used, and △Vpgm2 < △Vpgm1.

[0208] During the last few pulse stages / high programming state, the programming voltage is relatively large. When the programming voltage shows an upward trend, it will further increase the boosting potential, thereby reducing the margin loss caused by programming interference. Among them, △Vpgm3 < △Vpgm2, otherwise over-programming will occur and cause margin loss.

[0209] Figure 12 It is a schematic structural diagram of a memory provided by an embodiment of the present application. As Figure 12 shown, the memory includes a peripheral circuit 1200 and a memory cell array 1210;

[0210] The peripheral circuit 1200 is used to write data into the memory cell array 1210 and read data from the memory cell array 1210.

[0211] The peripheral circuit 1200 includes: a voltage generator 1202, a page buffer / sense amplifier 1204, a column decoder / bit line (BL) driver / 1206, a row decoder / word line (WL) driver 1208, a peripheral logic unit 1212, a register 1214, an input / output circuit 1216, and a data bus 1218. It should be understood that in some examples, additional peripheral circuits not shown Figure 12 in may also be included.

[0212] The page buffer / sense amplifier 1204 can be configured to read data from the memory cell array 1210 and program (write) data to the memory cell array 1210 according to control signals from the peripheral logic unit 1212. In one example, the page buffer / sense amplifier 1204 can store a page of programming data (write data) to be programmed into a page in the memory cell array 1210. In another example, the page buffer / sense amplifier 1204 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cells coupled to the selected word line. In yet another example, the page buffer / sense amplifier 1204 can also sense a low-power signal from the bit line representing the data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level during a read operation.

[0213] The column decoder / bit line driver 1206 can be configured to be controlled by the peripheral logic unit 1212 and select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 1202.

[0214] The row decoder / word line driver 1208 can be configured to be controlled by the peripheral logic unit 1212, select / deselect the blocks of the memory cell array 1210, and select / deselect the word lines of the blocks. The row decoder / word line driver 1208 can also be configured to drive the word lines using the word line voltage (V WL ) generated from the voltage generator 1202. In some embodiments, the row decoder / word line driver 1208 can also select / deselect and drive the source select gate line and the drain select gate line. Schematically, the row decoder / word line driver 1208 is configured to perform an erase operation on the memory cells coupled to the selected word line(s).

[0215] The voltage generator 1202 can be configured to be controlled by the peripheral logic unit 1212 and generate the word line voltage (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltage, and source line voltage to be supplied to the memory cell array 1210.

[0216] The peripheral logic unit 1212 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The control circuit as shown above is included in the peripheral logic unit 1212. Figure 12 shown.

[0217] Register 1214 can be coupled to the peripheral logic unit 1212 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. The input / output circuit 1216 can be coupled to the peripheral logic unit 1212 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to the peripheral logic unit 1212, and buffer status information received from the peripheral logic unit 1212 and relay it to the host. The input / output circuit 1216 can also be coupled to the column decoder / bit line driver 1206 via the data bus 1218 and acts as a data input / output interface and a data buffer to buffer data and relay it to or from the memory cell array 1210.

[0218] It should be emphasized that the peripheral circuit 1200 is configured to perform the programming method of the memory provided by the embodiments of the present disclosure on a selected memory cell row among multiple memory cell rows.

[0219] Figure 13 is a structural block diagram of a storage system provided by an exemplary embodiment of the present application, as Figure 13 shown, the storage system 1300 includes: one or more memories 1310, and

[0220] a memory controller 1320 coupled to the memory 1310 and configured to control the memory 1310.

[0221] The storage system 1300 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage.

[0222] Optionally, the storage system 1300 can include a host and a storage subsystem having one or more memories 1310 and a memory controller 1320. The host can be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host can be configured to send data to the memory 1310. Alternatively, the host can be configured to receive data from the memory 1310.

[0223] According to some embodiments, the memory controller 1320 is also coupled to the host. The memory controller 1320 can manage the data stored in the memory 1310 and communicate with the host.

[0224] In some embodiments, the memory controller 1320 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0225] In some embodiments, the memory controller 1320 is designed to operate in a high duty cycle environment such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), which are used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0226] The memory controller 1320 may be configured to control the operations of the memory 1310, such as read, erase, and program operations. The memory controller 1320 may also be configured to manage various functions regarding the data stored in or to be stored in the memory 1310, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1320 is also configured to process the Error Correction Code (ECC) for the data read from or written to the memory 1310.

[0227] The memory controller 1320 may also perform any other suitable functions, such as formatting the memory 1310. The memory controller 1320 may communicate with external devices according to a specific communication protocol.

[0228] The memory controller 1320 and one or more memories 1310 may be integrated into various types of storage devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 1300 may be implemented and packaged into different types of terminal electronic products.

[0229] Schematically, the memory controller 1320 and a single memory 1310 may be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card may also include a memory card connector for coupling the memory card to a host.

[0230] Schematically, the memory controller 1320 and the multiple memories 1310 can be integrated into a solid state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the solid state drive are greater than those of the memory card.

[0231] It can be understood that the memory controller 1320 can execute the memory programming method provided in any embodiment of the present disclosure.

[0232] An embodiment of the present application provides a control circuit, which includes a programmable logic circuit and / or program instructions, and the control circuit can be used to implement the memory programming method provided in the foregoing embodiments of the present application.

[0233] Schematically, as Figure 13 shown, the memory 1310 includes: a storage array unit and a peripheral logic unit. The storage array unit includes memory strings, and the memory strings include memory cells. The peripheral logic unit includes a control circuit;

[0234] The control circuit is configured to apply a first programming voltage to a selected word line with a first pulse width in a first pulse stage; and apply a second programming voltage to the selected word line with a second pulse width in a second pulse stage;

[0235] The first pulse stage and the second pulse stage are two pulse stages among multiple pulse stages for programming a selected memory cell. The selected memory cell is a memory cell to be programmed, and the selected word line is the word line connected to the selected memory cell;

[0236] The selected memory cell is programmed using a stepped pulse voltage programming method. The first pulse stage is prior to the second pulse stage in timing, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage.

[0237] In an alternative embodiment, the multiple pulse stages are divided into a first programming stage and a second programming stage;

[0238] The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage;

[0239] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

[0240] In an alternative embodiment, the first programming stage includes a first number of pulse stages arranged in series, and the second programming stage includes a second number of pulse stages arranged in series;

[0241] Alternatively,

[0242] the programming voltage of each pulse stage in the first programming stage is less than the stage voltage threshold, and the programming voltage of each pulse stage in the second programming stage is greater than the stage voltage threshold.

[0243] In an alternative embodiment, the magnitude of the pulse width of the pulse stage is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0244] In an alternative embodiment, the first programming voltage corresponds to a first initial programming voltage at the initial moment of the first pulse stage, and the first programming voltage corresponds to a first termination programming voltage at the termination moment of the first pulse stage, and the first initial programming voltage is less than the first termination programming voltage;

[0245] the second programming voltage corresponds to a second initial programming voltage at the initial moment of the second pulse stage, and the second programming voltage corresponds to a second termination programming voltage at the termination moment of the second pulse stage, and the second initial programming voltage is less than the second termination programming voltage.

[0246] In an alternative embodiment, the difference between the first termination programming voltage and the first initial programming voltage is a first voltage difference;

[0247] the difference between the second termination programming voltage and the second initial programming voltage is a second voltage difference;

[0248] the first voltage difference is greater than the second voltage difference.

[0249] In an alternative embodiment, the first programming voltage shows a stepwise increasing trend during the first pulse stage and the second programming voltage shows a stepwise increasing trend during the second pulse stage;

[0250] Alternatively,

[0251] both the first programming voltage and the second programming voltage show a linear increasing trend during the pulse stage;

[0252] Alternatively,

[0253] the first programming voltage shows either a stepwise increasing trend or a linear increasing trend during the first pulse stage, and the second programming voltage shows the other of the stepwise increasing trend or the linear increasing trend during the second pulse stage.

[0254] In an optional embodiment, the control circuit is further configured to apply a third programming voltage to the selected word line with a third pulse width during a third pulse stage;

[0255] wherein, the second pulse stage is temporally prior to the third pulse stage, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

[0256] In summary, the memory provided by the embodiments of the present application uses different pulse bandwidths during three pulse stages respectively during the programming process, and performs programming with the corresponding pulse bandwidth according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth is used to ensure sufficient programming duration; while when the programming voltage is high, a shorter pulse bandwidth is used to increase the boosting potential and reduce the margin loss caused by programming voltage interference.

[0257] The embodiments of the present application provide a computer-readable storage medium, in which instructions are stored, and when the instructions run on a control circuit, they implement the programming method of the memory provided by the foregoing embodiments of the present application.

[0258] In the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "a plurality" means two or more, unless otherwise clearly defined.

[0259] The term "and / or" in the present application is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0260] The above are only exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A programming method for a memory, characterized in that, The method includes: Applying a first programming voltage to a selected word line with a first pulse width in a first pulse stage; Applying a second programming voltage to the selected word line with a second pulse width in a second pulse stage; The first pulse stage and the second pulse stage are two of a plurality of pulse stages for programming a selected memory cell, the selected memory cell is a memory cell to be programmed, and the selected word line is a word line connected to the selected memory cell; The selected memory cell is programmed by a stepped pulse voltage programming method. The first pulse stage is prior to the second pulse stage in timing, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage; The first programming voltage corresponds to a first initial programming voltage at the initial moment of the first pulse stage, and the first programming voltage corresponds to a first termination programming voltage at the termination moment of the first pulse stage. The first initial programming voltage is less than the first termination programming voltage; the second programming voltage corresponds to a second initial programming voltage at the initial moment of the second pulse stage, and the second programming voltage corresponds to a second termination programming voltage at the termination moment of the second pulse stage. The second initial programming voltage is less than the second termination programming voltage; the voltage difference between the first termination programming voltage and the first initial programming voltage is greater than the voltage difference between the second termination programming voltage and the second initial programming voltage.

2. The method according to claim 1, wherein The plurality of pulse stages are divided into a first programming stage and a second programming stage; The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage; The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

3. The method according to claim 2, wherein The first programming stage includes a first number of pulse stages arranged continuously, and the second programming stage includes a second number of pulse stages arranged continuously; Or, The programming voltage of each pulse stage in the first programming stage is less than a stage voltage threshold, and the programming voltage of each pulse stage in the second programming stage is greater than the stage voltage threshold.

4. The method according to claim 1, wherein The magnitude of the pulse width of the pulse stage is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

5. The method according to any one of claims 1 to 4, wherein The first programming voltage shows a stepped increasing trend in the first pulse stage and the second programming voltage shows a stepped increasing trend in the second pulse stage; Or, Both the first programming voltage and the second programming voltage show a linear increasing trend in the pulse stage; Or, The first programming voltage shows either a stepped increasing trend or a linear increasing trend in the first pulse stage, and the second programming voltage shows the other of a stepped increasing trend or a linear increasing trend in the second pulse stage.

6. The method according to any one of claims 1 to 4, characterized in that, The method further includes: In a third pulse stage, applying a third programming voltage to the selected word line with a third pulse width; Wherein, the second pulse stage is temporally prior to the third pulse stage, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

7. A memory, characterized in that, The memory includes: a storage array unit and a peripheral logic unit, and the peripheral logic unit includes a control circuit; The control circuit is configured to apply a first programming voltage to the selected word line with a first pulse width in a first pulse stage; and apply a second programming voltage to the selected word line with a second pulse width in a second pulse stage; The first pulse stage and the second pulse stage are two of multiple pulse stages for programming a selected memory cell, the selected memory cell is a memory cell to be programmed, and the selected word line is a word line connected to the selected memory cell; The selected memory cell is programmed using a stepped pulse voltage programming method, the first pulse stage is temporally prior to the second pulse stage, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage; The first programming voltage corresponds to a first initial programming voltage at the initial moment of the first pulse stage, and the first programming voltage corresponds to a first termination programming voltage at the termination moment of the first pulse stage, and the first initial programming voltage is less than the first termination programming voltage; the second programming voltage corresponds to a second initial programming voltage at the initial moment of the second pulse stage, and the second programming voltage corresponds to a second termination programming voltage at the termination moment of the second pulse stage, and the second initial programming voltage is less than the second termination programming voltage; the voltage difference between the first termination programming voltage and the first initial programming voltage is greater than the voltage difference between the second termination programming voltage and the second initial programming voltage.

8. The memory according to claim 7, wherein The multiple pulse stages are divided into a first programming stage and a second programming stage; The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage; The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

9. The memory according to claim 8, wherein The first programming stage includes a preset number of pulse stages arranged in sequence, and the second programming stage includes a preset number of pulse stages arranged in sequence; Or, The programming voltage of each pulse stage in the first programming stage is less than a stage voltage threshold, and the programming voltage of each pulse stage in the second programming stage is greater than the stage voltage threshold.

10. The memory according to claim 7, wherein The magnitude of the pulse width of the pulse stage is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

11. The memory according to any one of claims 7 to 10, wherein The first programming voltage shows a stepwise increasing trend during the first pulse phase, and the second programming voltage shows a stepwise increasing trend during the second pulse phase; Or, Both the first programming voltage and the second programming voltage show a linear increasing trend during the pulse phase; Or, The first programming voltage shows one of a stepwise increasing trend or a linear increasing trend during the first pulse phase, and the second programming voltage shows the other of a stepwise increasing trend or a linear increasing trend during the second pulse phase.

12. The memory according to any one of claims 7 to 10, characterized in that, The control circuit is further configured to apply a third programming voltage to the selected word line with a third pulse width during a third pulse phase; Wherein, the second pulse phase is temporally prior to the third pulse phase, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

13. A storage system, characterized in that, The storage system includes: One or more memories as claimed in any one of claims 7 to 12, and, A memory controller coupled to the memory and configured to control the memory.

14. A computer-readable storage medium, characterized in that, Instructions are stored in the computer-readable storage medium, and when the instructions run on the control circuit, a programming method of the memory as claimed in any one of claims 1 to 6 is implemented.

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