semiconductor memory devices

Abstract

One embodiment of the present invention provides a semiconductor memory device that can suppress a decrease in write speed and improve data reliability. The semiconductor memory device of one embodiment includes multiple memory cell transistors, a word line, multiple bit lines, and a controller. The word line is connected to the multiple memory cell transistors. The multiple bit lines are respectively connected to the multiple memory cell transistors. The controller performs a write operation that repeatedly performs a programming loop including a programming operation and a verification operation. During the verification operation of the first data, while applying a verification high voltage of the first data to the word line, the controller determines whether the memory cell transistor for writing the first data exceeds the verification high voltage of the first data, and determines whether the memory cell transistor for writing the second data exceeds the verification low voltage of the second data.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-208454 (filing date: December 16, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor memory device. Background Art

[0004] A NAND (Not And) type flash memory capable of storing data in a nonvolatile manner is known. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor memory device capable of suppressing a decrease in write speed and improving data reliability.

[0006] A semiconductor memory device according to one embodiment includes a plurality of memory cell transistors, a word line, a plurality of bit lines, and a controller. Each of the plurality of memory cell transistors can store multi-bit data depending on which state the threshold voltage belongs to among a plurality of states. The memory cell transistor stores first data when the threshold voltage belongs to the first state. The memory cell transistor stores second data when the threshold voltage belongs to the second state higher than the first state. The word line is connected to the plurality of memory cell transistors. The plurality of bit lines are respectively connected to the plurality of memory cell transistors. The controller performs a write operation that repeatedly performs a programming loop including a programming operation and a verification operation. A verification low voltage and a verification high voltage are set for each of the plurality of states. During the programming operation, while the controller applies a programming voltage to the word line, the controller applies a first voltage to the bit line connected to the memory cell transistor of the first programming target, applies a second voltage higher than the first voltage to the bit line connected to the memory cell transistor of the second programming target, and applies a third voltage higher than the second voltage to the bit line connected to the memory cell transistor that is programming-inhibited. During a verification operation, the controller sets, for each state of a write destination, a memory cell transistor whose threshold voltage is determined to be below the verification low voltage as a first programming target, a memory cell transistor whose threshold voltage is determined to be above the verification low voltage and below the verification high voltage as a second programming target, and a memory cell transistor whose threshold voltage is determined to be above the verification high voltage as program-inhibited. During a verification operation for the first data, while the verification high voltage of the first data is applied to the word line, the controller determines whether the memory cell transistor for writing the first data exceeds the verification high voltage of the first data, and determines whether the memory cell transistor for writing the second data exceeds the verification low voltage of the second data. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing an example of the configuration of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a circuit diagram showing an example of the circuit configuration of a row decoder module included in the semiconductor memory device according to the first embodiment.

[0010] Figure 4 This is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory device according to the first embodiment.

[0011] Figure 5 This is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit included in the sense amplifier module included in the semiconductor memory device according to the first embodiment.

[0012] Figure 6 This is a conceptual diagram showing an example of a data storage method in the semiconductor memory device according to the first embodiment.

[0013] Figure 7 This is a timing chart showing an overview of a write operation of the semiconductor memory device according to the first embodiment.

[0014] Figure 8 This is a table showing an example of settings of a program loop in a write operation of the semiconductor memory device according to the first embodiment.

[0015] Figure 9 (1) and (2) are threshold voltage distribution diagrams showing an example of two verification voltages and two programming methods that can be used for each write state in the write operation of the semiconductor memory device according to the first embodiment.

[0016] Figure 10 This is a timing chart showing an example of a programming operation of the semiconductor memory device according to the first embodiment.

[0017] Figure 11 This is a table showing an example of setting the verification voltage in the write operation of the semiconductor memory device according to the first embodiment.

[0018] Figure 12 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the first embodiment.

[0019] Figure 13 This is a timing chart showing a more detailed example of the verification operation of the semiconductor memory device according to the first embodiment.

[0020] Figure 14 This is a table showing an example of setting the verification voltage in the first modification of the first embodiment.

[0021] Figure 15 This is a table showing an example of setting the verification voltage in the second modification of the first embodiment.

[0022] Figure 16 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the second embodiment.

[0023] Figure 17 (1) and (2) are conceptual diagrams showing an example of the substantial verification voltage in the semiconductor memory device according to the second embodiment.

[0024] Figure 18 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the third embodiment.

[0025] Figure 19 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the fourth embodiment.

[0026] Figure 20 (1) and (2) are conceptual diagrams showing an example of the actual verification voltage in the semiconductor memory device according to the fourth embodiment.

[0027] Figure 21 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the fifth embodiment.

[0028] Figure 22 This is a flowchart showing an example of a programming operation of the semiconductor memory device according to the sixth embodiment.

[0029] Figure 23 This is a flowchart showing an example of programming operations in a variation of the sixth embodiment.

[0030] Figure 24 This is a table showing an example of setting the verification voltage in the write operation of the semiconductor memory device according to the seventh embodiment.

[0031] Figure 25 This is a timing chart showing an example of a write operation of the semiconductor memory device according to the seventh embodiment.

[0032] Figure 26 This is a table showing an example of setting the verification voltage in a modification of the seventh embodiment.

[0033] Figure 27 This is a timing chart showing an example of a verification operation of the semiconductor storage device according to the eighth embodiment.

[0034] Figure 28 (1) and (2) are conceptual diagrams showing an example of the actual verification voltage in the semiconductor memory device according to the eighth embodiment. DETAILED DESCRIPTION

[0035] The following describes the embodiments with reference to the accompanying drawings. Each embodiment exemplifies an apparatus and method for embodying the technical concept of the invention. The drawings are schematic or conceptual. Dimensions and proportions in the drawings may not necessarily correspond to actual objects. The technical concept of the present invention is not determined by the shape, structure, or arrangement of the components.

[0036] In the following description, components having substantially the same function and configuration are denoted by the same reference numerals. The numerals following the characters constituting the reference numerals are used to distinguish components having the same configuration from each other. When it is not necessary to distinguish components denoted by reference numerals containing the same characters, these components are denoted by reference numerals consisting solely of the characters.

[0037] [1] First embodiment

[0038] The semiconductor memory device 1 of the first embodiment is a NAND flash memory capable of storing data in a nonvolatile manner.

[0039] [1-1] Composition

[0040] [1-1-1] Overall Configuration of Semiconductor Memory Device 1

[0041] Figure 1 FIG. 1 shows an example of the configuration of the semiconductor memory device 1 according to the first embodiment. Figure 1 As shown, semiconductor memory device 1 is configured to be controllable by external memory controller 2. Semiconductor memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0042] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Each block BLK includes a collection of memory cells capable of nonvolatile data storage. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines described below. Each memory cell is associated with one bit line and one word line.

[0043] The command register 11 stores the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes instructions for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.

[0044] The address register 12 stores address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. The block address BA, page address PA, and column address CA are associated with a block BLK, a word line, and a bit line, respectively.

[0045] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, based on the command CMD stored in the command register 11, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 to execute read, write, and erase operations.

[0046] The driver module 14 is connected to the row decoder module 15 via a plurality of signal lines, and generates voltages used in read operations, write operations, erase operations, etc. For example, the driver module 14 applies a specified voltage to a signal line connected to a word line selected based on the page address PA stored in the address register 12, and to signal lines connected to other word lines.

[0047] The row decoder module 15 transmits the voltages applied to the plurality of signal lines by the driver module 14 to the memory cell array 10. Furthermore, the row decoder module 15 selects one block BLK associated with the block address BA stored in the address register 12 within the memory cell array 10, and transmits the voltages applied to different signal line groups for the selected block BLK and unselected blocks BLK.

[0048] The sense amplifier module 16 transmits and receives data DAT to and from the memory controller 2 via input and output circuits (not shown). During a write operation, the sense amplifier module 16 applies a voltage corresponding to the write data received from the memory controller 2 to each bit line. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transmits the read data determined based on the determination result to the memory controller 2.

[0049] The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard. For example, input / output signals I / O, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a ready busy signal RBn are used in the communication between the semiconductor memory device 1 and the memory controller 2.

[0050] The input / output signal I / O is, for example, an 8-bit wide signal and may include a command CMD, address information ADD, data DAT, and the like. The command latch enable signal CLE is a signal indicating whether the input / output signal I / O received by the semiconductor memory device 1 is a command CMD. The address latch enable signal ALE is a signal indicating whether the input / output signal I / O received by the semiconductor memory device 1 is address information ADD. The write enable signal WEn is a signal used to instruct the semiconductor memory device 1 to input the input / output signal I / O. The read enable signal REn is a signal used to instruct the semiconductor memory device 1 to output the input / output signal I / O. The ready busy signal RBn is a signal that notifies the memory controller 2 whether the semiconductor memory device 1 is in a ready state or a busy state. The ready state is a state in which the semiconductor memory device 1 can accept commands from the memory controller 2. The busy state is a state in which the semiconductor memory device 1 cannot accept commands from the memory controller 2.

[0051] Furthermore, a semiconductor device may be formed by combining the semiconductor memory device 1 and the memory controller 2. As such a semiconductor device, for example, an SD card may be used. TM Memory cards such as cards, or SSDs (solid state drives).

[0052] [1-1-2] Circuit Configuration of Semiconductor Memory Device 1

[0053] (Circuit Configuration of Memory Cell Array 10)

[0054] Figure 2 1 is a circuit diagram showing an example of a circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment. Figure 2 One block BLK included in the memory cell array 10 is extracted and shown in the figure. Figure 2 As shown, block BLK includes, for example, four string units SU0 to SU3. Block BLK is connected to a plurality of bit lines BL0 to BLm (m is an integer greater than or equal to 1), a plurality of word lines WL0 to WL7, a plurality of select gate lines SGD0 to SGD3, a select gate line SGS, and a source line SL.

[0055] Each string unit SU contains multiple NAND strings NS. Different column addresses are assigned to each of the multiple NAND strings NS. The multiple NAND strings NS within each string unit SU are associated with bit lines BL0 through BLm. Each bit line BL is connected to multiple NAND strings NS assigned the same column address. A set consisting of multiple word lines WL0 through WL7, multiple select gate lines SGD0 through SGD3, and a select gate line SGS is provided for each block BLK. The source line SL is shared by multiple blocks BLK.

[0056] Each NAND string NS includes memory cell transistors MT0-MT7 and select transistors ST1 and ST2. Memory cell transistors MT include a control gate and a charge storage layer, and store data nonvolatilely based on a threshold voltage. Select transistors STD and STS are used to select string cells SU during read, write, and erase operations, respectively.

[0057] In each NAND string NS, memory cell transistors MT0-MT7 are connected in series. The drain of the select transistor STD is connected to its associated bit line BL. The source of the select transistor STD is connected to one end of the series-connected memory cell transistors MT0-MT7. The drain of the select transistor STS is connected to the other end of the series-connected memory cell transistors MT0-MT7. The source of the select transistor STS is connected to the source line SL.

[0058] The control gates of memory cell transistors MT0-MT7 included in the same block BLK are connected to word lines WL0-WL7, respectively. The gate of select transistor STD included in string unit SU0 is connected to select gate line SGD0. The gate of select transistor STD included in string unit SU1 is connected to select gate line SGD1. The gate of select transistor STD included in string unit SU2 is connected to select gate line SGD2. The gate of select transistor STD included in string unit SU3 is connected to select gate line SGD3. The gate of select transistor STS included in the same block BLK is connected to select gate line SGS.

[0059] Hereinafter, the collection of multiple memory cell transistors MT connected to a common word line WL within a string unit SU is referred to as a "unit set CU." For example, the storage capacity of an MT unit set CU, which includes multiple memory cell transistors each storing one bit of data, is defined as "one page of data." The memory cell transistor MT may also have a storage capacity for more than two bits of data. Depending on the number of bits stored by the memory cell transistor MT, the unit set CU may have a storage capacity for more than two pages of data. In the first embodiment, the structure and operation when one memory cell transistor MT stores three bits of data are described.

[0060] Furthermore, the memory cell array 10 may also have other circuit configurations. For example, the number of string units SU included in each block BLK, the number of memory cell transistors MT included in each NAND string NS, and the number of select transistors ST1 and ST2 included in each NAND string NS may also be changed. The NAND string NS may also include one or more dummy transistors. The select gate line SGS may also be provided separately for each string unit SU.

[0061] (Circuit Configuration of Row Decoder Module 15)

[0062] Figure 31 is a circuit diagram showing an example of the circuit configuration of the row decoder module 15 included in the semiconductor memory device 1 according to the first embodiment. Figure 3 As shown, the row decoder module 15 is connected to the driver module 14 via signal lines CG0-CG7, SGDD0-SGDD3, SGSD, USGD, and USGS. Furthermore, the row decoder module 15 includes row decoders RD0-RDn (n is an integer greater than or equal to 1). Row decoders RD0-RDn are associated with blocks BLK0-BLKn, respectively. The following describes the detailed circuit structure of row decoders RD, focusing on row decoder RD0.

[0063] The row decoder RD includes, for example, transistors TR0 to TR17 , transfer gate lines TG and bTG, and a block decoder BD.

[0064] Transistors TR0 through TR17 are each high-voltage N-type MOS (Metal Oxide Semiconductor) transistors. The gates of transistors TR0 through TR12 are connected to a transmission gate line TG. The gates of transistors TR13 through TR17 are connected to a transmission gate line bTG. Furthermore, the drain and source of each transistor TR are connected between any one of the multiple signal lines connected to the driver module 14 and any one of the multiple wiring lines connected to the block BLK associated with the row decoder RD.

[0065] Specifically, the drain of transistor TR0 is connected to signal line SGSD. The source of transistor TR0 is connected to select gate line SGS. The drains of transistors TR1 to TR8 are connected to signal lines CG0 to CG7, respectively. The sources of transistors TR1 to TR8 are connected to word lines WL0 to WL7, respectively. The drains of transistors TR9 to TR12 are connected to signal lines SGDD0 to SGDD3, respectively. The sources of transistors TR9 to TR12 are connected to select gate lines SGD0 to SGD3, respectively. The drain of transistor TR13 is connected to signal line USGS. The source of transistor TR13 is connected to select gate line SGS. The drains of transistors TR14 to TR17 are connected to signal line USGD. The sources of transistors TR14 to TR17 are connected to select gate lines SGD0 to SGD3, respectively.

[0066] The block decoder BD decodes the block address BA. Based on the decoding results, the block decoder BD applies a specific voltage to the transmission gate lines TG and bTG, respectively. The voltage applied to the transmission gate line TG is complementary to the voltage applied to the transmission gate line bTG. In other words, the inverse of the signal applied to the transmission gate line TG is input to the transmission gate line bTG.

[0067] The row decoder module 15 selects a block BLK by inputting a block address BA to each of the block decoders BD in the row decoders RD0 to RDn. For example, when performing a read or write operation, the block decoder BD associated with the selected block BLK applies an "H" level voltage to the transmission gate lines TG and bTG, respectively. On the other hand, the block decoders BD associated with the unselected blocks BLK apply an "L" level voltage to the transmission gate lines TG and bTG, respectively. This allows voltages applied to different signal line groups to be transmitted to the selected block BLK and the unselected blocks BLK.

[0068] In addition, the row decoder module 15 may also be composed of other circuits. For example, the number of transistors TR included in the row decoder module 15 may also be changed according to the number of wiring lines provided in each block BLK. The signal line CG is shared by multiple blocks BLK and can therefore be called a "global word line." The word line WL is provided for each block and can therefore be called a "local word line." The signal lines SGDD and SGSD are shared by multiple blocks BLK and can therefore be called a "global transfer gate line." The select gate lines SGD and SGS are provided for each block and can therefore be called a "local transfer gate line."

[0069] (Circuit Configuration of Sense Amplifier Module 16)

[0070] Figure 4 1 is a circuit diagram showing an example of the circuit configuration of the sense amplifier module 16 included in the semiconductor memory device 1 according to the first embodiment. Figure 4 As shown, the sense amplifier module 16 includes sense amplifier units SAU0 to SAUm (m is an integer greater than or equal to 1). Sense amplifier units SAU0 to SAUm are associated with bit lines BL0 to BLm, respectively. The following describes the detailed circuit configuration of the sense amplifier unit SAU, focusing on sense amplifier unit SAU0.

[0071] The sense amplifier unit SAU includes, for example, a bit line connection unit BLHU, a sense amplifier unit SA, a bus line LBUS, and latch circuits SDL, ADL, BDL, CDL, VLDL, VHDL, and XDL. The bit line connection unit BLHU includes a high-voltage transistor connected between the bit line BL and the sense amplifier unit SA. The sense amplifier unit SA includes a circuit for determining the threshold voltage of the memory cell transistor MT based on the voltage of the bit line BL. The latch circuits SDL, ADL, BDL, CDL, VLDL, VHDL, and XDL are each circuits capable of temporarily storing data.

[0072] The sense amplifier SA and latch circuits SDL, ADL, BDL, CDL, VLDL, VHDL, and XDL are connected to a bus LBUS. Latch circuits SDL, ADL, BDL, CDL, VLDL, VHDL, and XDL can exchange data with each other via bus LBUS. Latch circuit XDL is used to input and output data DAT between the input / output circuits of semiconductor memory device 1 and sense amplifier unit SAU. Latch circuit XDL also functions as cache memory CM of semiconductor memory device 1. As long as at least latch circuit XDL is idle, semiconductor memory device 1 is in a ready state.

[0073] Each sense amplifier SA receives a control signal STB generated by the sequencer 13. When the control signal STB asserts, the sense amplifier SA determines the data stored in the selected memory cell transistor MT. In short, when the control signal STB asserts, the sense amplifier SA discharges the bus line LBUS based on the voltage of its associated bit line BL. The data ("0" or "1") based on the current voltage on the bus line LBUS is then stored in one of the latch circuits on the shared bus line LBUS.

[0074] Figure 5 1 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit SAU included in the sense amplifier module 16 included in the semiconductor memory device 1 according to the first embodiment. Figure 5 As shown, sense amplifier SA includes transistors 20 to 27, capacitor 28, nodes ND1 and ND2, and sense node SEN. Bit line connection BLHU includes transistor 29. Latch circuit SDL includes inverters 30 and 31, transistors 32 and 33, and nodes SINV and SLAT.

[0075] Transistor 20 is a P-type MOS transistor. Transistors 21 to 27 are each N-type MOS transistors. The source of transistor 20 is connected to a power supply line. Power supply voltage VDD is applied to the power supply line. The drain of transistor 20 is connected to node ND1. The gate of transistor 20 is connected to node SINV. The drain of transistor 21 is connected to node ND1. The source of transistor 21 is connected to node ND2. The gate of transistor 21 is connected to node BLX. The drain of transistor 22 is connected to node ND1. The source of transistor 22 is connected to sense node SEN. The gate of transistor 22 is connected to node HLL. The drain of transistor 23 is connected to sense node SEN. The source of transistor 23 is connected to node ND2. The gate of transistor 23 is connected to node XXL.

[0076] The drain of transistor 24 is connected to node ND2. The gate of transistor 24 is connected to node BLC. The drain of transistor 25 is connected to node ND2. The source of transistor 25 is connected to node SRC. Node SRC is applied with, for example, ground voltage VSS. The gate of transistor 25 is connected to node SINV. The source of transistor 26 is grounded. The gate of transistor 26 is connected to sense node SEN. The drain of transistor 27 is connected to bus line LBUS. The source of transistor 27 is connected to the drain of transistor 26. Control signal STB is input to the gate of transistor 27. One electrode of capacitor 28 is connected to sense node SEN. Clock CLK is input to the other electrode of capacitor 28.

[0077] Transistor 29 is an N-type MOS transistor having a higher withstand voltage than transistors 20 to 27. The drain of transistor 29 is connected to the source of transistor 24. The source of transistor 29 is connected to bit line BL. The gate of transistor 29 is connected to node BLS.

[0078] The input node of inverter 30 is connected to node SLAT. The output node of inverter 30 is connected to node SINV. The input node of inverter 31 is connected to node SINV. The output node of inverter 31 is connected to node SLAT. Transistors 32 and 33 are each N-type MOS transistors. The source and drain of transistor 32 are connected between node SINV and bus line LBUS. The gate of transistor 32 is connected to node STI. The source and drain of transistor 33 are connected between node SLAT and bus line LBUS. The gate of transistor 33 is connected to node STL. Latch circuit SDL stores data at node SLAT. On the other hand, latch circuit SDL stores the inverse of the data stored in node SLAT at node SINV.

[0079] The circuit configurations of latch circuits ADL, BDL, CDL, VLDL, VHDL, and XDL are similar to those of latch circuit SDL. Briefly, latch circuit ADL has a configuration in which nodes SLAT and SINV are replaced with nodes ALAT and AINV, respectively, and nodes STL and STI are replaced with nodes ATL and ATI, respectively. Latch circuit ADL stores data at node ALAT and stores the inverse of the data stored at node AINV. Descriptions of latch circuits BDL, CDL, VLDL, VHDL, and XDL are omitted.

[0080] Nodes BLX, HLL, XXL, BLC, BLS, STI, STL, ATL, and ATI are shared by, for example, multiple sense amplifier units SAU. Control signals generated by sequencer 13 are input to each of nodes BLX, HLL, XXL, BLC, BLS, STI, STL, ATL, and ATI. Sense amplifier module 16 may also have other circuit configurations. For example, the number of latch circuits included in each sense amplifier unit SAU may be varied depending on the number of bits that can be stored in a single memory cell transistor MT.

[0081] [1-1-3] Data storage method

[0082] Figure 6 This is a conceptual diagram showing an example of a data storage method in the semiconductor memory device 1 according to the first embodiment. Figure 6 This diagram shows an example of the threshold voltage distribution of memory cell transistors MT, data allocation, and the voltage used for data reading. In the threshold voltage distribution diagram referenced below, the vertical axis "NMTs" represents the number of memory cell transistors MT, and the horizontal axis "Vth" represents the threshold voltage of the memory cell transistor MT.

[0083] like Figure 6 As shown, when one memory cell transistor MT stores 3 bits of data, the threshold voltage distribution formed by the multiple memory cell transistors MT included in the unit set CU can have 8 states. Hereinafter, the 8 states are referred to as "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state in order of threshold voltage from low to high. The method of making one memory cell transistor store 3 bits of data is also called TLC (Triple-Level Cell) method.

[0084] When the memory cell transistor MT is in the erased state, the threshold voltage of the memory cell transistor MT is in the "S0" state. When data is written to the memory cell transistor MT, the threshold voltage of the memory cell transistor MT is in any of the "S0" to "S7" states. Each of the "S0" to "S7" states is assigned a different 3-bit data. The data assignments for two adjacent states are preferably set so that only a single bit of data differs. An example of data assignment for the eight states is listed below.

[0085] "S0" state: "111 (upper bit / middle bit / lower bit)" data "S1" state: "110" data "S2" state: "100" data "S3" state: "000" data "S4" state: "010" data "S5" state: "011" data "S6" state: "001" data "S7" state: "101" data

[0086] Between adjacent states, a verification voltage used to confirm data writing and a read voltage used to read data are set. Specifically, between the "S0" and "S1" states, verification voltage V1 and read voltage R1 are set. Between the "S1" and "S2" states, verification voltage V2 and read voltage R2 are set. Between the "S2" and "S3" states, verification voltage V3 and read voltage R3 are set. Between the "S3" and "S4" states, verification voltage V4 and read voltage R4 are set. Between the "S4" and "S5" states, verification voltage V5 and read voltage R5 are set. Between the "S5" and "S6" states, verification voltage V6 and read voltage R6 are set. Between the "S6" and "S7" states, verification voltage V7 and read voltage R7 are set. Verification voltages V1 to V7 are preferably set higher than read voltages R1 to R7.

[0087] Verification voltages V1 to V7 are associated with states "S1" to "S7," respectively. During a write operation, the semiconductor memory device 1 uses a read operation (hereinafter referred to as a verify read) using the verification voltages to confirm whether the threshold voltage of the memory cell transistor MT, in which data is to be stored, exceeds the verification voltage associated with the data. Once the sequencer 13 detects that the threshold voltage of the memory cell transistor MT exceeds the verification voltage associated with the data, the data write to the memory cell transistor MT is completed.

[0088] The read voltage R1 is used to distinguish between the "S0" state and the state above "S1". The read voltage R2 is used to distinguish between the state below "S1" and the state above "S2". The read voltage R3 is used to distinguish between the state below "S2" and the state above "S3". The read voltage R4 is used to distinguish between the state below "S3" and the state above "S4". The read voltage R5 is used to distinguish between the state below "S4" and the state above "S5". The read voltage R6 is used to distinguish between the state below "S5" and the state above "S6". The read voltage R7 is used to distinguish between the state below "S6" and the state above "S7". In addition, the read pass voltage VREAD is set to a voltage higher than the highest state. The memory cell transistor MT whose gate is applied with the read pass voltage VREAD becomes turned on regardless of the data to be stored.

[0089] During a read operation, semiconductor memory device 1 uses at least one read voltage to determine the state of memory cell transistor MT. For example, a set of lower bit data, i.e., lower page data, is determined by a read operation using read voltages R1 and R5, respectively. A set of middle bit data, i.e., middle page data, is determined by a read operation using read voltages R2, R4, and R6, respectively. A set of upper bit data, i.e., upper page data, is determined by a read operation using read voltages R3 and R7, respectively. In a page read operation using multiple read voltages, appropriate calculation processing is performed.

[0090] Furthermore, the semiconductor memory device 1 can also use other data allocations in the TLC method. The semiconductor memory device 1 can also use storage methods other than the TLC method, thereby utilizing all data allocations. For example, a single memory cell transistor MT can store 2 bits of data, or 4 bits or more of data. The operations described in this specification can be performed regardless of the data storage method or data allocation type.

[0091] In this specification, the term "preceding state" refers to the adjacent state with the lower threshold voltage. For example, the state preceding the "S2" state is the "S1" state. The term "preceding two states" refers to two states separated by a state and having the lower threshold voltage. For example, the state preceding the "S3" state is the "S1" state. Similarly, the relationship between two states can also be expressed by the number of states located in between.

[0092] [1-2] Action

[0093] Next, the operation of the semiconductor memory device 1 according to the first embodiment will be described. In the following description, the word line WL selected based on the page address PA is referred to as "word line WLsel," and the unselected word line WL is referred to as "word line WLusel." The memory cell transistor MT connected to the word line WLsel is referred to as "memory cell transistor MTsel." The driver module 14 and the row decoder module 15 apply voltage to the word line WL. The sense amplifier unit SAU applies voltage to the bit line BL.

[0094] [1-2-1] Overview of write operation

[0095] Figure 7 1 is a timing chart showing an overview of the write operation of the semiconductor memory device 1 according to the first embodiment. Figure 7 As shown, the semiconductor memory device 1 repeatedly executes a program loop during a write operation. Figure 7The number of program loops executed in a write operation (hereinafter referred to as the loop count) and the voltage change of the word line WLsel (WLsel voltage) are shown. Each program loop includes a program operation (Program) and a verify operation (Verify).

[0096] The programming operation can increase the threshold voltage of the memory cell transistor MT. During the programming operation, the multiple memory cell transistors MTsel connected to the word line WLsel are set as program-target or program-inhibit based on the write data stored in their associated sense amplifier unit SAU. Specifically, the memory cell transistors MTsel whose threshold voltage has not reached the write target state (hereinafter referred to as the write state) are set as program-target. On the other hand, the memory cell transistors MTsel whose threshold voltage has reached the write state are set as program-inhibit.

[0097] During the programming operation, a programming voltage VPGM is applied to the word line WLsel. The programming voltage VPGM is a high voltage that can increase the threshold voltage of the memory cell transistor MTsel. The programming voltage VPGM increases, for example, with the repetition of programming loops. In other words, the programming voltage VPGM can increase with the number of programming loops performed. After the programming voltage VPGM is applied to the word line WLsel, the threshold voltage of the memory cell transistor MTsel connected to the word line WLsel and to the bit line BL to be programmed increases. On the other hand, the increase in the threshold voltage of the memory cell transistor MTsel connected to the word line WLsel and to the programming-inhibited bit line BL is suppressed by self-boosting technology, etc. After the sequencer 13 completes the programming operation, it performs a verification operation.

[0098] The verify operation is a read operation that confirms whether the threshold voltage of the memory cell transistor MTsel has reached the threshold voltage for the written state. Within the same programming loop, the sequencer 13 performs a read operation using a specified verify voltage on the memory cell transistor MTsel that is set as the programming target and has the same written state as the verify target. Hereinafter, the read operation performed during the verify operation is also referred to as a verify read.

[0099] During a verify read, the sense amplifier unit SAU determines whether the threshold voltage of the memory cell transistor MTsel exceeds the verify voltage applied to the word line WLsel based on the voltage of the bit line BL. Each sense amplifier unit SAU determines a memory cell transistor MTsel as "verified" if its threshold voltage exceeds the verify voltage, meaning it can be considered to have reached the threshold voltage for the write state. On the other hand, each sense amplifier unit SAU determines a memory cell transistor MTsel as "verified" if its threshold voltage is below the verify voltage, meaning it can be considered to have not reached the threshold voltage for the write state. Each sense amplifier unit SAU stores the verification result of the write state described above in one of its internal latch circuits. After the verification operation is completed, the sequencer 13 sets each memory cell transistor MTsel as either program-targeted or program-inhibited based on the verification result of the current programming loop and begins processing the next programming loop.

[0100] Furthermore, the semiconductor memory device 1 can appropriately perform a detection operation ("Detection") after each programming loop. During the detection operation, the number of memory cell transistors MT that have passed verification is counted for each write state. Furthermore, the sequencer 13 determines for each write state whether writing has been completed. During the repetition of the programming loop, if the sequencer 13 detects that the number of memory cell transistors MT that have failed verification in states "S1" to "S7" falls below a specified number, for example, it terminates the write operation.

[0101] Figure 8 This is a table showing an example of settings of a program loop in a write operation of the semiconductor memory device 1 according to the first embodiment. Figure 8 The table shows the relationship between the number of cycles and the write status of the verification object assigned to the cycle, and the part where the verification read is performed is marked with "○". Figure 8 As shown, the type and number of states to be verified can change as the programming loop progresses. In this example, the sequencer 13 executes a maximum of 19 programming loops. Furthermore, the sequencer 13 executes a verification read for at least one state in each of the 19 programming loops.

[0102] Specifically, the "S1" state is set as the verification target in the 1st to 6th programming loops. The "S2" state is set as the verification target in the 2nd to 8th programming loops. The "S3" state is set as the verification target in the 4th to 10th programming loops. The "S4" state is set as the verification target in the 6th to 12th programming loops. The "S5" state is set as the verification target in the 8th to 14th programming loops. The "S6" state is set as the verification target in the 10th to 16th programming loops. The "S7" state is set as the verification target in the 12th to 19th programming loops.

[0103] Furthermore, the number of programming loops that the semiconductor memory device 1 can perform in one write operation may be another number. If the sequencer 13 does not complete the write operation in all states, it may terminate the write operation after executing a specified number of programming loops. The state of the verification target associated with the number of loops may also be another setting. The sequencer 13 may also omit the verification read based on the results of the detection operation.

[0104] [1-2-2] Details of programming method

[0105] Figure 9 This is a threshold voltage distribution diagram showing an example of two verification voltages and two programming methods that can be used for each write state in the write operation of the semiconductor memory device 1 according to the first embodiment. Figure 9 (1) and (2) show the threshold voltage distribution corresponding to the verification action and programming action in the same programming loop. Figure 9 The write states of the plurality of memory cell transistors MTsel having the threshold voltage distribution shown are the same. Figure 9 As shown, in the semiconductor memory device 1 of the first embodiment, a verification low voltage VL and a verification high voltage VH can be set for each write state. The verification high voltage VH is a reference voltage. Figure 6 The verification low voltage VL is set to be lower than the verification high voltage VH.

[0106] like Figure 9 As shown in (1), the sequencer 13 can perform verification readout using a verification low voltage VL (hereinafter referred to as VL verification) and verification readout using a verification high voltage VH (hereinafter referred to as VH verification) during the verification operation. Through this verification operation, the plurality of memory cell transistors MTsel are classified into MTsel having a threshold voltage below VL (MTsel failing VL), MTsel having a threshold voltage higher than VL and below VH (MTsel passing VL), and MTsel having a threshold voltage higher than VH (MTsel passing VH). Figure 9 (1) shows MTsel that failed VL and MTsel that passed VL.

[0107] During the programming operation, the sequencer 13 sets the MTsel that failed VL and the MTsel that passed VL as programming targets, and sets the MTsel that passed VH as programming prohibited. Furthermore, the sequencer 13 applies the first programming method to the MTsel that failed VL and the second programming method to the MTsel that passed VL. After executing the programming operation, Figure 9 As shown in (2), the threshold voltage rise amount ( Figure 9 (A)) becomes greater than the threshold voltage rise amount ( Figure 9 (B)) is small. As a result, the spread of the threshold voltage distribution formed by the memory cell transistors MTsel that have passed the VH verification is suppressed.

[0108] Figure 10 This is a timing chart showing an example of a programming operation of the semiconductor memory device 1 according to the first embodiment. Figure 10 An example of the voltage changes of the word line WLsel and the bit line BL during programming is shown. Hereinafter, the bit line BL connected to the memory cell transistor MTsel that has failed VL is referred to as "bit line BLprog(A)." The bit line BL connected to the memory cell transistor MTsel that has passed VL is referred to as "bit line BLprog(B)." The bit line BL connected to the memory cell transistor MTsel that has been program-inhibited is referred to as "bit line BLinh."

[0109] like Figure 10 As shown, at the start of a programming operation, the voltages of word line WLsel, bit lines BLprog(A), BLprog(B), and BLinh are each, for example, VSS. While programming voltage VPGM is applied to word line WLsel, ground voltage VSS is applied to bit line BLprog(A), voltage VQPW is applied to bit line BLprog(B), and voltage VINH is applied to bit line BLinh. VQPW is a voltage higher than VSS, and VINH is a voltage higher than VPCH.

[0110] At this time, in the NAND string NS connected to bit line BLprog(A), the select transistor STD is turned on. As VSS is applied to bit line BLprog(A), the increase in the channel voltage is suppressed. In the NAND string NS connected to bit line BLprog(B), the select transistor STD is turned on. As VQPW is applied to bit line BLprog(B), the channel voltage increases. In the NAND string NS connected to bit line BLinh, the select transistor STD is turned off, and the channel enters a floating state.

[0111] As a result, in the memory cell transistor MTsel connected to bit line BLprog(A) (MTsel that failed VL), electrons are injected into the charge storage layer as the voltage difference between the channel and the control gate increases, causing the threshold voltage to rise. In the memory cell transistor MTsel connected to bit line BLprog(B) (MTsel that passed VL), electrons are injected into the charge storage layer similarly to the MTsel that failed VL. However, because the voltage difference between the channel and the control gate is smaller than that of the MTsel that failed VL, the rise in threshold voltage is more suppressed than that of the MTsel that failed VL. In the memory cell transistor MTsel connected to bit line BLinh (MTsel that passed VH), the voltage of the floating channel rises as the voltage applied to each word line WL increases, so the rise in threshold voltage is more suppressed than that of the MTsel that passed VL.

[0112] [1-2-3] Details of verification method

[0113] Figure 11 This is a table showing an example of setting the verification voltage in the write operation of the semiconductor memory device according to the first embodiment. Figure 11 As shown, as the verification high voltage VH of each written state, the reference voltage is used. Figure 6 Specifically, the verification high voltage VH in the "S1" state is "V1". The verification high voltage VH in the "S2" state is "V2". The verification high voltage VH in the "S3" state is "V3". The verification high voltage VH in the "S4" state is "V4". The verification high voltage VH in the "S5" state is "V5". The verification high voltage VH in the "S6" state is "V6". The verification high voltage VH in the "S7" state is "V7".

[0114] On the other hand, as the verification low voltage VL for each write state, the verification high voltage VH of the "S(N-1)" state (N is a number assigned to the write state), that is, the verification voltage V(N-1) is used. Specifically, the verification low voltage VL of the "S1" state is not defined in the first embodiment. The verification low voltage VL of the "S2" state is "V1", which is the same as the verification high voltage VH of the "S1" state. The verification low voltage VL of the "S3" state is "V2", which is the same as the verification high voltage VH of the "S2" state. The verification low voltage VL of the "S4" state is "V3", which is the same as the verification high voltage VH of the "S3" state. The verification low voltage VL of the "S5" state is "V4", which is the same as the verification high voltage VH of the "S4" state. The verification low voltage VL of the "S6" state is "V5", which is the same as the verification high voltage VH of the "S5" state. The verification low voltage VL of the "S7" state is "V6", which is the same as the verification high voltage VH of the "S6" state.

[0115] Figure 12 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the first embodiment. Figure 12 The following diagram illustrates the operation of the sequencer 13 during a verify operation when performing verify reads in the "S(N-1)" state and verify reads in the "S(N)" state. In this example, "N" is a number between 2 and 7. Hereinafter, the bit line BL connected to the memory cell transistor MTsel whose write state is the "S(N)" state is referred to as the "bit line BLprog(N)."

[0116] like Figure 12 As shown, when the programming operation begins, the voltages of word line WLsel, bit lines BLprog(N-1), BLprog(N), and BLinh are each at, for example, VSS. Sequencer 13 then appropriately charges bit line BL connected to memory cell transistor MTsel to be verified and performs a verify operation. The bit line BL to be read for verification is charged from VSS to VPCH.

[0117] When performing verify read in the "S(N-1)" state, verify voltage V(N-1) is applied to word line WLsel, and VPCH is applied to bit lines BLprog(N-1) and BLprog(N). At this time, sequencer 13 performs a VH verify on memory cell transistor MTsel connected to bit line BLprog(N-1), and a VL verify on memory cell transistor MTsel connected to bit line BLprog(N). The result of the VH verify is stored in latch circuit VHDL within sense amplifier unit SAU connected to bit line BLprog(N-1), while the result of the VL verify is stored in latch circuit VLDL within sense amplifier unit SAU connected to bit line BLprog(N).

[0118] When performing verify read in the "S(N)" state, verify voltage V(N) is applied to word line WLsel, and VPCH is applied to bit line BLprog(N). At this time, sequencer 13 performs a VH verify on memory cell transistor MTsel connected to bit line BLprog(N). The result of this VH verify is stored in latch circuit VHDL within sense amplifier unit SAU connected to bit line BLprog(N).

[0119] As described above, the sequencer 13 performs a VL verify of the "S(N)" state when executing a verify read associated with the previous written state. In other words, if the sequencer 13 sets a VH verify of the "S(N-1)" state in each programming loop, the sequencer 13 can execute the VH verify of the "S(N-1)" state and the VL verify of the "S(N)" state in parallel.

[0120] In the semiconductor memory device 1 of the first embodiment, when VH verification is set for the "S(N)" state but VH verification is not set for the "S(N-1)" state in each programming loop, VL verification for the "S(N)" state is omitted in that programming loop.

[0121] Figure 13 This is a timing chart showing a more detailed example of the verification operation of the semiconductor memory device according to the first embodiment. Figure 13 The following figure shows the detailed operation of sequencer 13 during a verify operation when performing a verify read in the "S(N-1)" state. The figure also shows an example of the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N-1) and BLprog(N), sense nodes SEN(N-1) and SEN(N), and control signal STB. Sense node SEN(N) represents the voltage of sense node SEN in sense amplifier unit SAU connected to memory cell transistor MTsel in the "S(N)" state. Furthermore, VHDL(N-1) corresponds to the data stored in latch circuit VHDL in sense amplifier unit SAU connected to memory cell transistor MTsel in the "S(N-1)" state. VLDL(N) corresponds to the data stored in latch circuit VLDL in sense amplifier unit SAU connected to memory cell transistor MTsel in the "S(N)" state.

[0122] like Figure 13 As shown, before the verify operation begins, the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N-1) and BLprog(N), and sense node SEN are each at, for example, VSS. At this point, transistors 21-24, with VSS applied to their gates, are off in each sense amplifier unit SAU. Furthermore, in this example, VHDL(N-1) stores "L" level data, and VLDL(N) stores "L" level data. In other words, in the verify operation performed in the previous programming loop of this programming loop, both the VH verify in the "S(N-1)" state and the VL verify in the "S(N)" state failed. After the sequencer 13 begins the programming operation, it sequentially executes the processes from times t1 to t6.

[0123] At time t1, a verification voltage V(N-1) is applied to word line WLsel, and VREAD is applied to word line WLusel. Application of the verification voltage V(N-1) to word line WLsel turns the selected memory cell transistor MTsel on or off, while application of the verification voltage V(N-1) to word line WLusel turns the unselected memory cell transistors MT on.

[0124] At time t1, VBLX is applied to node BLX, VBLC is applied to node BLC, and VHHL is applied to node HHL. VBLX, VBLC, and VHLL are each higher than VSS. Transistor 21, with VBLX applied to its gate, transistor 24, with VBLC applied to its gate, and transistor 22, with VHLL applied to its gate, are each turned on. Thereafter, current flows through transistors 20, 21, 24, and 29 into bit lines BLprog(N-1) and BLprog(N), respectively, causing the voltages of these bit lines to rise from VSS to VPCH. Current flows through transistors 20 and 22 into sense nodes SEN(N-1) and SEN(N), respectively, causing the voltages of these sense nodes SEN(N-1) and SEN(N) to rise from VSS to VSEN.

[0125] At time t2, VSS is applied to node HHL. Transistor 22, with VSS applied to its gate, is then turned off, blocking the current path between node ND1 and sense node SEN. At this point, sense node SEN is in a floating state, maintaining the voltage at which it was charged between times t1 and t2.

[0126] At time t3, VXXL is applied to node XXL. VXXL is a voltage higher than VSS. The transistor 23 to which VXXL is applied to the gate is turned on. Thereafter, the voltages of the sensing nodes SEN(N-1) and SEN(N) decrease or remain constant depending on the state of the memory cell transistor MTsel associated therewith. Specifically, when the memory cell transistor MTsel to which the verification voltage V(N-1) is applied is turned on, the voltage of the sensing node SEN decreases ( Figure 13 , MTsel (ON)), when the memory cell transistor MTsel to which the verification voltage V(N-1) is applied is in the OFF state, the voltage of the sensing node SEN remains unchanged ( Figure 13 Furthermore, when the memory cell transistor MTsel is in the on state, the falling speed of the voltage of the sensing node SEN may also vary depending on the magnitude relationship between the threshold voltage of the memory cell transistor MTsel and the applied verification voltage.

[0127] At time t4, VSS is applied to node XXL. Thereafter, transistor 23, with VSS applied to its gate, is turned off, blocking the current path between sense node SEN and node ND2. At this point, sense node SEN is in a floating state, maintaining the voltage after being discharged between times t3 and t4. In this specification, the time from when VXXL is applied to node XXL after sense node SEN is charged (in this example, between times t3 and t4) is referred to as the "discharge time of sense node SEN."

[0128] At time t5, sequencer 13 activates control signal STB. In other words, sequencer 13 temporarily transitions control signal STB from an "L" level to an "H" level, causing sense amplifier module 16 to determine the threshold voltage of memory cell transistor MTsel. Specifically, transistor 27, with an "H" level voltage applied to its gate, is turned on, and the voltage of bus line LBUS, which has been previously charged, is either reduced or maintained, depending on the state of transistor 26. For example, if the voltage of sense node SEN is greater than the threshold voltage of transistor 26, transistor 26 is turned on, and the voltage of bus line LBUS is reduced. On the other hand, if the voltage of sense node SEN is less than the threshold voltage of transistor 26, transistor 26 is turned off, and the voltage of bus line LBUS is maintained.

[0129] Furthermore, sequencer 13 stores data based on the voltage of bus line LBUS in a designated latch circuit. In this example, when the write state of sense amplifier unit SAU is "S(N-1)", sequencer 13 stores data based on the voltage of sense node SEN(N-1) in latch circuit VHDL(N-1). On the other hand, when the write state of sense amplifier unit SAU is "S(N)", sequencer 13 stores data based on the voltage of sense node SEN(N) in latch circuit VHDL(N). In this example, when storing data corresponding to MTsel (on), the voltage of each latch circuit is at an "H" level. When storing data corresponding to MTsel (off), the voltage of each latch circuit is at an "L" level.

[0130] At time t6, the voltages on word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N-1) and BLprog(N), and sense node SEN return to their pre-verification states. Sequencer 13 then completes the verification operation for the "S(N-1)" state.

[0131] As described above, the semiconductor memory device 1 of the first embodiment simultaneously performs a determination of whether the memory cell transistor MT for writing the first data exceeds the verification high voltage (e.g., V(N-1)") of the first data, and a determination of whether the memory cell transistor MT for writing the second data (e.g., "S(N) state") exceeds the verification low voltage (e.g., VL(N)=V(N-1)) of the second data during the verification operation of the first data (e.g., "S(N) state"). This "determination" corresponds to the sequencer 13 making the control signal STB effective.

[0132] Furthermore, in the semiconductor memory device 1 of the first embodiment, the sequencer 13 can also sequentially perform the same verification readout as the verification readout for the "S(N-1)" state described above, targeting multiple write states during the verification operation. If there is only one write state targeted for verification readout during the verification operation, VL verification using the verification readout for that write state may be performed or omitted. VL verification for a particular write state may also be performed after VH verification for that write state has begun and when VH verification for the previous write state is about to be performed.

[0133] [1-3] Effects of the First Embodiment

[0134] According to the semiconductor memory device 1 of the first embodiment described above, it is possible to suppress a decrease in write speed and improve data reliability. The effects of the semiconductor memory device 1 of the first embodiment will be described in detail below.

[0135] In a semiconductor memory device, the threshold voltage of the memory cell transistor MT to which data is written is determined by the threshold voltage before exceeding the verification voltage of the write state and the amount of increase in the threshold voltage during the subsequent programming operation. The threshold voltages of the multiple memory cell transistors MT after the write operation have a distribution that is close to a normal distribution. This unevenness in the threshold voltages of the memory cell transistors MT may be caused by unevenness in the write characteristics of the memory cell transistors MT and the increase in the programming voltage. In order to speed up the write operation, it is preferable to increase the increase in the programming voltage. However, increasing the increase in the programming voltage may cause the threshold voltage distribution of the memory cell transistors MT to spread.

[0136] To address this issue, the semiconductor memory device 1 of the first embodiment sets two verification voltages (a low verification voltage VL and a high verification voltage VH) for each write state, and varies the amount by which the threshold voltage rises as the write progresses. Simply put, if the semiconductor memory device 1 passes the VH verification using the high verification voltage VH, it deems the write complete and sets the memory cell transistor MT to write-inhibit mode for subsequent programming operations. On the other hand, if the semiconductor memory device 1 passes the VL verification using the low verification voltage VL, the programming operation is performed while the bit line BL connected to the memory cell transistor MT is already charged.

[0137] As a result, the threshold voltage of memory cell transistors MT that have passed the VL verification is suppressed from increasing, thereby preventing the threshold voltage from significantly exceeding the verification high voltage VH. Consequently, even when the programming voltage is increased, semiconductor memory device 1 can suppress the spread of the threshold voltage distribution of memory cell transistors MT. However, when performing a verification operation in which both the verification low voltage VL and the verification high voltage VH are set for each write state, the number of read operations may increase with the verification operation, thereby increasing the processing time of the write operation.

[0138] Therefore, the semiconductor memory device 1 of the first embodiment allocates the same voltage as the verification high voltage VH set for the previous written state as the verification low voltage VL. Furthermore, when performing a verification operation for the "S(N-1)" state, the semiconductor memory device 1 performs the VH verification for the "S(N-1)" state and the VL verification for the "S(N)" state in parallel. Thus, based on the results of the VL verification performed in parallel with the VH verification for the previous state, the semiconductor memory device 1 adjusts the amount of increase in the threshold voltage of the memory cell transistor MT during the subsequent programming operation.

[0139] In this manner, the semiconductor memory device 1 according to the first embodiment can perform VL verification without extending the processing time of the programming operation. In other words, the processing time of VL verification is offset by the time of VH verification. Furthermore, by performing VL verification, the semiconductor memory device 1 can suppress the spread of the threshold voltage distribution of the memory cell transistors MT. As a result, the semiconductor memory device 1 according to the first embodiment can suppress a decrease in write speed and improve data reliability.

[0140] [1-4] Modifications of the First Embodiment

[0141] In semiconductor memory device 1, when setting low verify voltage VL to utilize the second programming method, it is preferably optimized according to the write characteristics of memory cell transistor MT. Hereinafter, first and second variations of the first embodiment will be described as variations in setting low verify voltage VL.

[0142] (First Modification of the First Embodiment)

[0143] Figure 14 This is a table showing an example of the setting of the verification action in the first variation of the first embodiment. Figure 14 As shown, the verification high voltage VH of the first two states can also be used as the verification low voltage VL for each written state. In other words, the verification high voltage VH of the "S(N-2)" state, that is, the verification voltage V(N-2), can also be used as the verification low voltage VL for each written state.

[0144] Specifically, in the first variation of the first embodiment, the low-verify voltages VL for the "S1" and "S2" states are undefined, and the low-verify voltages VL for the "S3" to "S7" states are V1 to V5, respectively. In this case, the semiconductor memory device 1 of the first variation of the first embodiment can also achieve the same effects as the first embodiment. Furthermore, the high-verify voltages VH of the first three or more states can be used as the low-verify voltages VL for each write state.

[0145] (Second Modification of the First Embodiment)

[0146] Figure 15 This is a table showing an example of the setting of the verification action in the second variation of the first embodiment. Figure 15 As shown, when verify low voltage VL is assigned to each written state, verify high voltage VH for the first written state and verify high voltage VH for the first two states can be used interchangeably. In other words, verify high voltage VH for the "S(N-1)" state and verify high voltage VH for the "S(N-2)" state can be used separately as verify low voltage VL for each written state.

[0147] Specifically, in the second variation of the first embodiment, the low-verify voltage VL for the "S1" state is undefined. The low-verify voltages VL for the "S2" to "S4" states are V1 to V3, respectively, and the low-verify voltages VL for the "S5" to "S7" states are V3 to V5, respectively. In this case, the semiconductor memory device 1 of the second variation of the first embodiment can also achieve the same effects as the first embodiment. Furthermore, the high-verify voltages VH for the first three or more states can be used as the low-verify voltages VL for each write state. The combination of low-verify voltages VL can be modified as appropriate.

[0148] [2] Second embodiment

[0149] The configuration of the semiconductor memory device 1 of the second embodiment is the same as that of the first embodiment. The semiconductor memory device 1 of the second embodiment adjusts the actual verification low voltage by making the sensing time during the VL verification longer than the VH verification. The following describes the differences between the semiconductor memory device 1 of the second embodiment and the first embodiment.

[0150] [2-1] Verification method

[0151] Figure 16 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the second embodiment. Figure 16 The verification readout of the "S(N-1)" state is shown. Figure 13 An example of voltage changes of the same items in the timing chart shown.

[0152] like Figure 16 As shown, the status before the verification action starts is the same as Figure 13 The timing diagram shown is the same. After the sequencer 13 starts the verification operation, it sequentially executes the processing from time t1 to t11. The period from time t1 to t6 corresponds to the VH verification of the "S(N-1)" state. The period from time t6 to t11 corresponds to the VL verification of the "S(N)" state.

[0153] The VH verification of the “S(N-1)” state has the following characteristics: Figure 13 The verification read of the "S(N-1)" state described above is formed by removing the operation corresponding to the latch circuit VLDL(N). The operations at time t1 to t4 are respectively the same as Figure 13 The operations from times t1 to t4 shown are identical. Specifically, a verification voltage V(N-1) is applied to word line WLsel. Bit line BLprog and sense node SEN are charged separately. While VXXL is applied to node XXL, the voltage of sense node SEN decreases or remains constant depending on the state of memory cell transistor MTsel. Hereinafter, the discharge time of sense node SEN during this VH verification is referred to as "T1." At time t5, sequencer 13 asserts control signal STB, storing the result of the VH verification in the "S(N-1)" state in latch circuit VHDL(N-1).

[0154] The VL verification of the "S(N)" state has Figure 13 The operation corresponding to the latch circuit VLDL(N-1) is removed from the verification read of the "S(N-1)" state. The operations at time t6 to t9 are respectively the same as Figure 13The actions at times t1 to t4 shown are the same. To put it simply, the sensing node SEN is charged again. While VXXL is applied to the node XXL, the voltage of the sensing node SEN drops or remains constant depending on the state of the memory cell transistor MTsel. Hereinafter, the discharge time of the sensing node SEN in this VL verification is referred to as "T2". T2 is longer than T1. Thus, when the discharge time of the sensing node SEN in the VH verification is T1, a voltage higher than VL(N-1) becomes the state actually used in the VL verification. At time t10, the sequencer 13 enables the control signal STB and stores the result of the VL verification of the "S(N)" state in the latch circuit VLDL(N).

[0155] At time t11, the voltages on word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N-1) and BLprog(N), and sense node SEN return to their pre-verification states. Sequencer 13 then completes the verification operation for the "S(N-1)" state.

[0156] As described above, the semiconductor memory device 1 of the second embodiment uses the verification high voltage VH of the S(N-1) state during the verification operation of the S(N-1) state to sequentially perform the VH verification of the S(N-1) state and the VL verification of the S(N) state. Furthermore, in the second embodiment, the discharge time T2 of the sense node SEN during the VL verification of the S(N) state is set to be longer than the discharge time T1 of the sense node SEN during the VH verification of the S(N-1) state. The other operations of the semiconductor memory device 1 of the second embodiment are the same as those of the first embodiment. Furthermore, in the second embodiment, the order of the VH verification of the S(N-1) state and the VL verification of the S(N) state can be reversed.

[0157] [2-2] Effects of the Second Embodiment

[0158] Figure 17 This is a conceptual diagram showing an example of an actual verification voltage in the semiconductor memory device 1 according to the second embodiment. Figure 17 (1) shows the threshold voltage distribution during sensing of the VH verification in the “S(N−1)” state and the verification voltage V(N−1) to be applied. Figure 17 (2) shows the threshold voltage distribution during sensing and the actual verification voltage for the VL verification of the "S(N)" state. In this example, when executing the verification operation for the "S(N-1)" state, both the VH verification of the "S(N-1)" state and the VL verification of the "S(N)" state are performed.

[0159] In order to compare the threshold voltages of memory cell transistors MT under the same conditions during a verify read and a normal read operation, the discharge time of sense node SEN during a verify read is preferably set to be the same as the discharge time of sense node SEN during a read operation. On the other hand, in semiconductor memory device 1 according to the second embodiment, the discharge time of sense node SEN during a VL verify in the "S(N)" state is set to be longer than during a VH verify in the "S(N-1)" state.

[0160] like Figure 17 As shown in (1), when executing the verification operation of the "S(N-1)" state, the verification voltage V(N-1) is applied to the word line WLsel. If the discharge time of the sensing node SEN is set to be longer than the VH verification of the "S(N-1)" state, then Figure 16 As shown in FIG. 1 , the voltage change of the sensing node SEN(N) (weakly turned on cell) increases the amount of voltage drop of the sensing node SEN corresponding to the threshold voltage of the memory cell transistor MT. This voltage change of the sensing node SEN is equivalent to increasing the verification voltage applied to the word line WLsel, assuming that the discharge time of the sensing node SEN is the same as that of the VH verification. In other words, Figure 17 As shown in (2), in the semiconductor memory device 1 of the second embodiment, the actual verification voltage used in the VL verification of the "S(N)" state can be regarded as a voltage higher than the actually applied verification voltage V(N-1).

[0161] As described above, the semiconductor memory device 1 according to the second embodiment can substantially use the low verification voltage VL(N), which is higher than the verification voltage V(N-1) applied to the word line WLsel, for VL verification. As a result, the semiconductor memory device 1 according to the second embodiment can perform a verification operation using a more preferable low verification voltage VL, thereby suppressing the spread of the threshold voltage distribution of the memory cell transistors MT.

[0162] Furthermore, the semiconductor memory device 1 of the second embodiment performs charging and discharging of the sense node SEN, as well as sensing, during both the VH verification in the "S(N-1)" state and the VL verification in the "S(N)" state. When multiple read operations are performed in this manner, the processing time for the verification operation becomes longer than that of the first embodiment. However, the semiconductor memory device 1 of the second embodiment shortens the processing time for the verification operation by performing the verification operation for each written state while maintaining a constant voltage on the word line WLsel. This effect is described in detail below.

[0163] The wiring resistance of the word line WL tends to increase due to high integration measures such as stacking memory cells. Changing the voltage of the word line WL is more difficult than changing the voltage applied to each node within the sense amplifier unit SAU. In other words, the verification operation time can be extended by limiting the time required for the voltage change of the word line WL. In response to this, the semiconductor memory device 1 of the second embodiment uses a common verification voltage when performing the verification operation, performing VH verification and VL verification. Thus, the semiconductor memory device 1 of the second embodiment can eliminate the time required to increase the voltage of the word line WL and the time required to stabilize the voltage. As a result, the semiconductor memory device 1 of the second embodiment can shorten the verification operation time compared to a case where the voltage of the word line WLsel changes between the VH verification and the VL verification.

[0164] [3] Third embodiment

[0165] The configuration of the semiconductor memory device 1 of the third embodiment is the same as that of the first embodiment. The semiconductor memory device 1 of the third embodiment performs the VL verification and VH verification described in the second embodiment by charging the sense node SEN once. The differences between the semiconductor memory device 1 of the third embodiment and the first and second embodiments are described below.

[0166] [3-1] Verification method

[0167] Figure 18 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the third embodiment. Figure 18 The verification readout of the "S(N-1)" state is shown. Figure 13 An example of voltage changes of the same items in the timing chart shown.

[0168] like Figure 18 As shown, the status before the verification action starts is the same as Figure 13 The timing diagram shown is the same. After the sequencer 13 starts the verification operation, it sequentially executes the processing from time t1 to t9. The period from time t1 to t6 corresponds to the VH verification of the "S(N-1)" state. The period from time t6 to t9 corresponds to the VL verification of the "S(N)" state.

[0169] VH verification and reference of “S(N-1)” state Figure 16 The VH verification of the "S(N-1)" state is the same as that of the previous one. That is, the actions at time t1 to t5 are respectively the same as those at time t1 to t5. Figure 16The operations from times t1 to t5 shown are identical. Specifically, a verification voltage V(N-1) is applied to word line WLsel. Bit line BLprog and sense node SEN are charged separately. While VXXL is applied to node XXL, the voltage of sense node SEN decreases or remains constant depending on the state of memory cell transistor MTsel. The discharge time of sense node SEN during this VH verification is "T1." Sequencer 13 asserts control signal STB, storing the result of the VH verification in the "S(N-1)" state in latch circuit VHDL(N-1).

[0170] In the third embodiment, the charging of the sense node SEN is omitted in the VL verification of the "S(N)" state performed following the VH verification of the "S(N-1)" state. Specifically, at time t6, VXXL is applied to the node XXL to discharge the sense node SEN. At time t7, VSS is applied to the node XXL, and the sense node SEN maintains the voltage after being discharged from time t6 to t7. Hereinafter, the discharge time of the sense node SEN in this VH verification is referred to as "T3". The sum of T1 and T3 corresponds to the discharge time T2 described in the second embodiment. At time t8, the sequencer 13 enables the control signal STB and stores the result of the VL verification of the "S(N)" state in the latch circuit VLDL(N).

[0171] At time t11, the voltages on word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N-1) and BLprog(N), and sense node SEN return to their states before the start of the verify operation. Sequencer 13 then completes the verify operation for the "S(N-1)" state. The remainder of the operation of semiconductor memory device 1 in the third embodiment is the same as in the first embodiment.

[0172] [3-2] Effects of the Third Embodiment

[0173] As described above, the semiconductor memory device 1 of the third embodiment uses the verification high voltage VH of the "S(N-1)" state in the verification action of the "S(N-1)" state, and continuously performs the VH verification of the "S(N-1)" state and the VL verification of the "S(N)" state by charging the sense node SEN once. In addition, in the third embodiment, the discharge time of the sense node SEN(N) before sensing in the VH verification is set to "T1" as in the second embodiment, and the total discharge time of the sense node SEN(N-1) before sensing in the VL verification is set to T1+T3. That is, in the third embodiment, the discharge time of the sense node SEN in the VL verification of the "S(N)" state becomes longer than the VH verification of the "S(N-1)" state, and as Figure 18As shown in the voltage change of the sensing node SEN(N) (weakly on cell), the drop amount of the voltage of the sensing node SEN corresponding to the threshold voltage of the memory cell transistor MT becomes larger than that of VH verify.

[0174] Thus, in the semiconductor memory device 1 of the third embodiment, similar to the second embodiment, the actual verification voltage during the VL verification in the "S(N)" state can be made higher than the verification high voltage VH applied to the word line WLsel. Furthermore, in the third embodiment, the charging of the sense node SEN is omitted during the VL verification in the "S(N)" state, and the discharge time of the sense node SEN is shorter than that during the VL verification in the "S(N)" state in the second embodiment. Therefore, the semiconductor memory device 1 of the third embodiment can achieve the same effects as the second embodiment, while shortening the verification operation time compared to the second embodiment.

[0175] [4] Fourth embodiment

[0176] The configuration of the semiconductor memory device 1 of the fourth embodiment is the same as that of the first embodiment. The semiconductor memory device 1 of the fourth embodiment adjusts the actual verification low voltage by shortening the sensing time during VL verification compared to VH verification. The following describes the differences between the semiconductor memory device 1 of the fourth embodiment and the first to third embodiments.

[0177] [4-1] Verification method

[0178] Figure 19 This is a timing chart showing an example of a verification operation of the semiconductor memory device according to the fourth embodiment. Figure 19 The verification readout of the "S(N-1)" state is shown. Figure 13 An example of voltage changes of the same items in the timing chart shown.

[0179] like Figure 19 As shown, the status before the verification action starts is the same as Figure 13 The timing diagram shown is the same. After the sequencer 13 starts the verification operation, it sequentially executes the processing from time t1 to t11. The period from time t1 to t6 corresponds to the VL verification of the "S(N)" state. The period from time t6 to t11 corresponds to the VH verification of the "S(N-1)" state.

[0180] The VL verification of the "S(N)" state has Figure 13 The verification readout of the "S(N-1)" state described above is formed by removing the operation corresponding to the latch circuit VHDL(N-1). Specifically, the operations at time t1 to t4 are respectively the same as Figure 13The actions at times t1 to t4 shown are the same. Specifically, a verification voltage V(N-1) is applied to word line WLsel, and bit line BLprog and sense node SEN are charged, respectively. While VXXL is applied to node XXL, the voltage of sense node SEN decreases or remains constant depending on the state of memory cell transistor MTsel. Hereinafter, the discharge time of sense node SEN during this VL verification will be referred to as "T4." Thus, in this example, when the discharge time of sense node SEN during VH verification is T1, a voltage lower than V(N-1) becomes the state actually used during VL verification. At time t5, sequencer 13 validates control signal STB, storing the result of VL verification in the "S(N)" state in latch circuit VLDL(N).

[0181] The VH verification of the “S(N-1)” state has the following characteristics: Figure 13 The operation corresponding to the latch circuit VLDL(N-1) is removed from the verification read of the "S(N-1)" state. The operations at time t6 to t9 are respectively the same as Figure 13 The operations from times t1 to t4 shown are identical. Specifically, the sense node SEN is recharged. While VXXL is applied to node XXL, the voltage of the sense node SEN decreases or remains constant depending on the state of the memory cell transistor MTsel. The discharge time of the sense node SEN during this VH verification is "T1." T1 is longer than T4. At time t10, the sequencer 13 asserts the control signal STB, storing the result of the VH verification in the "S(N-1)" state in the latch circuit VHDL(N-1).

[0182] At time t11, the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N-1) and BLprog(N), and sense node SEN return to their states before the start of the verify operation. Thus, sequencer 13 completes the verify operation for the "S(N-1)" state. The remaining operations of the semiconductor memory device 1 in the fourth embodiment are the same as those in the first embodiment. Furthermore, in the fourth embodiment, the order of the VL verify in the "S(N)" state and the VH verify in the "S(N-1)" state can be reversed.

[0183] As described above, the semiconductor memory device 1 of the fourth embodiment uses the verification high voltage VH of the "S(N-1)" state during the verification operation of the "S(N-1)" state to continuously perform the VL verification of the "S(N)" state and the VH verification of the "S(N-1)" state. Furthermore, in the fourth embodiment, the discharge time T4 of the sense node SEN during the VL verification of the "S(N)" state is set to be shorter than the discharge time T1 of the sense node SEN during the VH verification of the "S(N-1)" state. The remaining operations of the semiconductor memory device 1 of the fourth embodiment are the same as those of the first embodiment.

[0184] [4-2] Effects of the Fourth Embodiment

[0185] Figure 20 This is a conceptual diagram showing an example of an actual verification voltage in the semiconductor memory device 1 according to the fourth embodiment. Figure 20 (1) shows the threshold voltage distribution during sensing of the VH verification in the “S(N−1)” state and the verification voltage V(N−1) to be applied. Figure 20 (2) shows the threshold voltage distribution and actual verification voltage during sensing for the VL verification of the "S(N)" state. In this example, when executing the verification operation for the "S(N-1)" state, both the VH verification of the "S(N-1)" state and the VL verification of the "S(N)" state are performed. Furthermore, in the semiconductor memory device 1 of the fourth embodiment, the discharge time of the sense node SEN is set to be shorter during the VL verification of the "S(N)" state than during the VH verification of the "S(N-1)" state.

[0186] like Figure 20 As shown in (1), when the verification operation of the "S(N-1)" state is executed, the verification voltage V(N-1) is applied to the word line WLsel. If the discharge time of the sensing node SEN is set to be shorter than the VH verification of the "S(N-1)" state, then Figure 19 As shown in FIG. 1 , the voltage change of the sensing node SEN(N) (weakly turned on cell) is similar to the voltage change of the sensing node SEN(N) shown in FIG. 1 . The voltage drop of the sensing node SEN corresponding to the threshold voltage of the memory cell transistor MT is reduced. Assuming that the discharge time of the sensing node SEN is the same as that of the VH verify, this voltage change of the sensing node SEN is equivalent to a lower verification voltage applied to the word line WLsel. In other words, Figure 20 As shown in (2), in the semiconductor memory device 1 of the fourth embodiment, the actual verification voltage used in the VL verification of the "S(N)" state can be regarded as a voltage lower than the actually applied verification voltage V(N-1).

[0187] As described above, the semiconductor memory device 1 according to the fourth embodiment can substantially use the verification low voltage VL(N), which is lower than the verification voltage V(N-1) applied to the word line WLsel, for VL verification. As a result, the semiconductor memory device 1 according to the fourth embodiment can perform a verification operation using a more preferable verification low voltage VL, thereby suppressing the spread of the threshold voltage distribution of the memory cell transistors MT.

[0188] Furthermore, similarly to the second embodiment, the semiconductor memory device 1 of the fourth embodiment performs VH verification and VL verification while a common verification voltage is applied. Therefore, similarly to the second embodiment, the semiconductor memory device 1 of the fourth embodiment can omit the time required for the voltage of the word line WL to change between the VL verification and the VH verification, thereby shortening the processing time of the verification operation.

[0189] [5] Fifth embodiment

[0190] The configuration of the semiconductor memory device 1 of the fifth embodiment is the same as that of the first embodiment. The semiconductor memory device 1 of the fifth embodiment performs the VL verification and VH verification described in the fourth embodiment by charging the sense node SEN once. The following describes the differences between the semiconductor memory device 1 of the fifth embodiment and the first to fourth embodiments.

[0191] [5-1] Verification method

[0192] Figure 21 This is a timing chart showing an example of a verification operation of the semiconductor memory device 1 according to the fifth embodiment. Figure 21 The detailed operation when the sequencer 13 performs the verification read of the "S(N-1)" state in the verification operation is shown, and the Figure 13 An example of voltage changes of the same items in the timing chart shown.

[0193] like Figure 21 As shown, the status before the programming action starts is the same as Figure 13 The timing diagram shown is the same. After the sequencer 13 starts the verification operation, it sequentially executes the processing from time t1 to t9. The period from time t1 to t6 corresponds to the VL verification of the "S(N)" state. The period from time t6 to t9 corresponds to the VH verification of the "S(N-1)" state.

[0194] VL verification and reference of "S(N)" state Figure 19 The VL verification of the "S(N-1)" state is the same as that of the previous one. That is, the actions at time t1 to t5 are respectively the same as those at time t1 to t5. Figure 19The operations from times t1 to t5 shown are identical. Specifically, a verify voltage V(N-1) is applied to word line WLsel. Bit line BLprog and sense node SEN are charged separately. While VXXL is applied to node XXL, the voltage of sense node SEN decreases or remains constant depending on the state of memory cell transistor MTsel. Sequencer 13 asserts control signal STB, storing the VH verify result for the "S(N-1)" state in latch circuit VHDL(N-1).

[0195] In the third embodiment, the charging of the sense node SEN is omitted in the VL verification of the "S(N)" state, which is performed following the VH verification of the "S(N-1)" state. Specifically, at time t6, VXXL is applied to the node XXL, causing the sense node SEN to discharge. At time t7, VSS is applied to the node XXL, and the sense node SEN maintains the voltage after being discharged between times t6 and t7. Hereinafter, the discharge time of the sense node SEN in this VH verification is referred to as "T5". The sum of T4 and T5 corresponds to the discharge time T1. At time t8, the sequencer 13 activates the control signal STB and stores the result of the VL verification of the "S(N)" state in the latch circuit VLDL(N).

[0196] At time t11, the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N-1) and BLprog(N), and sense node SEN return to their states before the start of the verify operation. Sequencer 13 then completes the verify operation for the "S(N-1)" state. The remainder of the operation of semiconductor memory device 1 in the fifth embodiment is the same as in the first embodiment.

[0197] [5-2] Effects of the Fifth Implementation

[0198] As described above, the semiconductor memory device 1 of the fifth embodiment uses the verification high voltage VH of the "S(N-1)" state in the verification action of the "S(N-1)" state, and continuously performs the VH verification of the "S(N-1)" state and the VL verification of the "S(N)" state by charging the sense node SEN once. In addition, in the fifth embodiment, the discharge time of the sense node SEN(N) before sensing in the VL verification is the same as that in the fourth embodiment, and is set to "T4", and the total discharge time of the sense node SEN(N-1) before sensing in the VH verification is set to "T4+T5=T1". That is, in the fifth embodiment, the discharge time of the sense node SEN in the VL verification of the "S(N)" state becomes shorter than the VH verification of the "S(N-1)" state, and as Figure 21As shown in FIG. 1 , the voltage change of the sensing node SEN(N) (weakly on cell) is smaller than that of the sensing node SEN(N) before the VL verification.

[0199] Thus, in the semiconductor memory device 1 of the fifth embodiment, similar to the fourth embodiment, the actual verification voltage during the VL verification in the "S(N)" state can be lower than the verification high voltage VH applied to the word line WLsel. Furthermore, in the fifth embodiment, charging of the sense node SEN is omitted during the VH verification in the "S(N-1)" state, and the discharge time of the sense node SEN is shorter than during the VH verification in the "S(N)" state in the fourth embodiment. Therefore, the semiconductor memory device 1 of the fifth embodiment can achieve the same effects as the fourth embodiment, while shortening the verification operation time compared to the fourth embodiment.

[0200] [6] Sixth embodiment

[0201] The configuration of the semiconductor memory device 1 of the sixth embodiment is the same as that of the first embodiment. The semiconductor memory device 1 of the sixth embodiment starts using the second programming method based on a specified condition without performing a verify read of the previous written state of the verify target state. The following describes the differences between the semiconductor memory device 1 of the sixth embodiment and the first to fifth embodiments.

[0202] [6-1] Programming Method

[0203] Figure 22 FIG. 1 is a flowchart showing an example of a programming operation of the semiconductor memory device 1 according to the sixth embodiment. Figure 22 As shown, the voltage applied to each bit line BL during the programming operation is determined for each programming loop. The operations described below are executed by the sequencer 13 and the sense amplifier unit SAU.

[0204] First, a plurality of memory cell transistors MTsel are classified according to whether they have passed VH verification (ST10).

[0205] If VH verification is passed (ST10, YES), the sense amplifier unit SAU applies VINH to the bit line BL connected to the memory cell transistors MTsel of the group when performing programming (ST11). In other words, the memory cell transistors MTsel of the group are set to write-inhibit.

[0206] If the VH verification is not passed (ST10, No), the memory cell transistors MTsel of the group are classified according to whether the VL verification was performed in the previous programming loop (ST12).

[0207] When VL verification is executed in the previous programming loop (ST12, YES), the memory cell transistors MTsel of the group are classified according to whether they have passed VL verification (ST13).

[0208] If VL verification has not been executed in the previous program loop ( ST12 , No), the process proceeds to ST15 .

[0209] If the VL verification is passed (ST13, YES), when executing the programming operation, the sense amplifier unit SAU applies VQPW to the bit line BL connected to the memory cell transistors MTsel of the group (ST14). In other words, the memory cell transistors MTsel of the group are set as programming targets, and the second programming method is applied.

[0210] If the VL verification is not passed (ST13, No), the process proceeds to ST15.

[0211] In ST15, it is checked whether the current cycle number is less than the designated cycle number set for each write state. In other words, the cycle number for ST15 processing is set for each write state, and it is checked for each write state whether the current cycle number is less than the set cycle number.

[0212] If the number of cycles is less than the designated number set for each write state, the sense amplifier unit SAU applies VQPW to the bit line BL connected to the memory cell transistors MTsel of the group when performing a programming operation (ST14). In other words, the memory cell transistors MTsel of the group are set as programming targets, and the second programming method is applied.

[0213] If the number of cycles set for each write state is greater than or equal to the specified number, the sense amplifier unit SAU applies VSS to the bit line BL connected to the memory cell transistors MTsel in the group when the programming operation is performed (ST16). In other words, the memory cell transistors MTsel in the group are set as programming targets, and the first programming method is applied. The remaining operations of the semiconductor memory device 1 in the sixth embodiment are the same as those in the first embodiment.

[0214] [6-2] Effects of the Sixth Implementation

[0215] As described above, the semiconductor memory device 1 of the sixth embodiment performs a programming operation using the second programming method based on specified conditions without performing a verification operation of the previous written state, that is, without performing a VL verification, in the previous programming loop. In other words, the semiconductor memory device 1 of the sixth embodiment can determine whether to apply the second programming method regardless of whether the VL verification is passed.

[0216] As a result, the semiconductor memory device 1 of the sixth embodiment can reduce the number of verification reads during the verification operation, thereby shortening the processing time of the write operation. In addition, the semiconductor memory device 1 of the sixth embodiment can also apply the second programming method to the memory cell transistors MT that failed the VL verification during the programming loop in which the VL verification is performed, thereby suppressing the spread of the threshold voltage distribution of the memory cell transistors MT.

[0217] [6-3] Modification of the Sixth Embodiment

[0218] Figure 23 This is a flowchart showing an example of programming operations in a variation of the sixth embodiment. Figure 23 The flowchart shown has Figure 22 In the flowchart shown, ST15 is replaced by ST20. In ST20, it is confirmed whether the memory cell transistors MTsel of the group have passed the verification of the specified state associated with the written state. The specified state is any state with a threshold voltage lower than the written state.

[0219] If verification of the designated state associated with the write state is successful (ST20, YES), the sense amplifier unit SAU applies VQPW to the bit line BL connected to the memory cell transistors MTsel of the group when executing the programming operation (ST14). In other words, the memory cell transistors MTsel of the group are set as programming targets, and the second programming method is applied.

[0220] If verification of the designated state associated with the write state fails (ST20, No), the sense amplifier unit SAU applies VSS to the bit line BL connected to the memory cell transistors MTsel of the group when executing the programming operation (ST16). In other words, the memory cell transistors MTsel of the group are set as programming targets, and the first programming method is applied. The remaining operations in the modification of the sixth embodiment are the same as those of the sixth embodiment.

[0221] As described above, when VL verification is omitted, the conditions for using the second programming method can also be changed. In the variation of the sixth embodiment, whether verification of a specified state has been passed is set as a trigger, but the present invention is not limited to this. For example, the second programming method can also be applied based on the number of memory cell transistors MTsel read after verification of a specified state exceeds a specified number.

[0222] [7] Seventh embodiment

[0223] The configuration of the semiconductor memory device 1 of the seventh embodiment is the same as that of the first embodiment. The semiconductor memory device 1 of the seventh embodiment performs a VL verification of the verify target state without performing a verify read of the previous written state of the verify target state. The following describes the differences between the semiconductor memory device 1 of the seventh embodiment and the first to sixth embodiments.

[0224] [7-1] Verification method

[0225] Figure 24 This is a table showing an example of the setting of the verification operation in the write operation of the semiconductor memory device 1 according to the seventh embodiment. Figure 14 As shown in FIG. 1 , as the verification high voltage VH for each write state in the seventh embodiment, the reference voltage VH is used as in the first embodiment. Figure 6 On the other hand, in the seventh embodiment, a low-verification voltage VL1 is set as the low-verification voltage VL in the "S1" state. The low-verification voltage VL1 is lower than V1. The settings of the low-verification voltage VL in other write states in the seventh embodiment are the same as those in the first embodiment.

[0226] Figure 25 This is a timing chart showing an example of a write operation of the semiconductor memory device 1 according to the seventh embodiment. Figure 25 The cycle number and WLsel voltage are shown in FIG. Figure 25 As shown, in the first to third programming loops, verify reads are performed in the "S1" state. During the verify reads in the "S1" state, verify low voltage VL1 and verify voltage V1 are applied to word line WLsel, respectively. Thus, sequencer 13 performs both VL verify in the "S1" state and VH verify in the "S1" state during the verify operation. The remaining operations of semiconductor memory device 1 in the seventh embodiment are the same as those in the first embodiment.

[0227] [7-2] Effects of the Seventh Implementation

[0228] As described above, the semiconductor memory device 1 of the seventh embodiment adds an arbitrary verification low voltage VL when there is no verification operation for the previous written state. As a result, the semiconductor memory device 1 of the seventh embodiment can perform VL verification even during a write operation in a write state such as the "S1" state where there is no previous written state. Furthermore, the semiconductor memory device 1 of the sixth embodiment, by utilizing the second programming method based on the VL verification results, can suppress the spread of the threshold voltage distribution in the "S1" state, thereby improving data reliability.

[0229] [7-3] Modification of the Seventh Embodiment

[0230] Figure 26This is a table showing an example of the setting of the verification action in the variation of the seventh embodiment. Figure 26 As shown in the figure, when performing a write operation for special pattern data, the programming and verification operations for some of the written states can be omitted. In this example, the "S1," "S3," "S5," and "S7" states are set as write states, and the writing of data assigned to the other states is omitted. In this case, the verification operation for the first written state is not performed in the "S1," "S3," "S5," and "S7" states.

[0231] Therefore, in a variation of the seventh embodiment, a verification low voltage VL is set for each of the "S1," "S3," "S5," and "S7" states. Specifically, "VL1" is set as the verification low voltage VL for the "S1" state, "VL3" is set as the verification low voltage VL for the "S3" state, "VL5" is set as the verification low voltage VL for the "S5" state, and "VL7" is set as the verification low voltage VL for the "S7" state. VL1 is lower than V1. VL3 is lower than V3. VL5 is lower than V5. VL7 is lower than V7.

[0232] For example, the sequencer 13 performs VL verification using these low-verification voltages VL during a verification operation that includes VH verification of the associated written state. In this way, even when a verification operation for the written state that utilizes the low-verification voltage VL is not performed, the low-verification voltage VL for VL verification can be added. Thus, the semiconductor memory device 1 according to the variation of the seventh embodiment can utilize the second programming method, thereby improving data reliability.

[0233] [8] Implementation 8

[0234] The configuration of the semiconductor memory device 1 of the eighth embodiment is the same as that of the first embodiment. When performing VL verification and VH verification by charging the sense node SEN once, the semiconductor memory device 1 of the eighth embodiment performs the desired VL verification by combining the voltage applied to the word line WLsel and the discharge time of the sense node SEN. The following describes the differences between the semiconductor memory device 1 of the eighth embodiment and the first to seventh embodiments.

[0235] [8-1] Verification method

[0236] Figure 27 This is a timing chart showing an example of a verification operation of the semiconductor memory device 1 according to the eighth embodiment. Figure 27The figure shows the detailed operation of sequencer 13 during a verify operation when performing a verify read in the "S(N)" state. The figure also shows an example of the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit line BLprog(N), sense node SEN(N), and control signal STB. Furthermore, VHDL(N) and VLDL(N) correspond to the data stored in latch circuits VHDL and VLDL, respectively, within sense amplifier unit SAU connected to memory cell transistor MTsel in the "S(N)" state.

[0237] like Figure 27 As shown, before the verify operation begins, the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit lines BLprog(N) and BLprog(N), and sense node SEN(N) are each at, for example, VSS. VHDL(N) and VLDL(N) each store "L" level data. The period from time t1 to t6 corresponds to VL verify for the "S(N)" state. The period from time t6 to t11 corresponds to VH verify for the "S(N)" state.

[0238] At time t1, verify voltage VM(N) is applied to word line WLsel, VREAD is applied to word line WLusel, VBLX is applied to node BLX, VBLC is applied to node BLC, and VHHL is applied to node HHL. Verify voltage VM(N) is higher than verify low voltage VL and lower than verify high voltage VH. Thus, bit line BLprog and sense node SEN are each charged, similar to the first embodiment.

[0239] At time t2, VSS is applied to the node HHL. Thereafter, the sense node SEN enters a floating state and is maintained at the voltage charged between time t1 and time t2.

[0240] At time t3, VXXL is applied to the node XXL. Thereafter, the voltage of the sensing node SEN(N) drops or remains constant according to the state of its associated memory cell transistor MTsel.

[0241] At time t4, VSS is applied to node XXL. Thereafter, the discharge path of sense node SEN is blocked. At this point, sense node SEN is in a floating state, maintaining the voltage after being discharged between times t3 and t4. Hereinafter, the discharge time of sense node SEN during VL verification is referred to as "T6." T6 is shorter than T1. Therefore, in this example, when the discharge time of sense node SEN during VH verification is T1, VL(N), which is lower than VM(N-1), becomes the state actually used during VL verification.

[0242] At time t5 , the sequencer 13 asserts the control signal STB, and stores the result of the VL verification in the “S(N)” state in the latch circuit VHDL(N−1).

[0243] At time t6 , the verify voltage V(N) is applied to the word line WLsel, and VHHL is applied to the node HHL. Thus, the bit line BLprog and the sense node SEN are charged, respectively, similarly to the first embodiment.

[0244] At time t7, VSS is applied to the node HHL. Thereafter, the sense node SEN enters a floating state and is maintained at the voltage charged at time t6 to t7.

[0245] At time t8, VXXL is applied to the node XXL. Thereafter, the voltage of the sensing node SEN(N) drops or remains constant according to the state of its associated memory cell transistor MTsel.

[0246] At time t9, VSS is applied to node XXL. Thereafter, the discharge path of sense node SEN is blocked. At this point, sense node SEN is in a floating state, maintaining the voltage at which it was discharged between times t8 and t9. The discharge time of sense node SEN during this VH verification is "T1."

[0247] At time t10 , the sequencer 13 asserts the control signal STB, and stores the result of the VH verification of the “S(N)” state in the latch circuit VHDL(N).

[0248] At time t11, the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL, and XXL, bit line BLprog(N), and sense node SEN return to their states before the start of the verify operation. Sequencer 13 then completes the verify operation for the "S(N)" state. The remaining operations of semiconductor memory device 1 in the eighth embodiment are similar to those in the fourth embodiment.

[0249] [8-2] Effects of the Eighth Implementation

[0250] Figure 28 This is a conceptual diagram showing an example of an actual verification voltage in the semiconductor memory device 1 according to the eighth embodiment. Figure 28 (1) shows the threshold voltage distribution during sensing of the VL verification of the “S(N)” state, the applied verification voltage VM(N), and the actual verification voltage. Figure 28(2) shows the threshold voltage distribution during sensing for the VH verification of the "S(N)" state, and the verification voltage V(N) applied. In this example, when executing the verification operation for the "S(N)" state, both the VL verification and the VH verification for the "S(N)" state are performed. During the VL verification, the verification voltage VM(N) applied to the word line WLsel is set between the verification low voltage VL(N) and the verification voltage V(N).

[0251] Furthermore, in the semiconductor memory device 1 of the eighth embodiment, the discharge time of the sense node SEN is set to be shorter during the VL verification than during the VH verification. Figure 20 As shown in (1), the actual verification voltage used in the VL verification of the "S(N)" state can be considered to be lower than the actually applied verification voltage VM(N). As a result, the semiconductor memory device 1 of the eighth embodiment can perform VL verification using the desired verification low voltage VL.

[0252] In addition, in the semiconductor memory device 1 of the eighth embodiment, as Figure 20 As shown in (2), the difference between the verification voltage applied during VL verification and the verification voltage applied during VH verification is smaller than when the verification low voltage VL is applied to the word line WLsel during VL verification. As a result, the semiconductor memory device 1 of the eighth embodiment can reduce the voltage change of the word line WLsel caused by the transition from VL verification to VH verification, thereby shortening the time required for the voltage of the word line WL to stabilize.

[0253] From another perspective, the semiconductor memory device 1 of the eighth embodiment combines shortening the discharge time of the sense node SEN with changing the voltage of the word line WL, thereby expanding the adjustment range of the verify low voltage VL during VL verification. As a result, the semiconductor memory device 1 of the eighth embodiment can optimize the setting of the verify low voltage VL, thereby suppressing the spread of the threshold voltage distribution during the write operation.

[0254] [9] Other

[0255] The aforementioned embodiments and variations can be combined within the permitted range. For example, semiconductor memory device 1 can also change the VL verification method for each write state. The first and second variations of the first embodiment can each be combined with other embodiments. The write state applying the VL verification described in the eighth embodiment and the write state applying the VL verification described in the fifth embodiment can be mixed. Other combinations are also possible, and the operations of three or more embodiments can be combined.

[0256] The method for detecting the voltage of the sense node SEN described in the above embodiment is merely an example. If the circuit configuration of the sense amplifier unit SAU is different, the voltage of the sense node SEN may be detected using a method different from that in the above embodiment. The semiconductor memory device can achieve the same effects as in the above embodiment as long as the charge and discharge times of the sense node SEN during VL and VH verifications in the write operation of each write state are handled in the same manner as in the above embodiment.

[0257] In the above embodiment, the example of storing the result of the verification read using the verification high voltage VH in the latch circuit VHDL is described, but the present invention is not limited to this. For example, the semiconductor memory device 1 may also determine that the VH verification has been passed by overwriting the data stored in the sense amplifier unit SAU to a state identical to the erased state.

[0258] In the above embodiment, the case where the programming operation using the second programming method passes the VH verification is exemplified, but the present invention is not limited thereto. If the VH verification fails after passing the VL verification, the programming operation using the second programming method can be performed multiple times on the specific memory cell transistor MTsel.

[0259] In the above embodiment, the sequencer 13 is shown as performing various operations, but the present invention is not limited to this. The processing of the sequencer 13 described in the embodiment may also be performed by other circuits. For example, the semiconductor memory device 1 may include a counter, and the counter may count the number of memory cell transistors MT that have passed verification.

[0260] The timing diagram used to illustrate the write operation in the above embodiment is merely an example. For example, the timing of the control signals and the voltages of the wirings at each moment may be staggered. Furthermore, the order of some of the processes in each flowchart may be reversed within an acceptable range. Furthermore, in the above embodiment, the voltages applied to the various wirings within the memory cell array 10 may be inferred based on the voltages of the signal lines CG, SGDD, SGDS, USGD, and USGS. For example, the voltage applied to the word line WLsel may be inferred based on the voltage of the signal line CG.

[0261] The term "connection" as used in this specification means electrical connection, and does not exclude the situation where other elements are inserted in between. The so-called "on state" means that a voltage greater than the threshold voltage of the transistor is applied to the gate of the transistor. The so-called "off state" means that a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor. The off state does not exclude the situation where a small amount of current such as leakage current flows through the transistor. The voltage at the "H" level is a voltage that turns the N-type MOS transistor with the gate applied with this voltage into the on state, and turns the P-type MOS transistor with the gate applied with this voltage into the off state. The voltage at the "L" level is a voltage that turns the N-type MOS transistor with the gate applied with this voltage into the off state, and turns the P-type MOS transistor with the gate applied with this voltage into the on state.

[0262] In this specification, the sense amplifier unit SAU may also be referred to as a sense circuit. "Applying the first programming method to the programming action" may also be referred to as a "first programming object." "Applying the second programming method to the programming action" may also be referred to as a "second programming object." The sequencer 13 may also be referred to as a sequence controller, a controller, or a control circuit. The actions performed by each component based on the control of the sequencer 13 may also be recorded as actions of the sequencer 13. "Charging the sensing node SEN" corresponds to the period during which VHHL is applied to the node HHL. "Discharging the sensing node SEN" corresponds to the period during which VXXL is applied to the node XXL. VHHL and VXXL each only need to exceed at least the "H" level, and may also be applied in multiple stages.

[0263] While several embodiments of the present invention have been described, these embodiments are provided for illustrative purposes only and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0264] [Explanation of Symbols]

[0265] 1: Semiconductor storage device

[0266] 2: Storage Controller

[0267] 10: Memory cell array

[0268] 11: Instruction register

[0269] 12: Address register

[0270] 13: Sequencer

[0271] 14: Driver module

[0272] 15: Row decoder module

[0273] 16: Sense amplifier module

[0274] BLK: Block

[0275] SU: string unit

[0276] SAU: Sense Amplifier Unit

[0277] RD: Row Decoder

[0278] CG, SGDD, SGSD, USGD, USGS: signal lines

[0279] BL: bit line

[0280] WL: Word Line

[0281] SGD, SGS: select gate lines

[0282] MT: Memory cell transistor

[0283] STD, STS: Select transistor.

Claims

1. A semiconductor memory device comprising: a plurality of memory cell transistors, each capable of storing multi-bit data depending on which of a plurality of states a threshold voltage belongs to, storing first data when the threshold voltage belongs to a first state, and storing second data when the threshold voltage belongs to a second state higher than the first state; a word line connected to the plurality of memory cell transistors; a plurality of bit lines, respectively connected to the plurality of memory cell transistors; and A controller capable of executing a repetitive write operation including a programming loop, wherein the programming loop includes a programming operation and a verification operation; and Each of the plurality of states is set with a verification low voltage and a verification high voltage, As the controller, In the programming operation, while a programming voltage is applied to the word line, a first voltage is applied to a bit line connected to a memory cell transistor to be first programmed, a second voltage higher than the first voltage is applied to a bit line connected to a memory cell transistor to be second programmed, and a third voltage higher than the second voltage is applied to a bit line connected to a memory cell transistor to be program-inhibited. In the verification operation, for each state of a write destination, a memory cell transistor whose threshold voltage is determined to be less than a verification low voltage is set as the first programming target, a memory cell transistor whose threshold voltage is determined to be greater than the verification low voltage and less than a verification high voltage is set as the second programming target, and a memory cell transistor whose threshold voltage is determined to be greater than the verification high voltage is set as the program-inhibited state; In the verification operation of the first data, while the verification high voltage of the first data is applied to the word line, it is determined whether the voltage of the storage cell transistor for writing the first data exceeds the verification high voltage of the first data, and it is determined whether the voltage of the storage cell transistor for writing the second data exceeds the verification low voltage of the second data.

2. The semiconductor memory device according to claim 1, wherein The first state is adjacent to the second state.

3. The semiconductor memory device according to claim 1, wherein Another state is set between the first state and the second state.

4. The semiconductor memory device according to claim 1, wherein Each of the plurality of memory cell transistors stores third data when the threshold voltage is in a third state, and stores fourth data when the threshold voltage is in a fourth state higher than the third state. The controller determines whether the memory cell transistor for writing the third data exceeds the verification high voltage while applying the verification high voltage of the third data to the word line in a verification operation of the third data, and determines whether the memory cell transistor for writing the fourth data exceeds the verification low voltage. The number of other states set between the first state and the second state is different from the number of other states set between the third state and the fourth state.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein During the verification operation of the first data, the controller simultaneously determines whether the voltage of the memory cell transistor for writing the first data exceeds the verification high voltage of the first data, and determines whether the voltage of the memory cell transistor for writing the second data exceeds the verification low voltage of the second data.

6. The semiconductor memory device according to any one of claims 1 to 4, wherein The device further includes a plurality of sensing circuits, each of which is connected to the plurality of bit lines and can determine the threshold voltage of the memory cell transistor based on the voltage of the sensing node. In the verification operation of the first data, the controller Before determining whether the memory cell transistor for writing the first data exceeds a verification high voltage of the first data, discharging the sensing nodes of the plurality of sensing circuits for a first time, Before determining whether a memory cell transistor for writing the second data exceeds a verification low voltage of the second data, the sense nodes of the plurality of sense circuits are discharged for a second time that is longer than the first time.

7. The semiconductor memory device according to any one of claims 1 to 4, wherein The device further includes a plurality of sensing circuits, each of which is connected to the plurality of bit lines and can determine the threshold voltage of the memory cell transistor based on the voltage of the sensing node. In the verification operation of the first data, the controller Before determining whether the memory cell transistor for writing the first data exceeds a verification high voltage of the first data, discharging the sensing nodes of the plurality of sensing circuits for a first time, After determining whether the storage cell transistor for writing the first data exceeds the verification high voltage of the first data, and before determining whether the storage cell transistor for writing the second data exceeds the verification low voltage of the second data, the sensing nodes of each of the multiple sensing circuits are discharged for a third time without being charged.

8. The semiconductor memory device according to any one of claims 1 to 4, wherein The device further includes a plurality of sensing circuits, each of which is connected to the plurality of bit lines and can determine the threshold voltage of the memory cell transistor based on the voltage of the sensing node. In the verification operation of the first data, the controller Before determining whether the memory cell transistor for writing the first data exceeds a verification high voltage of the first data, discharging the sensing nodes of the plurality of sensing circuits for a first time, Before determining whether a voltage of a memory cell transistor into which the second data is written exceeds a verification low voltage of the second data, the sense nodes of each of the plurality of sense circuits are discharged for a fourth time that is shorter than the first time.

9. The semiconductor memory device according to any one of claims 1 to 4, wherein The device further includes a plurality of sensing circuits, each of which is connected to the plurality of bit lines and can determine the threshold voltage of the memory cell transistor based on the voltage of the sensing node. In the verification operation of the first data, the controller Before determining whether the memory cell transistor for writing the second data exceeds a verification low voltage of the second data, discharging the sensing nodes of the plurality of sensing circuits for a fourth time, After determining whether the storage cell transistor for writing the second data exceeds the verification high voltage of the second data, and before determining whether the storage cell transistor for writing the first data exceeds the verification high voltage of the first data, the sensing nodes of each of the multiple sensing circuits are discharged for a fifth time without charging.

10. The semiconductor memory device according to any one of claims 1 to 4, wherein The controller sets the storage cell transistor for writing the fifth data as the second programming object when the threshold voltage of the storage cell transistor for writing the fifth data does not exceed the verification high voltage during the repetition of the programming loop, and it is not determined whether it exceeds the verification low voltage of the fifth data in the previous programming loop, and the current programming loop number is greater than the first number.

11. The semiconductor memory device according to any one of claims 1 to 4, wherein The controller sets the memory cell transistor for writing the sixth data as the second programming object when the threshold voltage of the memory cell transistor for writing the sixth data does not exceed the verification high voltage during the repetition of the programming loop, and whether it exceeds the verification low voltage of the sixth data is not determined in the previous programming loop, and when the number of memory cell transistors that have passed the verification of the seventh data at the time point of the current programming loop is greater than the second number.

12. The semiconductor memory device according to any one of claims 1 to 4, wherein The controller performs a verification operation on the eighth data allocated to a state in which a program operation and a verification operation for the previous state have not been performed in a write operation. During the period when the verification low voltage of the eighth data is applied to the word line, determining whether the voltage of the memory cell transistor for writing the eighth data exceeds the verification low voltage of the eighth data, While the verification high voltage of the eighth data is applied to the word line, it is determined whether the voltage of the memory cell transistor into which the eighth data is written exceeds the verification high voltage of the eighth data.

13. A semiconductor memory device comprising: a plurality of memory cell transistors, each capable of storing multiple bits of data based on a threshold voltage; a word line connected to the plurality of memory cell transistors; a plurality of bit lines, respectively connected to the plurality of memory cell transistors; a plurality of sensing circuits, respectively connected to the plurality of bit lines, each capable of determining a threshold voltage of a memory cell transistor based on a voltage at a sensing node; and A controller capable of executing a repetitive write operation including a programming loop, wherein the programming loop includes a programming operation and a verification operation; and As the controller, In the programming operation, while a programming voltage is applied to the word line, a first voltage is applied to a bit line connected to a memory cell transistor to be first programmed, a second voltage higher than the first voltage is applied to a bit line connected to a memory cell transistor to be second programmed, and a third voltage higher than the second voltage is applied to a bit line connected to a memory cell transistor to be program-inhibited. In the verification operation, for each state of a write destination, a memory cell transistor whose threshold voltage is determined to be less than a verification low voltage is set as the first programming target, a memory cell transistor whose threshold voltage is determined to be greater than the verification low voltage and less than a verification high voltage is set as the second programming target, and a memory cell transistor whose threshold voltage is determined to be greater than the verification high voltage is set as the program-inhibited state; In the verification operation of the first data, The controller causes the sensing nodes of the plurality of sensing circuits to discharge for a first time period while a fourth voltage between a verification low voltage of the first data and a verification high voltage of the first data is applied to the word line, and causes the sensing nodes of the plurality of sensing circuits to discharge for a second time period that is longer than the first time period while the verification high voltage of the first data is applied to the word line. The sensing circuit connected to the memory cell transistor for writing the first data determines whether the memory cell transistor for writing the first data exceeds the verification low voltage of the first data during the period when the fourth voltage is applied to the word line, and determines whether the memory cell transistor for writing the first data exceeds the verification high voltage of the first data during the period when the verification high voltage of the first data is applied to the word line.

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