Level shifter with low transmission delay

Abstract

The embodiment of the present application discloses a level shifter with low transmission delay, comprising: a low level adjusting circuit, which selectively pulls the level of one of a first input node and a second input node to a first low power voltage according to an input signal; a first comparison circuit, which outputs the one with higher level between the level of the first input node and a second low power voltage to a first output node, wherein the second low power voltage is higher than the first low power voltage; and a high level adjusting circuit, which selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node, to generate an output signal.

Description

TECHNICAL FIELD

[0001] The present application relates to level shifters, and more particularly to level shifters capable of fast switching signal levels. BACKGROUND

[0002] Electronic devices usually include several different circuit systems. In some applications, these circuit systems can operate at different voltage levels. In order to enable these circuit systems to communicate data or signals with each other, level shifters can be provided between these circuit systems to ensure that the levels of the signals conform to the voltage levels of the corresponding circuit systems. In some related arts, level shifters use cross-coupled inverters to perform level shifting. However, due to the influence of other clamping circuits and the operation delay of the inverters, a large transmission delay can be generated during the level switching of the signals. As a result, the switching process of the signals will be delayed, and a higher uncertainty of the transition edges of the signals will be generated. SUMMARY

[0003] In some embodiments, one of the objectives of the present application is to provide a level shifter with low transmission delay to improve the deficiencies of the prior art.

[0004] In some embodiments, the level shifter includes a low level adjustment circuit, a first comparison circuit, and a high level adjustment circuit. The low level adjustment circuit selectively pulls the level of one of a first input node and a second input node to a first low power voltage according to an input signal. The first comparison circuit outputs the one with a higher level between the level of the first input node and a second low power voltage to a first output node, wherein the second low power voltage is higher than the first low power voltage. The high level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.

[0005] In some embodiments, the level shifter can provide additional paths to quickly adjust the level of the output node, thereby reducing the delay generated during the level switching of the signals. As a result, the output signal generated by the level shifter can have fast switching transition edges, thereby reducing the uncertainty of the transition edges of the output signal. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0007] Figure 1 is a schematic diagram of a level shifter provided by an embodiment of the present application;

[0008] Figure 2 is a circuit schematic diagram of a level shifter provided by an embodiment of the present application; Figure 1

[0009] Figure 3A is an operation schematic diagram of a level shifter provided by an embodiment of the present application when an input signal in the level shifter has a low logic value; Figure 2

[0010] Figure 3B is an operation schematic diagram of a level shifter provided by an embodiment of the present application when an input signal in the level shifter has a high logic value; Figure 2

[0011] Figure 4A is a schematic diagram of a level shifter provided by an embodiment of the present application;

[0012] Figure 4B is a circuit schematic diagram of a level shifter provided by an embodiment of the present application; Figure 4A is a waveform diagram of related signals in the level shifter; and

[0013] Figure 5 is a schematic diagram of an input-output driver provided by an embodiment of the present application.

[0014] Reference signs:

[0015] 100: level shifter

[0016] 110: low-level adjustment circuit

[0017] 112, 114: inverters

[0018] 120, 130: comparison circuits

[0019] 140: high-level adjustment circuit

[0020] 142, 144: inverters

[0021] 400: level shifter

[0022] 410: selection circuit

[0023] 411, 412: inverters

[0024] 413, 414: logic gates

[0025] 415: multitasker

[0026] 500: input-output driver

[0027] 501: input-output point​​​

[0028] 510: level shifter

[0029] 520: delay matching circuit

[0030] 530: non-overlap circuit

[0031] 540: protection circuit

[0032] A, B: control node

[0033] D1, D2: diode

[0034] I1, I2: input node

[0035] MN1, MN2, MP1, MP2, N1 ~ N4, P1 ~ P8: transistor

[0036] O1, O2: output node

[0037] S1 ~ S5: signal

[0038] SC1, SC2: control signal

[0039] SEL: selection signal

[0040] SIN: input signal

[0041] VDDH, VDDL: high power voltage

[0042] VN, VP: clamping signal

[0043] VO, VO': output signal

[0044] VSS, VSSH, VSSL: low power voltage DETAILED DESCRIPTION

[0045] All the terms used herein have their ordinary meanings. The definitions of the above-mentioned terms in the generally used dictionaries are included in the content of the present application, and the use examples of any one of the terms discussed herein are only examples, and should not be limited to the scope and meaning of the present application. Similarly, the present application is not limited to the various embodiments shown in the specification.

[0046] As used herein, "coupled" or "connected" can mean that two or more components are directly or indirectly connected, electrically or physically, and can mean that two or more components operate or act in conjunction with each other. As used herein, the term "circuit" can be a device that processes a signal by connecting at least one transistor and / or at least one active or passive component in a certain manner.

[0047] Figure 1is a schematic diagram of a level shifter 100 provided by an embodiment of the present application. The level shifter 100 can be used to convert the level of a signal to be suitable for a voltage range of different power domains. For example, the level shifter 100 can receive an input signal SIN from other digital circuits (not shown), where the level of the input signal SIN can range from a low power supply voltage VSSL to a high power supply voltage VDDL. The level shifter 100 can generate an output signal VO according to the input signal SIN, where the level of the output signal VO can range from a low power supply voltage VSSH to a high power supply voltage VDDH, where the high power supply voltage VDDH is higher than the low power supply voltage VSSH, the low power supply voltage VSSH can be higher than or the same as the high power supply voltage VDDL, and the high power supply voltage VDDL is higher than the low power supply voltage VSSL.

[0048] The level shifter 100 includes a low level adjustment circuit 110, a comparison circuit 120, a comparison circuit 130, and a high level adjustment circuit 140. The low level adjustment circuit 110 selectively pulls down the level of one of the input nodes II and I2 to the high power supply voltage VDDL according to the input signal SIN. The comparison circuit 120 outputs the level of the input node II to the output node Ol with the higher level of the low power supply voltages VSSH. The comparison circuit 130 outputs the level of the input node I2 to the output node O2 with the higher level of the low power supply voltages VSSH. The high level adjustment circuit 140 selectively adjusts the level of the output node Ol and the level of the output node O2 according to the level of the input node II and the level of the input node I2, and generates the output signal VO according to the level of the output node O2.

[0049] In some embodiments, the low level adjustment circuit 110 operates in a first power domain defined by the low power supply voltage VSSL and the high power supply voltage VDDL. The low level adjustment circuit 110 can pull up or pull down the amplitude of the input signal SIN to the high power supply voltage VDDL or the low power supply voltage VSSL, and accordingly adjust the level of the input node II and the level of the input node I2. The high level adjustment circuit 140 operates in a second power domain defined by the low power supply voltage VSSH and the high power supply voltage VDDH. The high level adjustment circuit 140 can further pull up or pull down the level of the output node Ol (and the output node O2) to the high power supply voltage VDDH or the low power supply voltage VSSH according to the level of the input node II and the level of the input node I2, and accordingly generate the output signal VO.

[0050] As will be explained later, the comparison circuit 120 can assist in accelerating the pulling down of the level of the output node O1 to the low supply voltage VSSH, and the comparison circuit 130 can assist in accelerating the pulling down of the level of the output node O2 to the low supply voltage VSSH. In this way, the output signal VO can be quickly switched to the level of the low supply voltage VSSH during the level shifting, thereby reducing the temporal delay and uncertainty of the falling edge of the output signal VO.

[0051] Figure 2 The level shifter 100 of Figure 1 a circuit schematic diagram of the level shifter 100. In some embodiments, the low level adjustment circuit 110 includes an inverter 112, an inverter 114, a transistor N1, and a transistor N2. The inverter 112 generates a signal S1 according to an input signal SIN. The inverter 114 generates a signal S2 according to the signal S1. A first end (e.g., a drain) of the transistor N1 is coupled to an input node I2, a second end (e.g., a source) of the transistor N1 receives the signal S1, and a control end (e.g., a gate) of the transistor N1 receives a high supply voltage VDDL. A first end of the transistor N2 is coupled to an input node I1, a second end of the transistor N2 receives the signal S2, and a control end of the transistor N2 receives the high supply voltage VDDL.

[0052] By the above arrangement, the transistors N1 and N2 can be biased by the high supply voltage VDDL, the transistor N1 can selectively pull down the level of the input node I2 to the low supply voltage VSSH according to the signal S1, and the transistor N2 can selectively pull down the level of the input node I1 to the low supply voltage VSSH according to the signal S2. For example, when the input signal SIN is a logic value 0, the level of the signal S1 is the high supply voltage VDDL, and the level of the signal S2 is the low supply voltage VSSH. Under this condition, the transistor N1 is turned off and the transistor N2 is turned on to pull down the level of the input node I1 to the low supply voltage VSSH. Alternatively, when the input signal SIN is a logic value 1, the level of the signal S1 is the low supply voltage VSSH, and the level of the signal S2 is the high supply voltage VDDL. Under this condition, the transistor N2 is turned off and the transistor N1 is turned on to pull down the level of the input node I2 to the low supply voltage VSSH.

[0053] The high level adjustment circuit 140 includes a plurality of transistors P1-P4, a plurality of transistors N3-N4, and a plurality of inverters 142 and 144. The first end (e.g., source) of the transistor P1 receives a high supply voltage VDDH, the second end (e.g., drain) of the transistor P1 is coupled to the control node A, and the control end (e.g., gate) of the transistor P1 is coupled to the output node O2. The transistor P1 can selectively pull up the level of the control node A to the high supply voltage VDDH according to the level of the output node O2. The first end of the transistor P2 receives the high supply voltage VDDH, the second end of the transistor P1 is coupled to the control node B, and the control end of the transistor P2 is coupled to the output node O1. The transistor P2 can selectively pull up the level of the control node B to the high supply voltage VDDH according to the level of the output node O1. The first end of the transistor N3 is coupled to the control node A, the second end of the transistor N3 receives a low supply voltage VSSH, and the control end of the transistor N3 is coupled to the control node B. The transistor N3 can selectively pull down the level of the control node A to the low supply voltage VSSH according to the level of the control node B. The first end of the transistor N4 is coupled to the control node B, the second end of the transistor N4 receives the low supply voltage VSSH, and the control end of the transistor N4 is coupled to the control node A. The transistor N4 can selectively pull down the level of the control node B to the low supply voltage VSSH according to the level of the control node A. The first end of the transistor P3 is coupled to the control node A, the second end of the transistor P3 is coupled to the input node I1, and the control end of the transistor P3 receives the low supply voltage VSSH. The transistor P3 can be biased by the low supply voltage VSSH and selectively turned on according to the level of the control node A to adjust the level of the input node I1. The first end of the transistor P4 is coupled to the control node B, the second end of the transistor P4 is coupled to the input node I2, and the control end of the transistor P4 receives the low supply voltage VSSH. The transistor P4 can be biased by the low supply voltage VSSH and selectively turned on according to the level of the control node B to adjust the level of the input node I2.

[0054] The plurality of inverters 142 and 144 are powered by the high supply voltage VDDH and the low supply voltage VSSH and coupled in series to operate as a buffer that can generate an output signal VO according to the level of the output node O1.

[0055] The comparison circuit 120 includes transistors P5 and P6. The first end of the transistor P5 is coupled to the output node O1, the second end of the transistor P5 receives the low supply voltage VSSH, and the control end of the transistor P5 is coupled to the input node I1. The first end of the transistor P6 is coupled to the output node O1, the second end of the transistor P6 is coupled to the input node I1, and the control end of the transistor P6 receives the low supply voltage VSSH. By the above arrangement, the transistor P5 can be selectively turned on to transmit the low supply voltage VSSH to the output node O1 according to the level of the input node I1, and the transistor P6 can be selectively turned on to connect the input node I1 to the output node O1 according to the level of the input node I1. For example, when the low supply voltage VSSH is higher than the level of the input node I1, the transistor P5 is turned on and the transistor P6 is turned off to transmit the low supply voltage VSSH to the output node O1. Alternatively, when the level of the input node I1 is higher than the low supply voltage VSSH, the transistor P6 is turned on and the transistor P5 is turned off to connect the input node I1 to the output node O1.

[0056] The comparison circuit 130 includes transistors P7 and P8. The first end of the transistor P7 is coupled to the output node O2, the second end of the transistor P7 receives the low supply voltage VSSH, and the control end of the transistor P7 is coupled to the input node I2. The first end of the transistor P8 is coupled to the output node O2, the second end of the transistor P8 is coupled to the input node I2, and the control end of the transistor P8 receives the low supply voltage VSSH. By the above arrangement, the transistor P7 can be selectively turned on to transmit the low supply voltage VSSH to the output node O2 according to the level of the input node I2, and the transistor P8 can be selectively turned on to connect the input node I2 to the output node O2 according to the level of the input node I2. For example, when the low supply voltage VSSH is higher than the level of the input node I2, the transistor P7 is turned on and the transistor P8 is turned off to transmit the low supply voltage VSSH to the output node O2. Alternatively, when the level of the input node I2 is higher than the low supply voltage VSSH, the transistor P8 is turned on and the transistor P7 is turned off to connect the input node I2 to the output node O2.

[0057] It should be understood that the comparison circuit 120 and the comparison circuit 130 are equivalent to high-voltage selection circuits, and the present application is not limited to the above arrangement. Various comparison circuits that can output higher voltages are also within the scope of the present application.

[0058] Figure 3A is provided by the embodiment of the present application when the input signal in the level shifter 100 has a low logic value. In the above embodiment, the low supply voltage VSSH is transmitted to the output node O1 when the input signal has a low logic value. Alternatively, the low supply voltage VSSH can be transmitted to the output node O2 when the input signal has a low logic value. Figure 2 is provided by the embodiment of the present application when the input signal in the level shifter 100 has a low logic value. In the above embodiment, the low supply voltage VSSH is transmitted to the output node O1 when the input signal has a low logic value. Alternatively, the low supply voltage VSSH can be transmitted to the output node O2 when the input signal has a low logic value. Figure 3AFor example, when the input signal SIN switches from high level to low level (i.e. the input signal SIN has low logic value), the signal S1 has high level and the signal S2 has low level. Under this condition, the transistor N1 is turned off and the transistor N2 is turned on to pull down the level of the input node I1 to the low supply voltage VSSL. Since the low supply voltage VSSH is higher than the level of the input node I1 (equivalent to the low supply voltage VSSL), the transistor P6 is turned off and the transistor P5 is turned on to transmit the low supply voltage VSSH to the output node O1. In this way, the level of the output node O1 can be quickly pulled down to the low supply voltage VSSH to generate the output signal VO with corresponding low level.

[0059] In addition, since the output node O1 is at low level, the transistor P2 is turned on to pull up the level of the control node B to the high supply voltage VDDH. Under this condition, the transistor N4 is turned off, the transistor N3 is turned on to pull down the level of the control node A to the low supply voltage VSSH to turn off the transistor P3, and the transistor P4 is turned on to connect the control node B to the input node I2. In this way, the level of the input node I2 can be pulled up to the high supply voltage VDDH through the transistor P4 and the transistor P2. Since the level of the input node I2 is higher than the low supply voltage VSSH, the transistor P7 is turned off and the transistor P8 is turned on to connect the input node I2 to the output node O2 to turn off the transistor P1.

[0060] Figure 3B is provided by the embodiment of the present application when the input signal in the level converter 100 has high logic value. In the example of the level converter 100, when the input signal SIN switches from low level to high level (i.e. the input signal SIN has high logic value), the signal S2 has high level and the signal S1 has low level. Under this condition, the transistor N2 is turned off and the transistor N1 is turned on to pull down the level of the input node I2 to the low supply voltage VSSL. Since the low supply voltage VSSH is higher than the level of the input node I2 (equivalent to the low supply voltage VSSL), the transistor P8 is turned off and the transistor P7 is turned on to transmit the low supply voltage VSSH to the output node O2. In this way, the level of the output node O2 can be quickly pulled down to the low supply voltage VSSH. Figure 2 Figure 3B

[0061] ​​Furthermore, since output node O2 is low, transistor P1 is turned on, pulling the level of control node A up to the high supply voltage VDDH. Under this condition, transistor N3 is turned off, transistor N4 is turned on to pull the level of control node B down to the low supply voltage VSSH, thereby turning off transistor P4, and transistor P3 is turned on to connect control node A to input node I1. In this way, the level of input node I1 can be pulled up to the high supply voltage VDDH via transistors P3 and P1. Since the level of input node I1 is higher than the low supply voltage VSSH, transistor P5 is turned off and transistor P6 is turned on to connect input node I1 to output node O1, thereby turning off transistor P2. In this way, the level of input node I1 can be pulled up to the high supply voltage VDDH to generate an output signal VO with a corresponding high level.

[0062] based on Figure 3A and Figure 3B As explained above, when the input signal SIN switches to a low level, the comparator circuit 120 can quickly pull down the output node O1 to a low power supply voltage VSSH. Thus, when the input signal SIN switches from a high level to a low level, the output signal VO can have a low-delay level switch with a rapidly falling transition edge (i.e., a falling edge). Conversely, when the input signal SIN switches to a high level, the level of the input node I1 is pulled up through the coordinated operation of the comparator circuit 130 and the high-level adjustment circuit 140, thereby raising the level of the output signal VO to a high power supply voltage VDDH. In some embodiments, in practical applications, the instantaneous time for the output signal VO to switch from a low level to a high level may be longer than the instantaneous time for the output signal VO to switch from a high level to a low level.

[0063] Figure 4A This is a schematic diagram of a level converter 400 provided in an embodiment of this application. Compared to Figure 2 In some embodiments, the level shifter 400 further includes a selection circuit 410, and the high-level adjustment circuit 140 does not include multiple inverters 142 and 144, and generates the output signal VO via the selection circuit 410. As mentioned earlier, in the aforementioned examples, the instantaneous time for the output signal VO to switch from a low level to a high level may be longer than the instantaneous time for the output signal VO to switch from a high level to a low level. To further ensure that the output signal VO can have a fast-rising transition edge (i.e., rising edge), the selection circuit 410 can be used to further generate the output signal VO according to the level of the output node O2.

[0064] In detail, the selection circuit 410 selects a corresponding node from output nodes O1 and O2 based on the levels of output nodes O1 and O2, and generates an output signal VO based on the level of this corresponding node. For example, the selection circuit 410 includes an inverter 411, an inverter 412, a logic gate 413, a logic gate 414, and a multiplexer 415. Inverter 411 generates signal S3 based on the level of output node O1. Inverter 412 generates signal S4 based on the level of output node O2. Logic gate 413 generates signal S5 based on signal S3 and the selection signal SEL. Logic gate 414 generates the selection signal SEL based on signals S4 and S5. In some embodiments, logic gates 413 and 414 may be (but are not limited to) NAND gates and may operate as SR flip-flops. The multiplexer 415 outputs signal S4 as output signal VO based on the selection signal SEL, or generates output signal VO based on the level of output node O1.

[0065] Figure 4B This is provided by the embodiments of this application. Figure 4A The waveform diagrams of the relevant signals are shown. When the input signal SIN is high, output node O1 is high and output node O2 is low. Under this condition, the selection signal SEL is low, so the multiplexer 415 generates the output signal VO according to the level of output node O1. When the input signal SIN switches from high to low, the level of output node O1 is quickly pulled down to the low power supply voltage VSSL by the comparator circuit 120, so the multiplexer 415 can generate the corresponding output signal VO according to the level of output node O1. Then, when the level of output node O2 is pulled up to the high power supply voltage VDDH by the coordinated operation of the high-level adjustment circuit 140 and the comparator circuit 130 (see reference...), Figure 3A The selection signal SEL is high. Under this condition, the output signal S4 of the multiplexer 415 is the output signal VO. When the input signal SIN switches from low to high, the level of the output node O2 can be quickly pulled down to the low supply voltage VSSL via the comparator circuit 130 (see reference). Figure 3B This allows signal S4 to have a rapidly rising transition edge. Thus, the multiplexer 415 can output this signal S4 as the output signal VO.

[0066] In other words, the selection circuit 410 can select a corresponding node from the output node O1 and the output node O2 according to the level of the output node O1 and the level of the output node O2, and the selection circuit 410 generates the output signal VO according to the level of the corresponding node when the level of the corresponding node switches from a high level (e.g., the high power voltage VDDH) to a low level (e.g., the low power voltage VSSL). In this way, the selection circuit 410 can generate the output signal VO according to the level with fast falling, thereby reducing the delay time of the level switching of the output signal VO.

[0067] Generally speaking, the operation speed of a circuit will gradually slow down as the circuit is used for a longer time. Since the selection circuit 410 can select the output node O1 of the comparison circuit 120 or the output node O2 of the comparison circuit 130 to generate the output signal VO, and the number of transistors used in the path for pulling down the output node O1 or the output node O2 is not large, the selection circuit 410 is less affected by the time of use. In other words, by using the selection circuit 410, the durability of the level shifter 400 can be further improved.

[0068] In the above embodiments, the transistors N1-N4 are N-type transistors, and the transistors P1-P8 are P-type transistors. The above transistors can be implemented by metal oxide semiconductor field effect transistors (MOSFETs), but the present application is not limited thereto. Various types or conductive types of transistors that can perform similar operations are also within the scope of the present application.

[0069] Figure 5 A schematic diagram of an input / output driver 500 according to some embodiments of the present application is shown. The input / output driver 500 includes a level shifter 510, a delay matching circuit 520, a non-overlapping circuit 530, and a protection circuit 540. The level shifter 510 can be implemented by the level shifter 100 of Figure 1 or Figure 2 or the level shifter 200 of Figure 4AThe level shifter 400 is implemented. The level shifter 510 can generate an output signal VO according to an input signal SIN. The delay matching circuit 520 generates an output signal VO' according to the input signal SIN, wherein the delay matching circuit 520 introduces a delay time to the input signal SIN which is the same as (or close to) the delay time introduced by the level shifter 510 to the input signal SIN. In other words, the non-overlapping circuit 530 receives the output signal VO and the output signal VO' at the same (or close) time. In some embodiments, the delay matching circuit 520 can have a similar circuit structure as the level shifter 510 (but operating in a different power domain) to achieve a close delay time. The non-overlapping circuit 530 generates a control signal SC1 according to the output signal VO and generates a control signal SC2 according to the output signal VO'. The non-overlapping circuit 530 can delay the output signal VO to generate the control signal SC1 and delay the output signal VO' to generate the control signal SC2, wherein there is a non-overlapping period between the control signal SC1 and the control signal SC2 (e.g. the time interval between the transition edge of the control signal SC1 and the transition edge of the control signal SC2).

[0070] The protection circuit 540 includes transistors MP1, MP2, MN1 and MN2 and diodes D1 and D2. The transistors MP1- MP4 and the diodes D1 and D2 operate the voltage protection circuit to provide basic voltage protection to the input / output point 501. The transistor MP1 receives the high power voltage VDDH and is selectively turned on according to the control signal SC1. The transistor MP2 is controlled by the clamping signal VP and is coupled to the input / output point 501. The transistor MN2 is controlled by the clamping signal VN and is coupled to the input / output point 501. The transistor MN1 receives the low power voltage VSS and is selectively turned on according to the control signal SC2.

[0071] By setting the non-overlapping period between the control signal SCI and the control signal SC2, it is ensured that the transistor MP1 and the transistor MN1 are not turned on at the same time, thereby avoiding the generation of short circuit current by the protection circuit 540. As mentioned above, in some related arts, there is an operation delay in the level shifter, resulting in a high uncertainty in the transition edge of the signal. If the level shifter of these technologies is used to generate the output signal VO, the transition edge of the control signal SCI generated by the non-overlapping circuit 530 will also be uncertain (i.e., the time point state of the control signal SCI cannot be accurately controlled). In this way, the non-overlapping period between the control signal SCI and the control signal SC2 can be too long to reduce the effect of the input-output driver 500. Alternatively, in some extreme cases, the transistor MP1 and the transistor MN1 can be turned on at the same time according to the control signal SCI and the control signal SC2, resulting in the generation of short circuit current. Compared with the above technologies, the level shifter 100 or the level shifter 400 provided by some embodiments of the present application can accurately control the time point state of the control signal SCI to ensure that the control signal SCI and the control signal SC2 have a certain non-overlapping period, and can accurately control the non-overlapping period to have a shorter time length, thereby improving the effect of the input-output driver 500.

[0072] In summary, the level shifter in some embodiments of the present application can provide an additional path to quickly adjust the level of the output node, thereby reducing the delay generated in the level switching process of the signal. In this way, the output signal generated by the level shifter can have a fast switching transition edge, thereby reducing the uncertainty of the transition edge of the output signal.

[0073] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application. Any such changes may fall within the scope of the patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be subject to the scope of the patent application defined in the specification.

Claims

1. A level shifter with low transmission delay, characterized in that, comprises: a low-level adjusting circuit selectively pulls a level of one of a first input node and a second input node to a first low power supply voltage according to an input signal; a first comparison circuit outputs a level of the first input node to a first output node with a higher level of a second low power supply voltage, wherein the second low power supply voltage is higher than the first low power supply voltage; and a high-level adjusting circuit selectively adjusts a level of the first output node according to the level of the first input node and a level of the second input node to generate an output signal. The first comparison circuit comprises: a first transistor selectively conducts according to the level of the first input node to transmit the second low power supply voltage to the first output node; and a second transistor selectively conducts according to the level of the first input node to connect the first input node to the first output node. The low-level adjusting circuit operates in a first power supply domain defined by the first low power supply voltage and a first high power supply voltage, and the high-level adjusting circuit operates in a second power supply domain defined by the second low power supply voltage and a second high power supply voltage, wherein the second high power supply voltage is higher than the first high power supply voltage.

2. The level shifter of claim 1, wherein, The low-level adjusting circuit comprises:

3. The level shifter of claim 1, wherein, a first inverter generating a first signal according to the input signal; a second inverter generating a second signal according to the first signal; a first transistor biased by a high power supply voltage and selectively pulling the level of the second input node to the first low power supply voltage according to the first signal; and a second transistor biased by the high power supply voltage and selectively pulling the level of the first input node to the first low power supply voltage according to the second signal. The high-level adjusting circuit comprises: a first transistor selectively pulling up a level of a first control node to a high power supply voltage according to a level of a second output node; 4. The level shifter of claim 1, wherein, a second transistor selectively pulling up a level of a second control node to the high power supply voltage according to a level of the first output node; a third transistor selectively pulling down the level of the first control node to a second low power supply voltage according to the level of the second control node; a fourth transistor selectively pulling down the level of the second control node to the second low power supply voltage according to the level of the first control node; a fifth transistor biased by the second low power supply voltage and selectively conducting according to the level of the first control node to adjust the level of the first input node; and a sixth transistor biased by the second low power supply voltage and selectively conducting according to the level of the second control node to adjust the level of the second input node. comprises: a low-level adjusting circuit selectively pulls a level of one of a first input node and a second input node to a first low power supply voltage according to an input signal; a first comparison circuit outputs a level of the first input node to a first output node with a higher level of a second low power supply voltage, wherein the second low power supply voltage is higher than the first low power supply voltage; and 5. A level shifter, characterized by, a high-level adjusting circuit selectively adjusts a level of the first output node according to the level of the first input node and a level of the second input node to generate an output signal. ​ ​ a high level adjusting circuit selectively adjusts a level of the first output node according to a level of the first input node and a level of the second input node to generate an output signal; a second comparing circuit outputs a higher one of the second input node and the second low power voltage to a second output node; wherein the high level adjusting circuit further selectively adjusts a level of the second output node according to the level of the first input node and the level of the second input node; a selecting circuit selects a corresponding node from the first output node and the second output node according to a level of the first output node and a level of the second output node, and generates the output signal according to a level of the corresponding node.

6. The level shifter of claim 5, wherein, The selecting circuit generates the output signal according to the level of the corresponding node when the level of the corresponding node switches from a first level to a second level, and the first level is higher than the second level.

7. The level shifter of claim 5, wherein, The selecting circuit includes: a first inverter generates a first signal according to the level of the first output node; a second inverter generates a second signal according to the level of the second output node; a first logic gate generates a third signal according to the first signal and a selection signal; a second logic gate generates the selection signal according to the second signal and the third signal; and a multiplexer outputs the second signal as the output signal according to the selection signal or generates the output signal according to the level of the first output node.

8. The level shifter of claim 5, wherein, The first comparing circuit is used to assist accelerating the level of the first output node to the second low power voltage when the input signal switches from a first level to a second level, and the first level is higher than the second level.

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