Sensor circuit

Abstract

A sensor circuit including a sensor input includes a delta-sigma analog-to-digital converter. The delta-sigma analog-to-digital converter includes a switched capacitor, a common-mode voltage source, a reference voltage source, and a switch network. The switch network connects the switched capacitor to charge it to a sum voltage or a difference voltage in a first clock phase, and connects the switched capacitor to transfer the charge to a summing node in a second clock phase. A controller controls the switch network in response to a comparator output to selectively connect the switched capacitor to one of the common-mode voltage and the reference voltage in the first clock phase. An embodiment of the sensor circuit transfers charge in each clock cycle and has low noise and high sensitivity.

Description

Technical Field

[0001] The present description generally relates to sensor circuits including delta-sigma analog-to-digital converters. The sensor circuits can be used with light sensors and other sensors. Background Art

[0002] For electronic devices such as mobile phones, it is useful to be able to sense ambient light levels, for example so that display lighting can be controlled to reduce power consumption. Previous disclosures of environmental sensor circuits include US2014 / 293272 (US9146162) and EP2863192. US 2014 / 293272 describes an integrating analog-to-digital converter that can switch between a light sensor and a temperature sensor. EP2863192 describes an analog-to-digital converter with two-stage operation, one stage including a charge balancing operation. Summary of the invention

[0003] Generally, a sensor circuit is described that includes a delta-sigma analog-to-digital converter having a switch network configuration that facilitates increased gain and lower noise operation compared to some prior art delta-sigma analog-to-digital conversion techniques.

[0004] According to a first aspect, a sensor circuit is provided that includes a sensor input. The sensor circuit may include a delta-sigma analog-to-digital converter, the delta-sigma analog-to-digital converter including a first integrator having a first summing node at a first integrator input, a first feedback capacitor, and a first integrator output. The sensor input may be coupled to the first summing node. The sensor circuit may also include a comparator that is coupled to the first integrator output and is configured to compare the first integrator output with a comparator reference to generate a comparator output. The sensor circuit may also include a digital output coupled to the comparator output and a converter clock.

[0005] The delta-sigma analog-to-digital converter may further include a first switched capacitor, a common-mode voltage (V cm ) common-mode voltage source, providing a reference voltage (V ref ) and a first switch network. The first switch network may be configured to: in a first clock phase, connect the first switch capacitor to one of a common mode voltage and a reference voltage to charge the switch capacitor to the sum of the common mode voltage and the reference voltage or the difference between the common mode voltage and the reference voltage, and in a second clock phase, connect the first switch capacitor to transfer charge from the first switch capacitor to a first summing node, and a controller that controls the first switch network in response to the comparator output to selectively connect the first switch capacitor to one of the common mode voltage and the reference voltage in the first clock phase.

[0006] In an embodiment, this approach allows the first switched capacitor to depend on the comparator output pair (V cm +V ref ) or (V cm -V ref ) for sampling. Therefore, in embodiments, the integrator output (and digital code) may depend on the period (frequency) of the clock rather than the total conversion time. However, simple implementations of this approach may result in clock feedthrough. The above-described implementation of the first switch network may significantly reduce this and other switch-related errors, such as those caused by charge injection. In some embodiments, V ref Can be less than V cm .

[0007] Some other advantages of the features described above and later include gain programmability, such as by changing the clock frequency or reference voltage. The described circuit configuration facilitates high gain and low noise, for example, resolving current in the fA range, which helps measure very low light levels. In an embodiment, the noise is reduced by the over-sampling ratio (OSR), and for a given gain, the noise can be independent of the sensed signal (light input). The described switching arrangement can provide noise shaping and facilitate extraction for improved signal-to-noise ratio (SNR) sensing.

[0008] Embodiments of the sensor circuit can measure both positive and negative photodiode currents, in particular photodiode leakage or dark current. A zero light condition corresponding to a zero current input can then be defined for a digital output; this can be defined as an intermediate code digital output.

[0009] In an embodiment, the switch network includes a controllable common mode voltage switch and a controllable reference voltage switch, each of which is coupled to a first terminal of a first switched capacitor. A controllable ground switch may be coupled to a second terminal of the first switched capacitor. A controllable integrator input switch may be coupled between the second terminal of the first switched capacitor and a summing node. This provides an efficient implementation of the first switch network.

[0010] The controller may then be configured to control the controllable common-mode voltage switch and the controllable reference voltage switch to connect the first terminal of the first switched capacitor to one of the common-mode voltage and the reference voltage in a first clock phase, and to control the controllable ground switch to ground the second terminal of the first switched capacitor. The controller may be configured to control the controllable integrator input to couple the second terminal of the first switched capacitor to the summing node in a second clock phase.

[0011] In an embodiment, the analog-to-digital converter further comprises a second integrator coupled between the first integrator and the comparator, the second integrator comprising a second summing node at the second integrator input, a second feedback capacitor, and a second integrator output, the second integrator input is coupled to the first integrator output, and the second integrator output is coupled to the comparator input. This can help to increase gain with low noise.

[0012] The sensor circuit may further include a coupling capacitor and a coupling switch network to couple the first integrator output to the second integrator input. The coupling switch network may be configured to first couple the voltage from the first integrator output to charge the coupling capacitor and then couple the charge from the coupling capacitor to the second integrator input. The gain of the sensor circuit may be determined by the ratio of the value of the second feedback capacitor to the value of the coupling capacitor.

[0013] In a particular embodiment, the coupling switch network includes: a first coupling switch coupling the first integrator output with a first terminal of a coupling capacitor; a second coupling switch coupling the first terminal of the coupling capacitor with a common-mode voltage source, a third coupling switch coupling the second terminal of the coupling capacitor to the second integrator input, and a fourth coupling switch coupling the second terminal of the coupling capacitor to the common-mode voltage source.

[0014] This facilitates coupling the two stages of a second-order delta-sigma analog-to-digital converter, where each stage includes a switching network as previously described.

[0015] Therefore, the sensor circuit may also include a second switched capacitor coupled to the second summing node, and a second switching network, which is configured to: in the second clock phase, connect the second switched capacitor to one of the common-mode voltage and the reference voltage to charge the switched capacitor to the sum of the common-mode voltage and the reference voltage or the difference between the common-mode voltage and the reference voltage, and in the first clock phase, connect the second switched capacitor to transfer charge from the switched capacitor to the second summing node.

[0016] In a second-order delta-sigma analog-to-digital converter, the converter clock may be configured to provide a first phase timing signal (φ1) defining a first clock phase and controlling a third coupling switch, a first further phase timing signal (φ2) controlling a second coupling switch, and 1d ), a second phase timing signal (φ2) defining a second clock phase and controlling a fourth coupling switch, and a second additional phase timing signal (φ) controlling the first coupling switch 2d ).

[0017] In an embodiment, one or more of the first switched capacitor, the coupling capacitor, the second switched capacitor, the first feedback capacitor, and the second feedback capacitor (where present) may be variable (e.g., a switched capacitor). This may facilitate programming the gain of the analog-to-digital converter. However, in some embodiments, it may be preferred to use a clock frequency and / or a reference voltage to vary the gain rather than introducing a switch into the signal path.

[0018] The sensor circuit may further include a decimator coupled between the comparator output and the digital output. This further helps reduce noise. In an embodiment, the decimator may include a cascaded integrator-comb (CIC) filter, such as a third-order CIC filter.

[0019] In an embodiment, the controller further comprises a latch circuit coupled between the comparator output and the controller to synchronize changes in the comparator output to one or both of the first clock phase and the second clock phase. This can help ensure non-overlapping control signals.

[0020] In some embodiments, the controller may further include logic circuitry to synchronize the comparator output synchronized with the first clock phase (φ1) with the first additional phase timing signal (φ 1d ) combination; and the comparator output synchronized with the second clock stage (φ2) and the second additional stage timing signal (φ 2d ) to generate a combination signal for a logic circuit to generate one or more control signals to control the first switch network. However, in some other embodiments, such logic circuits may be omitted, and switches of the first (or second) switch network, such as the controllable common-mode voltage switch and the controllable reference voltage switch, may be replicated.

[0021] In some implementations, the sensor circuit is configured to transfer charge to the first feedback capacitor at each clock cycle regardless of the comparator decision indicated by the comparator output.

[0022] The circuit may be used with a photodiode for a light sensor (such as an ambient light sensor) of an electronic device such as a portable computing device or a mobile phone. Thus, the photodiode may be coupled to the sensor input. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The sensor circuit will now be described by way of example embodiments with reference to the following drawings:

[0024] Figure 1 is a schematic diagram of an ambient light sensor system.

[0025] Figure 2 is a schematic diagram of a sensor circuit according to an embodiment.

[0026] Figure 3 is a schematic diagram of a first switch network according to an embodiment.

[0027] Figure 4 is a flowchart indicating the operation of the controller according to the embodiment.

[0028] FIG. 5( a ) is a schematic diagram of a switch network configured according to a first clock phase.

[0029] FIG5( b ) is a schematic diagram of a switch network configured according to the second clock phase.

[0030] Figure 6 is a schematic diagram of a sensor circuit with a second stage integrator according to an embodiment.

[0031] Figure 7 is a schematic diagram of a coupling circuit according to an embodiment.

[0032] Figure 8 is a schematic diagram of a second switch network according to an embodiment.

[0033] FIG9(a) is a diagram showing a timing circuit.

[0034] FIG. 9( b ) is a timing diagram showing output signals of the timing circuit of FIG. 9( a ).

[0035] Fig.10 is a schematic diagram showing a latch circuit according to an embodiment.

[0036] Fig.11 It shows that according to Fig.10 A timing diagram of input, output and intermediate signals of a latch circuit of an embodiment.

[0037] 12(a) and 12(b) are schematic diagrams of example sensor circuits according to an embodiment. DETAILED DESCRIPTION

[0038] A low noise, high sensitivity delta-sigma analog-to-digital converter sensor circuit for a sensor is described herein. The sensor may be a light sensor, such as an ambient light sensor; and the delta-sigma analog-to-digital converter may be a second order converter.

[0039] Figure 11 is a schematic diagram of an ambient light sensor system 100. The system includes a photodiode 101, an operational amplifier 102 configured to operate as an integrator via an integrating capacitor CF 103, a switched reference circuit 104 including a reference capacitor CREF, a comparator 105, and control logic 106 that provides a digital output 107 and optionally a trim signal 108 to control the offset of the operational amplifier 102. High and low (e.g., ground) reference voltages VREFh and VREFl are provided to the switched reference circuit 104.

[0040] In operation, the integrator integrates the current 101a through the photodiode, thereby ramping up the voltage at the output of the op amp. This voltage is compared to a reference voltage using a comparator. When the output voltage of the op amp crosses the reference voltage, the comparator triggers and provides a voltage at the output, and the process repeats. The number of times the comparator output is triggered in a given time is called the count; this count gives an indication of the ambient light level. The system uses an asynchronous clock.

[0041] The voltage provided at the output is given by:

[0042] (VREFl+VREFh)*(CF / CREF) Equation 1

[0043] The counting equation is:

[0044]

[0045] A low noise, high sensitivity delta-sigma analog-to-digital converter sensor circuit is now described. More specifically, a delta-sigma converter is described in which a charge dump includes two levels determined by a comparator. In an embodiment, the charge dump occurs at each clock cycle. In another embodiment, a second stage for the delta-sigma converter is provided. This enables an improved signal-to-noise ratio. A decimator can provide further improvements in signal-to-noise ratio and noise shaping.

[0046] In an embodiment, the output signal is proportional to the clock rate Tclk and is independent of the total conversion time compared to a conventional optical-to-digital converter. An embodiment has the ability to measure positive dark current and negative dark current (photodiode leakage, circuit leakage). The zero light condition (zero current input) can be called an intermediate code. In addition, gain programmability can be achieved by changing the clock rate and reference voltage. Results using an apparatus according to an embodiment of the present disclosure show that higher gain (up to 40 times) can be achieved compared to a conventional optical-to-digital converter. The device according to an embodiment of the present disclosure can also measure very low light levels with reduced noise.

[0047] In a first embodiment, a single-stage delta-sigma converter is provided. In this embodiment, a two-stage method is used. The sensor circuit includes a diode connected to the negative terminal of the integrator, a sampling network and a comparator, the sampling network being configured to sample a reference voltage in the first stage and transmit the sampled voltage to the integrator circuit in the second stage. The transmitted voltage depends on the comparator decision of the previous clock cycle. Two voltage levels are provided. In an embodiment, these voltages are a common mode voltage (referred to as Vcm) and a reference voltage Vref. Typically, the reference voltage is lower than the common mode voltage. In an embodiment, the common mode voltage is also the decision level voltage of the comparator. If the comparator decides to be high, the connected reference voltage is equal to Vcm+Vref, and if the comparator decides to be low, Vcm-Vref is connected. In this way, charge transfer occurs in each clock cycle, where the clock cycle Tclk includes a first stage and a second stage. Transfer occurs on each clock cycle, regardless of the comparator decision. Those skilled in the art will understand that there are alternative implementations, such as providing two voltage levels, one higher than the comparator decision level and one lower than the comparator decision level. The present invention is not limited to the details of the arrangement of the sampling circuit.

[0048] Using a single reference scheme to create balanced references Vrefp (Vcm+Vref) and Vrefn (Vcm-Vref)) can overcome the problem that small mismatches can lead to large errors in the output code. The single reference scheme uses only Vref and Vcm to create a balanced reference. In some embodiments, the switching timing described later is facilitated by latching the comparator outputs at each clock phase φ1 and φ2.

[0049] Figure 2 2 is a schematic diagram of a sensor circuit 200 according to an embodiment. The sensor circuit includes a sensor input 201, a delta-sigma analog-to-digital converter 202, a first switch network 203, a converter clock 204, and a controller 205. In an implementation, the sensor input 201 receives an analog input signal, such as a current input signal.

[0050] exist Figure 2 In the embodiment of FIG. 1 , the sensor input is shown as being attached to a photodiode 206. A second terminal of the photodiode can be connected to ground or another reference voltage. In some embodiments, the sensor circuit can have a multi-channel input and a digital output, such as by replicating Figure 2, and / or by multiplexing the circuit. For example, the photodiode 206 can sense more than one wavelength, for example, it can sense red, green and / or blue and / or can sense more than one of these colors. For example, a sensor such as a photopixel can be used, for example, with red, green, blue and clear filters on one or more light sensing elements (e.g., photodiodes). In other applications, the circuit can be used with other input devices, such as, but not limited to, temperature sensors.

[0051] The delta-sigma converter 202 includes a first integrator 207, a first feedback capacitor 208, a first integrator input 209, a first integrator output 210, and a comparator 211. The integrator has a first summing node 212 at the first integrator input, wherein the sensor input is coupled to the first summing node. In an embodiment, the integrator is configured as an inverting amplifier, wherein the negative terminal is the first integrator input and the positive terminal is at ground or another reference voltage. The output 210 of the first integrator is coupled to a first input 219 of the comparator 211. The second input 220 of the comparator is coupled to a reference voltage level, which in an embodiment is a common mode voltage. The output 221 of the comparator is connected to the controller 205 and may also provide a digital output from the analog-to-digital converter.

[0052] The sensor circuit also includes a first switched capacitor 213, which is charged to a first voltage level or a second voltage level in operation. In this embodiment, the first voltage level is equal to the sum of the common mode voltage and the reference voltage, and the second voltage level is equal to the difference between the common mode voltage and the reference voltage. In an embodiment, the common mode voltage is equal to the reference voltage of the comparator 211. The first switch network 203 controls the charging of the first switched capacitor and has a common mode voltage source 215 that provides the common mode voltage and a reference voltage source 216 that provides the reference voltage.

[0053] In operation, according to Figure 2 The device of an embodiment has two phases. In the first phase, the voltage is sampled by the first switching network. In the second phase, the first switching network is connected to the summing input of the integrator. In this way, a charge dump occurs onto the first feedback capacitor.

[0054] In an embodiment, the converter clock provides a first timing signal 217 and the second timing signal 218, to start the first phase and the second phase respectively. In the first phase, the first switch network is configured to connect the first switched capacitor to one or more voltage sources to provide a first voltage level or a second voltage level. In an embodiment, a common mode voltage and a reference voltage are provided to charge the switched capacitor to the sum of the common mode voltage and the reference voltage or the difference between the common mode voltage and the reference voltage.

[0055] In the second phase, the first switched capacitor is coupled to the summing node of the first integrator so as to transfer charge from the first switched capacitor to the first summing node. The level of the voltage is sampled by the first switched capacitor at the comparator output. If the comparator output is a logic "1", the voltage is equal to the first level, which is the sum of the common mode voltage and the reference voltage. If the comparator output is a logic "0", the voltage is equal to the second level, which is the difference between the common mode voltage and the reference voltage.

[0056] In an embodiment, the first switching network includes a controllable common-mode voltage switch and a controllable reference voltage switch, each coupled to a first terminal of a first switching capacitor, a controllable ground switch coupled to a second terminal of the first switching capacitor, and a controllable integrator input switch coupled between the second terminal of the first switching capacitor and a summing node.

[0057] Figure 3 3 is a schematic diagram of a switch network 300 according to an embodiment. A voltage source providing a common mode voltage 301, a voltage source providing a reference voltage 302, a controllable common mode voltage switch 303, a controllable reference voltage switch 304 and a controllable ground switch 305 are provided. The controllable common mode voltage switch 303 and the controllable reference voltage switch 304 are connected to a first terminal 306 of a first switched capacitor 307. The controllable common mode voltage switch 303 enables the first terminal 306 to be connected to the common mode voltage source 301, and the controllable reference voltage switch 304 enables the first terminal 306 to be connected to the reference voltage source 302. The controllable ground switch 305 enables a second terminal 308 of the first switched capacitor to be connected to ground 309. The controllable common mode voltage switch and the controllable reference voltage switch enable charging of the first switched capacitor 307. The first switch network further includes a controllable integrator input switch 310, which enables a second terminal of the first switched capacitor to be connected to an output 311 of the first switch network.

[0058] Figure 4 It is shown Figure 2Flowchart of the operating steps of an embodiment of the present invention. These steps are controlled by the controller 205 in response to the comparator decision and the first and second timing signals provided by the converter clock 204. After the first timing signal 401, if the comparator decision 402 is at a logic level "1" 405, the sampled voltage is set 404 to be equal to the sum of the common mode voltage and the reference voltage. If the comparator decision 402 is at a logic level "0" 403, the sampled voltage is set 406 to be equal to the difference between the common mode voltage and the reference voltage. The voltage is sampled 407 and the first switched capacitor is charged. Upon receiving the second timing signal 408, the first switched capacitor is coupled 409 to the summing node. This causes a charge to be dumped onto the first feedback capacitor.

[0059] Figure 5(a) and 5(b) are respectively shown during the first clock phase 500 and the second clock phase 501 Figure 3 Schematic diagram of a first switch network of an embodiment of an embodiment of the present invention. In FIG. 5( a), the controllable common mode voltage switch 303, the controllable reference voltage switch 304 and the controllable ground switch 305 are shown as closed to enable charging of the first switch capacitor. The controllable integrator input switch 310 is open. In FIG. 5( b), the controllable common mode voltage switch 303, the controllable reference voltage switch 304 and the controllable ground switch 305 are open, and the controllable integrator input switch 310 is closed to couple the switch capacitor to the summing node of the integrator circuit. During the second phase, coupling the switch capacitor to the summing node causes a charge dump onto the feedback capacitor of the integrator circuit. The charge dump can be at two levels, one corresponding to a first voltage level and a second corresponding to a second voltage level. The voltage level and therefore the level of the charge dump is controlled by a comparator decision of the previous clock cycle. In an embodiment, the first voltage level is equal to the sum of the common mode voltage and the reference voltage, and the second voltage level is equal to the difference between the common mode voltage and the reference voltage. The arrangement implements a mixed voltage and current input, wherein the sensor input is continuously connected to the integrator circuit.During a clock cycle comprising the first and second phases, the current from the sensor is accumulated on the first feedback capacitor.

[0060] In an embodiment, the delta-sigma converter is a two-stage device. Compared to a single-stage device, a two-stage delta-sigma converter can achieve increased noise reduction and thus improve the signal-to-noise ratio. In addition to the features of a single-stage device, a two-stage converter typically has a second integrator, a second feedback capacitor, a feedback circuit, and a coupling circuit for coupling the device to the first stage. The second stage receives an input from the first stage and provides an output to a comparator.

[0061] Figure 6 is a schematic diagram of a sensor circuit with a two-stage Σ-Δ converter according to an embodiment. Figure 6 The embodiments shown in Figure 2 The features of an embodiment of the present invention, and an additional second stage 601. A second integrator 602 coupled between the first integrator 207 and the comparator 211 is provided. The second integrator 602 includes a second summing node 603 at a second integrator input 604, a second feedback capacitor 605, and a second integrator output 606. The second integrator input 604 is coupled to the first integrator output 210, and the second integrator output 606 is coupled to the first comparator input 219. In an embodiment, the second integrator is configured as an inverting amplifier, wherein the negative terminal is the second integrator input and the positive terminal is at a reference voltage such as a common mode voltage. In an embodiment, a coupling switch network 607 is provided to connect the first and second stages of the delta-sigma converter. In an embodiment, a second switching circuit 608 with a second switching capacitor 609 is provided to provide a feedback circuit for the second stage integrator.

[0062] Figure 7 is a schematic diagram of a coupling switch network 700 according to an embodiment. The coupling switch network includes a first input 701, which is coupled to the first integrator output 210. A first coupling switch 702 couples the first integrator output via the first input 701 and couples a first terminal 703 of a coupling capacitor 704. A second coupling switch 705 couples the first terminal 703 of the coupling capacitor 704 and a common mode voltage source 706. A third coupling switch 707 couples a second terminal 708 of the coupling capacitor 704 to a common mode voltage source 709. A fourth coupling switch 710 couples the second terminal 708 of the coupling capacitor 704 to an output 711 of the coupling network, which is coupled to the second integrator input 604.

[0063] Figure 8 is a schematic diagram of a second switch network 800. The network includes a first input 801, a second input 802, a second controllable common voltage switch 803, a second controllable reference switch 804, a second switched capacitor 807 having a first terminal 806 and a second terminal 808, a second controllable ground switch 805 connected to ground 809, and a second controllable output switch 810 connected to an output 811. The first input 801 is connected to a common mode voltage source, the second input 802 is connected to a reference voltage source, and an output 811 of the second switch network is coupled to a summing node of a second integrator.

[0064] In an embodiment, the timing engine provides four timing signals in each clock cycle. FIG. 9( a) is a diagram of an arrangement of a timing engine 901. A clock signal 902 is received, and the timing engine 901 is configured to sequentially provide four timing signals, namely a first phase timing signal (φ1) 903 defining a first clock phase, a first additional phase timing signal (φ2) 904, and a second additional phase timing signal (φ3) 905. 1d) 904, a second phase timing signal (φ2) 905 defining a second clock phase and a second additional phase timing signal (φ2) 906 controlling the first coupling switch 2d )906.

[0065] FIG9( b) is a diagram of clock signals output by the timing engine of FIG9( a) according to an embodiment. The figure shows four output signals 903, 904, 905, 906, wherein the first additional timing signal 904 is a slightly delayed version of the first timing signal 903. The first timing signal leads the first additional timing signal by a first delay 907. The second timing signal is approximately inverted from the first timing signal, but there is a second delay 908 between the falling edge of the first timing signal and the rising edge of the second timing signal. The second additional timing signal lags the second timing signal by a third delay 909. The falling edge of the second additional timing signal leads the rising edge of the first timing input signal by a fourth delay 910. Thus, in an embodiment, φ 1d and φ 2d is the delayed clock of φ1 and φ2, and the first and second stage timing signals do not overlap as shown (i.e., φ1, φ2 1d Non-overlapping φ2, φ 2d ). The relative timing of the corresponding timing signals may be varied, and the present invention is not limited to any one particular timing sequence.

[0066] Timing signal and Respectively control the phase of the first switching circuit. Timing signal The first phase is initiated where the voltage is sampled in the first switching circuit and the first switching capacitor is charged using one of two voltage levels depending on the comparator output. A second phase is initiated in which the first switched capacitor is connected to the summing node of the first integrator and a charge dump onto the first feedback capacitor occurs.

[0067] In operation, the coupling switch network and the second switching network are controlled by the timing signal. The first coupling switch 702 is controlled by the second additional timing signal (φ 2d ) is controlled. The second coupling switch 705 is controlled by the first additional timing signal (φ 1d ). The third coupling switch 707 is controlled by the first signal (φ1). The fourth coupling switch 710 is controlled by the second timing signal (φ2).

[0068] In an embodiment, the timing signal and The second switch network is also controlled. In an embodiment, the timing of the switching is in the opposite order to the first switch network. The second network is configured such that the first timing signal controls the operation of the second controllable output switch 810 and the second timing signal controls the operation of the second controllable ground switch 805.

[0069] Fig.10 1 is a schematic diagram of a latch circuit according to an embodiment. The latch circuit includes a latch circuit input 1001, a first flip-flop 1002, a second flip-flop 1003, a first AND gate 1004, a second AND gate 1005, a third AND gate 1006, a fourth AND gate 1007, a first output 1028, a second output 1029, a third output 1030, and a fourth output 1031. There are also four timing signal inputs 1016, 1018, 1020, 1022 (for φ respectively) connected to the inputs of the AND gates. 2d ,φ 2d ,φ 1d ,φ 1d ). A first timing signal input 1016 and a second timing signal input 1018 linked to the inputs of the first and second AND gates, respectively, receive a signal from the second additional timing signal. A third timing signal input 1020 and a fourth timing signal input 1022 linked to the inputs of the third and fourth AND gates, respectively, receive a signal from the first additional timing signal. The first flip-flop 1002 has a first input 1008 connected to an input 1001 of a latch circuit, the input 1001 of the latch circuit receiving an input for the output of the comparator. A second input 1009 of the first flip-flop receives a signal from the second timing signal. The second flip-flop also receives a first input 1012 from the input of the latch circuit 1001 and a second input 1013 of the second flip-flop from the first timing signal. A first output 1010 and a second output 1011 of the first flip-flop are output to the second inputs of the first and second AND gates, respectively. A first output 1014 and a second output 1015 of the second flip-flop are provided to the second inputs of the third and fourth AND gates, respectively. The output of the first AND gate 1024 is connected to a first output 1028 of the latch circuit. The output of the second AND gate 1025 is connected to the second output 1029 of the latch circuit. The output of the third AND gate 1026 is connected to the third output 1030 of the latch circuit. The output of the fourth AND gate 1027 is connected to the fourth output 1031 of the latch circuit. In an embodiment, the first output 1028 and the third output 1030 are connected to the control terminal of the controllable reference voltage switch 304, and the second output 1029 and the fourth output 1031 are connected to the control terminal of the common mode voltage switch 305.

[0070] In an embodiment, the first output 1028 and the third output 1030 are additionally connected to a control terminal of the second controllable reference switch 804, and the second output 1029 and the fourth output 1031 are additionally connected to a control terminal of the common mode voltage switch 305. In an embodiment, the second output 1029 and the fourth output 1031 are additionally connected to the second coupling switch 705 and the third coupling switch 707.

[0071] Fig.11 1 is a timing diagram showing the timing input, intermediate signals and output of the latch circuit. The input includes a first timing signal 1102 and a second timing signal 1103 derived from a clock signal 1101 by a timing engine. Two intermediate signals 1104 and 1105 are first outputs of the first flip-flop and the second flip-flop, respectively. Four output signals 1106, 1107, 1108, and 1109 are output to the first latch output 1028, the second latch output 1029, the third latch output 1030, and the fourth latch output 1031, respectively. These outputs provide control signals for common mode voltage and reference voltage.

[0072] FIG. 12A is a sensor circuit according to an embodiment. The embodiment includes Figure 3 The first switch network 1201 of the embodiment of Figure 8 The first stage integrator 1202, the photodiode 1203, and the second switch network 1204 of the embodiment of the invention. The integrator 1202 may be provided with a controllable auto-zero switch AZ configured to connect the integrator input. Figure 7 In an embodiment of the present invention, the sensor circuit may include a coupling network 1205. The sensor circuit may also include, for example, Fig.10 The second stage integrator 1206, the comparator 1207 and the latch circuit 1208 of the embodiment. The latch circuit 1208 may include a logic block 1215, the logic block 1215 is combined Fig.10 The signals shown in FIG. 1 are used to provide a control signal P_V to the first switch network 1201, for example, through an OR operation. REF 、V_V CM. The system is controlled by a clock and timing engine 1209, such as shown in Figure 9(a). A decimator 1210 or other filter can be used to filter a digital output derived, for example, from a comparator output (Q) of the circuit to provide a multi-bit (e.g., 16-bit) digital output 1216, which is a digitized version of the analog input signal. Alternatively, the digital signal derived from the comparator output can be used as a digital output signal without further filtering. In an embodiment, the decimator 1210 includes a third-order decimator. In an embodiment, gain can be achieved by selecting the relative capacitance of the second switched capacitor and the second feedback capacitor. A typical ratio of capacitances is 1:4, but the present invention is not limited to any given ratio and subsequent gain value. As shown, a flip switch can be used to reduce switch-induced errors. This has been shown to achieve 50% better performance.

[0073] In an embodiment, gain programmability is achieved through Vref, and Tclk, rather than introducing programmability in the feedback capacitor (which would have more switches in the signal path and therefore be prone to more switch-induced errors). Noise can be further reduced by oversampling. The architecture according to the embodiment can achieve the same noise performance regardless of the optical input for a given gain setting. Compared to conventional asynchronous optical-to-digital converters, the architecture according to the embodiment can achieve very low noise performance.

[0074] In an embodiment, the output code may be truncated to 16 bits. Therefore, the digital output code (code) may be given by the following equation:

[0075]

[0076] Where Iphoto is the photodiode current, Tclk is the frequency of Σ-Δ operation, 4*C S1 is the feedback capacitor, and Vref is the reference voltage. Other truncations are possible, and the invention is not limited to any one encoding scheme.

[0077] Figure 12b An alternative sensor circuit according to an embodiment is shown; elements identical to those of FIG. 12( a) are denoted by the same reference numerals. In the alternative sensor circuit, instead of using an Figure 3 The first switch network 1201 of the embodiment, but one or both of the first switch network 1201 and the second switch network 1204 include a V CM and V REF Each of the two switches has a pair of switches. These switches can be controlled by the signal QB.φ 1d 、Q.φ 2d and Q.φ 1d 、QB.φ 2dcontrol, where Q represents the (synchronous) comparator output (and ).

[0078] List of reference numerals:

[0079] 100 Schematic diagram of ambient light sensor system

[0080] 101 Photodiode

[0081] 101a Photodiode current

[0082] 102 Operational Amplifier

[0083] 103 Integrating capacitor

[0084] 104 Switch Reference Circuit

[0085] 105 Comparator

[0086] 106 Control Logic

[0087] 107 Digital outputs

[0088] 108 Fine-tuning signal

[0089] Schematic diagram of the 200 sensor circuit

[0090] 201 Sensor Input

[0091] 202 Delta-Sigma Analog-to-Digital Converter

[0092] 203 First Switch Network

[0093] 204 Converter Clock

[0094] 205 Controller

[0095] 206 Photodiode

[0096] 207 First Integrator

[0097] 208 First feedback capacitor

[0098] 209 First integrator input

[0099] 210 First integrator output

[0100] 211 Comparator

[0101] 212 First summing node

[0102] 213 First switched capacitor

[0103] 215 Common-mode voltage source

[0104] 216 Reference voltage source

[0105] 217 First timing signal

[0106] 218 Second timing signal

[0107] 219 First comparator input

[0108] 220 Second comparator input

[0109] 221 Comparator output

[0110] 300 Switching Network

[0111] 301 Common mode voltage

[0112] 302 Reference voltage

[0113] 303 Controllable Common Mode Voltage Switch

[0114] 304 Controllable reference voltage switch

[0115] 305 Controllable earthing switch

[0116] 306 A first terminal of a first switched capacitor

[0117] 307 First switched capacitor

[0118] 308 The second terminal of the first switched capacitor

[0119] 309 Land

[0120] 310 Controllable integrator input switch

[0121] 311 Output of the first switch network

[0122] 401 First timing signal

[0123] 402 Comparator judgment

[0124] 403 Comparator determines logic level "0"

[0125] 404 The sampling voltage is set to Vcm-Vref

[0126] 405 Comparator determines logic level "1"

[0127] 406 The sampling voltage is set to Vcm+Vref

[0128] 407 Voltage Sampling

[0129] 408 Receive the second timing signal

[0130] 409 coupling the second terminal of the first switched capacitor to the summing node

[0131] 500 First Clock Phase

[0132] 501 Second Clock Phase

[0133] 601 Second Level

[0134] 602 Second Integrator

[0135] 603 Second summing node

[0136] 604 Second integrator input

[0137] 605 Second feedback capacitor

[0138] 606 Second integrator output

[0139] 607 Coupled Switch Network

[0140] 608 Second switch circuit

[0141] 609 Second switched capacitor

[0142] 700 Coupled Switch Network

[0143] 701 First Input

[0144] 702 first coupling switch

[0145] 703 First terminal of coupling capacitor

[0146] 704 Coupling capacitor

[0147] 705 Second coupling switch

[0148] 706 Common Mode Voltage Source

[0149] 707 third coupling switch fourth coupling switch

[0150] 708 Second terminal of coupling capacitor

[0151] 709 Common Mode Voltage Source

[0152] 710 Fourth coupling switch

[0153] 711 Output of coupling network

[0154] 800 Second Switch Network

[0155] 801 First Input

[0156] 802 Second Input

[0157] 803 Second controllable common voltage switch

[0158] 804 Second controllable reference switch

[0159] 805 Second controllable earthing switch

[0160] 806 First terminal

[0161] 807 Second switched capacitor

[0162] 808 Second terminal

[0163] 809 Land

[0164] 810 Second controllable output switch

[0165] 811 Output

[0166] 901 Timing Engine

[0167] 902 Clock signal

[0168] 903 First stage timing signal

[0169] 904 First additional stage timing signal

[0170] 905 Second stage timing signal

[0171] 906 Second additional stage timing signal

[0172] 907 First Delay

[0173] 908 Second Delay

[0174] 909 Third Delay

[0175] 910 Fourth Delay

[0176] 1001 Latch circuit input

[0177] 1002 First Trigger

[0178] 1003 Second Trigger

[0179] 1004 First AND Gate

[0180] 1005 Second AND Gate

[0181] 1006 The third AND gate

[0182] 1007 Fourth AND Gate

[0183] 1008 First Output

[0184] 1009 The second input of the first trigger

[0185] 1010 The first output of the first trigger

[0186] 1011 The second output of the first flip-flop

[0187] 1012 The first input of the second trigger

[0188] 1013 The second input of the second trigger

[0189] 1014 The first output of the second flip-flop

[0190] 1015 The second output of the second flip-flop

[0191] 1016 Timing signal input

[0192] 1018 Timing signal input

[0193] 1020 Timing signal input

[0194] 1022 Timing signal input

[0195] 1024 Output of the first AND gate

[0196] 1025 Output of the second AND gate

[0197] 1026 Output of the third AND gate

[0198] 1027 Output of the fourth AND gate

[0199] 1028 The first output of the latch circuit

[0200] 1029 The second output of the latch circuit

[0201] 1030 The second output of the latch circuit

[0202] 1031 The second output of the latch circuit

[0203] 1201 First Switch Network

[0204] 1202 First-stage integrator

[0205] 1203 Photodiode

[0206] 1204 Second switch network

[0207] 1205 Coupling Network

[0208] 1206 Second stage integrator

[0209] 1207 Comparator

[0210] 1208 Latch Circuit

[0211] 1209 Timing Engine

[0212] 1210 Extractor

[0213] 1215 Logic Block

[0214] 1216 Digital Output

[0215] Features of circuits and methods that have been described or depicted in combination herein, for example in the embodiments, may be implemented individually or in sub-combinations. Features from different embodiments may be combined. Therefore, each feature disclosed or shown in this specification may be incorporated into the present invention individually or in any suitable combination with any other features disclosed or shown herein. Unless otherwise specified, method steps should not be construed as requiring a particular order, such as the order in which they are described or depicted.

[0216] Various aspects of the method and system have been described according to embodiments, but these embodiments are only illustrative, and the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and substitutions in light of this disclosure, which are considered to fall within the scope of the claims.

Claims

1. A sensor circuit comprising: Sensor input; Delta-Sigma Analog-to-Digital Converters, including: a first integrator having a first summing node at a first integrator input, a first feedback capacitor, and a first integrator output, wherein the sensor input is coupled to the first summing node, a comparator coupled to the first integrator output and configured to compare the first integrator output with a comparator reference to generate a comparator output, digital output, which is coupled to the comparator output, and Converter clock; Wherein, the delta-sigma analog-to-digital converter further comprises: a first switched capacitor; A common mode voltage source for providing a common mode voltage; A reference voltage source for providing a reference voltage; a first switch network configured to: connect the first switch capacitor to one of the common mode voltage and the reference voltage in a first clock phase to charge the first switch capacitor to a sum of the common mode voltage and the reference voltage or a difference between the common mode voltage and the reference voltage, and connect the first switch capacitor to transfer charge from the first switch capacitor to the first summing node in a second clock phase; A controller controls the first switch network in response to the comparator output to selectively connect the first switched capacitor to one of the common mode voltage and the reference voltage in the first clock phase.

2. The sensor circuit of claim 1 , wherein the switch network comprises a controllable common-mode voltage switch and a controllable reference voltage switch, each coupled to a first terminal of the first switch capacitor, a controllable ground switch coupled to a second terminal of the first switch capacitor, and a controllable integrator input switch coupled between the second terminal of the first switch capacitor and the summing node.

3. The sensor circuit of claim 2 , wherein the controller is configured to control the controllable common-mode voltage switch and the controllable reference voltage switch in the first clock phase to connect the first terminal of the first switched capacitor to one of the common-mode voltage and the reference voltage, and to control the controllable grounding switch to ground the second terminal of the first switched capacitor, and is configured to control the controllable integrator input in the second clock phase to couple the second terminal of the first switched capacitor to the summing node.

4. The sensor circuit of any one of claims 1 to 3, wherein the delta-sigma analog-to-digital converter further comprises a second integrator coupled between the first integrator and the comparator, the second integrator comprising a second summing node at a second integrator input, a second feedback capacitor, and a second integrator output, the second integrator input being coupled to the first integrator output, and the second integrator output being coupled to the comparator input.

5. The sensor circuit of claim 4 further comprising a coupling capacitor and a coupling switch network to couple the first integrator output to the second integrator input, wherein the coupling switch network is configured to first couple a voltage from the first integrator output to charge the coupling capacitor and then couple the charge from the coupling capacitor to the second integrator input.

6. The sensor circuit of claim 5, wherein the coupling switch network comprises: a first coupling switch coupling the first integrator output to a first terminal of the coupling capacitor; a second coupling switch coupling the first terminal of the coupling capacitor with the common mode voltage source; a third coupling switch coupling a second terminal of the coupling capacitor to the second integrator input; as well as A fourth coupling switch couples the second terminal of the coupling capacitor to the common mode voltage source.

7. The sensor circuit according to claim 5 further includes a second switched capacitor coupled to the second summing node, and a second switching network, wherein the second switching network is configured to connect the second switched capacitor to one of the common-mode voltage and the reference voltage in the second clock phase to charge the second switched capacitor to the sum of the common-mode voltage and the reference voltage or the difference between the common-mode voltage and the reference voltage, and to connect the second switched capacitor in the first clock phase to transfer charge from the second switched capacitor to the second summing node.

8. The sensor circuit according to claim 6, wherein: The converter clock is configured to provide: a first phase timing signal (φ1) defining the first clock phase and controlling the third coupling switch; The first additional phase timing signal (φ) for controlling the second coupling switch 1d ); a second phase timing signal (φ2) defining the second clock phase and controlling the fourth coupling switch; and A second additional phase timing signal (φ) for controlling the first coupling switch 2d ). 9 . The sensor circuit of claim 5 , wherein a gain of the sensor circuit is determined by a ratio of a value of the second feedback capacitor to a value of the coupling capacitor. 10 . The sensor circuit of claim 7 , wherein one or more of the first switched capacitor, the coupling capacitor, the second switched capacitor, the first feedback capacitor, and the second feedback capacitor are variable capacitors.

11. The sensor circuit of any one of claims 1 to 3, further comprising a decimator coupled between the comparator output and the digital output.

12. The sensor circuit according to any one of claims 1 to 3, wherein the controller further comprises a latch circuit coupled between the comparator output and the controller to synchronize a change of the comparator output to one or both of the first clock phase and the second clock phase.

13. The sensor circuit of claim 8, wherein the controller further comprises a latch circuit coupled between the comparator output and the controller to synchronize changes in the comparator output to one or both of the first clock phase and the second clock phase, wherein the controller further comprises a logic circuit and is configured to i) synchronize the comparator output synchronized with the first clock phase (φ1) with the first additional phase timing signal (φ2); 1d ) and ii) combining the comparator output synchronized with the second clock phase (φ2) with the second additional phase timing signal (φ 2d ) to generate a combination signal for the logic circuit to generate one or more control signals to control the first switch network.

14. The sensor circuit of any one of claims 1 to 3, configured to transfer charge to the first feedback capacitor at each clock cycle regardless of a comparator decision indicated by the comparator output.

15. A light sensor comprising a sensor circuit according to any one of claims 1 to 14 and a photodiode, wherein the photodiode is coupled to the sensor input.

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