Field programmable gate array circuit, configuration parameter determination method and electronic device

Abstract

The application discloses a field programmable gate array circuit, a configuration parameter determination method and electronic equipment. The circuit comprises a plurality of cascaded logic blocks, a clock circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit is used for duty cycle adjustment on a first clock signal output by the clock circuit to obtain a second clock signal, and the rising edge of the second clock signal has an offset compared with the rising edge of the first clock signal. One of the first clock signal and the second clock signal is used for timing control on each logic block, so that at least one logic block that does not meet a condition in the plurality of logic blocks delays to meet a delay constraint condition when timing control is performed by using the second clock signal. The logic block that does not meet the condition is a logic block that does not meet a constraint condition when timing control is performed by using the first clock signal. Clock signals corresponding to any two logic blocks are the same or different.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a field programmable gate array circuit, a configuration parameter determination method and an electronic device. BACKGROUND

[0002] A field programmable gate array (FPGA) is a chip with strong versatility, and thus has an irreplaceable position in a chip market with a wide variety of chips.

[0003] The FPGA usually includes a plurality of cascaded logic blocks and a clock circuit providing clock signals to the logic blocks. The clock circuit needs to provide clock signals to the plurality of logic blocks at the same time. The logic block usually includes a plurality of registers. At a rising edge of a clock signal of a clock cycle, data is transmitted from an input end to an output end of the register and remains unchanged until the rising edge of the next clock cycle. Due to the inherent delay attribute of a complementary metal oxide semiconductor (CMOS) device such as a register, if the data changes at a time before and after the rising edge of the clock signal, a register data sampling error will be caused. The time before the rising edge is referred to as a setup time, and the time after the rising edge is referred to as a hold time. That is, the time when the data reaches the input end of the register cannot be within the setup time and the hold time. Since the plurality of cascaded logic blocks are controlled by one clock signal, and the delay of data transmission between adjacent logic blocks is not a fixed value, the one clock signal cannot guarantee that the input end of each register receives data that meets the requirements of the setup time and the hold time.

[0004] In the related art, a solution to the problem by using a delay circuit is provided. For example, the time when the data reaches the register in the first logic block overlaps with the setup time, and the time when the data reaches the register in the second logic block is still a long distance from the beginning of the setup time. At this time, the rising edge of the clock signal of the first logic block can be moved backward by borrowing the time of the second logic block, so that the time when the data reaches the register of the first logic block no longer overlaps with the setup time. The delay circuit can be implemented by connecting a plurality of delay modules in series. However, since each delay module can only move the clock signal backward for a short time, only a small delay of the clock signal can be achieved. SUMMARY

[0005] The application provides a field programmable gate array circuit, a configuration parameter determination method and an electronic device. A duty cycle adjustment circuit is used to adjust the duty cycle of a clock signal, so that the rising edge of the clock signal can be greatly delayed, thereby solving the timing problem that cannot be solved by a delay module in the related art.

[0006] In a first aspect, the application provides an FPGA circuit, comprising a plurality of cascaded logic blocks, a clock circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit is connected to the clock circuit and the plurality of cascaded logic blocks.

[0007] The clock circuit provides a first clock signal. The duty cycle adjustment circuit adjusts the duty cycle of the first clock signal to obtain a second clock signal, and the rising edge of the second clock signal is offset compared with the rising edge of the first clock signal. Then, one of the first clock signal and the second clock signal is output to each logic block in the plurality of cascaded logic blocks. Each logic block selects one of the first clock signal and the second clock signal for timing control, rather than each logic block selecting the first clock signal for timing control. The purpose of this is to enable a logic block whose timing delay does not meet the constraint condition when using the first clock signal for timing control to meet the constraint condition when using the second clock signal for timing control.

[0008] In the application, the first clock signal output by the clock circuit is adjusted in duty cycle by the duty cycle adjustment circuit, so that the rising edge of the first clock signal is offset to become the second clock signal. The first clock signal and the second clock signal are used for timing control of the logic block. Since the second clock signal obtained by duty cycle adjustment can be greatly delayed compared with the rising edge of the first clock signal, the timing problem caused by the small delay of the rising edge of the clock signal in the related art delay module can be solved. At the same time, the second clock signal obtained by duty cycle adjustment can also be slightly delayed compared with the rising edge of the first clock signal, so that the circuit structure can meet the clock signal adjustment requirements in different situations.

[0009] It should be noted that the rising edge offset here refers to the forward or backward movement of the rising edge of the first clock signal, which is usually backward movement, and the forward or backward movement time is not an integer multiple of the period of the first clock signal.

[0010] In a possible implementation, the duty cycle adjustment circuit first inverts the first clock signal, i.e. makes the rising edge and the falling edge of the first clock signal opposite, and then adjusts the duty cycle of the inverted first clock signal to obtain the second clock signal.

[0011] In the implementation, the duty cycle adjustment circuit is first flipped, so that the falling edge of the first clock signal becomes the rising edge of the second clock signal, and the rising edge of the second clock signal has been offset from the rising edge of the first clock signal, and then duty cycle adjustment is performed to obtain the final second clock signal. When a large degree of offset is required for the first clock signal, the flipping first reduces the adjustment amount in subsequent duty cycle adjustment, saves the processing amount of duty cycle adjustment, and speeds up the processing speed.

[0012] In a possible implementation, the plurality of cascaded logic blocks includes a first logic block and a second logic block, the first logic block and the second logic block are two logic blocks in cascade, and the first logic block is before the second logic block, that is, the output of the first logic block is connected to the input of the second logic block.

[0013] The first logic block is controlled in timing by using a first clock signal, and the second logic block is controlled in timing by using a second clock signal. At this time, the delay constraint condition is as follows:

[0014] Tck1+Tc1_min>Tshift+Th;

[0015] Tck1+Tc1_max<Tshift+Tcycle-Tsu;

[0016] Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, Tck1 is the time from the rising edge of the first clock signal to the appearance of data at the output end of the first logic block, Tc1_min is the shortest time for data to be transmitted from the first logic block to the second logic block, Tc1_max is the longest time for data to be transmitted from the first logic block to the second logic block, Th is the hold time of the first logic block and the second logic block, Tsu is the setup time of the first logic block and the second logic block, and Tcycle is the cycle time of the first clock signal and the second clock signal.

[0017] In another possible implementation, the plurality of cascaded logic blocks includes a second logic block and a third logic block, the second logic block and the third logic block are two logic blocks in cascade, and the second logic block is before the third logic block, that is, the output of the second logic block is connected to the input of the third logic block.

[0018] The second logic block is controlled in timing by using a second clock signal, and the third logic block is controlled in timing by using a first clock signal. At this time, the delay constraint condition is as follows:

[0019] Tck2+Tc2_min>Th-Tshift;

[0020] Tck2+Tc2_max<Tcycle-Tshift-Tsu;

[0021] Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, Tck2 is the time from the rising edge of the second clock signal to the appearance of data at the output end of the second logic block, Tc2_min is the shortest time for data to be transmitted from the second logic block to the third logic block, Tc2_max is the longest time for data to be transmitted from the second logic block to the third logic block, Th is the hold time of the second logic block and the third logic block, Tsu is the setup time of the second logic block and the third logic block, and Tcycle is the cycle time of the first clock signal and the second clock signal.

[0022] Exemplarily, the logic block comprises a plurality of cascaded registers, a plurality of multi-level serially connected selectors, and a plurality of delay modules.

[0023] The input ends of the first-level selector in the plurality of multi-level serially connected selectors are respectively used to receive the first clock signal and the second clock signal, and are used to select one of them for timing control of the logic block.

[0024] The output end of the last-level selector in the plurality of multi-level serially connected selectors is respectively connected with the plurality of cascaded registers, so as to output the clock signal that has passed through the plurality of multi-level serially connected selectors to each register.

[0025] A delay module is connected between any two adjacent selectors, one input end of the selector is connected with the output end of the previous-level selector through the delay module, and the other input end of the selector is directly connected with the output end of the previous-level selector. Through the above connection, each selector starting from the second-level selector can select whether to delay the clock signal, so as to select the length of the delay time.

[0026] In a second aspect, the present application provides a method for determining FPGA circuit configuration parameters, which comprises:

[0027] Obtaining delay constraint conditions of a plurality of cascaded logic blocks and time delay information of the plurality of cascaded logic blocks;

[0028] Determining an offset based on the delay constraint conditions of the plurality of cascaded logic blocks and the time delay information of the plurality of cascaded logic blocks.

[0029] Based on the offset, a configuration parameter of a duty cycle adjustment circuit is determined, the configuration parameter being used to control the duty cycle adjustment circuit to adjust a duty cycle of the first clock signal to obtain a second clock signal, a rising edge of the second clock signal having an offset compared with a rising edge of the first clock signal; the duty cycle adjustment circuit is used to perform timing control on each logic block by using one of the first clock signal and the second clock signal, so that at least one logic block that does not meet a condition in the plurality of logic blocks delays to meet a delay constraint condition when the timing control is performed by using the second clock signal, the logic block that does not meet the condition being a logic block that does not delay to meet a constraint condition when the timing control is performed by using the first clock signal, and clock signals corresponding to any two logic blocks being the same or different.

[0030] Exemplarily, the delay information of the plurality of cascaded logic blocks includes:

[0031] a time from a rising edge of the clock signal to appearance of data at an output end of each logic block, a shortest time of data transmission between adjacent two logic blocks, a longest time of data transmission between adjacent two logic blocks, a hold time of the logic block, a setup time of the logic block, and a cycle time of the clock signal.

[0032] Exemplarily, the plurality of cascaded logic blocks include a first logic block and a second logic block connected to an output end of the first logic block, a clock end of the first logic block being used to receive the first clock signal, a clock end of the second logic block being used to receive the second clock signal,

[0033] The delay constraint condition is as follows:

[0034] Tck1+Tc1_min>Tshift+Th;

[0035] Tck1+Tc1_max

[0036] Tshift is an offset of a rising edge of the second clock signal relative to a rising edge of the first clock signal, Tck1 is a time from the rising edge of the first clock signal to appearance of data at an output end of the first logic block, Tc1_min is a shortest time of data transmission from the first logic block to the second logic block, Tc1_max is a longest time of data transmission from the first logic block to the second logic block, Th is a hold time of the first logic block and the second logic block, Tsu is a setup time of the first logic block and the second logic block, and Tcycle is a cycle time of the first clock signal and the second clock signal.

[0037] Exemplarily, the plurality of cascaded logic blocks include a second logic block and a third logic block connected to an output end of the second logic block, a clock end of the second logic block being used to receive the second clock signal, a clock end of the third logic block being used to receive the first clock signal,

[0038] The delay constraint condition is as follows:

[0039] Tck2+Tc2_min>Th-Tshift;

[0040] Tck2+Tc2_max<Tcycle-Tshift-Tsu;

[0041] Tshift is an offset of a rising edge of the second clock signal relative to a rising edge of the first clock signal, Tck2 is a time from the rising edge of the second clock signal to appearance of data at an output end of the second logic block, Tc2_min is a shortest time for data to be transmitted from the second logic block to the third logic block, Tc2_max is a longest time for data to be transmitted from the second logic block to the third logic block, Th is a hold time of the second logic block and the third logic block, Tsu is a setup time of the second logic block and the third logic block, and Tcycle is a cycle time of the first clock signal and the second clock signal.

[0042] Optionally, the offset is determined based on the delay constraint condition of the plurality of cascaded logic blocks and the delay information of the plurality of cascaded logic blocks, and the determining comprises:

[0043] when there are a plurality of logic blocks that do not satisfy the condition, selecting a plurality of offset values in steps;

[0044] determining a first offset value from the plurality of offset values as the offset, the first offset value corresponding to the second clock signal that makes a first number of the logic blocks that do not satisfy the condition satisfy the delay constraint condition, and other offset values in the plurality of offset values corresponding to the second clock signal that makes a second number of the logic blocks that do not satisfy the condition satisfy the delay constraint condition, the second number being less than or equal to the first number.

[0045] In a third aspect, at least one embodiment of the present application provides an electronic device, comprising a processor and a memory; the memory is used to store a software program and a module, and the processor realizes the method in any possible implementation manner of the second aspect above by running or executing the software program and / or the module stored in the memory.

[0046] Optionally, the processor is one or more, and the memory is one or more.

[0047] Optionally, the memory can be integrated with the processor, or the memory and the processor are separately arranged.

[0048] In a specific implementation process, the memory can be a non-transitory memory, for example, a read only memory (ROM), which can be integrated on the same chip with the processor, or can be separately arranged on different chips. The type of memory and the arrangement manner of the memory and the processor are not limited in the embodiments of the present application.

[0049] In a fourth aspect, at least one embodiment of the present application provides a computer program (product), which comprises computer program code, when the computer program code is run by a computer, the computer program code causes the computer to execute the method in any possible implementation manner of the second aspect.

[0050] In a fifth aspect, at least one embodiment of the present application provides a computer readable storage medium, which is used to store program code executed by a processor, and the program code comprises code for implementing the method in any possible implementation manner of the second aspect.

[0051] In a sixth aspect, a chip is provided, which comprises a processor, and the processor is used to call and run instructions stored in a memory, so that a communication device installed with the chip executes the method in any possible implementation manner of the second aspect.

[0052] In a seventh aspect, another chip is provided, which comprises an input interface, an output interface, a processor and a memory, and the input interface, the output interface, the processor and the memory are connected through an internal connection path. The processor is used to execute code in the memory, and when the code is executed, the processor is used to execute the method in any possible implementation manner of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 is a structural schematic diagram of an FPGA circuit provided by an embodiment of the present application;

[0054] Figure 2 is a structural schematic diagram of a multi-stage logic block provided by an embodiment of the present application;

[0055] Figure 3 is a timing schematic diagram provided by an embodiment of the present application;

[0056] Figure 4 is a timing schematic diagram provided by an embodiment of the present application;

[0057] Figure 5 is a structural schematic diagram of a multi-stage logic block provided by an embodiment of the present application;

[0058] Figure 6 is a structural schematic diagram of a logic block provided by an embodiment of the present application;

[0059] Figure 7 is a timing schematic diagram provided by an embodiment of the present application;

[0060] Figure 8 is a flowchart of an FPGA circuit configuration parameter determination method provided by an embodiment of the present application;

[0061] Figure 9 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0062] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0063] Unless otherwise defined, the technical terms or scientific terms used in the present application should be understood as the common meanings understood by those with ordinary skills in the art to which the present application belongs. The terms "first", "second", "third" and the like used in the specification and claims of the present application do not represent any order, number or importance, but are only used to distinguish different components. Similarly, "one" or "a" and the like do not represent a quantity limitation, but represent the existence of at least one. The terms "include" or "contain" and the like mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and the like are not limited to electrical connections, but can include physical or mechanical connections, whether direct or indirect.

[0064] Figure 1 is a structural schematic diagram of an FPGA circuit provided by an embodiment of the present application. Referring to Figure 1 , the FPGA circuit comprises a clock circuit 101, a duty cycle adjustment circuit 102 and a plurality of cascaded logic blocks 103. The duty cycle adjustment circuit 102 is connected with the clock circuit 101 and the logic blocks 103 respectively.

[0065] The clock circuit 101 is configured to output a first clock signal, Figure 1 indicated as CLK1; the duty cycle adjustment circuit 102 is configured to perform duty cycle adjustment on the first clock signal to obtain a second clock signal, Figure 1The CLK2 is shown. After obtaining the second clock signal, the duty cycle adjustment circuit 102 uses one of the first clock signal and the second clock signal to perform timing control on each logic block 103, so that at least one logic block that does not meet the condition in the plurality of logic blocks 103 delays to meet the delay constraint condition when using the second clock signal for timing control. The logic block that does not meet the condition is a logic block that does not meet the constraint condition when using the first clock signal for timing control. The clock signals corresponding to any two logic blocks are the same or different.

[0066] In this application, the first clock signal output by the clock circuit is duty cycle adjusted by the duty cycle adjustment circuit, so that the rising edge of the first clock signal can be offset to become the second clock signal. The timing control of the logic block using the first clock signal and the second clock signal can solve the timing problem caused by the small amplitude of the rising edge of the clock signal in the related art. At the same time, the duty cycle adjustment can also obtain a second clock signal with a small offset of the rising edge compared to the first clock signal, so that the circuit structure can meet the clock signal adjustment requirements in different situations.

[0067] Exemplarily, in the FPGA circuit, the clock circuit 101 is a phase-locked loop circuit.

[0068] In a possible implementation, the duty cycle adjustment circuit 102 is configured to invert the first clock signal, and perform duty cycle adjustment on the inverted first clock signal to obtain the second clock signal.

[0069] In this implementation, the duty cycle adjustment circuit is inverted first, so that the falling edge of the first clock signal becomes the rising edge of the second clock signal. The rising edge of the second clock signal has been offset compared to the rising edge of the first clock signal. Then, the duty cycle adjustment is performed to obtain the final second clock signal. When a large degree of offset is required for the first clock signal, inverting first can reduce the adjustment amount when performing the subsequent duty cycle adjustment, save the processing amount of the duty cycle adjustment, and speed up the processing speed.

[0070] In other possible implementations, the duty cycle adjustment circuit 102 is configured to directly perform duty cycle adjustment on the first clock signal to obtain the second clock signal.

[0071] In Figure 1 In the circuit structure shown, the configuration parameters used by the duty cycle adjustment circuit 102 for duty cycle adjustment, and whether the clock signal to be selected by each logic block 103 is the first clock signal or the second clock signal, are determined and configured in the FPGA design stage.

[0072] In the FPGA design stage, a hardware description language such as Verilog HDL is needed to be used to perform logic design, and the layout and routing of the FPGA circuit are completed. After the layout and routing are completed, there are still paths in the FPGA circuit that cannot meet the delay constraint conditions, for example, a certain logic block cannot meet the delay constraint condition, and different FPGA designs have different situations that do not meet the delay constraint condition, which are affected by device selection, precision, process and other aspects. At this time, the duty cycle adjustment circuit proposed in the application needs to be added in the FPGA circuit, and the configuration parameters used for duty cycle adjustment are determined, and whether the clock signal to be selected by each logic block is the first clock signal or the second clock signal.

[0073] Because the circuit structures obtained by different FPGA designs are different, the delay information of the circuit is different, and the selection of the clock signal of the logic block exists the following several cases:

[0074] The first kind is that only the logic block described in the foregoing that does not meet the condition needs to be controlled by the second clock signal, and the other logic blocks are controlled by the first clock signal.

[0075] The second kind is that in addition to the logic block described in the foregoing that does not meet the condition needing to be controlled by the second clock signal, there is also a logic block in the other logic blocks that needs to be controlled by the second clock signal.

[0076] The following will describe the two cases respectively:

[0077] Figure 2 is a structure schematic diagram of a multi-stage logic block provided by an embodiment of the application. Referring to Figure 2 , a plurality of cascaded logic blocks 130 include a first logic block 131, a second logic block 132 and a third logic block 133. The second logic block 132 is connected to the output end of the first logic block 131, and the third logic block 133 is connected to the output end of the second logic block 132.

[0078] As shown in Figure 2 , there is a combinational logic circuit 130, for example, a gate circuit, between the adjacent two logic blocks, and the two logic blocks are transmitted through the combinational logic circuit 130. The time required when the data passes through the combinational logic circuit 130 is not a fixed time length, so the transmission time between the output end of the first logic block 131 and the input end of the second logic block 132 is not a fixed value, but there is a maximum value Tc1_max and a minimum value Tc1_min. Similarly, the transmission time between the output end of the second logic block 132 and the input end of the third logic block 133 also has a maximum value Tc2_max and a minimum value Tc3_min.

[0079] Since data may reach the input of the second logic block 132 within the range between the end of Tc1_min (arrow position) and the end of Tc1_max, for the stability of data writing, this range cannot coincide with the setup time and hold time of the logic block.

[0080] In the related art, the first logic block 131, the second logic block 132 and the third logic block 133 are controlled by the same timing signal (ie the first clock signal mentioned above). Figure 3 As shown, CK1 to CK3 correspond to the timing of the first logic block 131 to the third logic block 133, and CK1 to CK3 are all first clock signals. The two shadows before and after the rising edge in the figure represent the setup time Tsu and the hold time Th of the logic block respectively. Figure 3 It can be seen that the range from the end of Tc1_min to the end of Tc1_max coincides with the setup time Tsu of the second logic block 132 , and thus meets the timing requirement.

[0081] In order to solve the above-mentioned timing problem, the present application flips and adjusts the duty cycle of the first clock signal through the duty cycle adjustment circuit 102 to obtain a second clock signal. Figure 4 As shown, CK1 and CK3 are first clock signals, and CK2 is the second clock signal. Figure 4 Compared to Figure 3 The difference is that CK2 uses a second clock signal after duty cycle adjustment. Therefore, the clock end of the first logic block 131 is used to receive the first clock signal, the clock end of the second logic block 132 is used to receive the second clock signal, and the clock end of the third logic block 133 is used to receive the first clock signal.

[0082] like Figure 4 As shown, in this application, after flipping CK1, the duty cycle is increased during duty cycle adjustment, that is, the length of the high level is increased, and the rising edge of the resulting CK2 is shifted back compared to the rising edge of CK1. Moreover, the smaller the duty cycle of the second clock signal, the more the rising edge is shifted back. By adjusting the duty cycle of the inverted clock signal, a large clock delay can be achieved. For example, if the duty cycle adjustment range is between 20% and 80% and the clock period is 5ns, the adjustment range of the clock signal reaches 1ns to 4ns, which is far greater than the adjustment capability of the delay module. Figure 4 The duty cycle of CK2 shown in FIG is about 80%.

[0083] See also Figure 4, the rising edge of CK2 is obviously delayed (actually borrowing the transmission time of the next stage combinational logic circuit 130), and the setup time Tse and the hold time Th of the second logic block 132 are also delayed accordingly, so that they no longer overlap the range from Tc1_min end to Tc1_max end, thus solving the aforementioned timing problem. Meanwhile, from Figure 4 It can be seen that although the rising edge of the timing signal CK2 of the second logic block 132 is delayed, it does not cause the range from Tc2_min end to Tc2_max end to overlap the setup time Tse and the hold time Th of the third logic block 133, that is, after the timing adjustment of the second logic block 132, the third logic block 133 still satisfies the timing requirement.

[0084] In combination with Figure 3 and Figure 4 , the delay constraint condition in the present application is exemplarily explained as follows: for the first logic block and the second logic block, the delay constraint condition is as formula (1) :

[0085] Tck1+Tc1_min>Tshift+Th;

[0086] Tck1+Tc1_max<Tshift+Tcycle-Tsu; (1)

[0087] Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, Tck1 is the time from the rising edge of the first clock signal to the appearance of data at the output end of the first logic block, Tc1_min is the shortest time for data transmission from the first logic block to the second logic block, Tc1_max is the longest time for data transmission from the first logic block to the second logic block, Th is the hold time of the first logic block and the second logic block, Tsu is the setup time of the first logic block and the second logic block, and Tcycle is the cycle time of the first clock signal and the second clock signal.

[0088] In combination with Figure 4 The two formulas in formula (1) are simply explained as follows: Tck1+Tc1_min>Tshift+Th means that the arrow position of Tc1_min must be on the right side of the first hold time Th in CK2; Tck1+Tc1_max<Tshift+Tcycle-Tsu means that the arrow position of Tc1_max must be on the left side of the second setup time Tsu in CK2, so that the range from Tc1_min end to Tc1_max end does not overlap the setup time or the hold time.

[0089] For the second logic block and the third logic block, the delay constraint condition is as formula (2) :

[0090] Tck2+Tc2_min > Th - Tshift

[0091] Tck2+Tc2_max < Tcycle - Tshift - Tsu (2)

[0092] Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, Tck2 is the time from the rising edge of the second clock signal to the appearance of data at the output of the second logic block, Tc2_min is the shortest time for data to be transmitted from the second logic block to the third logic block, Tc2_max is the longest time for data to be transmitted from the second logic block to the third logic block, Th is the hold time of the second logic block and the third logic block, Tsu is the setup time of the second logic block and the third logic block, and Tcycle is the cycle time of the first clock signal and the second clock signal.

[0093] Figure 2 The first case is shown above, Figure 5 The second case is shown above. Referring to Figure 5 , a plurality of cascaded logic blocks 130, including: a first logic block 131, a second logic block 132, a third logic block 133, and a fourth logic block 134. The second logic block 132 is connected to the output of the first logic block 131, the third logic block 133 is connected to the output of the second logic block 132, and the fourth logic block 134 is connected to the output of the third logic block 133.

[0094] Wherein, the delay of the combinational logic circuit 130 between the first logic block 131 and the second logic block 132 does not meet the timing requirements, the delay of the combinational logic circuit 130 between the second logic block 132 and the third logic block 133 meets the timing requirements, and the delay of the combinational logic circuit 130 between the third logic block 133 and the fourth logic block 134 also meets the timing requirements.

[0095] According to the foregoing method, the rising edge of the clock signal of the second logic block 132 needs to be shifted backward, and the transmission time of the combinational logic circuit 130 between the second logic block 132 and the third logic block 133 is borrowed. However, there is a case that if the transmission time of the combinational logic circuit 130 between the second logic block 132 and the third logic block 133 is borrowed, and the delay of the combinational logic circuit 130 between the first logic block 131 and the second logic block 132 meets the timing requirements, then the delay of the combinational logic circuit 130 between the second logic block 132 and the third logic block 133 does not meet the requirements.

[0096] In this case, the rising edges of the clock signal of the second logic block 132 and the clock signal of the third logic block 133 can be delayed simultaneously, so as to borrow the transmission time of the combinational logic circuit 130 between the second logic block 132 and the third logic block 133 and the transmission time of the combinational logic circuit 130 between the third logic block 133 and the fourth logic block 134.

[0097] In this case, in addition to the logic block (the second logic block 132) that does not meet the condition and needs to be controlled by the second clock signal, there is also a logic block (the third logic block 133) that needs to be controlled by the second clock signal.

[0098] Figure 6 FIG. 1 is a structural diagram of a logic block provided by an embodiment of the present application. As shown in FIG. 1, Figure 6 The logic block 103 includes a plurality of cascaded registers 1031, a plurality of multi-level serially connected multiplexers 1032, and a plurality of delay modules 1033.

[0099] The number of the registers 1031 in the logic block 103 is usually 4 or 8, and each register is composed of a plurality of Dtype flip-flops (DFFs). The clock signal is actually used to control the DFFs, and all the DFFs in each logic block are controlled by the same clock signal. The data end, the clock end, and the like of each device in the logic block 103 are connected to the pins of the logic block 103, so as to realize the correct connection between the devices.

[0100] As shown in FIG. 1, Figure 6 The input ends of the first-level multiplexers in the plurality of multi-level serially connected multiplexers 1032 are respectively used to receive the first clock signal CLK1 and the second clock signal CLK2, so as to select one of them to control the timing of the logic block 103.

[0101] The output ends of the last-level multiplexers in the plurality of multi-level serially connected multiplexers 1032 are respectively connected to the plurality of cascaded registers 1031, so as to output the clock signal that has passed through the plurality of multi-level serially connected multiplexers 1032 to each register 1031. The plurality of cascaded registers 1031 are controlled by the same clock signal.

[0102] A delay module 1033 is connected between any two adjacent multiplexers 1032. One input end of the multiplexer 1032 is connected to the output end of the previous-level multiplexer 1032 through the delay module 1033, and the other input end of the multiplexer 1032 is directly connected to the output end of the previous-level multiplexer 1032. Through the above connection, each multiplexer 1032 starting from the second-level multiplexer can select whether to delay the clock signal, so as to select the length of the delay time.

[0103] For example, if there are 3 multiplexers to select the clock signal that has passed through the delay module 1033, the clock signal is delayed for a duration of 3 delay times of the delay module 1033.

[0104] Since the delay time of the delay module 1033 is small, for example, it can reach 60 picoseconds (ps), the second clock signal or the first clock signal after duty cycle adjustment can be finely adjusted in a small range by the plurality of delay modules 1033. It should be noted that the duty cycle adjustment circuit and the delay module work independently of each other. For example, if the clock signal is adjusted only by using the duty cycle adjustment circuit, the problem of not meeting the delay constraint condition can be solved, and then the delay module in the logic block can no longer process the clock signal. The main difference between the duty cycle adjustment circuit and the delay module is that the granularity of the clock signal delay adjustment is different. The duty cycle adjustment circuit has a wider adjustment range, and the delay module is more fine-tuned.

[0105] In the embodiment of the present application, the total number of delay modules 1033 can be designed according to the actual delay adjustment requirements of the clock signal, but the total number should not be too large to avoid the area of the logic block being too large, for example, 5 can be designed. Exemplarily, the circuit structures in each different logic block 103 are the same, that is, the same number of delay modules 1033 are used, but the configurations can be the same or different, that is, the configurations of each multiplexer are different.

[0106] As shown in Figure 6 , the configurations of the control ends A of the multiplexers 1031 are different, which causes the multiplexers to select the signal corresponding to the 0 pin or the signal corresponding to the 1 pin for input, thereby realizing the control of whether the clock signal passes through the delay module.

[0107] Exemplarily, the control end of the multiplexer 1031 is a configuration word control, the configuration word of the control end of each multiplexer 1031 is stored in a random access memory (RAM), and the control end of each multiplexer 1031 is connected to the corresponding RAM.

[0108] Exemplarily, the delay module 1033 is a logic gate circuit.

[0109] Figure 7 is a timing diagram provided by the embodiment of the present application. Referring to Figure 7 , Figure 7 The difference between the timing in Figure 4 and the timing in Figure 7 is that CK2 in has been delayed by the delay module inside the logic block.

[0110] In the embodiment of the present application, the duty cycle adjustment circuit 102 comprises a flip sub-circuit and a duty cycle sub-circuit. The flip sub-circuit is configured to perform signal flipping. The duty cycle sub-circuit is configured to perform duty cycle adjustment based on the configuration parameters (e.g. duty cycle) determined in the design stage.

[0111] For example, the flip sub-circuit can be implemented by means of a NOT gate.

[0112] The duty cycle sub-circuit can be implemented based on a cycle counting method, for example, based on the duty cycle, the clock signal corresponding to the value of the predetermined proportion in the counting time is output as a high level, thereby obtaining the clock signal with the predetermined duty cycle. Of course, the duty cycle sub-circuit can also be implemented based on other principles. Two structures of the duty cycle sub-circuit are introduced as examples below:

[0113] For example, the duty cycle sub-circuit is a phase-locked loop-based duty cycle adjustment circuit.

[0114] For example, the duty cycle adjustment circuit comprises a frequency divider, a delay generator and a pulse width generator. The delay generator is connected to the frequency divider and the pulse width generator. The frequency divider is configured to divide the flipped first clock signal to obtain a first pulse signal; the delay generator is configured to control the pulse interval of the first pulse signal to obtain a second pulse signal; and the pulse width generator is configured to control the pulse width of the second pulse signal to obtain a second clock signal.

[0115] The FPGA circuit provided by the embodiment of the present application belongs to an FPGA chip, or belongs to an FPGA module integrated with an application specific integrated circuit (ASIC) chip. The FPGA chip or the FPGA module integrated with the ASIC chip can be used in various scenarios, such as communication equipment, servers, etc.

[0116] Figure 8 is a flowchart of a method for determining configuration parameters of an FPGA circuit provided by the embodiment of the present application. Referring to Figure 8 , the method comprises:

[0117] 201, obtaining the delay constraint conditions of a plurality of cascaded logic blocks and the delay information of the plurality of cascaded logic blocks.

[0118] In the FPGA design stage, a hardware description language such as Verilog HDL is needed to perform logic design, and the layout of the FPGA circuit is completed. For example, the FPGA design stage mainly includes two steps of synthesis and layout routing. The synthesis step: first, the user's source code is translated and optimized to generate a netlist by synthesis, which includes the connection relationship of the device, the delay information, etc. The layout routing step: on the basis of the netlist, the position information of each device, the wiring information, etc. are added, and all the constraints set by the user are satisfied to the greatest extent. When there is a conflict in the constraints, the higher priority is given priority. For example, the constraints include: frequency 1Ghz, area 20mm, and the frequency priority is higher. If the two targets cannot be achieved at the same time, the frequency of 1Ghz is selected.

[0119] After the layout routing is completed, there are still paths in the FPGA circuit that cannot meet the delay constraint condition, for example, a certain logic block cannot meet the delay constraint condition. At this time, steps 201-203 provided by the embodiment of the application are executed.

[0120] In step 201, the delay information of the plurality of cascaded logic blocks is obtained from the netlist in the design stage or by performing report_timing on the circuit generated by the design.

[0121] Exemplarily, the delay information of the plurality of cascaded logic blocks includes:

[0122] The time from the rising edge of the clock signal to the appearance of the data at the output end of each logic block, the shortest time of data transmission between adjacent two logic blocks, the longest time of data transmission between adjacent two logic blocks, the hold time of the logic block, the setup time of the logic block, and the period time of the clock signal.

[0123] 202, based on the delay constraint condition of the plurality of cascaded logic blocks and the delay information of the plurality of cascaded logic blocks, determine the offset.

[0124] Exemplarily, step 202 includes:

[0125] When there are a plurality of logic blocks that do not meet the condition, a plurality of offset values are selected according to the step length;

[0126] From the plurality of offset values, a first offset value is determined as the offset, the second clock signal corresponding to the first offset value makes the delay of the first number of logic blocks that do not meet the condition meet the delay constraint condition, and the second clock signal corresponding to the other offset values in the plurality of offset values makes the delay of the second number of logic blocks that do not meet the condition meet the delay constraint condition, and the second number is less than or equal to the first number.

[0127] For example, the length of a period A is determined, in the range (-A, A) (since it is usually a delay, the range can also be simplified as (0, A)), a plurality of offset values are selected according to the minimum precision as a step length. Then, the rising edge of the first clock signal is moved using each offset value, and it is determined whether the rising edge of the first clock signal after moving can meet the timing requirements of each logic block that does not meet the condition. If the timing requirements of each logic block that does not meet the condition cannot be met, the offset value that can meet the timing requirements of the most logic blocks that do not meet the condition is selected.

[0128] When moving the rising edge of the first clock signal using an offset value, various moving methods can be traversed, that is, there are two choices for the clock signal of each register, using the first clock signal and using the second clock signal after moving, and the two choices of each register are combined. The optimal combination is selected, that is, the combination that can meet the timing requirements of the most logic blocks that do not meet the condition is selected. Through the above process, not only is the first offset value determined, but also it is determined which registers use the first clock signal and which registers use the second clock signal. It should be noted that part of the registers may use the first clock signal to meet the timing requirements, but in order to make other registers that do not originally meet the timing requirements meet the timing requirements, part of the registers that originally meet the timing requirements may also use the second clock signal, but it needs to be noted that after using the second clock signal, it is still ensured that the part of the registers that originally meet the timing requirements still meet the timing requirements.

[0129] It should be noted that in the above process of moving the rising edge, the delay length of the delay module in the logic block needs to be considered, that is, the maximum offset that can be moved is the sum of the offset value and the delay length of all delay modules.

[0130] In calculation, it needs to be considered whether each logic block can meet the delay constraint condition under a certain offset value. The following illustrates whether the logic block can meet the delay constraint condition under a certain offset value:

[0131] Example 1, assuming that a certain FPGA design project, the clock constraint is 5ns, the worst path delay is 5.306ns (equivalent to Tck1+Tc1_max in the foregoing), exceeding the timing requirement by 0.306ns, and the layout and routing fail. The delay information is as shown in Table 1:

[0132] Table 1

[0133]

[0134] From Table 1, the worst path from the first logic block to the second logic block is 5.306 ns, and according to formula (1), at least 0.306 ns of shift (Tshift lower limit) is required to meet the delay constraint condition, and at most 1.448-Tsu (Tshift upper limit 1) of rightward shift is allowed, and according to formula (2), at most 3.758-Tsu (Tshift upper limit 2) of rightward shift is allowed. According to the data in Table 1 and the upper and lower limits of Tshift, the range of the shift is between 0.306 ns and 1.448-Tsu. Based on this conclusion, if the shift value is selected by traversal, the shift value within the above range can meet the delay constraint condition.

[0135] For example, when the shift is 1 ns, the first to third logic blocks can all meet the delay constraint condition, and at this time, the duty cycle adjustment circuit adjusts the duty cycle of the first clock signal by 20%.

[0136] For another example, considering the effect of the delay module, the duty cycle can also not be adjusted in the duty cycle adjustment circuit, but the shift amount above the lower limit can be realized inside the logic block, that is, the clock shift amount is made to be above 0.306 ns.

[0137] Example 2, assuming that a certain FPGA design project has a clock constraint of 2 ns, and the delay information is as shown in Table 2:

[0138] Table 2

[0139]

[0140] In this case of Table 2, the rising edges of the clock signals of the second logic block 132 and the third logic block 133 can be both delayed, so as to simultaneously borrow the transmission time of the combinational logic circuit 130 between the second logic block 132 and the third logic block 133 and the transmission time of the combinational logic circuit 130 between the third logic block 133 and the fourth logic block 134.

[0141] For example, the shift range is 0.3-0.5 ns, and the clock signal CK2 of the second logic block and the clock signal CK3 of the third logic block are both delayed by 0.3-0.5 ns, and the 0.5 ns (2-1.5) timing margin from the third logic block to the fourth logic block is used, so that the combinational logic circuit between the first logic block and the second logic block can still work normally for 2.3 ns.

[0142] 203、determining a configuration parameter of the duty cycle adjustment circuit based on the offset, the configuration parameter being used to control the duty cycle adjustment circuit to adjust a duty cycle of the first clock signal to obtain a second clock signal, a rising edge of the second clock signal having an offset compared with a rising edge of the first clock signal; the duty cycle adjustment circuit being used to perform timing control on each logic block by using one of the first clock signal and the second clock signal, so that at least one unsatisfied condition logic block in the plurality of logic blocks delays to satisfy the delay constraint condition when performing timing control by using the second clock signal, the unsatisfied condition logic block being a logic block that delays to not satisfy the constraint condition when performing timing control by using the first clock signal, and clock signals corresponding to any two logic blocks being the same or different.

[0143] Exemplarily, the plurality of cascaded logic blocks include a first logic block and a second logic block connected to an output terminal of the first logic block, a clock terminal of the first logic block being used to receive the first clock signal, a clock terminal of the second logic block being used to receive the second clock signal,

[0144] The delay constraint condition is as follows:

[0145] Tck1+Tc1_min>Tshift+Th;

[0146] Tck1+Tc1_max<Tcycle-Tshift-Tsu;

[0147] Tshift is an offset of a rising edge of the second clock signal relative to a rising edge of the first clock signal, Tck1 is a time from the rising edge of the first clock signal to appearance of data at an output terminal of the first logic block, Tc1_min is a shortest time for data to be transmitted from the first logic block to the second logic block, Tc1_max is a longest time for data to be transmitted from the first logic block to the second logic block, Th is a hold time of the first logic block and the second logic block, Tsu is a setup time of the first logic block and the second logic block, and Tcycle is a period time of the first clock signal and the second clock signal.

[0148] Exemplarily, the plurality of cascaded logic blocks include a second logic block and a third logic block connected to an output terminal of the second logic block, a clock terminal of the second logic block being used to receive the second clock signal, a clock terminal of the third logic block being used to receive the first clock signal,

[0149] The delay constraint condition is as follows:

[0150] Tck2+Tc2_min>Th-Tshift;

[0151] Tck2+Tc2_max<Tcycle-Tshift-Tsu;

[0152] Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, Tck2 is the time from the rising edge of the second clock signal to the appearance of data at the output end of the second logic block, Tc2_min is the shortest time for data to be transmitted from the second logic block to the third logic block, Tc2_max is the longest time for data to be transmitted from the second logic block to the third logic block, Th is the hold time of the second logic block and the third logic block, Tsu is the setup time of the second logic block and the third logic block, and Tcycle is the cycle time of the first clock signal and the second clock signal.

[0153] In the embodiment of the present application, the FPGA circuit configuration parameter determination method can be executed by an electronic device, and the following is combined with Figure 9 The structure of this electronic device will be described.

[0154] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 9 As shown, the electronic device includes a processor 10, a memory 20 and a communication interface 30. Those skilled in the art will understand that Figure 9 The structure shown in the figure does not constitute a limitation of the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange components differently.

[0155] The processor 10 is the control center of the electronic device. It uses various interfaces and lines to connect all parts of the electronic device. By running or executing software programs and / or modules stored in the memory 20 and calling data stored in the memory 20, it performs various functions of the electronic device and processes data, thereby controlling the electronic device as a whole. The processor 10 can be a CPU, or other general-purpose processors, digital signal processing (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. It is worth noting that the processor can be a processor that supports the advanced reduced instruction set machine (ARM) architecture.

[0156] The memory 20 can be used to store software programs and modules. The processor 10 performs various functional applications and data processing by running the software programs and modules stored in the memory 20. The memory 20 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system 21, an obtaining module 22, a first determining module 23, a second determining module 24, and an application program 25 (such as an encoding application program, etc.) required by one or more functions, etc.; and the data storage area can store data (such as a service type identification model, etc.) created according to the use of the UE or the target server, etc. The memory 20 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. The non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used. For example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate synchronous DRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synchlink DRAM (SLDRAM), and a direct rambus RAM (DR RAM) can be used. Accordingly, the memory 20 can also include a memory controller to provide the processor 10 with access to the memory 20.

[0157] The processor 20 performs the following functions by running the obtaining module 22: obtaining delay constraint conditions of a plurality of cascaded logic blocks and time delay information of the plurality of cascaded logic blocks; the processor 20 performs the following functions by running the first determining module 23: determining an offset based on the delay constraint conditions of the plurality of cascaded logic blocks and the time delay information of the plurality of cascaded logic blocks; the processor 20 performs the following functions by running the second determining module 24: determining a configuration parameter of a duty cycle adjustment circuit based on the offset, the configuration parameter being used to control the duty cycle adjustment circuit to adjust a duty cycle of the first clock signal to obtain a second clock signal, the rising edge of the second clock signal having the offset compared with the rising edge of the first clock signal; the duty cycle adjustment circuit is used to adopt one of the first clock signal and the second clock signal to perform timing control on each logic block, so that at least one logic block that does not meet the condition in the plurality of logic blocks meets the delay constraint condition when timing control is performed by using the second clock signal, the logic block that does not meet the condition being a logic block that does not meet the constraint condition when timing control is performed by using the first clock signal, and the clock signals corresponding to any two logic blocks being the same or different.

[0158] The embodiment of the present application further provides a chip, which comprises a processor, the processor is used to call and run instructions stored in a memory, so that a communication device installed with the chip performs the FPGA circuit configuration parameter determination method provided in any of the embodiments of the present application.

[0159] The embodiment of the present application further provides a chip, which comprises an input interface, an output interface, a processor and a memory, the input interface, the output interface, the processor and the memory are connected through internal connection paths, and the processor is used to execute code in the memory, when the code is executed, the processor is used to perform the FPGA circuit configuration parameter determination method provided in any of the embodiments of the present application.

[0160] It should be understood that the processor described above can be a CPU, and can also be other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It should be noted that the processor can be a processor supporting ARM architecture.

[0161] Further, in an optional embodiment, the processor described above is one or more, and the memory is one or more. Optionally, the memory can be integrated with the processor, or the memory is arranged separately from the processor. The memory described above can include read-only memory and random access memory, and provide instructions and data for the processor. The memory can also include non-volatile random access memory. For example, the memory can also store reference blocks and target blocks.

[0162] The memory can be volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. Where the memory is nonvolatile, it can be ROM, PROM, EPROM, EEPROM, or flash memory. Where the memory is volatile, it can be SRAM, DRAM, SDRAM, DDR SDRAM, ESDRAM, SLDRAM, and DR RAM.

[0163] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or can be instructed by programs to complete the related hardware, and the programs can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0164] The above only describes optional embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A field programmable gate array circuit, characterized by The field programmable gate array circuit comprises: a plurality of cascaded logic blocks; a clock circuit for outputting a first clock signal; a duty cycle adjustment circuit connected with the clock circuit and the plurality of cascaded logic blocks respectively, for duty cycle adjustment on the first clock signal to obtain a second clock signal, the rising edge of the second clock signal has an offset compared with the rising edge of the first clock signal; one of the first clock signal and the second clock signal is used for timing control on each of the logic blocks, so that at least one of the plurality of logic blocks which does not meet a condition is delayed to meet a delay constraint condition when timing control is performed by using the second clock signal, the logic block which does not meet the condition is a logic block which does not meet a constraint condition when timing control is performed by using the first clock signal, and the clock signals corresponding to any two of the logic blocks are the same or different; the plurality of cascaded logic blocks comprise: a first logic block, a clock terminal of the first logic block being used for receiving the first clock signal; a second logic block connected with an output terminal of the first logic block, a clock terminal of the second logic block being used for receiving the second clock signal; the delay constraint condition comprises that the setup time and the hold time of the second logic block do not overlap with the range from the shortest time to the longest time of data transmission from the first logic block to the second logic block.

2. The field programmable gate array circuit of claim 1, wherein, the duty cycle adjustment circuit is used for inverting the first clock signal and duty cycle adjustment on the inverted first clock signal to obtain the second clock signal.

3. The field programmable gate array circuit of claim 1 or 2, wherein, the delay constraint condition is as follows: Tck1+Tc1_min>Tshift+Th; Tck1+Tc1_max<Tshift+Tcycle-Tsu; Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, Tck1 is the time from the rising edge of the first clock signal to the appearance of data at the output terminal of the first logic block, Tc1_min is the shortest time of data transmission from the first logic block to the second logic block, Tc1_max is the longest time of data transmission from the first logic block to the second logic block, Th is the hold time of the first logic block and the second logic block, Tsu is the setup time of the first logic block and the second logic block, and Tcycle is the period time of the first clock signal and the second clock signal.

4. The field programmable gate array circuit of claim 1 or 2, wherein, the plurality of cascaded logic blocks further comprise: a third logic block connected with an output terminal of the second logic block, a clock terminal of the third logic block being used for receiving the first clock signal.

5. The field programmable gate array circuit of claim 4, wherein, the delay constraint condition is as follows: Tck2+Tc2_min>Th-Tshift; Tck2+Tc2_max<Tcycle-Tshift-Tsu; The Tshift is an offset of a rising edge of the second clock signal relative to a rising edge of the first clock signal, the Tck2 is a time from the rising edge of the second clock signal to appearance of data at an output end of the second logic block, the Tc2_min is a shortest time for data to be transmitted from the second logic block to the third logic block, the Tc2_max is a longest time for data to be transmitted from the second logic block to the third logic block, the Th is a hold time of the second logic block and the third logic block, the Tsu is a setup time of the second logic block and the third logic block, and the Tcycle is a cycle time of the first clock signal and the second clock signal.

6. The field programmable gate array circuit of claim 1 or 2, wherein, The logic block comprises: a plurality of cascaded registers; a plurality of multi-level selectors connected in series, an input end of a first multi-level selector in the plurality of multi-level selectors being configured to receive the first clock signal and the second clock signal respectively, and an output end of a last multi-level selector in the plurality of multi-level selectors being connected to the plurality of cascaded registers respectively; a plurality of delay modules, each of the plurality of delay modules being connected between any two adjacent multi-level selectors, one input end of the multi-level selector being connected to an output end of a previous multi-level selector through the delay module, and the other input end of the multi-level selector being directly connected to the output end of the previous multi-level selector.

7. A method of determining configuration parameters of a field programmable gate array circuit, characterized by, The method comprises: obtaining delay constraint conditions of a plurality of cascaded logic blocks and time delay information of the plurality of cascaded logic blocks; determining an offset based on the delay constraint conditions of the plurality of cascaded logic blocks and the time delay information of the plurality of cascaded logic blocks; determining configuration parameters of a duty cycle adjustment circuit based on the offset, the configuration parameters being used to control the duty cycle adjustment circuit to adjust a duty cycle of a first clock signal to obtain a second clock signal, a rising edge of the second clock signal having the offset relative to a rising edge of the first clock signal, the duty cycle adjustment circuit being used to perform timing control on each of the logic blocks by using one of the first clock signal and the second clock signal, so that at least one logic block that does not meet a delay constraint condition in a plurality of the logic blocks meets the delay constraint condition when timing control is performed by using the second clock signal, the logic block that does not meet the condition being a logic block that does not meet the constraint condition when timing control is performed by using the first clock signal, and clock signals corresponding to any two of the logic blocks being the same or different; the plurality of cascaded logic blocks comprising a first logic block and a second logic block connected to an output end of the first logic block, a clock end of the first logic block being configured to receive the first clock signal, and a clock end of the second logic block being configured to receive the second clock signal; the delay constraint conditions comprising a setup time and a hold time of the second logic block, and a range from a shortest time to a longest time for data to be transmitted from the first logic block to the second logic block not overlapping.

8. The method of claim 7, wherein, the time delay information of the plurality of cascaded logic blocks comprising: The time from a rising edge of the clock signal to the time when data appears at the output of each logic block, the minimum time for data transmission between two adjacent logic blocks, the maximum time for data transmission between two adjacent logic blocks, the hold time of the logic block, the setup time of the logic block, and the cycle time of the clock signal.

9. The method according to claim 7 or 8, characterized in that, The delay constraint conditions are as follows: Tck1+Tc1_min>Tshift+Th; Tck1+Tc1_max The Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, the Tck1 is the time from the rising edge of the first clock signal to the time when data appears at the output of the first logic block, the Tc1_min is the minimum time for data transmission from the first logic block to the second logic block, the Tc1_max is the maximum time for data transmission from the first logic block to the second logic block, the Th is the hold time of the first logic block and the second logic block, the Tsu is the setup time of the first logic block and the second logic block, and the Tcycle is the cycle time of the first clock signal and the second clock signal.

10. The method according to claim 7 or 8, characterized in that, The plurality of cascaded logic blocks further include a third logic block connected to the output of the second logic block, a clock terminal of the third logic block is used to receive the first clock signal, The delay constraint conditions are as follows: Tck2+Tc2_min>Th-Tshift; Tck2+Tc2_max The Tshift is the offset of the rising edge of the second clock signal relative to the rising edge of the first clock signal, the Tck2 is the time from the rising edge of the second clock signal to the time when data appears at the output of the second logic block, the Tc2_min is the minimum time for data transmission from the second logic block to the third logic block, the Tc2_max is the maximum time for data transmission from the second logic block to the third logic block, the Th is the hold time of the second logic block and the third logic block, the Tsu is the setup time of the second logic block and the third logic block, and the Tcycle is the cycle time of the first clock signal and the second clock signal.

11. The method of claim 7 or 8, wherein, Based on the delay constraint conditions of the plurality of cascaded logic blocks and the delay information of the plurality of cascaded logic blocks, the offset is determined, including: When there are a plurality of logic blocks that do not meet the conditions, a plurality of offset values are selected by steps; A first offset value is determined from the plurality of offset values as the offset, the first offset value corresponds to the second clock signal that makes the delay of a first number of the logic blocks that do not meet the conditions meet the delay constraint conditions, and other offset values in the plurality of offset values correspond to the second clock signal that makes the delay of a second number of the logic blocks that do not meet the conditions meet the delay constraint conditions, and the second number is less than or equal to the first number.

12. An electronic device, comprising: The electronic device comprises a processor and a memory; the memory is used for storing a software program and a module; the processor realizes the field programmable gate array circuit configuration parameter determination method as claimed in any one of claims 7 to 11 by running or executing the software program and / or the module stored in the memory.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program code; the program code is loaded and executed by the processor to realize the field programmable gate array circuit configuration parameter determination method as claimed in any one of claims 7 to 11.

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