Solid State Drives and Data Processing Methods

Abstract

This invention provides a solid-state drive (SSD) and a data processing method. The SSD includes a peripheral interface, a control chip, a flash memory chipset, and a cache chipset. The SSD is connected to an external bus via the peripheral interface. The flash memory chipset includes multiple data storage blocks and a mapping table storage area. When the control chip receives a read command from the peripheral interface and there is no corresponding data to be read in the cache chipset, it retrieves the data to be read from the flash memory chipset and writes all data in the data storage block containing the data to be read to the cache chipset. This invention moves data from the flash memory chipset to the cache chipset in blocks, thus allowing data updates to be directly written from the cache chipset to the flash memory chipset, avoiding multiple read / write operations and significantly improving the data processing speed of the SSD.

Description

Technical Field

[0001] This invention relates to the field of computer equipment, and more specifically, to a solid-state drive and a data processing method. Background Technology

[0002] Solid-state drives (SSDs) are hard drives made using solid-state electronic storage chip arrays. They mainly consist of a control unit and storage units (FLASH chips and DRAM chips). Due to their advantages in data reading and environmental adaptability, SSDs are now widely used in many fields such as military, automotive, industrial control, video surveillance, network monitoring, network terminals, power, medical, aviation, and navigation equipment.

[0003] Existing solid-state drives typically use NAND flash chips as the main storage unit, with the smallest read / write unit being a data page. Most data pages are 4KB in size, meaning the smallest read / write unit of a NAND flash chip is 4KB.

[0004] However, NAND flash chips typically perform erase operations on a block-by-block basis, with each block usually containing several data pages. When updating only some pages within a block, all data within the block needs to be moved, resulting in slow operation speeds. Furthermore, during system data processing, the probability of adjacent instructions being processed simultaneously is often higher; the existing method of reading and writing data in blocks also impacts command response speed. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a new solid-state drive and data processing method to address the issue that solid-state drives (SSDs) affect overall read / write speed and response speed because they read and write data in pages as the smallest unit.

[0006] The technical solution of this invention to solve the above-mentioned technical problems is to provide a solid-state drive (SSD), including a peripheral interface, a control chip, a flash memory chipset, and a cache chipset, wherein the SSD is connected to an external bus through the peripheral interface, wherein:

[0007] The flash memory chipset includes multiple data storage blocks, and the control chip is connected to the flash memory chipset, the cache chipset, and the peripheral interface, respectively.

[0008] The flash memory chipset includes a mapping table storage area. When the control chip receives a read data command at the peripheral interface and there is no data to be read corresponding to the read data command in the cache chipset, it obtains the data to be read from the flash memory chipset and writes all the data in the data storage block where the data to be read is located into the cache chipset. It also establishes a mapping relationship between the physical location of the data storage block and the physical location of the data to be read in the cache chipset and writes it into the mapping table storage area.

[0009] As a further improvement of the present invention, the cache chipset includes multiple logical storage blocks, and the logical storage blocks and the data storage blocks have the same storage capacity;

[0010] When the control chip receives a read data command at the peripheral interface and there is no data to be read corresponding to the read data command in the cache chip group, it obtains the data to be read from the flash memory chip group, writes all the data in the data storage block where the data to be read is located into a logical storage block of the cache chip group, and establishes a mapping relationship between the physical location of the data storage block and the physical location of the logical storage block and writes it into the mapping table storage area.

[0011] As a further improvement of the present invention, the control chip stores a block maintenance table, which includes the status of each data storage block in the flash memory chip group;

[0012] When the control chip writes updated data from the cache chip group to the flash memory chip group, it writes all the data of the logical storage block containing the data to be written in the cache chip group to an idle data storage block in the flash memory chip group according to the block maintenance table in the cache chip group. It also erases the data in the data storage block corresponding to the logical storage block according to the mapping relationship in the mapping table storage area and updates the block maintenance table.

[0013] This invention also provides a data processing method applied to a solid-state drive (SSD). The SSD includes a peripheral interface, a control chip, a flash memory chipset, and a cache chipset. The SSD is connected to an external bus via the peripheral interface. The flash memory chipset includes multiple data storage blocks. The control chip is connected to the flash memory chipset, the cache chipset, and the peripheral interface, respectively. The method includes the following steps performed by the control chip:

[0014] Receive data processing commands from the external bus through the peripheral interface;

[0015] When the data processing command is a read data command, the cache chipset is retrieved, and if there is no data to be read corresponding to the read data command in the cache chipset, the data to be read is obtained from the flash memory chipset and all data in the data storage block where the data to be read is located is written to the cache chipset.

[0016] A mapping relationship is established between the physical location of the data storage block and the physical location of the data to be read in the cache chipset, and the mapping table is written.

[0017] As a further improvement of the present invention, the cache chipset includes multiple logical storage blocks, and the logical storage blocks and the data storage blocks have the same storage capacity;

[0018] The step of writing all the data in the data storage block where the data to be read is located into the cache chipset includes: writing all the data in the data storage block where the data to be read is located into a logical storage block of the cache chipset;

[0019] The step of establishing a mapping relationship between the physical location of the data storage block and the physical location of the data to be read in the cache chipset includes: establishing a mapping relationship between the physical location of the data storage block and the physical location of the logical storage block and writing it into the mapping table storage area.

[0020] As a further improvement of the present invention, the control chip stores a block maintenance table, the block maintenance table including the status of each data storage block in the flash memory chip group; the method further includes:

[0021] When writing updated data from the cache chipset to the flash memory chipset, according to the block maintenance table in the cache chipset, all data in the logical storage block where the data to be written in the cache chipset is located is written to an idle data storage block in the flash memory chipset, and the block maintenance table is updated.

[0022] According to the mapping relationship in the mapping table storage area, the data in the data storage block corresponding to the logical storage block is erased, and the block maintenance table is updated.

[0023] As a further improvement of the present invention, the step of writing all the data in the logical storage block where the data to be written is located in the cache chipset to a free data storage block of the flash memory chipset includes:

[0024] Multiple data pages are generated based on all the data in the logical storage block where the data to be written is located, and each data page includes an ECC checksum.

[0025] Multiple data pages are written into the same free data storage block of the flash memory chipset.

[0026] As a further improvement of the present invention, the step of obtaining the data to be read from the flash memory chipset and writing all data in the data storage block where the data to be read is located to the cache chipset includes:

[0027] Retrieve the flash memory chipset to obtain the data to be read;

[0028] Each data page is read from the data storage block where the data to be read is located, and each data page is verified according to the ECC checksum of each data page;

[0029] After verification, each data page is written to the flash memory chipset.

[0030] As a further improvement of the present invention, the method further includes the following steps performed by the control chip:

[0031] When a preset condition is met, select from the cache chipset a number of logical storage blocks that have been hit by the read data command the fewest times within a preset time period;

[0032] According to the block maintenance table in the cache chipset, all data of the logical storage blocks with the fewest hits are written into the free data storage blocks of the flash memory chipset, and the block maintenance table is updated.

[0033] According to the mapping relationship in the mapping table storage area, the data in the data storage block corresponding to the logical storage block is erased, and the block maintenance table is updated.

[0034] As a further improvement of the present invention, the preset condition is: the cache chipset is fully written, or a preset time is reached.

[0035] The solid-state drive and data processing method of this invention move data from the flash memory chipset to the cache chipset in blocks as the smallest unit. This allows data to be directly written from the cache chipset to the flash memory chipset when updating data, avoiding multiple read / write operations and significantly improving the data processing speed of the solid-state drive. Simultaneously, by moving data with a higher hit rate to the cache chipset in advance, the response speed of the solid-state drive is also greatly improved. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a solid-state drive provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram illustrating the principle of data caching operation of a solid-state drive provided in an embodiment of the present invention;

[0038] Figure 3 This is a flowchart illustrating the data processing method provided in an embodiment of the present invention;

[0039] Figure 4 This is a flowchart illustrating the process of updating the block maintenance table in the data processing method provided in this embodiment of the invention;

[0040] Figure 5 This is a schematic diagram of the process of writing data from the cache chipset to the flash memory chipset in the data processing method provided in this embodiment of the invention;

[0041] Figure 6 This is a schematic diagram of the process of moving data stored in a flash memory chipset to a cache chipset in the data processing method provided in this embodiment of the invention;

[0042] Figure 7 This is a schematic diagram of another process in the data processing method provided by the embodiments of the present invention, which involves moving data stored in a flash memory chipset to a cache chipset. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0044] like Figure 1 The diagram shows the structural block diagram of the solid-state drive (SSD) of this invention. This SSD can be applied to computer systems, such as personal computers and servers, for data storage. The SSD in this embodiment includes a peripheral interface 11, a control chip 12, a flash memory chipset 13, and a cache chipset 14. In this embodiment, the peripheral interface 11 is used to connect to the external bus of the computer system (e.g., a PCIe bus) to interact with the central processing unit of the computer system. Specifically, the peripheral interface 11 can be a SATA interface, mSATA interface, NGFF interface, PCLE interface, ATA interface, SCSI interface, etc.

[0045] The flash memory chipset 13 is used for data storage and includes one or more flash memory chips. These flash memory chips can specifically be NAND flash memory chips, which have relatively large storage capacity, relatively low cost, and relatively slow data access speeds. They can retain data even when power is off. Figure 2As shown, the flash memory chipset 13 includes multiple data storage blocks 131 with the same storage capacity. Each data storage block 131 can store multiple data pages. The flash memory chipset 13 uses blocks as the smallest erase unit. That is, when any data stored in the data storage block 131 changes, the data stored in the entire data storage block 131 needs to be erased (this erasure operation can be performed during idle time). The updated data and the unchanged data in the data storage block 131 before erasure are stored in a new data storage block 131.

[0046] The cache chipset 14 includes one or more DRAM chips. These DRAM chips can specifically be memory chips such as DDR, DDR2, DDR3, DDR4, DDR5, or phase-change memory, which have relatively small storage capacity, relatively high cost, and relatively fast data access speeds. However, these DRAM chips cannot retain stored data when power is off. Since the data access speed of the flash memory chipset 13 is much slower than that of high-speed devices in a computer system (such as the computer system's memory), the cache chipset 14 can compensate for this speed difference. That is, the cache chipset 14 can temporarily store data that needs to be stored in the flash memory chipset 13, and then gradually store it in the flash memory chipset 13. In this embodiment, the flash memory chipset includes a mapping table storage area and a data storage area (for example, the mapping table storage area may be located at the beginning of the physical address of the cache chipset 14), and the mapping table storage area stores the correspondence between the data stored in the data storage area and the data stored in the flash memory chipset 13.

[0047] The control chip 12 is connected to the peripheral interface 11, the flash memory chipset 13, and the cache chipset 14, respectively, and performs data processing and transmission / reception. For example, the control chip 12 can be connected to the flash memory chipset 13 via the NAND flash bus, to the cache chipset 14 via the DRAM bus, and to the peripheral interface 11 via the PCIe bus. In this embodiment, when the peripheral interface 11 receives a read data command (e.g., from the central processing unit of the computer system where the solid-state drive is located), the control chip 12 retrieves the data to be read corresponding to the read data command from the cache chipset 14. When no data to be read is found (i.e., the data to be read does not exist in the cache chipset 14), the control chip 12 obtains the data to be read from the flash memory chipset 13 and writes all the data in the data storage block 131 where the data to be read is located into the data storage area of ​​the cache chipset 14. It also establishes a mapping relationship between the physical location (i.e., address) of the data storage block 131 and the physical location of the data to be read in the cache chipset 14 and writes it into the mapping table storage area.

[0048] In this way, the central processing unit (or DMA) of the computer system where the solid-state drive is located can directly write the updated data (such as the result of instruction execution) into the cache chipset 14. The control chip 12 then writes the data (updated) corresponding to the storage capacity of the data storage block 131 in the cache chipset 14 into a new data storage block 131 of the flash memory chipset 13 according to the instructions or set rules, and erases the data in the original data storage block 131 used to store the corresponding data, while updating the mapping relationship in the cache chipset 14.

[0049] The aforementioned solid-state drive (SSD) moves data from the flash memory chipset 13 to the cache chipset 14 in blocks, allowing data updates to be directly written from the cache chipset 14 to the flash memory chipset 13. This avoids multiple read / write operations (i.e., no need to read and move other data from the flash memory chipset to the data storage block 131), significantly improving the SSD's data processing speed. Simultaneously, by moving data with higher hit rates (i.e., data stored in other data pages within the same data storage block 131, which are more likely to be read by the central processing unit due to the continuity of data processing) to the cache chipset in advance, the SSD's response speed (i.e., the speed at which it responds to read commands from the central processing unit) is also greatly improved.

[0050] In one embodiment of the present invention, combined with Figure 2 As shown, the data storage area of ​​the cache chipset 14 includes multiple logical storage blocks 141 with the same storage capacity, and the aforementioned logical storage blocks 141 have the same storage capacity as the data storage blocks 131 of the flash memory chipset 13.

[0051] Accordingly, when the peripheral interface 11 receives a read data command and there is no data to be read in the cache chip group 14 corresponding to the read data command, the control chip 12 obtains the data to be read from the flash chip group 13, writes all the data in the data storage block 131 where the data to be read is located into a logical storage block 141 of the cache chip group 14, and establishes a mapping relationship between the physical location (address) of the logical storage block 141 and the physical location of the data storage block 131 and writes it into the mapping table storage area.

[0052] By setting logical storage blocks 141 in the cache chipset 14 to store data read from the flash memory chipset 13, the data structure of the cache chipset 14 can be simplified. Furthermore, to improve data access efficiency, each logical storage block 141 can be composed of physically contiguous storage space within the cache chipset 14.

[0053] In one embodiment of the present invention, the solid-state drive may also adopt an open channel architecture, meaning that the data storage structure in the flash memory chipset 13 is directly managed by the central processing unit of the computer system. In this case, the control chip 12 stores a block maintenance table, which includes the status of each data storage block 131 in the flash memory chipset 13. The status of the data storage blocks in the block maintenance table includes occupied, free, bad blocks, etc. Specifically, the block maintenance table can be stored in the flash memory chipset 13 and loaded into the control chip 12 when the computer system containing the solid-state drive starts up. The control chip 12 then maintains the table; for example, when a data storage block in the flash memory chipset 13 fails, the control chip 12 modifies the status of the corresponding data storage block 131 in the block maintenance table to bad block.

[0054] When the control chip 12 receives a write data command at the peripheral interface 11, it writes all the data in the logical storage block 141 of the cache chip 14 containing the data to be written corresponding to the write data command to a free data storage block 131 of the flash memory chip 13 according to the block maintenance table in the cache chip 14. It also erases the data in the data storage block corresponding to the logical storage block according to the mapping relationship in the mapping table storage area, and updates the block maintenance table (for example, changing the status of the data storage block for newly written data in the block maintenance table to occupied, and the status of the data storage block for erased data to free).

[0055] In practical applications, when the storage space of the cache chipset 14 is full, the control chip 12 can also write the stored data of a portion of the logical storage block 141 in the cache chipset 14 to the idle data storage block 131 in the flash memory chipset 13 according to a preset rule, and clear the original logical storage block 141 for use in subsequent operations. For example, the preset rule could be a logical storage block 141 that has not been accessed within a preset time, or a data storage block 131 that has not been accessed for the longest time since the current time.

[0056] Combination Figure 3 As shown in the figure, this embodiment of the invention also provides a data processing method, which can be applied to a solid-state drive (SSD). The SSD includes a peripheral interface, a control chip, a flash memory chipset, and a cache chipset. The SSD is connected to an external bus via the peripheral interface. The flash memory chipset includes multiple data storage blocks. The control chip is connected to the flash memory chipset, the cache chipset, and the peripheral interface, respectively. The specific structure of this SSD can be found in [reference needed]. Figure 1 The corresponding implementation examples will not be described in detail here.

[0057] The data processing method in this embodiment is executed by the controller chip in the solid-state drive, and the method includes the following steps:

[0058] Step S31: Receive data processing commands from an external bus (e.g., the central processing unit of the computer system where the solid-state drive is located) through the peripheral interface.

[0059] Step S32: Determine whether the data processing command received through the peripheral interface is a read data command. If the data processing command is a read data command, execute step S34. If the data processing command is another command (e.g., a write data command, or a return operation result), execute step S33.

[0060] Step S33: The control unit writes the relevant data in the data processing command into the cache chipset.

[0061] Step S34: Retrieve the data to be read corresponding to the read data command in the cache chipset.

[0062] Step S35: Determine whether the data to be read corresponding to the read data command is found in the cache chipset. If the data to be read is not found (i.e., the data to be read does not exist in the cache chipset), proceed to step S37; otherwise, proceed to step S36.

[0063] Step S36: Return the data to be read corresponding to the read data command to the external bus through the external interface.

[0064] Step S37: Obtain the data to be read from the flash memory chipset and write all the data in the data storage block where the data to be read is located to the cache chipset, and then execute steps S36 and S38 respectively.

[0065] The data storage area of ​​the cache chipset in the aforementioned solid-state drive may include multiple logical storage blocks, and these logical storage blocks have the same storage capacity as the data storage blocks of the flash memory chipset. Each logical storage block can occupy a contiguous storage area. In this step, all data in the data storage block containing the data to be read is directly written into a logical storage block of the cache chipset.

[0066] Step S38: Establish a mapping relationship between the physical location of the data storage block and the physical location of the data to be read in the cache chipset, and write it into the mapping table. The mapping table can be located at the beginning of the physical address in the cache chipset.

[0067] When the above data processing method is applied to an Open Channel solid-state drive (SSD), the controller chip stores a block maintenance table. This table includes the status of each data storage block in the flash memory chipset, with statuses such as occupied, free, and bad. Specifically, the block maintenance table can be stored within the flash memory chipset and loaded into the controller chip when the computer system containing the SSD boots up. The controller chip then maintains this table; for example, if a data storage block in the flash memory chipset fails, the controller chip modifies the status of the corresponding data storage block in the block maintenance table to bad.

[0068] Accordingly, combined Figure 4 As shown, in addition to steps S31-S38, the data processing method of the present invention also includes the following steps executed by the control chip:

[0069] Step S41: Write all the data in the logical storage block where the data to be written is located in the cache chipset to a free data storage block in the flash memory chipset, and update the block maintenance table (for example, change the status of the data storage block in the block maintenance table to occupied).

[0070] Step S42: Erase the data in the data storage block corresponding to the logical storage block according to the mapping relationship in the mapping table storage area, and update the block maintenance table (for example, change the status of the data storage block whose data has been erased in the block maintenance table to idle).

[0071] To avoid data storage errors, Figure 4 In step S41, all data in the logical storage block containing the data to be written in the cache chipset is written to a free data storage block of the flash memory chipset, combined with... Figure 5 As shown, it may specifically include:

[0072] Step S411: Generate multiple data pages based on all data in the logical storage block containing the data to be written, with each data page including an ECC checksum. The ECC checksum is obtained by performing error checking and correction calculations on all data within its corresponding data page. When data within a data page of the flash memory chipset is corrupted, the correct data within the data page can be recovered using the ECC checksum.

[0073] Step S412: Write multiple data pages, each containing an ECC checksum, into the same free data storage block of the flash memory chipset.

[0074] Accordingly, combined Figure 6 As shown, Figure 3Step S37, which involves obtaining the data to be read from the flash memory chipset and writing all the data in the data storage block where the data to be read is located to the cache chipset, may specifically include the following steps executed by the control chip:

[0075] Step S371: Retrieve the flash memory chipset to obtain the data to be read corresponding to the read data command.

[0076] Step S372: Read each data page from the data storage block where the data to be read is located, and verify each data page according to the ECC checksum of each data page;

[0077] Step S373: After successful verification, each data page is written to the cache chipset. In case of verification failure, data can be recovered based on the ECC checksum, thereby improving the accuracy of the read data.

[0078] Combination Figure 7 As shown, in another embodiment of the present invention, in addition to steps S31-S38, the following steps are also performed by the control chip:

[0079] Step S71: When a preset condition is met, select a number of logical memory blocks from the cache chipset that have been hit by the fewest read data commands within a preset time period. Specifically, the preset condition can be: the cache chipset is full, or a preset time period has been reached, etc.

[0080] Step S72: Based on the block maintenance table in the cache chipset, write all the data of the logical storage blocks with the fewest hits to the free data storage blocks of the flash chipset, and update the block maintenance table (for example, modify the status of the data storage block for newly written data to occupied).

[0081] Step S73: Erase the data in the data storage block corresponding to the logical storage block according to the mapping relationship in the mapping table storage area, and update the block maintenance table (e.g., modify the status of the data storage block of the erased data to free) for use in subsequent operations.

[0082] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A solid-state drive, characterized in that, The solid-state drive includes a peripheral interface, a control chip, a flash memory chipset, and a cache chipset, and is connected to an external bus via the peripheral interface, wherein: The flash memory chipset includes multiple data storage blocks, and each data storage block includes multiple data pages; the control chip is connected to the flash memory chipset, the cache chipset, and the peripheral interface respectively. The cache chipset includes a mapping table storage area. When the control chip receives a read data command from the peripheral interface and there is no data to be read in the cache chipset corresponding to the read data command, it obtains the data to be read from the flash memory chipset and writes all the data in the data storage block where the data to be read is located into the cache chipset. It also establishes a mapping relationship between the physical location of the data storage block and the physical location of the data to be read in the cache chipset and writes it into the mapping table storage area. After the updated data is written to the cache chip group, the control chip, according to instructions or set rules, directly writes the data corresponding to the storage capacity of the data storage block in the cache chip group to a new data storage block in the flash memory chip group, erases the data in the original data storage block used to store the corresponding data, and updates the mapping relationship in the cache chip group.

2. The solid-state drive according to claim 1, characterized in that, The cache chipset includes multiple logical storage blocks, and the logical storage blocks and the data storage blocks have the same storage capacity; When the control chip receives a read data command at the peripheral interface and there is no data to be read corresponding to the read data command in the cache chip group, it obtains the data to be read from the flash memory chip group, writes all the data in the data storage block where the data to be read is located into a logical storage block of the cache chip group, and establishes a mapping relationship between the physical location of the data storage block and the physical location of the logical storage block and writes it into the mapping table storage area.

3. A data processing method applied to a solid-state drive, characterized in that, The solid-state drive (SSD) includes a peripheral interface, a controller chip, a flash memory chipset, and a cache chipset. The SSD is connected to an external bus via the peripheral interface. The flash memory chipset includes multiple data storage blocks, each of which includes multiple data pages. The cache chipset includes a mapping table storage area. The controller chip is connected to the flash memory chipset, the cache chipset, and the peripheral interface. The method includes the following steps performed by the controller chip: Receive data processing commands from the external bus through the peripheral interface; When the data processing command is a read data command, the cache chipset is retrieved, and if there is no data to be read corresponding to the read data command in the cache chipset, the data to be read is obtained from the flash memory chipset and all data in the data storage block where the data to be read is located is written to the cache chipset. A mapping relationship is established between the physical location of the data storage block and the physical location of the data to be read in the cache chipset, and the mapping table is written into the storage area. After the updated data is written to the cache chipset, according to instructions or set rules, the data corresponding to the storage capacity of the data storage block in the cache chipset is directly written to a new data storage block in the flash memory chipset, and the data in the original data storage block used to store the corresponding data is erased. At the same time, the mapping relationship in the cache chipset is updated.

4. The data processing method according to claim 3, characterized in that, The cache chipset includes multiple logical storage blocks, and the logical storage blocks and the data storage blocks have the same storage capacity; The step of writing all the data in the data storage block where the data to be read is located into the cache chipset includes: writing all the data in the data storage block where the data to be read is located into a logical storage block of the cache chipset; The step of establishing a mapping relationship between the physical location of the data storage block and the physical location of the data to be read in the cache chipset includes: establishing a mapping relationship between the physical location of the data storage block and the physical location of the logical storage block and writing it into the mapping table storage area.

5. The data processing method according to claim 4, characterized in that, The control chip stores a block maintenance table, which includes the status of each data storage block in the flash memory chipset; the method further includes: When writing updated data from the cache chipset to the flash memory chipset, according to the block maintenance table in the cache chipset, all data in the logical storage block where the data to be written in the cache chipset is located is written to an idle data storage block in the flash memory chipset, and the block maintenance table is updated. According to the mapping relationship in the mapping table storage area, the data in the data storage block corresponding to the logical storage block is erased, and the block maintenance table is updated.

6. The data processing method according to claim 5, characterized in that, The step of writing all the data in the logical storage block containing the data to be written in the cache chipset to a free data storage block in the flash memory chipset includes: Multiple data pages are generated based on all the data in the logical storage block where the data to be written is located, and each data page includes an ECC checksum. Multiple data pages are written into the same free data storage block of the flash memory chipset.

7. The data processing method according to claim 6, characterized in that, The step of obtaining the data to be read from the flash memory chipset and writing all the data in the data storage block where the data to be read is located to the cache chipset includes: Retrieve the flash memory chipset to obtain the data to be read; Each data page is read from the data storage block where the data to be read is located, and each data page is verified according to the ECC checksum of each data page; After verification, each data page is written to the flash memory chipset.

8. The data processing method according to claim 4, characterized in that, The method further includes the following steps performed by the control chip: When a preset condition is met, select from the cache chipset a number of logical storage blocks that have been hit by the read data command the fewest times within a preset time period; According to the block maintenance table in the cache chipset, all data of the logical storage blocks with the fewest hits are written into the free data storage blocks of the flash memory chipset, and the block maintenance table is updated. According to the mapping relationship in the mapping table storage area, the data in the data storage block corresponding to the logical storage block is erased, and the block maintenance table is updated.

9. The data processing method according to claim 8, characterized in that, The preset condition is that the cache chipset is full or a preset time is reached.

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