Circuit, computing chip and method for performing a hashing algorithm

Abstract

The present disclosure relates to a circuit, a computing chip, and a method for performing a hash algorithm. A circuit for performing a hash algorithm includes: a plurality of operation levels arranged in a pipeline structure, each including 0th to 15th extension registers for storing extended data of the current operation level; and a plurality of extended data operation logic modules, each disposed between two adjacent operation levels including a first operation level and a subsequent second operation level, and including a first sub-module for calculating extended data in the 0th extension register of the second operation level based on the extended data in the 1st extension register of the first operation level and a second sub-module for calculating extended data in the 15th extension register of the second operation level based on the extended data in the 0th extension register of the first operation level, wherein the extended data in the (i-1)th extension register of the second operation level is the extended data in the ith extension register of the first operation level, where 2≤i≤15 and i is an integer.

Description

Technical Field

[0001] The present disclosure generally relates to circuits, computing chips, and related methods for performing hash algorithms. Background Art

[0002] A hash algorithm is an algorithm that takes variable-length data as input and produces a fixed-length hash value as output, and its essence is the refinement of information. Since 1993, the National Institute of Standards and Technology of the United States has designed and released multiple versions of the Secure Hash Algorithm (SHA). SHA-256 is exactly one of the secure hash algorithms with a hash length of 256 bits. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a circuit for performing a hash algorithm, including: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data. The operation module includes: a plurality of operation levels arranged in a pipeline structure, each operation level of the plurality of operation levels including an extension register from register 0 to register 15, each extension register being configured to store extension data of the current operation level; and a plurality of extension data operation logic modules, each extension data operation logic module being disposed between two adjacent operation levels of the plurality of operation levels. The two adjacent operation levels include a first operation level and a second operation level after the first operation level. Each extension data operation logic module includes: a first sub-module configured to calculate extension data for storing into register 0 of the second operation level based on the extension data stored in register 1 of the first operation level; and a second sub-module configured to calculate extension data for storing into register 15 of the second operation level based on the extension data stored in register 0 of the first operation level. Wherein, the extension data for storing into register (i - 1) of the second operation level is the extension data stored in register i of the first operation level, where 2 ≤ i ≤ 15 and i is an integer.

[0004] According to a second aspect of the present disclosure, there is provided a circuit for performing a hash algorithm, including: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, where the operation module includes: a plurality of operation levels arranged in a pipeline structure, each of the plurality of operation levels including an extension register from register 0 to register 15 and an additional register, each extension register being configured to store extended data of the current operation level, and the additional register being configured to store intermediate data for calculating the extended data; and a plurality of extended data operation logic modules, each extended data operation logic module being disposed between two adjacent operation levels of the plurality of operation levels, the two adjacent operation levels including a first operation level and a second operation level after the first operation level, each extended data operation logic module including: a first sub-module configured to calculate intermediate data for storing in the additional register of the second operation level based on the extended data stored in the extension register of the first operation level; and a second sub-module configured to calculate extended data for storing in the extension register 15 of the second operation level based on the intermediate data stored in the additional register of the first operation level, where the extended data for storing in the extension register (i - 1) of the second operation level is the extended data stored in the extension register i of the first operation level, where 1 ≤ i ≤ 15 and i is an integer.

[0005] According to a third aspect of the present disclosure, there is provided a computing chip including the circuit as described in the above aspect.

[0006] According to a fourth aspect of the present disclosure, there is provided a method for calculating extended data in a circuit for performing a hash algorithm, the circuit including an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module including a plurality of operation levels arranged in a pipeline structure, each of the plurality of operation levels including an extension register from register 0 to register 15, each extension register being configured to store extended data of the current operation level, the method including: for two adjacent operation levels of the plurality of operation levels including a first operation level and a second operation level after the first operation level: calculating extended data for storing in the extension register 0 of the second operation level based on the extended data stored in the extension register 1 of the first operation level; calculating extended data for storing in the extension register 15 of the second operation level based on the extended data stored in the extension register 0 of the first operation level; and using the extended data stored in the extension register i of the first operation level as the extended data for storing in the extension register (i - 1) of the second operation level, where 2 ≤ i ≤ 15 and i is an integer.

[0007] According to a fifth aspect of the present disclosure, there is provided a method for calculating extended data in a circuit for performing a hash algorithm. The circuit includes an input module configured to receive data and an arithmetic module configured to calculate a hash value based on the received data. The arithmetic module includes a plurality of arithmetic stages arranged in a pipeline structure. Each arithmetic stage of the plurality of arithmetic stages includes an extended register 0 to an extended register 15 and an additional register. Each extended register is configured to store extended data of the current arithmetic stage, and the additional register is configured to store intermediate data for calculating the extended data. The method includes: for two adjacent arithmetic stages of the plurality of arithmetic stages including a first arithmetic stage and a second arithmetic stage after the first arithmetic stage: calculating intermediate data for storing in the additional register of the second arithmetic stage based on the extended data stored in the extended registers of the first arithmetic stage; calculating extended data for storing in the extended register 15 of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage; and using the extended data stored in the extended register i of the first arithmetic stage as the extended data for storing in the extended register (i - 1) of the second arithmetic stage, where 1 ≤ i ≤ 15 and i is an integer.

[0008] Other features and advantages of the present disclosure will become clearer from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0010] With reference to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, where:

[0011] Figure 1 A schematic diagram showing an exemplary pipeline structure for performing the SHA-256 algorithm is shown;

[0012] Figure 2 Schematically shows Figure 1 the conventional arithmetic logic between the extended data in the extended registers of two adjacent arithmetic stages in the pipeline structure shown in;

[0013] Figure 3 A schematic block diagram showing a circuit for performing a hash algorithm according to some embodiments of the present disclosure is shown;

[0014] Figures 4 to 7 Schematically shows according to an embodiment of the present disclosure as Figure 3 an exemplary configuration of a part including an extended data arithmetic logic module in the circuit shown;

[0015] Figure 8Schematically shows a block diagram of a circuit for performing a hashing algorithm according to some embodiments of the present disclosure;

[0016] Figures 9 to 14 Schematically shows an exemplary configuration of a part of the circuit including an extended data operation logic module as shown in Figure 8 accordance with an embodiment of the present disclosure; and

[0017] Figure 15 and Figure 16 shows an exemplary flowchart of a method for calculating extended data according to an embodiment of the present disclosure.

[0018] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to represent the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0019] For ease of understanding, the positions, sizes, ranges, etc. of the various structures shown in the drawings and the like sometimes do not represent the actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show the details of specific components. Detailed Embodiments

[0020] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

[0021] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way limits the present disclosure, its application, or its use. Those skilled in the art will understand that they merely illustrate exemplary ways in which the invention can be implemented, rather than exhaustive ways.

[0022] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered as part of the authorized specification.

[0023] To more clearly and intuitively present the inventive concept of the present disclosure, the SHA-256 algorithm will be briefly introduced below and used as an example representation of a hash algorithm to describe the circuit and related methods for performing a hash algorithm according to embodiments of the present disclosure. Those skilled in the art will understand that the circuit and related methods for performing a hash algorithm according to embodiments of the present disclosure are applicable to any hash algorithm and can even be further applied to any other suitable circuits and methods, not limited to implementing the SHA-256 algorithm.

[0024] Figure 1 FIG. shows a schematic diagram of an exemplary pipeline structure for performing the SHA-256 algorithm. The input of SHA-256 is data with a maximum length less than 2 64 bits, and the output is a 256-bit data digest, i.e., a hash value. The input data is processed in units of 512-bit data blocks. To implement the SHA-256 algorithm, 64 rounds of repeated operations need to be performed for each 512-bit data block. Therefore, a pipeline structure including 64 operation levels can be used to perform parallel operations on 64 groups of data. As Figure 1 shown, the pipeline structure includes operation levels from 0 to 63. Each operation level includes 8 32-bit compression registers A to H for storing intermediate values and 16 32-bit extended registers R 0 to R 15 . The 0th operation level can receive the input data block, divide it into 8 32-bit data, store them in compression registers A to H respectively, and then perform arithmetic processing on it and provide it to the 1st operation level. After that, each operation level performs arithmetic operations on the arithmetic result received from the previous operation level and provides its own arithmetic result to the next operation level. Finally, after 64 operation levels of arithmetic operations, the arithmetic core can output the hash operation result of performing the SHA-256 algorithm once on the input data.

[0025] The internal logic of one round of operation performed by SHA-256 at each operation level will be discussed in detail below. The t-th round of operation performed at the t-th operation level is defined by the following operation formula (t is an integer and satisfies 0 ≤ t ≤ 63):

[0026] T1 = H + ∑ 1 (E) + Ch(E, F, G) + K t + W t ;

[0027] T2 = ∑ 0 (A) + Maj(A, B, C);

[0028] H = G;

[0029] G = F;

[0030] F = E;

[0031] E = D + T1;

[0032] D = C;

[0033] C = B;

[0034] B = A;

[0035] A = T1 + T2; (Expression 1)

[0036] Where:

[0037]

[0038] Where, ROTR n (x) represents a 32-bit variable x rotated n bits to the right; W t is a 32-bit word derived from the current 256-bit input data block; K t is a 32-bit additional constant; + is modulo 2 32 addition; AND is a 32-bit bitwise AND operation; NOT is a negation operation; is an exclusive OR operation.

[0039] Next, describe how the 32-bit word W t is derived from the 512-bit data block. W t can be obtained according to the following expression:

[0040] For 0 ≤ t ≤ 15: W t is directly taken from the input data block;

[0041] For 16 ≤ t ≤ 63:

[0042] W t = σ 1 (W t-2 ) + W t-7 + σ 0 (W t-15 ) + W t-16 (Expression 2)

[0043] Where:

[0044]

[0045] Where, ROTRn(x) represents a 32-bit variable x rotated n bits to the right; SHRn(x) represents a 32-bit variable x shifted n bits to the right, filled with 0 on the left; is an exclusive OR operation; + is modulo 2 32 addition.

[0046] Note that the above ∑0(x), ∑ 1 (x), σ0 (x), σ 1 The formula of the (x) function is given by taking SHA - 256 as an example, which is a specific form for processing 32 - bit data. Those skilled in the art know that in other SHA algorithms (such as SHA - 512, etc.) and even other hash algorithms, these functions can be adaptively adopted in other corresponding forms for processing data of other sizes (such as 64 - bit data, etc.).

[0047] Specifically, Figure 2 shows Figure 1 the conventional arithmetic logic between the extended data in the extended registers of two adjacent operation levels in the pipeline structure shown in. The extended registers R0, R 1 , R 9 and R 14 in each operation level are needed to calculate the extended data to be stored in the extended register R 15 in the subsequent operation level. In addition, the extended data in the extended registers R 1 to R 15 can be directly shifted to the corresponding extended registers R 0 to R 14 in the subsequent operation level. Specifically, the extended data w 15 in the extended register R 15 at the (t + 1) - th operation level is obtained by adding the extended data w 0 in the extended register R 0 at the t - th operation level, the extended data σ 0 (w 0 ) in the extended register R 1 at the t - th operation level after being operated by the σ 0 arithmetic unit, the extended data w 1 in the extended register R 9 at the t - th operation level, and the extended data σ 9 (w 1 ) in the extended register R 1 at the t - th operation level after being operated by the σ 14 arithmetic unit in sequence, that is, w 1 ' = w 14 + σ 15 (w 0 ) + w 0 + σ 1 (w 9 ). It can be seen that from the extended registers R 1 , R 14 , R 0 and R 1 , R 9 and R 14The extended data w in 0 , w 1 , w 9 , w 14 Calculate the extended data w to be stored in the extended register R of the next operation level 15 The extended data w in 15 ' needs to go through up to 4 levels of arithmetic logic, which brings significant calculation latency, limits the operation speed of the pipeline structure, and thus makes it difficult to achieve a low power consumption computing ratio.

[0048] In response, the inventors of the present application noticed that there is a direct connection between the extended register R of the (t + 1)th operation level 0 and the extended register R of the tth operation level 1 , that is, the extended data stored in the extended register R of the tth operation level 1 is directly shifted to the extended register R of the (t + 1)th operation level 0 . Therefore, the inventors of the present application thought that the direct connection relationship of the extended registers R 0 , R 1 can be utilized to advance part of the process of calculating the extended data to be stored in the extended register R of the (t + 2)th operation level 15 that involves the extended data in the extended register R of the (t + 1)th operation level 0 (i.e., the extended data in the extended register R of the tth operation level 1 ) to be simultaneous with the process of calculating the extended data to be stored in the extended register R of the (t + 1)th operation level 15 and store it in the extended register R of the (t + 1)th operation level 0 . In this way, after disassembling the process of calculating the extended data to be stored in the extended register R of the (t + 2)th operation level 15 , the disassembled part can be processed in parallel with the process of calculating the extended data to be stored in the extended register R of the (t + 1)th operation level 15 . Through parallel processing, the number of levels of arithmetic logic required to calculate the extended data in each round of operation can be reduced.

[0049] Therefore, the present disclosure provides a circuit for executing a hash algorithm with an improved extended data arithmetic logic module and an improved method for calculating extended data in a circuit for executing a hash algorithm, which can reduce the number of levels of arithmetic logic required to calculate the extended data of the next operation level based on the extended data of the previous operation level between adjacent operation levels, significantly improve the operation speed of the circuit and thus the computing chip including the circuit, and thereby facilitate the achievement of a lower power consumption computing ratio.

[0050] Figure 3FIG. 0 shows a schematic block diagram of a circuit 100 for performing a hash algorithm according to some embodiments of the present disclosure, where the arrows indicate the data transfer direction. The circuit 100 may include an input module 110 and an arithmetic module 120. The input module 110 may be configured to receive data. The arithmetic module 120 may be configured to calculate a hash value based on the received data. The arithmetic module 120 may include a plurality of arithmetic stages 120-0, …, 120-63 arranged in a pipeline structure, and each arithmetic stage may include an extension register R from register 0 0 to register 15 15 of the extension register, and each extension register may be configured to store the extended data of the current arithmetic stage.

[0051] It should be understood that although the arithmetic module 120 is depicted as including 64 arithmetic stages in the drawings, as previously mentioned, only the circuit for performing the SHA-256 algorithm is used herein as a non-limiting example. The circuit according to the present disclosure can actually be applicable to perform any hash algorithm known now or developed in the future (not limited to the SHA series algorithms), and may include any appropriate number of arithmetic stages. It should also be understood that the actual circuit may also have additional other components (such as compression registers, etc.), but in order to avoid obscuring the key points of the present disclosure, these other components are not shown in the drawings and are not discussed herein.

[0052] Generally, the extended data stored in the extension register R from register 0 0 to register 15 15 of the first arithmetic stage 120-0 of the arithmetic module 120 may be directly taken from the data received by the input module 110, and the extended data to be stored in the extension register R from register 0 0 to register 15 15 of each arithmetic stage starting from the arithmetic stage 120-1 may be determined based on the extended data stored in the extension register R from register 0 0 to register 15 15 of the previous arithmetic stage. The present disclosure mainly discusses how to determine the extended data to be stored in the extension register R from register 0 0 to register 15 15 of the previous arithmetic stage for the extension register R from register 0 0 to register 15 15 of the subsequent arithmetic stage.

[0053] The operation module 120 may further include a plurality of extended data operation logic modules 130, and each extended data operation logic module 130 is disposed between two corresponding adjacent operation levels among the plurality of operation levels 120-0, …, 120-63 of the operation module 120. In this document, the operation level in the front among two adjacent operation levels may be referred to as the first operation level and the operation level in the rear among two adjacent operation levels may be referred to as the second operation level. Note that “first” and “second” are only used for distinction and are not restrictive. For example, as Figure 3 shown, an extended data operation logic module 130 is disposed between two adjacent operation levels 120-a and 120-b. Each extended data operation logic module 130 may include a first sub-module 131 and a second sub-module 132.

[0054] The extended data operation logic module 130 may be configured to calculate the extended data to be stored in the extended register of the second operation level (e.g., 120-b) based on the extended data stored in the extended register of the first operation level (e.g., 120-a). The first sub-module 131 may be configured to calculate the extended data to be stored in the 0th extended register R 1 of the second operation level based on the extended data stored in the 1st extended register R 0 of the first operation level. The second sub-module 132 may be configured to calculate the extended data to be stored in the 15th extended register R 0 of the second operation level based on the extended data stored in the 0th extended register R 15 of the first operation level. In addition, the extended data to be stored in the (i-1)th extended register of the second operation level may be the extended data stored in the ith extended register of the first operation level, where 2≤i≤15 and i is an integer. That is to say, in the circuit 100, the extended data to be stored in the 0th extended register R 0 and the 15th extended register R 15 of the second operation level is obtained by operating on the extended data stored in the extended register of the first operation level, while the extended data to be stored in the 1st extended register R 1 to the 14th extended register R 14 of the second operation level is obtained by directly shifting the extended data stored in each of the 2nd extended register R 2 to the 15th extended register R 15 of the first operation level to the corresponding extended register in the 1st extended register R 1 to the 14th extended register R 14 of the second operation level.

[0055] In some embodiments, the 15th extended register R 15The extended data stored therein may be based on the first-level operation's first extended register R 1 , the second extended register R 2 , the tenth extended register R 10 , the fifteenth extended register R 15 determined by the extended data stored therein. In some embodiments, the extended data w 15 stored in the fifteenth extended register R 15 ″ of the subsequent operation level of the second operation level, the extended data w 1 stored in the first extended register R 1 of the first operation level, the extended data w 2 stored in the second extended register R 2 of the first operation level, the extended data w 10 stored in the tenth extended register R 10 of the first operation level, and the extended data w 15 stored in the fifteenth extended register R 15 of the first operation level may satisfy the following relationship: w 15 ″ = w 1 + σ 0 (w 2 ) + w 10 + σ 1 (w 15 ), where the definitions of σ 0 , σ 1 , and + are as described above.

[0056] In some embodiments, the first sub-module 131 may be configured to calculate the extended data to be stored in the zeroth extended register R0 of the second operation level based on the extended data stored in one or both of the second extended register R 2 , the tenth extended register R 10 , and the fifteenth extended register R 15 of the first operation level and the extended data stored in the first extended register R 1 of the first operation level.

[0057] In some embodiments, the second sub-module 132 may be configured to calculate the extended data to be stored in the fifteenth extended register R 1 of the second operation level based on the extended data stored in one or both of the first extended register R 9 , the ninth extended register R 14 , and the fourteenth extended register R 15 of the first operation level and the extended data stored in the zeroth extended register R0 of the first operation level.

[0058] Next, in conjunction with Figures 4 to 7Describing several non - restrictive example configurations of the part including the extended data operation logic module in the circuit as shown in Figure 3 In these figures, taking two adjacent operation levels 120 - a and 120 - b as examples for illustration, it can be understood that any two adjacent operation levels in the operation module 120 can be the operation levels 120 - a and 120 - b discussed below. Additionally, in these figures, for clarity, the first sub - module 131 and the second sub - module 132 are indicated by dashed boxes, the moving direction of the extended data that is directly shifted without going through operations is indicated by dotted - line arrows, the moving direction of the extended data processed by the first sub - module 131 is indicated by dash - dotted arrows, and the moving direction of the extended data processed by the second sub - module 132 is indicated by solid arrows.

[0059] In some embodiments, the first sub - module 131 can be configured to calculate the extended data to be stored in the 0th extended register R 1 of the second operation level based on the extended data stored in the 1st extended register R 2 and the 2nd extended register R 0 of the first operation level, and the second sub - module 132 can be configured to calculate the extended data to be stored in the 15th extended register R 0 of the second operation level based on the extended data stored in the 0th extended register R 9 the 9th extended register R 14 and the 14th extended register R 15 of the first operation level.

[0060] For example, in some examples, as Figure 4 shown, the extended data w 0 in the 0th extended register R 0 of the operation level 120 - b is obtained by processing the extended data w 1 stored in the 1st extended register R 1 and the extended data w 2 stored in the 2nd extended register R 2 of the operation level 120 - a by the first sub - module 131. Specifically, in this example, the first sub - module 131 includes a σ 0 operator for performing the σ 0 operation and an adder ADD1 for performing an addition operation, where the extended data w 2 is input to the σ 0 operator, the output of the σ 0 operator and the extended data w 1 are input to the adder ADD1, and the output of the adder ADD1 is provided to the 0th extended register R 0 of the operation level 120 - b, such that w0 ' = w 1 + σ 0 (w 2 ).

[0061] Furthermore, as shown in Figure 4 the extended data w 15 in the 15th extended register R 15 of operation level 120-b is obtained by the second sub-module 132 processing the extended data w 0 stored in the 0th extended register R 0 of operation level 120-a, the extended data w 9 stored in the 9th extended register R 9 and the extended data w 14 stored in the 14th extended register R 14 . Specifically, in this example, the second sub-module 132 includes a σ 1 operator for performing the σ 1 operation and a full adder FAA and an adder ADD2 for performing an addition operation, where the extended data w 14 is input to the σ 1 operator, the output of the σ 1 operator, the extended data w 0 and the extended data w 9 are input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R 15 of operation level 120-b, such that w 15 ' = w 0 + w 9 + σ 1 (w 14 ).

[0062] Furthermore, as shown in Figure 4 the extended data stored in the ith extended register of operation level 120-a is directly shifted to the (i - 1)th extended register of operation level 120-b, where 2 ≤ i ≤ 15 and i is an integer.

[0063] In Figure 4 the example shown, the number of operation logic levels experienced by the first sub-module 131 is 2 levels, and the number of operation logic levels experienced by the second sub-module 132 is 3 levels. The first sub-module 131 and the second sub-module 132 can operate independently and in parallel with each other, such that the number of operation logic levels required to finally calculate the extended data for operation level 120-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0064] In some embodiments, the first sub-module 131 may be configured to calculate extended data for storage in the 0th extended register R of the second operation level based on the extended data stored in the 1st extended register R and the 10th extended register R of the first operation level. 1 and the 10th extended register R 10 and the extended data stored in the 0th extended register R of the second operation level, and the second sub-module 132 may be configured to calculate extended data for storage in the 15th extended register R of the second operation level based on the extended data stored in the 0th extended register R, the 1st extended register R, and the 14th extended register R of the first operation level. 0 In some examples, for instance, as 0 shown, the extended data w 1 ' in the 0th extended register R of operation level 120-b is obtained by the first sub-module 131 processing the extended data w 14 stored in the 1st extended register R and the extended data w 15 stored in the 10th extended register R of operation level 120-a. Specifically, in this example, the first sub-module 131 includes an adder ADD1 for performing an addition operation, where the extended data w

[0065] For example, in some examples, as Figure 5 shown, the extended data w 0 in the 0th extended register R of operation level 120-b is obtained by the first sub-module 131 processing the extended data w 0 stored in the 1st extended register R of operation level 120-a and the extended data w 1 stored in the 10th extended register R. Specifically, in this example, the first sub-module 131 includes an adder ADD1 for performing an addition operation, where the extended data w 1 and the extended data w 10 are input into the adder ADD1, and the output of the adder ADD1 is provided to the 0th extended register R of operation level 120-b, such that w 10 ' = w 1 + w 10 . 0 such that w 0 ' = w 1 + w 10 .

[0066] Furthermore, as Figure 5 shown, the extended data w 15 ' in the 15th extended register R of operation level 120-b is obtained by the second sub-module 132 processing the extended data w 15 stored in the 0th extended register R, the extended data w 0 stored in the 1st extended register R, and the extended data w 0 stored in the 14th extended register R of operation level 120-a. Specifically, in this example, the second sub-module 132 includes a σ 1 operation unit for performing a σ 1 operation, a σ 14 and the extended data w 14 stored in the 14th extended register R. Specifically, in this example, the second sub-module 132 includes a σ 0 operation unit for performing a σ 0 operation, a σ 1The σ of the operation 1 An arithmetic unit, a full adder FAA for performing addition operations, and an adder ADD2, where the extended data w 1 is input to σ 0 The arithmetic unit, the extended data w 14 is input to σ 1 The arithmetic unit, σ 0 The operation with σ 1 The operations, for example, can be performed simultaneously. Then, σ 0 The output of the arithmetic unit, σ 1 The output of the arithmetic unit, and the extended data w 0 are input to the full adder FAA. The output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R of the operation level 120-b 15 , such that w 15 ′ = w 0 +σ o (w 1 ) + σ 1 (w 14 ).

[0067] Furthermore, as Figure 5 shown, the extended data stored in the i-th extended register of the operation level 120-a is directly shifted to the (i - 1)-th extended register of the operation level 120-b, where 2 ≤ i ≤ 15 and i is an integer.

[0068] In Figure 5 the example shown, the number of operation logic levels experienced by the first sub-module 131 is 1 level, and the number of operation logic levels experienced by the second sub-module 132 is 3 levels. The first sub-module 131 and the second sub-module 132 can operate independently and in parallel with each other, such that the number of operation logic levels required to finally calculate the extended data for the operation level 120-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0069] In some embodiments, the first sub-module 131 can be configured to calculate the extended data to be stored in the 0th extended register R of the second operation level based on the extended data stored in the 1st extended register R 1 , the 2nd extended register R 2 and the 10th extended register R 10 of the first operation level, and the second sub-module 132 can be configured to calculate the extended data to be stored in the 15th extended register R 0 of the second operation level based on the extended data stored in the 0th extended register R 14 and the 14th extended register R 15 of the first operation level.

[0070] For example, in some examples, as Figure 6 shown, the extended data w 0 in the 0th extended register R of operation level 120-b 0 ′ is obtained by the first sub-module 131 processing the extended data w 1 stored in the 1st extended register R of operation level 120-a 1 , the extended data w 2 stored in the 2nd extended register R 2 and the extended data w 10 stored in the 10th extended register R 10 . Specifically, in this example, the first sub-module 131 includes a σ 0 operator for performing the σ 0 operation, a full adder FAA and an adder ADD1 for performing addition operations, where the extended data w 2 is input to the σ 0 operator, the output of the σ 0 operator, the extended data w 1 and the extended data w1 0 are input to the full adder FAA, the output of the full adder FAA is input to the adder ADD1, and the output of the adder ADD1 is provided to the 0th extended register R of operation level 120-b 0 , such that w 0 ′ = w 1 + σ 0 (w 2 ) + w 10 .

[0071] Furthermore, as Figure 6 shown, the extended data w 15 in the 15th extended register R of operation level 120-b 15 ′ is obtained by the second sub-module 132 processing the extended data w 0 stored in the 0th extended register R of operation level 120-a 0 and the extended data w 14 stored in the 14th extended register R 14 . Specifically, in this example, the second sub-module 132 includes a σ 1 operator for performing the σ 1 operation and an adder ADD2 for performing addition operations, where the extended data w 14 is input to the σ 1 operator, the output of the σ 1 operator and the extended data w 0is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R of the operation stage 120-b 15 , such that w 15 ′ = w 0 + σ 1 (w 14 ).

[0072] Furthermore, as Figure 6 shown, the extended data stored in the i-th extended register of the operation stage 120-a is directly shifted to the (i - 1)-th extended register of the operation stage 120-b, where 2 ≤ i ≤ 15 and i is an integer.

[0073] In Figure 6 the example shown, the number of operation logic levels experienced by the first sub-module 131 is 3 levels, and the number of operation logic levels experienced by the second sub-module 132 is 2 levels. The first sub-module 131 and the second sub-module 132 can operate in parallel independently of each other, so that the number of operation logic levels required to finally calculate the extended data for the operation stage 120-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0074] In some embodiments, the first sub-module 131 can be configured to calculate the extended data to be stored in the 0th extended register R 1 and the 15th extended register R 15 of the first operation stage based on the extended data stored therein for the extended data to be stored in the 0th extended register R 0 of the second operation stage, and the second sub-module 132 can be configured to calculate the extended data to be stored in the 15th extended register R 0 of the second operation stage based on the extended data stored in the 0th extended register R 1 , the 1st extended register R 9 and the 9th extended register R 15 of the first operation stage.

[0075] For example, in some examples, as Figure 7 shown, the extended data w 0 in the 0th extended register R 0 of the operation stage 120-b is obtained by the first sub-module 131 processing the extended data w 1 stored in the 1st extended register R 1 of the operation stage 120-a and the extended data w 15 stored in the 15th extended register R 15 . Specifically, in this example, the first sub-module 131 includes a σ 1 for performing the σ 1An arithmetic unit and an adder ADD1 for performing an addition operation, where the extended data w 15 is input to σ 1 the arithmetic unit, and σ 1 the output of the arithmetic unit and the extended data w 1 are input to the adder ADD1, and the output of the adder ADD1 is provided to the 0th extended register R of the operation stage 120-b 0 , such that w 0 ′ = w 1 + σ 1 (w 15 ).

[0076] Furthermore, as Figure 7 shown, the extended data w 15 in the 15th extended register R of the operation stage 120-b 15 is obtained by the second sub-module 132 processing the extended data w 0 stored in the 0th extended register R of the operation stage 120-a 0 , the extended data w 1 stored in the 1st extended register R 1 and the extended data w 9 stored in the 9th extended register R 9 . Specifically, in this example, the second sub-module 132 includes a σ 0 arithmetic unit for performing the σ 0 operation and a full adder FAA and an adder ADD2 for performing an addition operation, where the extended data w 1 is input to the σ 0 arithmetic unit, the output of the σ 0 arithmetic unit, the extended data w 0 and the extended data w 9 are input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R of the operation stage 120-b 15 , such that w 15 ′ = w 0 + σ 0 (w 1 ) + w 9 .

[0077] Furthermore, as Figure 7 shown, the extended data stored in the ith extended register of the operation stage 120-a is directly shifted to the (i - 1)th extended register of the operation stage 120-b, where 2 ≤ i ≤ 15 and i is an integer.

[0078] In Figure 7In the illustrated example, the number of arithmetic logic levels experienced by the first sub-module 131 is 2 levels, and the number of arithmetic logic levels experienced by the second sub-module 132 is 3 levels. The first sub-module 131 and the second sub-module 132 can operate in parallel independently of each other, so that the number of arithmetic logic levels required to finally calculate the extended data for arithmetic level 120-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0079] In some embodiments, the first sub-module 131 may be configured to calculate the extended data to be stored in the 0th extended register R0 of the second arithmetic level based on the extended data stored in the 1st extended register R 1 , the 2nd extended register R 2 and the 15th extended register R 15 of the first arithmetic level, and the second sub-module 132 may be configured to calculate the extended data to be stored in the 15th extended register R 0 based on the extended data stored in the 0th extended register R 9 and the 9th extended register R 15 of the first arithmetic level. Specifically, in some examples, the extended data w 0 in the 0th extended register R 0 of arithmetic level 120-b can be obtained by the first sub-module 131 processing the extended data w 1 stored in the 1st extended register R 1 of arithmetic level 120-a, the extended data w 2 stored in the 2nd extended register R 2 and the extended data w 15 stored in the 15th extended register R 15 . The extended data w 15 in the 15th extended register R 15 of arithmetic level 120-b can be obtained by the second sub-module 132 processing the extended data w 0 stored in the 0th extended register R 0 and the extended data w 9 stored in the 9th extended register R 9 , such that w 0 ′ = w 1 + σ 0 (w 2 ) + σ 1 (w 15 ), w 15 ′ = w 0 + w 9 .

[0080] In some embodiments, the first sub-module 131 may be configured to calculate extended data for storing in the 0th extended register R0 of the second operation level based on the extended data stored in the 1st extended register R 1 , the 10th extended register R 10 and the 15th extended register R 15 of the first operation level, and the second sub-module 132 may be configured to calculate extended data for storing in the 15th extended register of the second operation level based on the extended data stored in the 0th extended register R 0 and the 1st extended register R 1 of the first operation level. Specifically, in some examples, the extended data w 0 in the 0th extended register R 0 of the operation level 120-b may be obtained by the first sub-module 131 processing the extended data w 1 stored in the 1st extended register R 1 of the operation level 120-a, the extended data w1 10 stored in the 10th extended register R 0 and the extended data w 15 stored in the 15th extended register R 15 of the operation level 120-a, and the extended data w 15 in the 15th extended register R 15 of the operation level 120-b may be obtained by the second sub-module 132 processing the extended data w 0 stored in the 0th extended register R 0 and the extended data w 1 stored in the 1st extended register R 1 of the operation level 120-a, such that w 0 ′ = w 1 + w 10 + σ 1 (w 15 ), w 15 ′ = w 0 + σ 0 (w 1 ).

[0081] Correspondingly, the present disclosure also provides a method for calculating extended data in a circuit for performing a hash algorithm. Figure 13FIG. 0 shows an exemplary flowchart of method 300 for calculating extended data in a circuit for performing a hash algorithm according to an embodiment of the present disclosure. Such a circuit may include an input module configured to receive data and an arithmetic module configured to calculate a hash value based on the received data, where the arithmetic module may include a plurality of arithmetic levels arranged in a pipeline structure, and each arithmetic level may include extension registers from extension register 0 to extension register 15, and each extension register may be configured to store the extended data of the current arithmetic level. For two adjacent arithmetic levels among the plurality of arithmetic levels of the arithmetic module, including the first arithmetic level and the second arithmetic level after the first arithmetic level, method 300 may include: at S301, calculating the extended data to be stored in extension register 0 of the second arithmetic level based on the extended data stored in extension register 1 of the first arithmetic level; at S302, calculating the extended data to be stored in extension register 15 of the second arithmetic level based on the extended data stored in extension register 0 of the first arithmetic level; and at S303, using the extended data stored in extension register i of the first arithmetic level as the extended data to be stored in extension register (i - 1) of the second arithmetic level, where 2 ≤ i ≤ 15 and i is an integer. Note that S301 - S303 do not need to be executed in sequential order, but may be executed in any order, or may be executed at least partially in parallel.

[0082] In some embodiments, calculating the extended data to be stored in extension register 0 of the second arithmetic level and calculating the extended data to be stored in extension register 15 of the second arithmetic level may be performed simultaneously.

[0083] In some embodiments, the extended data stored in extension register 15 of the arithmetic level subsequent to the second arithmetic level may be determined based on the extended data stored in extension registers 1, 2, 10, and 15 of the first arithmetic level.

[0084] Method 300 may also calculate the extended data in various ways described above regarding the first sub-module 131 and the second sub-module 132, which will not be elaborated here. Method 300 can reduce the calculation delay caused by calculating the extended data in the circuit for performing the hash algorithm, thereby significantly improving the operation speed of the circuit and thus the computing chip including the circuit, and thus achieving a lower power consumption computing ratio.

[0085] In addition, in the circuit and method according to the above embodiments of the present disclosure, the extended register R 0 is used to store the process of the extended data involved in the previous arithmetic level in advance during the process of originally calculating the extended data to be stored in the extended register R 15 for the subsequent arithmetic level 1The portion of the extended data in. In some alternative embodiments, additional registers may also be used to alternatively implement the extended register R 0 The role played in the above embodiments. Moreover, when additional registers are used, they can not only be used to advance the process of storing the extended data in the extended register R that was originally used to calculate the subsequent operation level 15 During the process of storing the extended data to be stored in R, the extended register R of the previous operation level is involved 1 The portion of the extended data in, and can also advance any suitable part of the process of storing the extended data to be stored in the extended register R that was originally used to calculate the subsequent operation level 15 In the process.

[0086] Figure 8 FIG. shows a schematic block diagram of a circuit 200 for performing a hash algorithm according to some further embodiments of the present disclosure. The arrows therein indicate the data transfer direction. The circuit 200 may include an input module 210 and an operation module 220. The input module 210 may be configured to receive data. The operation module 220 may be configured to calculate a hash value based on the received data. The operation module 220 may include a plurality of operation levels 220-0,..., 220-63 arranged in a pipeline structure, and each operation level may include a 0th extended register R 0 To the 15th extended register R 15 And an additional register X. Each extended register may be configured to store the extended data of the current operation level, and the additional register may be configured to store intermediate data for calculating the extended data. In some embodiments, the intermediate data stored in the additional register X of the foremost operation level 220-0 may be the same as the extended data stored in the 0th extended register R 0 Of the foremost operation level 220-0.

[0087] The operation module 220 may further include a plurality of extended data operation logic modules 230, and each extended data operation logic module 230 is disposed between corresponding adjacent two operation levels among the plurality of operation levels 220-0,..., 220-63 of the operation module 220. Herein, the previous operation level among the adjacent two operation levels may be referred to as the first operation level and the subsequent operation level among the adjacent two operation levels may be referred to as the second operation level. Note that "first" and "second" are only for distinction and not restrictive. For example, as Figure 8 Shown, an extended data operation logic module 230 is disposed between two adjacent operation levels 220-a and 220-b. Each extended data operation logic module 230 may include a first sub-module 231 and a second sub-module 232.

[0088] The extended data operation logic module 230 may be configured to calculate the extended data for storage in the extended register of the second operation level (e.g., 220-b) and the intermediate data for storage in the additional register of the second operation level based on the extended data stored in the extended register of the first operation level (e.g., 220-a) and the intermediate data stored in the additional register of the first operation level (e.g., 220-a). The first submodule 231 may be configured to calculate the intermediate data for storage in the additional register of the second operation level based on the extended data stored in the extended register of the first operation level. The second submodule 232 may be configured to calculate the extended data for storage in the 15th extended register of the second operation level based on the intermediate data stored in the additional register of the first operation level. In addition, the extended data for storage in the (i-1)th extended register of the second operation level may be the extended data stored in the i-th extended register of the first operation level, where 1≤i≤15 and i is an integer. That is, in the circuit 200, the 15th extended register R of the second operation level 15 The extended data to be stored in is obtained by operating on the intermediate data stored in the additional register of the first operation stage, while the 0th extended register R of the second operation stage 0 To the 14th extended register R 14 The extended data to be stored in the first operation stage is obtained by placing the first extended register R 1 To the 15th extended register R 15 The extended data stored in each extended register in the second operation stage is directly shifted to the 0th extended register R 0 To the 14th extended register R 14 The corresponding extended register in is obtained.

[0089] In some embodiments, the 15th extended register R of the next operation stage after the second operation stage 15 The extended data stored in the first operation level may be based on the first extended register R 1 , the second extended register R 2 , 10th extended register R 10 , 15th extended register R 15 In some embodiments, the 15th extended register R of the next operation stage after the second operation stage 15 The extended data stored in 15 ″, the first extended register R of the first operation stage 1 The extended data stored in 1 , the second extended register R of the first operation stage 2 The extended data stored in 2 , the 10th extended register R of the first operation stage 10Extended data w1 stored in 0 and the 15th extended register R of the first operation level 15 The extended data w stored in 15 can satisfy the following relationship: w 15 ″ = w 1 + σ 0 (w 2 ) + w 10 + σ 1 (w 15 ), where σ 0 , σ 1 , and + are defined as described above.

[0090] In some embodiments, the first sub-module 231 may be configured to calculate intermediate data to be stored in the additional register X of the second operation level based on the extended data stored in two or three of the 1st extended register R 1 , the 2nd extended register R 2 , the 10th extended register R 10 , and the 15th extended register R 15 of the first operation level.

[0091] In some embodiments, the second sub-module 232 may be configured to calculate the extended data to be stored in the 15th extended register R 0 of the second operation level based on the extended data stored in one or two of the 0th extended register R 1 , the 1st extended register R 9 , the 9th extended register R 14 , and the 14th extended register R 15 of the first operation level and the intermediate data stored in the additional register X of the first operation level.

[0092] The following describes Figures 9 to 14 several non-limiting example configurations of the part including the extended data operation logic module in the circuit as shown in Figure 8 according to the embodiments of the present disclosure. In these figures, two adjacent operation levels 220-a and 220-b are taken as examples for illustration. It can be understood that any two adjacent operation levels in the operation module 220 can be the operation levels 220-a and 220-b discussed below. Additionally, in these figures, for clarity, the first sub-module 231 and the second sub-module 232 are indicated by dashed boxes, the movement direction of the extended data that is directly shifted without passing through the operation is indicated by dotted arrows, the movement direction of the extended data processed by the first sub-module 231 is indicated by dash-dotted arrows, and the movement direction of the extended data processed by the second sub-module 232 is indicated by solid arrows.

[0093] In some embodiments, the first sub-module 231 may be configured to calculate intermediate data for storage in the additional register X of the second operation level based on the extended data stored in the first extended register R 1 and the second extended register R 2 of the first operation level, and the second sub-module 232 may be configured to calculate the extended data for storage in the 15th extended register R 9 of the second operation level based on the intermediate data stored in the additional register X of the first operation level and the extended data stored in the 9th extended register R 14 and the 14th extended register R 15 of the first operation level.

[0094] For example, in some examples, as Figure 9 shown, the intermediate data w x ′ in the additional register X of the operation level 220-b is obtained by the first sub-module 231 processing the extended data w 1 stored in the first extended register R 1 of the operation level 220-a and the extended data w 2 stored in the second extended register R 2 of the operation level 220-a. Specifically, in this example, the first sub-module 231 includes a σ 0 operator for performing a σ 0 operation and an adder ADD1 for performing an addition operation, where the extended data w 2 is input to the σ 0 operator, the output of the σ 0 operator and the extended data w 1 are input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the operation level 220-b, such that w x ′ = w 1 + σ 0 (w 2 ).

[0095] Furthermore, as Figure 9 shown, the extended data w 15 in the 15th extended register R 15 of the operation level 220-b is obtained by the second sub-module 232 processing the intermediate data w x stored in the additional register X of the operation level 220-a, the extended data w 9 stored in the 9th extended register R 9 of the operation level 220-a, and the extended data w 14 stored in the 14th extended register R 14 of the operation level 220-a. Specifically, in this example, the second sub-module 232 includes a σ 1 operator for performing a σ1 An arithmetic unit, a full adder FAA for performing addition operations, and an adder ADD2, where the extended data w 14 is input to σ 1 arithmetic unit, and σ 1 the output of the arithmetic unit, the intermediate data w x and the extended data w 9 are input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R of the operation stage 220-b 15 , such that w 15 ′ = w x + w 9 + σ 1 (w 14 ).

[0096] Furthermore, as Figure 9 shown, the extended data stored in the ith extended register of the operation stage 220-a is directly shifted to the (i - 1)th extended register of the operation stage 220-b, where 1 ≤ i ≤ 15 and i is an integer.

[0097] In Figure 9 the example shown, the number of operation logic levels experienced by the first sub-module 231 is 2 levels, and the number of operation logic levels experienced by the second sub-module 232 is 3 levels. The first sub-module 231 and the second sub-module 232 can operate independently and in parallel with each other, such that the number of operation logic levels required to finally calculate the extended data for the operation stage 220-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0098] In some embodiments, the first sub-module 231 can be configured to calculate intermediate data for storing in the additional register X of the second operation stage based on the extended data stored in the 1st extended register R 1 and the 10th extended register R 10 of the first operation stage, and the second sub-module 232 can be configured to calculate the extended data for storing in the 15th extended register R 1 of the second operation stage based on the intermediate data stored in the additional register X of the first operation stage and the extended data stored in the 1st extended register R 14 and the 14th extended register R 15 of the first operation stage.

[0099] For example, in some examples, as Figure 10 shown, the intermediate data w x ′ in the additional register X of the operation stage 220-b is processed by the first sub-module 231 through the 1st extended register R of the operation stage 220-a1 Extended data w stored therein 1 and the 10th extended register R 10 Extended data w stored therein 10 is obtained. Specifically, in this example, the first sub-module 231 includes an adder ADD1 for performing an addition operation, where the extended data w 1 and the extended data w 10 are input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the operation stage 220-b, such that w x ′ = w 1 + w 10 .

[0100] Furthermore, as Figure 10 shown, the extended data w 15 in the 15th extended register R of the operation stage 220-b 15 ′ is obtained by the second sub-module 232 processing the intermediate data w stored in the additional register X of the operation stage 220-a x , the extended data w 1 stored in the 1st extended register R 1 and the extended data w 14 stored in the 14th extended register R 14 . Specifically, in this example, the second sub-module 232 includes a σ 0 operator for performing a σ 0 operation, a σ 1 operator for performing a σ 1 operation, and a full adder FAA and an adder ADD2 for performing an addition operation, where the extended data w 1 is input to the σ 0 operator, the extended data w 14 is input to the σ 1 operator, and the σ 0 operation and the σ 1 operation can be performed simultaneously, for example. Then, the output of the σ 0 operator, the output of the σ 1 operator, and the intermediate data w x are input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R of the operation stage 220-b 15 , such that w 15 ′ = w x + σ 0 (w 1 ) + σ 1 (w 14 ).

[0101] Furthermore, as Figure 10 shown, the extended data stored in the i-th extended register of arithmetic level 220-a is directly shifted to the (i-1)-th extended register of arithmetic level 220-b, where 1 ≤ i ≤ 15 and i is an integer.

[0102] In Figure 10 the example shown, the number of arithmetic logic levels experienced by the first sub-module 231 is 1 level, and the number of arithmetic logic levels experienced by the second sub-module 232 is 3 levels. The first sub-module 231 and the second sub-module 232 can operate in parallel independently of each other, so that the number of arithmetic logic levels required to finally calculate the extended data for arithmetic level 220-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0103] In some embodiments, the first sub-module 231 may be configured to calculate intermediate data for storing in the additional register X of the second arithmetic level based on the extended data stored in the 1st extended register R 1 , the 2nd extended register R 2 and the 10th extended register R 10 of the first arithmetic level, and the second sub-module 232 may be configured to calculate the extended data for storing in the 15th extended register R1 14 of the second arithmetic level based on the intermediate data stored in the additional register X of the first arithmetic level and the extended data stored in the 14th extended register R 5 of the first arithmetic level.

[0104] For example, in some examples, as Figure 11 shown, the intermediate data w x ′ in the additional register X of arithmetic level 220-b is obtained by the first sub-module 231 processing the extended data w 1 stored in the 1st extended register R 1 of arithmetic level 220-a, the extended data w 2 stored in the 2nd extended register R 2 and the extended data w 10 stored in the 10th extended register R 10 . Specifically, in this example, the first sub-module 231 includes a σ 0 operator for performing the σ 0 operation and a full adder FAA and an adder ADD1 for performing an addition operation, where the extended data w 2 is input to the σ 0 operator, and the output of the σ 0 operator, the extended data w 1 and the extended data w1 0is input to the full adder FAA, and the output of the full adder FAA is input to the adder ADD1. The output of the adder ADD1 is provided to the additional register X of the operation stage 220-b, such that w x ′ = w 1 + σ 0 (w 2 ) + w 10 .

[0105] Furthermore, as Figure 11 shown, the extended data w 15 in the 15th extended register R 15 of the operation stage 220-b is obtained by the second sub-module 232 processing the intermediate data w x stored in the additional register X of the operation stage 220-a and the extended data w 14 stored in the 14th extended register R 14 . Specifically, in this example, the second sub-module 232 includes a σ 1 operator for performing the σ 1 operation and an adder ADD2 for performing an addition operation. The extended data w 14 is input to the σ 1 operator. The output of the σ 1 operator and the intermediate data w x are input to the adder ADD2. The output of the adder ADD2 is provided to the 15th extended register R 15 of the operation stage 220-b, such that w 15 ′ = w x + σ 1 (w 14 ).

[0106] Furthermore, as Figure 11 shown, the extended data stored in the ith extended register of the operation stage 220-a is directly shifted to the (i - 1)th extended register of the operation stage 220-b, where 1 ≤ i ≤ 15 and i is an integer.

[0107] In Figure 11 the example shown, the number of operation logic levels experienced by the first sub-module 231 is 3 levels, and the number of operation logic levels experienced by the second sub-module 232 is 2 levels. The first sub-module 231 and the second sub-module 232 can operate independently and in parallel with each other, such that the number of operation logic levels required to finally calculate the extended data for the operation stage 220-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0108] In some embodiments, the first sub-module 231 may be configured to be based on the 1st extended register R 1and the 15th extended register R 15 calculate intermediate data to be stored in the additional register X of the second operation level based on the extended data stored in the additional register X of the first operation level and the 1st extended register R of the first operation level, and the second sub-module 232 can be configured to calculate the extended data to be stored in the 15th extended register R of the second operation level based on the intermediate data stored in the additional register X of the first operation level and the extended data stored in the 9th extended register R 1 and the 9th extended register R 9 in it. 15 The extended data in

[0109] For example, in some examples, as Figure 12 shown, the intermediate data w in the additional register X of the operation level 220-b x ′ is obtained by the first sub-module 231 processing the extended data w stored in the 1st extended register R of the operation level 220-a 1 in it. 1 and the 15th extended register R 15 in it. 15 Specifically, in this example, the first sub-module 231 includes a σ 1 operation for performing the σ 1 operation and an adder ADD1 for performing an addition operation, where the extended data w 15 is input to the σ 1 operation, the output of the σ 1 operation and the extended data w 1 are input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the operation level 220-b, so that w x ′ = w 1 + σ 1 (w 15 ).

[0110] Furthermore, as Figure 12 shown, the extended data w in the 15th extended register R of the operation level 220-b 15 in it 15 ′ is obtained by the second sub-module 232 processing the intermediate data w stored in the additional register X of the operation level 220-a, the extended data w stored in the 1st extended register R x in it, 1 the extended data w stored in the 9th extended register R 1 in it 9 and the extended data w stored in the 9th extended register R 9 in it. Specifically, in this example, the second sub-module 232 includes a σ 0 operation for performing the σ 0 operation and a full adder FAA and an adder ADD2 for performing an addition operation, where the extended data w1 is input into σ 0 the arithmetic unit, σ 0 the output of the arithmetic unit, intermediate data w x and extended data w 9 are input into the full adder FAA, the output of the full adder FAA is input into the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R of the operation level 220-b 15 , such that w 15 ′ = w x + σ 0 (w 1 ) + w 9 .

[0111] Furthermore, as Figure 12 shown, the extended data stored in the ith extended register of the operation level 220-a is directly shifted to the (i - 1)th extended register of the operation level 220-b, where 1 ≤ i ≤ 15 and i is an integer.

[0112] In Figure 12 the example shown, the number of operation logic levels experienced by the first sub-module 231 is 2 levels, and the number of operation logic levels experienced by the second sub-module 232 is 3 levels. The first sub-module 231 and the second sub-module 232 can operate in parallel independently of each other, so that the number of operation logic levels required to finally calculate the extended data for the operation level 220-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0113] In some embodiments, the first sub-module 231 can be configured to calculate the intermediate data for storing in the additional register X of the second operation level based on the extended data stored in the 1st extended register R 1 , the 2nd extended register R 2 and the 15th extended register R 15 of the first operation level, and the second sub-module 232 can be configured to calculate the extended data for storing in the 15th extended register R 9 of the second operation level based on the intermediate data stored in the additional register X of the first operation level and the extended data stored in the 9th extended register R 15 of the first operation level. Specifically, in some examples, the intermediate data w x ′ in the additional register X of the operation level 220-b can be obtained by the first sub-module 231 processing the extended data w 1 stored in the 1st extended register R 1 of the operation level 220-a 2 , the extended data w 2 stored in the 2nd extended register R 15Extended data w stored in 15 obtained from the 15th extended register R of arithmetic level 220-b 15 the extended data w in 15 ′ can be obtained by the second sub-module 232 processing the intermediate data w stored in the additional register X of arithmetic level 220-a x and the extended data w stored in the 9th extended register R of arithmetic level 220-a 9 the extended data w stored in 9 such that w x ′ = w 1 + σ 0 (w 2 ) + σ 1 (w 15 ), w 15 ′ = w x + w 9 .

[0114] In some embodiments, the first sub-module 231 may be configured to calculate intermediate data for storage in the additional register X of the second arithmetic level based on the extended data stored in the 1st extended register R, the 10th extended register R, and the 15th extended register R of the first arithmetic level, and the second sub-module 232 may be configured to calculate extended data for storage in the 15th extended register of the second arithmetic level based on the intermediate data stored in the additional register X of the first arithmetic level and the extended data stored in the 1st extended register R of the first arithmetic level. Specifically, in some examples, the intermediate data w′ in the additional register X of arithmetic level 220-b can be obtained by the first sub-module 231 processing the extended data w stored in the 1st extended register R of arithmetic level 220-a, the extended data w1 stored in the 10th extended register R, and the extended data w stored in the 15th extended register R. The extended data w′ in the 15th extended register R of arithmetic level 220-b can be obtained by the second sub-module 232 processing the intermediate data w in the additional register X of arithmetic level 220-a and the extended data w stored in the 1st extended register R of arithmetic level 220-a, such that w′ = w + w + σ 1 the 1st extended register R 10 the 10th extended register R 15 and the extended data stored in the 15th extended register R of the first arithmetic level, and the second sub-module 232 may be configured to calculate extended data for storage in the 15th extended register of the second arithmetic level based on the intermediate data stored in the additional register X of the first arithmetic level and the extended data stored in the 1st extended register R of the first arithmetic level. Specifically, in some examples, the intermediate data w′ in the additional register X of arithmetic level 220-b can be obtained by the first sub-module 231 processing the extended data w stored in the 1st extended register R of arithmetic level 220-a, the extended data w1 stored in the 10th extended register R, and the extended data w stored in the 15th extended register R. The extended data w′ in the 15th extended register R of arithmetic level 220-b can be obtained by the second sub-module 232 processing the intermediate data w in the additional register X of arithmetic level 220-a and the extended data w stored in the 1st extended register R of arithmetic level 220-a, such that w′ = w + w + σ 1 the 1st extended register R x the intermediate data w′ in the additional register X of arithmetic level 220-b 1 can be obtained by the first sub-module 231 processing the extended data w stored in the 1st extended register R of arithmetic level 220-a 1 the 10th extended register R 10 the extended data w1 stored in 0 and the extended data w stored in the 15th extended register R 15 the extended data w′ in the 15th extended register R of arithmetic level 220-b 15 can be obtained by the second sub-module 232 processing the intermediate data w in the additional register X of arithmetic level 220-a 15 and the extended data w stored in the 1st extended register R of arithmetic level 220-a 15 such that w x ′ = w 1 + w 1 + σ x ′ = w 1 + w 10 + σ1 (w 15 ), w 15 ′ = w x + σ 0 (w 1 ).

[0115] In some embodiments, the first sub-module 231 may be configured to calculate intermediate data for storage in the additional register X of the second arithmetic level based on the extended data stored in the 2nd extended register R 2 and the 10th extended register R 10 of the first arithmetic level, and the second sub-module 232 may be configured to calculate the extended data for storage in the 15th extended register R 14 of the second arithmetic level based on the intermediate data stored in the additional register X of the first arithmetic level and the extended data stored in the 0th extended register R0 and the 14th extended register R 15 of the first arithmetic level.

[0116] For example, in some examples, as Figure 13 shown, the intermediate data w x ′ in the additional register X of the arithmetic level 220-b is obtained by the first sub-module 231 processing the extended data w 2 stored in the 2nd extended register R 2 of the arithmetic level 220-a and the extended data w 10 stored in the 10th extended register R 10 . Specifically, in this example, the first sub-module 231 includes a σ 0 operator for performing the σ 0 operation and an adder ADD1 for performing an addition operation, where the extended data w 2 is input to the σ 0 operator, the output of the σ 0 operator and the extended data w1 0 are input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the arithmetic level 220-b, such that w x ′ = σ 0 (w 2 ) + w 10 .

[0117] Furthermore, as Figure 13 shown, the extended data w 15 ′ in the 15th extended register R 15 of the arithmetic level 220-b is obtained by the second sub-module 232 processing the intermediate data w x stored in the additional register X of the arithmetic level 220-a, the 0th extended register R 0Extended data w stored in 0 and the 14th extended register R 14 The extended data w stored in 14 is obtained. Specifically, in this example, the second sub-module 232 includes a sigma 1 operator for performing the sigma 1 operation, a full adder FAA and an adder ADD2 for performing addition operations. The extended data w 14 is input to the sigma 1 operator. The output of the sigma 1 operator, the intermediate data w x and the extended data w 0 are input to the full adder FAA. The output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R 15 of the operation stage 220-b, such that w 15 ' = w x + w 0 + sigma 1 (w 14 ).

[0118] Furthermore, as Figure 13 shown, the extended data stored in the i-th extended register of the operation stage 220-a is directly shifted to the (i - 1)-th extended register of the operation stage 220-b, where 1 ≤ i ≤ 15 and i is an integer.

[0119] In Figure 13 the shown example, the number of operation logic levels experienced by the first sub-module 231 is 2 levels, and the number of operation logic levels experienced by the second sub-module 232 is 3 levels. The first sub-module 231 and the second sub-module 232 can operate independently and in parallel with each other, such that the number of operation logic levels required to finally calculate the extended data for the operation stage 220-b is reduced to 3 levels, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0120] In some embodiments, the first sub-module 231 can be configured to calculate intermediate data for storing in the additional register X of the second operation stage based on the extended data stored in the 2nd extended register R 2 , the 10th extended register R 10 and the 15th extended register R 15 of the first operation stage, and the second sub-module 232 can be configured to calculate the extended data for storing in the 15th extended register R 15 of the second operation stage based on the intermediate data stored in the additional register X of the first operation stage and the extended data stored in the 0th extended register R0 of the first operation stage.

[0121] For example, in some examples, such as Figure 14 As shown, the intermediate data w in the additional register X of the operation stage 220-b x ′ is the second extended register R of the operation stage 220-a processed by the first submodule 231 2 The extended data stored in 2 , 10th extended register R 10 The extended data stored in 10 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the first submodule 231 includes a module for executing σ 0 σ of operation 0 Operator, used to execute σ 1 σ of operation 1 The arithmetic unit and the full adder FAA and the adder ADD1 for performing the addition operation, wherein the extended data w 2 is input into σ 0 Operator, extended data w 15 is input into σ 1 Operator, σ 0 Operation and σ 1 The operations can be performed simultaneously. Then, σ 0 The output of the operator, σ 1 Output of the operator and extended data w1 0 is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the operation stage 220-b, so that w x ′=σ 0 (w 2 )+w 10 +σ 1 (w 15 ).

[0122] Further Figure 14 As shown, the 15th extended register R of the operation stage 220-b 15 The extended data in w 15 ′ is the intermediate data w stored in the additional register X of the processing operation stage 220-a by the second submodule 232 x and the 0th extended register R 0 The extended data stored in 0 Specifically, in this example, the second submodule 232 includes an adder ADD2, in which the intermediate data w x And the extended data w 0 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 15th extended register R of the operation stage 220-b.15 , such that w 15 ' = w x + w 0 .

[0123] Furthermore, as Figure 14 shown, the extended data stored in the i-th extended register of arithmetic stage 220-a is directly shifted to the (i - 1)-th extended register of arithmetic stage 220-b, where 1 ≤ i ≤ 15 and i is an integer.

[0124] In Figure 14 the example shown, the number of arithmetic logic stages experienced by the first sub-module 231 is 3 stages, and the number of arithmetic logic stages experienced by the second sub-module 232 is 1 stage. The first sub-module 231 and the second sub-module 232 can operate in parallel independently of each other, so that the number of arithmetic logic stages required to finally calculate the extended data for arithmetic stage 220-b is reduced to 3 stages, greatly reducing the calculation delay and significantly improving the operation speed of the pipeline structure.

[0125] In some embodiments, the first sub-module 231 can be configured to calculate intermediate data for storage in the additional register X of the second arithmetic stage based on the extended data stored in the 2nd extended register R 2 and the 15th extended register R 15 of the first arithmetic stage, and the second sub-module can be configured to calculate the extended data for storage in the 15th extended register R 0 of the second arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the extended data stored in the 0th extended register R 9 and the 9th extended register R 15 of the first arithmetic stage. Specifically, in some examples, the intermediate data w x ' in the additional register X of arithmetic stage 220-b can be obtained by the first sub-module 231 processing the extended data w 2 stored in the 2nd extended register R 2 of arithmetic stage 220-a and the extended data w 15 stored in the 15th extended register R 15 of arithmetic stage 220-a. The extended data w 15 in the 15th extended register R 15 ' of arithmetic stage 220-b can be obtained by the second sub-module 232 processing the intermediate data w x in the additional register X of arithmetic stage 220-a and the extended data w 0 stored in the 0th extended register R 0 of arithmetic stage 220-a and the extended data w 9 stored in the 9th extended register R 9 of arithmetic stage 220-a, such that wx ' = σ 0 (w 2 ) + σ 1 (w 15 ),w 15 ' = w x + w 0 + w 9 。

[0126] In some embodiments, the first sub-module 231 may be configured to calculate intermediate data for storage in the additional register X of the second arithmetic level based on the extended data stored in the 10th extended register R 10 and the 15th extended register R 15 of the first arithmetic level, and the second sub-module 232 may be configured to calculate the extended data for storage in the 15th extended register R 0 of the second arithmetic level based on the intermediate data stored in the additional register X of the first arithmetic level and the extended data stored in the 0th extended register R 1 and the 1st extended register R 15 of the first arithmetic level. Specifically, in some examples, the intermediate data w x ' in the additional register X of the arithmetic level 220-b may be obtained by the first sub-module 231 processing the extended data w 10 stored in the 10th extended register R 10 of the arithmetic level 220-a and the extended data w 15 stored in the 15th extended register R 15 of the arithmetic level 220-a, and the extended data w 15 in the 15th extended register R 15 of the arithmetic level 220-b may be obtained by the second sub-module 232 processing the intermediate data w x in the additional register X of the arithmetic level 220-a and the extended data w 0 stored in the 0th extended register R 0 of the arithmetic level 220-a and the extended data w 1 stored in the 1st extended register R 1 of the arithmetic level 220-a, such that w x ' = w 10 + σ 1 (w 15 ), w 15 ' = w x + w 0 + σ 0 (w 1 )。

[0127] Correspondingly, the present disclosure also provides a method for calculating extended data in a circuit for performing a hash algorithm. Figure 14FIG. 0 shows an exemplary flowchart of a method 400 for calculating extended data in a circuit for performing a hash algorithm according to an embodiment of the present disclosure. Such a circuit may include an input module configured to receive data and an arithmetic module configured to calculate a hash value based on the received data, wherein the arithmetic module may include a plurality of arithmetic levels arranged in a pipeline structure, each arithmetic level may include an extended register 0 to an extended register 15 and an additional register, each extended register may be configured to store extended data of the current arithmetic level, and the additional register may be configured to store intermediate data for calculating the extended data. In some embodiments, the intermediate data stored in the additional register of the foremost arithmetic level may be the same as the extended data stored in the extended register 0 of the foremost arithmetic level. For two adjacent arithmetic levels including a first arithmetic level and a second arithmetic level after the first arithmetic level among the plurality of arithmetic levels of the arithmetic module, the method 400 may include: at S401, calculating intermediate data for storing into the additional register of the second arithmetic level based on the extended data stored in the extended registers of the first arithmetic level; at S402, calculating extended data for storing into the extended register 15 of the second arithmetic level based on the intermediate data stored in the additional register of the first arithmetic level; and at S403, using the extended data stored in the extended register i of the first arithmetic level as the extended data for storing into the extended register (i - 1) of the second arithmetic level, where 1 ≤ i ≤ 15 and i is an integer. Note that S401 - S403 do not need to be executed in sequential order, but may be executed in any order, or may be executed at least partially in parallel.

[0128] In some embodiments, calculating the intermediate data for storing into the additional register of the second arithmetic level and calculating the extended data for storing into the extended register 15 of the second arithmetic level may be performed simultaneously.

[0129] In some embodiments, the extended data stored in the extended register 15 of the arithmetic level after the second arithmetic level may be determined based on the extended data stored in the extended register 1, the extended register 2, the extended register 10, and the extended register 15 of the first arithmetic level.

[0130] The method 400 may also calculate the extended data in various ways described above regarding the first sub - module 231 and the second sub - module 232, which will not be elaborated here. The method 400 can reduce the calculation delay caused by calculating the extended data in the circuit for performing the hash algorithm, thereby significantly improving the operation speed of the circuit and thus the computing chip including the circuit, and achieving a lower power - to - computing - power ratio.

[0131] The present disclosure may also provide a computing chip including the circuit as described in any of the above embodiments.

[0132] The terms "left", "right", "front", "back", "top", "bottom", "upper", "lower", "higher", "lower", etc. in the specification and claims, if present, are used for descriptive purposes and not necessarily to describe an invariant relative position. It should be understood that such terms are interchangeable under appropriate circumstances so that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein. For example, when the device in the drawings is inverted, a feature originally described as "above" other features can then be described as "below" the other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0133] In the specification and claims, when an element is said to be "above", "attached" to, "connected" to, "coupled" to, or "in contact" with another element, etc., the element can be directly above, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or there can be one or more intervening elements. In contrast, when an element is said to be "directly" above, "directly attached" to, "directly connected" to, "directly coupled" to, or "directly in contact" with another element, there will be no intervening elements. In the specification and claims, a feature being arranged "adjacent" to another feature can mean that the feature has an overlapping portion with the adjacent feature or a portion that is above or below the adjacent feature.

[0134] As used herein, the term "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein exemplarily is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory, whether expressed or implied, given in the technical field, background art, summary of the invention, or detailed description. As used herein, the term "substantially" means including any minute variations due to defects in design or manufacture, tolerances of devices or elements, environmental effects, and / or other factors. The term "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0135] Additionally, for reference purposes only, terms such as "first", "second", and the like may also be used herein and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words "first", "second", and other such numerical words referring to a structure or element do not imply an order or sequence. It should also be understood that when the term "comprising / including" is used herein, it states the presence of the indicated features, wholes, steps, operations, units, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or their combinations. In the present disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0136] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0137] Those skilled in the art should be aware that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. The aspects and elements of all the embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the drawings should be regarded as illustrative rather than restrictive.

[0138] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustration purposes only and not for limiting the scope of the present disclosure. The embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A circuit for performing a hash algorithm, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: a plurality of operation levels arranged in a pipeline structure, each of the plurality of operation levels including an extension register from extension register 0 to extension register 15, each extension register being configured to store extension data of the current operation level; and a plurality of extension data operation logic modules, each extension data operation logic module being disposed between two corresponding adjacent operation levels of the plurality of operation levels, the two adjacent operation levels including a first operation level and a second operation level after the first operation level, each extension data operation logic module comprising: a first sub-module configured to calculate extension data for storage into extension register 0 of the second operation level based on the extension data stored in extension register 1 of the first operation level; and a second sub-module configured to calculate extension data for storage into extension register 15 of the second operation level based on the extension data stored in extension register 0 of the first operation level, wherein the extension data for storage into extension register (i - 1) of the second operation level is the extension data stored in extension register i of the first operation level, where 2 ≤ i ≤ 15 and i is an integer.

2. The circuit according to claim 1, wherein the extension data stored in extension register 15 of the operation level after the second operation level is determined based on the extension data stored in extension register 1, extension register 2, extension register 10, and extension register 15 of the first operation level.

3. The circuit according to claim 1, wherein the first sub-module is configured to calculate extension data for storage into extension register 0 of the second operation level based on one or both of the extension data stored in extension register 2, extension register 10, and extension register 15 of the first operation level and the extension data stored in extension register 1 of the first operation level.

4. The circuit according to claim 1, wherein the second sub-module is configured to calculate extension data for storage into extension register 15 of the second operation level based on one or both of the extension data stored in extension register 1, extension register 9, and extension register 14 of the first operation level and the extension data stored in extension register 0 of the first operation level.

5. The circuit according to any one of claims 1 - 4, wherein the first sub-module is configured to calculate extension data for storage into extension register 0 of the second operation level based on the extension data stored in extension register 1 and extension register 2 of the first operation level; and the second sub-module is configured to calculate extension data for storage into extension register 15 of the second operation level based on the extension data stored in extension register 0, extension register 9, and extension register 14 of the first operation level.

6. The circuit according to any one of claims 1-4, wherein, the first sub-module is configured to calculate the extended data for storing into the 0th extended register of the second operation level based on the extended data stored in the 1st extended register and the 10th extended register of the first operation level; and the second sub-module is configured to calculate the extended data for storing into the 15th extended register of the second operation level based on the extended data stored in the 0th extended register, the 1st extended register and the 14th extended register of the first operation level.

7. The circuit according to any one of claims 1-4, wherein, the first sub-module is configured to calculate the extended data for storing into the 0th extended register of the second operation level based on the extended data stored in the 1st extended register, the 2nd extended register and the 10th extended register of the first operation level; and the second sub-module is configured to calculate the extended data for storing into the 15th extended register of the second operation level based on the extended data stored in the 0th extended register and the 14th extended register of the first operation level.

8. The circuit according to any one of claims 1-4, wherein, the first sub-module is configured to calculate the extended data for storing into the 0th extended register of the second operation level based on the extended data stored in the 1st extended register and the 15th extended register of the first operation level; and the second sub-module is configured to calculate the extended data for storing into the 15th extended register of the second operation level based on the extended data stored in the 0th extended register, the 1st extended register and the 9th extended register of the first operation level.

9. The circuit according to any one of claims 1-4, wherein, the first sub-module is configured to calculate the extended data for storing into the 0th extended register of the second operation level based on the extended data stored in the 1st extended register, the 2nd extended register and the 15th extended register of the first operation level; and the second sub-module is configured to calculate the extended data for storing into the 15th extended register of the second operation level based on the extended data stored in the 0th extended register and the 9th extended register of the first operation level.

10. The circuit according to any one of claims 1-4, wherein, the first sub-module is configured to calculate the extended data for storing into the 0th extended register of the second operation level based on the extended data stored in the 1st extended register, the 10th extended register and the 15th extended register of the first operation level; and the second sub-module is configured to calculate the extended data for storing into the 15th extended register of the second operation level based on the extended data stored in the 0th extended register and the 1st extended register of the first operation level.

11. A circuit for performing a hash algorithm, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: A plurality of operation levels arranged in a pipeline structure, each operation level of the plurality of operation levels includes an extension register 0 to an extension register 15 and an additional register, each extension register is configured to store extension data of the current operation level, and the additional register is configured to store intermediate data for calculating the extension data; and A plurality of extended data operation logic modules, each extended data operation logic module is disposed between two corresponding adjacent operation levels of the plurality of operation levels, the two adjacent operation levels include a first operation level and a second operation level after the first operation level, and each extended data operation logic module includes: A first sub-module configured to calculate intermediate data for storing into the additional register of the second operation level based on the extended data stored in the extension register of the first operation level; and A second sub-module configured to calculate extended data for storing into the extension register 15 of the second operation level based on the intermediate data stored in the additional register of the first operation level, wherein, the extended data for storing into the extension register (i - 1) of the second operation level is the extended data stored in the extension register i of the first operation level, where 1 ≤ i ≤ 15 and i is an integer.

12. The circuit according to claim 11, wherein, The extended data stored in the extension register 15 of the operation level subsequent to the second operation level is determined based on the extended data stored in the extension register 1, extension register 2, extension register 10, and extension register 15 of the first operation level.

13. The circuit according to claim 11, wherein, The first sub-module is configured to calculate intermediate data for storing into the additional register of the second operation level based on two or three of the extended data stored in the extension register 1, extension register 2, extension register 10, and extension register 15 of the first operation level.

14. The circuit according to claim 11, wherein, The second sub-module is configured to calculate extended data for storing into the extension register 15 of the second operation level based on one or two of the extended data stored in the extension register 0, extension register 1, extension register 9, and extension register 14 of the first operation level and the intermediate data stored in the additional register of the first operation level.

15. The circuit according to any one of claims 11 - 14, wherein, The first sub-module is configured to calculate intermediate data for storing into the additional register of the second operation level based on the extended data stored in the extension register 1 and extension register 2 of the first operation level; and The second sub-module is configured to calculate extended data for storing into the extension register 15 of the second operation level based on the intermediate data stored in the additional register of the first operation level and the extended data stored in the extension register 9 and extension register 14 of the first operation level.

16. The circuit according to any one of claims 11 - 14, wherein, The first sub-module is configured to calculate intermediate data for storage in the additional register of the second arithmetic stage based on the extended data stored in the first extended register and the tenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the first extended register and the fourteenth extended register of the first arithmetic stage.

17. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in the additional register of the second arithmetic stage based on the extended data stored in the first extended register, the second extended register, and the tenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the fourteenth extended register of the first arithmetic stage.

18. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in the additional register of the second arithmetic stage based on the extended data stored in the first extended register and the fifteenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the first extended register and the ninth extended register of the first arithmetic stage.

19. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in the additional register of the second arithmetic stage based on the extended data stored in the first extended register, the second extended register, and the fifteenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the ninth extended register of the first arithmetic stage.

20. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in the additional register of the second arithmetic stage based on the extended data stored in the first extended register, the tenth extended register, and the fifteenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the first extended register of the first arithmetic stage.

21. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in an additional register of the second arithmetic stage based on the extended data stored in the second extended register and the tenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the zeroeth extended register and the fourteenth extended register of the first arithmetic stage.

22. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in an additional register of the second arithmetic stage based on the extended data stored in the second extended register and the fifteenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the zeroeth extended register and the ninth extended register of the first arithmetic stage.

23. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in an additional register of the second arithmetic stage based on the extended data stored in the second extended register, the tenth extended register, and the fifteenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the zeroeth extended register of the first arithmetic stage.

24. The circuit according to any one of claims 11-14, wherein, The first sub-module is configured to calculate intermediate data for storage in an additional register of the second arithmetic stage based on the extended data stored in the tenth extended register and the fifteenth extended register of the first arithmetic stage; and The second sub-module is configured to calculate extended data for storage in the fifteenth extended register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage and the extended data stored in the zeroeth extended register and the first extended register of the first arithmetic stage.

25. A computing chip, comprising the circuit according to any one of claims 1-24.

26. A method for calculating extended data in a circuit for performing a hash algorithm, the circuit comprising an input module configured to receive data and an arithmetic module configured to calculate a hash value based on the received data, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure, each arithmetic stage of the plurality of arithmetic stages comprising a zeroeth extended register to a fifteenth extended register, each extended register being configured to store extended data of the current arithmetic stage, the method comprises: For two adjacent operation levels among the multiple operation levels, including a first operation level and a second operation level after the first operation level: Calculate the extended data to be stored in the 0th extended register of the second operation level based on the extended data stored in the 1st extended register of the first operation level; Calculate the extended data to be stored in the 15th extended register of the second operation level based on the extended data stored in the 0th extended register of the first operation level; And Use the extended data stored in the ith extended register of the first operation level as the extended data to be stored in the (i - 1)th extended register of the second operation level, where 2 ≤ i ≤ 15 and i is an integer.

27. A method for calculating extended data in a circuit for performing a hash algorithm, the circuit including an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module including a plurality of operation levels arranged in a pipeline structure, each operation level among the plurality of operation levels including 0th to 15th extended registers and additional registers, each extended register being configured to store extended data of the current operation level, the additional register being configured to store intermediate data for calculating extended data, the method comprises: For two adjacent operation levels among the multiple operation levels, including a first operation level and a second operation level after the first operation level: Calculate the intermediate data to be stored in the additional register of the second operation level based on the extended data stored in the extended registers of the first operation level; Calculate the extended data to be stored in the 15th extended register of the second operation level based on the intermediate data stored in the additional register of the first operation level; And Use the extended data stored in the ith extended register of the first operation level as the extended data to be stored in the (i - 1)th extended register of the second operation level, where 1 ≤ i ≤ 15 and i is an integer.

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