A wafer-level fan-out package structure and a manufacturing method thereof

Abstract

The present invention relates to the technical field of integrated circuit packaging, and specifically discloses a wafer-level fan-out packaging structure, which includes: a wafer, a molding compound layer provided on the side surface and a part of the back surface surrounding the wafer, a groove is formed between the molding compound layer on the bottom surface of the wafer and the back surface of the wafer, a passivation layer and a metal heat dissipation layer are sequentially provided on the surface of the groove, a wafer functional area is provided in the wafer, an insulating layer and a metal wiring layer are provided on the front surface of the wafer, both the insulating layer and the metal wiring layer are in contact with the wafer functional area, and metal bumps are provided on the metal wiring layer. The present invention also discloses a manufacturing method of the wafer-level fan-out packaging structure. The wafer-level fan-out packaging structure provided by the present invention solves the problem of heat accumulation in high-density integrated modules and improves the heat dissipation performance of the packaging structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular, to a wafer-level fan-out packaging structure and a manufacturing method thereof. Background Art

[0002] With the miniaturization of semiconductors and the upsurge of 5G applications, fan-out packaging has received extensive attention. Currently, the heat of 5G is unprecedentedly high. 5G high-frequency devices have relatively high requirements for transmission loss. Fan-out packaging has broad application prospects because it can reduce the interconnection distance of devices. In addition, looking at the development of fan-out packaging in recent years, it is also widely used in fields such as power management integrated circuits (PMICs), radio frequency (RF) transceivers, connection modules, audio / codec modules, radar modules, and sensors.

[0003] Among them, the fan-out packaging process is mainly divided into two categories: chip first and chip last, with Infineon's eWLB and TSMC's InFO being the most representative respectively. The chip first fan-out solution is already very mature in the market. Since 2009, eWLB has been the most well-known fan-out packaging technology in the core market and can embed multiple dies and numerous passive devices, so it has been continuously adopted. The chip first packaging is further divided into two process routes: face up and face down. In the face down process route, in addition to the long-existing warping and chip offset problems, the height difference, i.e., the step, between the chip and the resin matrix after wafer reconstruction is the main cause of re-wiring open circuit and short circuit. At the same time, with the advent of the post-Moore era, whether it is the number of integrated chips or the number of I / Os will be increasing, the re-wiring size will be getting smaller, the density will gradually increase, and the heat dissipation of the chip has become a major difficulty. Summary of the Invention

[0004] The present invention provides a wafer-level fan-out packaging structure and a manufacturing method thereof, which solve the heat dissipation problem existing in the related technology.

[0005] As a first aspect of the present invention, a wafer-level fan-out packaging structure is provided, which includes: a wafer, a molding compound layer provided on the side surface and a part of the back surface surrounding the wafer, a molding compound layer located on the bottom surface of the wafer forms a groove with the back surface of the wafer, a passivation layer and a metal heat dissipation layer are sequentially provided on the surface of the groove, a wafer functional area is provided in the wafer, an insulating layer and a metal wiring layer are provided on the front surface of the wafer, both the insulating layer and the metal wiring layer are in contact with the wafer functional area, and metal bumps are provided on the metal wiring layer.

[0006] Further, two metal bumps are symmetrically provided on the metal wiring layer.

[0007] As a first aspect of the present invention, there is provided a method for manufacturing a wafer-level fan-out package structure for manufacturing the wafer-level fan-out package structure described above. Wherein, the manufacturing method includes:

[0008] Providing a wafer with a wafer functional area;

[0009] Forming a positive photoresist sacrificial layer on the upper surface of the wafer, and forming a back photoresist sacrificial layer on the lower surface of the wafer;

[0010] Dicing the wafer into individual chips;

[0011] Mounting an individual chip onto a carrier, wherein the positive photoresist sacrificial layer of the individual chip contacts the carrier;

[0012] Encapsulating the individual chip to form an encapsulant layer surrounding the back photoresist sacrificial layer and the side surface of the individual chip;

[0013] Separating the individual chip with the encapsulant layer from the carrier to obtain a reconstructed wafer;

[0014] Removing both the positive photoresist sacrificial layer and the back photoresist sacrificial layer of the reconstructed wafer to form a groove on the back of the reconstructed wafer;

[0015] Successively forming a passivation layer and a metal heat dissipation layer on the surface of the groove;

[0016] Successively forming an insulating layer and a metal wiring layer on the front of the reconstructed wafer, and both the insulating layer and the metal wiring layer contact the wafer functional area;

[0017] Forming metal bumps on the metal wiring layer.

[0018] Further, forming a positive photoresist sacrificial layer on the upper surface of the wafer, and forming a back photoresist sacrificial layer on the lower surface of the wafer, includes:

[0019] Respectively forming a positive photoresist sacrificial layer on the upper surface of the wafer and a back photoresist sacrificial layer on the lower surface of the wafer by spin coating, spraying or printing.

[0020] Further, mounting an individual chip onto a carrier, includes:

[0021] Mounting an individual chip onto a carrier with a temporary bonding adhesive, wherein the positive photoresist sacrificial layer of the individual chip contacts the temporary bonding adhesive.

[0022] Further, encapsulate the single chip, forming an encapsulant layer that surrounds the photoresist sacrificial layer on the back of the single chip and the side surfaces of the single chip, including:

[0023] Embed and cure the single chip with an encapsulant matrix to form an encapsulant layer that surrounds the photoresist sacrificial layer on the back of the single chip and the side surfaces of the single chip.

[0024] Further, separate the single chip with the encapsulant layer from the carrier substrate to obtain a reconstructed wafer, including:

[0025] Separate the single chip with the encapsulant layer from the carrier substrate with the temporary bonding adhesive through a debonding technique to obtain a reconstructed wafer.

[0026] Further, remove both the front photoresist sacrificial layer and the back photoresist sacrificial layer of the reconstructed wafer to form a groove on the back of the reconstructed wafer, including:

[0027] Remove the front photoresist sacrificial layer of the reconstructed wafer so that the front surface of the single chip is flush with the surface of the encapsulant layer;

[0028] Back grind the back of the reconstructed wafer until the back photoresist sacrificial layer is exposed, and remove the back photoresist sacrificial layer to form a groove on the back of the reconstructed wafer.

[0029] Further, form metal bumps on the metal wiring layer, including:

[0030] Form symmetric metal bumps on the metal wiring layer according to the redistribution technology.

[0031] Further, the carrier substrate includes a metal carrier substrate or a glass carrier substrate.

[0032] The wafer-level fan-out package structure provided by the present invention can effectively improve the overall heat dissipation performance of the package structure by forming a groove on the back of the wafer and forming a metal heat dissipation layer on the passivation layer in the groove. Additionally, metal bumps are formed on the front surface of the wafer, i.e., the metal wiring layer, to effectively improve the package structure. Therefore, the wafer-level fan-out package structure provided by the embodiments of the present invention solves the problem of heat accumulation in high-density integrated modules and improves the heat dissipation performance of the package structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the following detailed description to explain the present invention, but do not limit the present invention. In the drawings:

[0034] Figure 1Schematic diagram of the wafer-level fan-out package structure provided by the present invention.

[0035] Figure 2 Flowchart of the manufacturing method of the wafer-level fan-out package structure provided by the present invention.

[0036] Figure 3 Schematic diagram of a wafer with a sacrificial layer provided by the present invention.

[0037] Figure 4 Schematic diagram of a single chip after scribing the wafer provided by the present invention.

[0038] Figure 5 Schematic diagram of mounting a single chip provided by the present invention.

[0039] Figure 6 Schematic diagram of encapsulation provided by the present invention.

[0040] Figure 7 Schematic diagram of debonding provided by the present invention.

[0041] Figure 8 Schematic diagram of removing the photoresist sacrificial layers on the front and back sides provided by the present invention.

[0042] Figure 9 Schematic diagram of the passivation layer and the metal heat dissipation layer provided by the present invention.

[0043] Figure 10 Schematic diagram of forming the insulating layer and the metal wiring layer provided by the present invention. Detailed implementation manners

[0044] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0045] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the description, claims and the above drawings of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] In an embodiment of the present invention, a wafer-level fan-out package structure is provided. Figure 1 It is a schematic structural diagram of the wafer-level fan-out package structure provided according to an embodiment of the present invention, as Figure 1 shown, including: a wafer 102, a molding compound layer 108 provided on the side surface and part of the back surface surrounding the wafer 102, a groove 110 formed between the molding compound layer 108 on the bottom surface of the wafer 102 and the back surface of the wafer 102, a passivation layer 111 and a metal heat dissipation layer 112 are sequentially provided on the surface of the groove 110, a wafer functional area 101 is provided inside the wafer 102, an insulating layer 113 and a metal wiring layer 114 are provided on the front surface of the wafer 102, both the insulating layer 113 and the metal wiring layer 114 are in contact with the wafer functional area 101, and metal bumps 115 are provided on the metal wiring layer 114.

[0048] For the wafer-level fan-out package structure provided by the embodiment of the present invention, by forming a groove on the back surface of the wafer and forming a metal heat dissipation layer on the passivation layer in the groove, the overall heat dissipation performance of the package structure can be effectively improved. In addition, metal bumps are formed on the front surface of the wafer, that is, on the metal wiring layer, effectively improving the package structure. Therefore, the wafer-level fan-out package structure provided by the embodiment of the present invention solves the problem of heat accumulation in high-density integrated modules and improves the heat dissipation performance of the package structure.

[0049] It should be noted that, taking the Figure 1 shown direction as an example, the upper surface of the wafer is the front surface of the wafer, and the lower surface of the wafer is the back surface of the wafer.

[0050] Specifically, as Figure 1 shown, two metal bumps are symmetrically provided on the metal wiring layer 114.

[0051] In the embodiment of the present invention, the specific setting structure of the metal wiring layer 114 and the specific setting structure of the insulating layer 113 are well known to those skilled in the art and will not be elaborated here.

[0052] As another embodiment of the present invention, a method for manufacturing a wafer-level fan-out package structure is provided for manufacturing the wafer-level fan-out package structure described above. Among them, as Figure 2 shown, the manufacturing method includes:

[0053] S110. Provide a wafer with a wafer functional area;

[0054] S120. Form a positive photoresist sacrificial layer on the upper surface of the wafer and a back photoresist sacrificial layer on the lower surface of the wafer;

[0055] In the embodiment of the present invention, specifically, a positive photoresist sacrificial layer can be formed on the upper surface of the wafer and a back photoresist sacrificial layer can be formed on the lower surface of the wafer by means of spin coating, spraying or printing respectively.

[0056] As Figure 3 shown, provide a wafer 102 with a wafer functional area 101, and form a positive photoresist sacrificial layer 103 on the front surface of the wafer 102 and a back photoresist sacrificial layer 104 on the back surface of the wafer 102 by means of spin coating, spraying or printing.

[0057] Taking Figure 3 the direction shown as an example, the upper surface of the wafer 102 is the front surface of the wafer, and the lower surface of the wafer 102 is the back surface of the wafer.

[0058] S130. Dice the wafer into individual chips;

[0059] In the embodiment of the present invention, as Figure 4 shown, use dicing technology to dice the incoming wafer into individual chips 105.

[0060] S140. Mount the individual chips onto a carrier, wherein the positive photoresist sacrificial layer of the individual chips contacts the carrier;

[0061] Specifically, mount the individual chips 105 onto a carrier with a temporary bonding adhesive, wherein the positive photoresist sacrificial layer of the individual chips contacts the temporary bonding adhesive.

[0062] In the embodiment of the present invention, as Figure 5 shown, mount the diced individual chips 105 onto a carrier 107 with a temporary bonding adhesive 106 through high-precision chip mounting technology.

[0063] It should be understood that during specific operation, Figure 4 invert the individual chips 105 shown, so that the positive photoresist sacrificial layer 103 of the individual chips 105 contacts the temporary bonding adhesive 106.

[0064] In an embodiment of the present invention, the carrier plate 107 may specifically be a metal carrier plate or a glass carrier plate.

[0065] S150. Encapsulate the single chip 105 to form an encapsulant layer 108 that surrounds the back photoresist sacrificial layer 104 of the single chip 105 and the side surface of the single chip 105.

[0066] Specifically, embed and cure the single chip 105 with an encapsulant matrix to form an encapsulant layer 108 that surrounds the back photoresist sacrificial layer 104 of the single chip 105 and the side surface of the single chip.

[0067] In an embodiment of the present invention, the encapsulant of the encapsulant layer 108 may specifically be a composite material of resin and inorganic substances (SiO2, Al2O3, SiC, BN).

[0068] In an embodiment of the present invention, as Figure 6 shown, encapsulate the mounted single chip, that is, embed and cure the chip with an encapsulant matrix.

[0069] S160. Separate the single chip with the encapsulant layer 108 from the carrier plate 107 to obtain a reconstructed wafer.

[0070] In an embodiment of the present invention, separate the single chip with the encapsulant layer 108 from the carrier plate 107 with the temporary bonding adhesive 106 through a debonding technique to obtain a reconstructed wafer.

[0071] In an embodiment of the present invention, as Figure 7 shown, separate the carrier plate and the temporary bonding adhesive through a debonding technique to obtain a reconstructed wafer.

[0072] S170. Remove both the front photoresist sacrificial layer and the back photoresist sacrificial layer of the reconstructed wafer to form a groove on the back of the reconstructed wafer.

[0073] Specifically, remove the front photoresist sacrificial layer 103 of the reconstructed wafer so that the front surface of the single chip is on the same plane as the surface of the encapsulant layer 108.

[0074] Back grind the back of the reconstructed wafer until the back photoresist sacrificial layer 104 is exposed, and remove the back photoresist sacrificial layer 104 to form a groove 110 on the back of the reconstructed wafer.

[0075] In an embodiment of the present invention, as Figure 7 and Figure 8 shown, perform a degluing process on the reconstructed wafer with a photoresist sacrificial layer to eliminate the step 109, so that the front surface of the single chip is on the same plane as the surface of the encapsulant layer 108.

[0076] It should be understood that after removing the positive photoresist sacrificial layer 103 shown, the step 109 can be eliminated. Figure 7 As shown, the encapsulant layer 108 on the back of the reconstructed wafer is backgrinded until the back photoresist sacrificial layer is exposed, and then the photoresist is removed. An inorganic passivation layer 111 and a metal heat dissipation layer 112 are prepared on the exposed back of the chip.

[0077] As Figure 9 shown, a passivation layer and a metal heat dissipation layer are sequentially formed on the surface of the groove.

[0078] S180. A passivation layer and a metal heat dissipation layer are sequentially formed on the surface of the groove;

[0079] S190. An insulating layer and a metal wiring layer are sequentially formed on the front of the reconstructed wafer, and both the insulating layer and the metal wiring layer are in contact with the wafer functional area;

[0080] As Figure 10 shown, an insulating layer 113 and a metal wiring layer 114 are sequentially formed on the front of the reconstructed wafer.

[0081] In the embodiment of the present invention, the material of the insulating layer 113 may specifically be polyimide or a composite material of resin and inorganic substances (SiO2, Al2O3, SiC, BN); the material of the metal wiring layer 114 may specifically be one or a combination of several of Al, Ti, Ti / W, Ni, Cu, Sn, Ag, and Au.

[0082] S200. Metal bumps 115 are formed on the metal wiring layer.

[0083] Symmetric metal bumps 115 are formed on the metal wiring layer according to the redistribution technology.

[0084] In the embodiment of the present invention, the material of the metal bumps 115 may specifically be one or a combination of several of Ti, V, Ni, TiW, Cu, SnAg, SnAgCu, and SnPb.

[0085] In the embodiment of the present invention, the redistribution technology is used to realize n-layer redistribution (mainly including the above-mentioned insulating layer and metal wiring layer) and bumps. Finally, the packaged wafer is diced into single packaged chips to complete the final packaging, and the formed final packaging structure is as Figure 1 shown.

[0086] In summary, for the manufacturing method of the wafer-level fan-out package structure provided by the embodiments of the present invention, by covering a layer of photoresist sacrificial layer on the front and back sides of the wafer, after wafer reconstruction, the front sacrificial layer is removed to eliminate the steps, avoiding the open-short circuit problems caused by the damage or bubbles of the photoresist during the re-wiring process; the back sacrificial layer is removed and an inorganic passivation layer and a metal heat dissipation layer are fabricated, greatly improving the overall heat dissipation performance of the package body, solving the heat accumulation problem of high-density integrated modules, and the preparation method is simple and can be used for mass production.

[0087] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention, and the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A manufacturing method of a wafer-level fan-out package structure, including a wafer-level fan-out package structure, characterized in that, The wafer-level fan-out package structure includes: a wafer, a molding compound layer disposed on the side surface and a part of the back surface of the wafer, a groove formed between the molding compound layer on the bottom surface of the wafer and the back surface of the wafer, a passivation layer and a metal heat dissipation layer are sequentially disposed on the surface of the groove, a wafer functional area is disposed in the wafer, an insulating layer and a metal wiring layer are disposed on the front surface of the wafer, both the insulating layer and the metal wiring layer are in contact with the wafer functional area, and metal bumps are disposed on the metal wiring layer; The manufacturing steps of the manufacturing method of the wafer-level fan-out package structure are as follows: Provide a wafer with a wafer functional area; Form a front photoresist sacrificial layer on the upper surface of the wafer and a back photoresist sacrificial layer on the lower surface of the wafer; Cut the wafer into single chips; Mount the single chip on a carrier, wherein the front photoresist sacrificial layer of the single chip is in contact with the carrier; Encapsulate the single chip to form a molding compound layer surrounding the back photoresist sacrificial layer and the side surface of the single chip; Separate the single chip with the molding compound layer from the carrier to obtain a reconstituted wafer; Remove both the front photoresist sacrificial layer and the back photoresist sacrificial layer of the reconstituted wafer to form a groove on the back surface of the reconstituted wafer; Form a passivation layer and a metal heat dissipation layer on the surface of the groove in sequence; Form an insulating layer and a metal wiring layer on the front surface of the reconstituted wafer in sequence, and both the insulating layer and the metal wiring layer are in contact with the wafer functional area; Form metal bumps on the metal wiring layer.

2. The manufacturing method according to claim 1, wherein Two metal bumps are symmetrically disposed on the metal wiring layer.

3. The manufacturing method according to claim 1, characterized in that, Forming a front photoresist sacrificial layer on the upper surface of the wafer and a back photoresist sacrificial layer on the lower surface of the wafer includes: Form a front photoresist sacrificial layer on the upper surface of the wafer and a back photoresist sacrificial layer on the lower surface of the wafer respectively by spin coating, spraying or printing.

4. The manufacturing method according to claim 1, characterized in that, Mounting the single chip on a carrier includes: Mount the single chip on a carrier with a temporary bonding adhesive, wherein the front photoresist sacrificial layer of the single chip is in contact with the temporary bonding adhesive.

5. The manufacturing method according to claim 1, characterized in that, Encapsulating the single chip to form a molding compound layer surrounding the back photoresist sacrificial layer and the side surface of the single chip includes: Embed and cure the single chip with a molding compound matrix to form a molding compound layer surrounding the back photoresist sacrificial layer and the side surface of the single chip.

6. The manufacturing method according to claim 4, characterized in that, Separating the single chip with the molding compound layer from the carrier to obtain a reconstituted wafer includes: Separate the single chip with the molding compound layer from the carrier with the temporary bonding adhesive by a debonding technique to obtain a reconstituted wafer.

7. The manufacturing method according to claim 1, wherein Removing both the front photoresist sacrificial layer and the back photoresist sacrificial layer of the reconstituted wafer to form a groove on the back surface of the reconstituted wafer includes: Remove the front photoresist sacrificial layer of the reconstituted wafer so that the front surface of the single chip is flush with the surface of the molding compound layer; Back-grind the back surface of the reconstructed wafer until the backside photoresist sacrificial layer is exposed, and remove the backside photoresist sacrificial layer to form a groove on the back surface of the reconstructed wafer.

8. The manufacturing method according to claim 1, characterized in that, Form metal bumps on the metal wiring layer, including: Form symmetric metal bumps on the metal wiring layer according to the redistribution technology.

9. The manufacturing method according to claim 1, characterized in that, The carrier plate includes a metal carrier plate or a glass carrier plate.

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