Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor device with a P-N junction insulation structure and a method of manufacturing the semiconductor device. The semiconductor device has a substrate, a first well layer in the substrate and having a first electrical type, a lower conductive layer in the first well layer and having a second electrical type opposite to the first electrical type, a first isolation layer on the lower conductive layer, an insulation mask layer on the substrate and surrounding the first isolation layer, a first conductive line on the first isolation layer, and a bias layer in the first well layer and spaced apart from the lower conductive layer. The lower conductive layer, the first isolation layer, and the first conductive line together configure a programmable cell.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 126,609, filed December 18, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of fabricating the same. In particular, the present disclosure relates to a semiconductor device having a P-N junction isolation structure and a method of fabricating the same. BACKGROUND

[0003] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, different problems are increased during the process of size reduction, and such problems continue to increase in number and complexity. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of the background art is provided merely for purposes of background information and does not constitute an admission, by express or implied, that any of the above described art is prior art to the present disclosure, that any of the above described art is relevant to the combining prior art or that any of the above described art forms a part of the common general knowledge in the art. Any discussion of the references states what their authors assert, and the applicant reserves the right to challenge the accuracy and pertinency of any of the above referenced art to the present disclosure directly or through appropriate motion or request to the patent office. SUMMARY

[0005] One embodiment of the present disclosure provides a semiconductor device having a substrate; a first well layer in the substrate and having a first electrical type; a lower conductive layer in the first well layer and having a second electrical type opposite to the first electrical type; a first isolation layer on the lower conductive layer; an insulating mask layer on the substrate and surrounding the first isolation layer; a first conductive line on the first isolation layer; and a bias layer in the first well layer and spaced apart from the lower conductive layer. The lower conductive layer, the first isolation layer, and the first conductive line together configure a programmable cell.

[0006] In some embodiments, the semiconductor device further includes a second conductive line on the lower conductive layer and electrically coupled to the lower conductive layer.

[0007] In some embodiments, the semiconductor device further includes a first conductive layer on the bias layer and electrically coupled to the bias layer.

[0008] In some embodiments, the bias layer has the same electrical type as the first well layer, and a doping concentration of the bias layer is greater than a doping concentration of the first well layer.

[0009] In some embodiments, in a cross-sectional view, the first conductive line extends along a first direction, and the second conductive line extends along a second direction, the second direction being perpendicular to the first direction.

[0010] In some embodiments, a thickness of the first isolation layer is between about 30 nm and about 70 nm.

[0011] In some embodiments, the semiconductor element further comprises a first auxiliary layer on the biasing layer; wherein the first auxiliary layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0012] In some embodiments, a thickness of the first auxiliary layer is between about 2 nm and about 20 nm.

[0013] In some embodiments, the semiconductor element further comprises a plurality of first gap sub-layers on sidewalls of the first conductive line; wherein the first gap sub-layers comprise a dielectric material different from the first isolation layer.

[0014] In some embodiments, the semiconductor element further comprises a plurality of second gap sub-layers on sidewalls of the second conductive line; wherein the second gap sub-layers comprise silicon nitride, silicon oxynitride, or silicon nitride oxide.

[0015] In some embodiments, the semiconductor element further comprises a tip between the first isolation layer and the lower conductive layer; wherein the tip comprises silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, or indium phosphide.

[0016] In some embodiments, the first isolation layer comprises a cap layer on the tip, and a plurality of flat portions connected to two ends of the cap layer and on the lower conductive layer.

[0017] In some embodiments, the semiconductor element further comprises a deep well layer around the first well layer and having the second electrical type.

[0018] One embodiment of the present disclosure provides a semiconductor element having a substrate including a first well region; a first well layer in the first well region and having a first electrical type; a plurality of lower conductive layers in the first well layer and spaced apart from each other, wherein the lower conductive layers have a second electrical type opposite to the first electrical type; a plurality of first isolation layers on the lower conductive layers; an insulating mask layer on the first well region and surrounding the first isolation layers; a plurality of first conductive lines on the first isolation layers and parallel to each other; and a bias layer in the first well layer and spaced apart from the lower conductive layers. The lower conductive layers, the first isolation layers, and the first conductive lines together configure a plurality of programmable cells.

[0019] In some embodiments, the first isolation layers have the same thickness.

[0020] In some embodiments, the first isolation layers have different thicknesses.

[0021] In some embodiments, the semiconductor element further includes a plurality of second conductive lines on the first conductive lines and parallel to each other. The second conductive lines are electrically coupled to the lower conductive layers.

[0022] Another embodiment of the present disclosure provides a method of manufacturing a semiconductor element, including providing a substrate; forming a first well layer in the substrate and having a first electrical type; forming an insulating mask layer on the first well layer; forming a plurality of mask openings along the insulating mask layer to expose portions of the first well layer; forming a plurality of lower conductive layers in the portions of the first well layer, wherein the lower conductive layers have a second electrical type opposite to the first electrical type; forming a bias layer in the first well layer and spaced apart from the lower conductive layers; forming a plurality of first isolation layers on the lower conductive layers; and forming a plurality of first conductive lines on the first isolation layers and parallel to each other. The lower conductive layers, the first isolation layers, and the first conductive lines together configure a plurality of programmable cells.

[0023] In some embodiments, the method of manufacturing further includes a step of forming a plurality of second conductive lines on the first conductive lines to electrically couple to the lower conductive layers.

[0024] In some embodiments, the method of manufacturing further includes a step of forming a first conductive layer on the bias layer to electrically couple to the bias layer.

[0025] Because of the design of the semiconductor device disclosed herein, the lower conductive layer is electrically insulated in the presence of a bias voltage applied to the first well layer. This saves a significant amount of substrate area for more functional elements, such as programmable cells. Furthermore, it improves the uniformity of the first isolation layer. This, in turn, improves the reliability of programming the semiconductor device.

[0026] The technical features and advantages of this disclosure have been broadly summarized above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0030] Figure 3 An embodiment of this disclosure is illustrated along the edge Figure 2 A cross-sectional view of section line A-A'.

[0031] Figure 4 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 5 An embodiment of this disclosure is illustrated along the edge Figure 4 A cross-sectional view of section line A-A'.

[0033] Figure 6 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0034] Figure 7 An embodiment of this disclosure is illustrated along the edge Figure 6 A cross-sectional view of section line A-A'.

[0035] Figure 8A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0036] Figure 9 A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ is shown. Figure 8

[0037] Figure 10 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0038] Figure 11 A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ is shown. Figure 10

[0039] Figure 12 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0040] Figure 13 A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ is shown. Figure 12

[0041] A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 14

[0042] A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ and section line B-B’ is shown. Figure 15 Figure 16 Figure 14 A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ and section line B-B’ is shown.

[0043] Figure 17 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 18 Figure 14 A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ and section line B-B’ is shown.

[0044] Figure 19 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0045] Figure 20 Figure 19 A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ is shown.

[0046] Figure 21 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0047] Figure 22 A cross-sectional view schematic diagram of the intermediate semiconductor element according to an embodiment of the present disclosure along section line A-A’ and section line B-B’ is shown. Figure 23 Figure 21

[0048] Figure 24 ​​​​​​​​A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0049] Figure 25 An embodiment of this disclosure is illustrated along the edge Figure 24 A cross-sectional view of section line A-A'.

[0050] Figure 26 A top view schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure is shown.

[0051] Figure 27 An embodiment of this disclosure is illustrated along the edge Figure 26 A cross-sectional view of section line A-A'.

[0052] Figure 28 An intermediate semiconductor element illustrating another embodiment of this disclosure is along Figure 8 A cross-sectional view of section line A-A'.

[0053] Figure 29 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0054] Figure 30 Example of another embodiment of this disclosure Figure 29 A cross-sectional view of section line A-A'.

[0055] Figure 31 A top view schematic diagram illustrating another embodiment of the present disclosure of a semiconductor device.

[0056] Figure 32 Example of another embodiment of this disclosure Figure 31 A cross-sectional view of section line A-A'.

[0057] Figure 33 A semiconductor element illustrating another embodiment of this disclosure along Figure 31 A cross-sectional view of section line A-A'.

[0058] Figure 34 A top view schematic diagram illustrating another embodiment of the present disclosure of a semiconductor device.

[0059] Figure 35 Example of another embodiment of this disclosure Figure 34 A cross-sectional view of section line A-A'.

[0060] Figure 36 to Figure 38 Some semiconductor elements illustrating another embodiment of this disclosure are along Figure 26 A cross-sectional view of section line A-A'.

[0061] The reference numerals in the attached figures are explained as follows:

[0062] 1A: Semiconductor components

[0063] 1B: semiconductor element

[0064] 1C: semiconductor element

[0065] 1D: semiconductor element

[0066] 1E: semiconductor element

[0067] 1F: semiconductor element

[0068] 1G: semiconductor element

[0069] 10: method of making

[0070] 101: base

[0071] 103: first well layer

[0072] 105: insulating mask layer

[0073] 105O: mask opening

[0074] 107: lower conductive layer

[0075] 109: bias layer

[0076] 111: first isolation layer

[0077] 111C: cap portion

[0078] 111F: flat portion

[0079] 113: first conductive layer

[0080] 115: second isolation layer

[0081] 117: tip portion

[0082] 119: first auxiliary layer

[0083] 121: deep well layer

[0084] 201: second conductive via

[0085] 203: bias layer via

[0086] 205: first conductive via

[0087] 301: first well region

[0088] 303: active region

[0089] 305: programmable region

[0090] 401: interlayer dielectric

[0091] 403: interlayer dielectric

[0092] 405: interlayer dielectric

[0093] 407: interlayer dielectric

[0094] 501: implantation mask layer

[0095] FL1: first conductive line

[0096] FL2: first conductive line

[0097] FL3: first conductive line

[0098] FL4: first conductive line

[0099] FLS: first gap sub

[0100] P01: programmable unit

[0101] P02: programmable unit

[0102] P03: programmable unit

[0103] P04: programmable unit

[0104] P05: programmable unit

[0105] P06: programmable unit

[0106] P07: programmable unit

[0107] P08: programmable unit

[0108] P09: programmable unit

[0109] P10: programmable unit

[0110] P11: programmable unit

[0111] P12: programmable unit

[0112] P13: programmable unit

[0113] P14: programmable unit

[0114] P15: programmable unit

[0115] P16: programmable unit

[0116] S11: step

[0117] S13: step

[0118] S15: step

[0119] S17: step

[0120] S19: step

[0121] S21: step

[0122] S23: step

[0123] SL1: second conductive line

[0124] SL2: second conductive line

[0125] SL3: second conductive line

[0126] SL4: second conductive line

[0127] SLS: second gap sub

[0128] STI: insulating layer

[0129] x: axis

[0130] y: axis

[0131] Z: direction DETAILED DESCRIPTION

[0132] The following description describes specific examples of components and configurations to simplify the present disclosure. These specific examples are merely intended for the purpose of illustration and are not intended to limit the scope of the present disclosure. For example, in the description, a first component forming a second component on top can include an embodiment where the first and second components are formed in direct contact with each other, and can also include an embodiment where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. In addition, embodiments of the present disclosure can repeatedly refer to reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless specifically described in the context, it does not inherently represent a specific relationship between various embodiments and / or configurations discussed.

[0133] In addition, for ease of explanation, spatial relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein to describe a relationship of one element or feature to another (other) element or feature as illustrated in the drawings. The spatial relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device can have other orientations (rotated at 90 degrees or in other orientations) and the spatial relative terms used herein can be interpreted accordingly.

[0134] It should be understood that when a component is referred to as being "on", "connected to", or "coupled to" another component, it can be directly on, connected, or coupled to the other component, or intervening components can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element, there are no intervening components present. It will be appreciated that, unless otherwise indicated herein, like numbers in different figures represent a similar or identical element, and, as such, no individualized description of a figure will be rendered when it can be completely or at least partially understood from a description of another figure.

[0135] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and sections, these elements, components, regions, layers and sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0136] Unless otherwise indicated herein, when terms such as "same", "equal", "planar", or "coplanar" are used in this document, they do not necessarily mean an exact, complete identity in orientation, layout, position, shape, size, amount, or other measure, but rather mean an approximately identical orientation, layout, position, shape, size, amount, or other measure, including variations that can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to express this meaning. For example, "substantially the same", "substantially equal", or "substantially planar" means exactly the same, equal, or planar, or it can mean the same, equal, or planar within acceptable variations, which can occur, for example, due to manufacturing processes.

[0137] In the present disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor elements.

[0138] In the description of the present disclosure, above (or up) is the direction corresponding to the Z-direction arrow, and below (or down) is the opposite direction corresponding to the Z-direction arrow.

[0139] Figure 1 A flowchart illustrating a method 10 of manufacturing a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 A top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 A cross-sectional view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 2 A cross-sectional view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 4 A top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 A cross-sectional view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 4 A cross-sectional view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0140] Referring to Figure 1 to Figure 5 At step S11, a substrate 101 can be provided, and a first well layer 103 can be formed in the substrate 101.

[0141] Referring to Figure 2 and Figure 3 The substrate 101 can include a first well region 301. For example, in a cross-sectional view, the first well region 301 can be a rectangular area of the substrate 101. The first well region 301 can include a portion of the substrate 101 and a space above the portion of the substrate 101. Describing that an element is disposed on the first well region 301 means that the element is disposed on an upper surface of the portion of the substrate 101. Describing that an element is disposed in the first well region 301 means that the element is disposed in the portion of the substrate 101; however, an upper surface of the element can be flush with the upper surface of the portion of the substrate 101. Describing that an element is disposed above the first well region 301 means that the element is disposed above the upper surface of the portion of the substrate 101.

[0142] The substrate 101 can be a bulk semiconductor substrate. For example, the bulk semiconductor substrate can include an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II-VI compound semiconductor.

[0143] Referring to Figure 2 and Figure 3 A mask layer (not shown) can be formed on the substrate 101 to expose the first well region 301. An ion implantation process can be performed to dope the first well region 301 with a plurality of p-type dopants. The term "p-type dopant" means an impurity that, when added to a host semiconductor material, creates deficiencies in valence electrons. Examples of p-type dopants in a silicon-containing semiconductor material include boron, aluminum, gallium, or indium, but are not limited thereto. After the ion implantation process, a first well layer 103 can be formed in the first well region 301. The first well layer 103 can have a first electrical type.

[0144] Referring to Figure 4 and Figure 5 An insulating layer STI can be formed in the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101 to cover an active region 303. In a top view, the active region 303 can be smaller than the first well region 301. An etching process, such as a non-isotropic dry etching process, can be performed to form a plurality of trenches through the pad oxide layer, the pad nitride layer, and the substrate 101. Some portions of the first well layer 103 can also be removed. An isolation material can be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, can be performed until the top surface of the substrate 101 is exposed to remove excess filling material, provide a substantially planar surface for subsequent processing steps, and form the insulating layer STI at the same time. For example, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. The insulating layer STI can be disposed around the active region 303.

[0145] In the present disclosure, silicon oxynitride means a substance that includes silicon, nitrogen, and oxygen, in which a proportion of oxygen is greater than a proportion of nitrogen. Silicon nitride oxide means a substance that includes silicon, oxygen, and nitrogen, in which a proportion of nitrogen is greater than a proportion of oxygen.

[0146] Figure 6FIG. 1 illustrates a top view of a semiconductor device according to an embodiment of the present disclosure. Figure 7 FIG. 2 illustrates a cross-sectional view of the semiconductor device along the cross-sectional line A-A' of FIG. 1 according to an embodiment of the present disclosure. Figure 6

[0147] Figure 1 Figure 6 Figure 7 At step S13, an insulating mask layer 105 can be formed on the first well layer 103, and a plurality of mask openings 105O can be formed along the insulating mask layer 105 to define a plurality of programmable regions 305.

[0148] Figure 6 Figure 7 The insulating mask layer 105 can be formed on the active regions 303. A photolithography process and a subsequent etching process can be performed to form the mask openings 105O along the insulating mask layer 105. The mask openings 105O can define the programmable regions 305. The programmable regions 305 are locations for fabricating a plurality of programmable cells of a programming array, which will be described later. Each programmable region 305 can include a portion of the first well layer 103 and a space on the portion of the first well layer 103. Some portions of the upper surface of the first well layer 103 can be exposed through the mask openings 105O. The boundary of the insulating mask layer 105 can define a total area of the programming array. In this embodiment, in a top view, the insulating mask layer 105 and the mask openings 105O can have a grid pattern with four rows and four columns of the programmable regions 305. The number of the programmable regions 305 can be adjusted depending on the intended environment.

[0149] Figure 4 to Figure 7 The insulating layer STI can be formed only on the outside of the active regions 303. Therefore, a large amount of space can be used to form the programming array.

[0150] In some embodiments, for example, the insulating mask layer 105 can include a material different from the first isolation layer 111, which will be described later. In some embodiments, for example, the insulating mask layer 105 can include silicon nitride, silicon oxynitride, or silicon oxynitride. In some embodiments, the insulating mask layer 105 can include silicon nitride.

[0151] ​​​​​​​For example, the insulating shielding layer 105 may include a carbon film. As used herein, the term "carbon film" describes a material primarily composed of carbon, whose structure is mainly defined by multiple carbon atoms, or whose physical and chemical properties are controlled by its carbon content. The term "carbon film" also excludes materials that are simple mixtures or carbon-containing compounds; for example, such materials are dielectric materials, such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polycrystalline silicon.

[0152] The fabrication technology for this carbon film may involve a deposition process that includes introducing a process gas mixture into a processing chamber. This process gas mixture is composed of one or more hydrocarbon compounds. The hydrocarbon compound has the chemical formula C2. x H y Where x ranges from 2 to 4, and y ranges from 2 to 10. For example, the hydrocarbon may be propylene (C3H6), propyne (C3H4), propane (C3H8), or butane (C4H4). 10 ), butene (butylene, C4H8), butadiene (butadiene, C4H6) or acetylene (acetylene, C2H2) or combinations thereof.

[0153] In some embodiments, the carbon film can be deposited from the process gas mixture by maintaining a substrate temperature between about 100°C and about 700°C; in some embodiments, the substrate temperature is between about 350°C and about 550°C. In some embodiments, the carbon film can be deposited from the process gas mixture by maintaining a chamber temperature between about 1 Torr and about 20 Torr. In some embodiments, the carbon film can be deposited from the process gas mixture by introducing the hydrocarbon gas and an inert gas or a plurality of reactive gases, respectively, wherein the introduction of the hydrocarbon gas and the inert gas or the reactive gas is performed at a flow rate between about 50 sccm and about 200 sccm.

[0154] In some embodiments, the processing gas mixture may further include an inert gas, such as argon. However, other inert gases, such as nitrogen, or other noble gases, such as helium, may also be used. The inert gas can be used to control the density and deposition rate of the carbon film. Furthermore, different gases can be added to the processing gas mixture to modify some properties of the carbon film. The gas may be a plurality of reactive gases, such as hydrogen, ammonia, a mixture of hydrogen and nitrogen, or combinations thereof. The addition of hydrogen or ammonia can be used to control the hydrogen ratio of the carbon film, thereby controlling various properties of the layer, such as etch selectivity, chemical mechanical abrasion resistance, and reflectivity. In some embodiments, a mixture of the reactive gas and the inert gas may be added to the processing gas mixture to deposit the carbon film.

[0155] The carbon film may contain carbon and hydrogen atoms, and its carbon:hydrogen ratio may be adjustable, ranging from approximately 10% to approximately 60% hydrogen. Controlling the hydrogen ratio of the carbon film allows for adjustment of individual etch resistance and chemical mechanical abrasion resistance.

[0156] Figure 8 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 9 An embodiment of this disclosure is illustrated along the edge Figure 8 A cross-sectional view of section line A-A'. Figure 10 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 11 An embodiment of this disclosure is illustrated along the edge Figure 10 A cross-sectional view of section line A-A'.

[0157] Please refer to Figure 1 and Figure 8 to Figure 11 In step S15, a plurality of lower conductive layers 107 may be formed in the first well layer 103, and two bias layers 109 may be formed in the first well layer 103 and spaced apart from the lower conductive layers 107.

[0158] Please refer to Figure 8 and Figure 9The ion implantation process can be performed to form the lower conductive layer 107 in the programmable region 305. In other words, the lower conductive layer 107 can be formed in the first well layer 103. In some embodiments, the ion implantation process can be performed with a mask layer (not shown) covering the areas outside the active region 303. The mask layer can be removed after the lower conductive layer 107 is formed. The ion implantation process can be performed using n-type dopants. The term "n-type dopant" refers to an impurity that, when added to a intrinsic semiconductor material, donates an electron to the intrinsic semiconductor material. In a silicon-containing material, examples of the n-type dopants include antimony, arsenic, or phosphorus, but are not limited thereto. That is, the lower conductive layer 107 can have a second electrical type that is opposite to the first electrical type. The depth of the lower conductive layer 107 can be between about 0.24 μm (micrometer) and about 0.26 μm. The doping concentration of the lower conductive layer 107 can be between about 4E20 atoms / cm 3 and about 2E21 atoms / cm 3 In the present embodiment, the interfaces between the lower conductive layer 107 and the first well layer 103 can represent P-N junctions.

[0159] During the programming process, baseline voltages can be applied to the lower conductive layer 107. For example, the baseline voltages can have values of 0 volt, 3 volt, 4 volt, 5 volt, or any value between 0 volt and 5 volt.

[0160] Referring to Figure 10 and Figure 11 An implantation process can be performed to form the bias layers 109 in the first well layer 103. In some embodiments, a mask layer (not shown) can be formed to cover the insulating mask layer 105 and the programmable region 305 during the implantation process. In a top view, the bias layers 109 can be at both ends of the insulating mask layer 105. Each bias layer 109 can be separated from the lower conductive layer 107, and the insulating mask layer 105 can be interposed between each bias layer 109 and the lower conductive layer 107. In a cross-sectional view, the depth of the bias layers 109 can be shallower than the depth of the lower conductive layer 107. The implantation process can be performed using the p-type dopants. The bias layers 109 can have the first electrical type. The doping concentration of the bias layers 109 can be greater than the doping concentration of the first well layer 103. For example, the doping concentration of the bias layers 109 can be between about 4E20 atoms / cm 3 and about 2E21 atoms / cm 3 .

[0161] A plurality of bias voltages can be applied to the second biasing layer 109. The bias voltages can have a magnitude less than the magnitude of the reference voltage. For example, the bias voltages can have a magnitude of -1 volt, -2 volt, -3 volt, or any value between -0.5 volt and -3 volt. When the bias voltages are applied to the second biasing layer 109 and when the reference voltage is applied to the lower conductive layer 107, a plurality of depletion regions (not shown) can be formed to surround the lower conductive layer 107. The depletion regions can act as electrical insulators to the lower conductive layer 107.

[0162] Figure 12 A top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 13 A cross-sectional view of the intermediate semiconductor device according to an embodiment of the present disclosure along the cross-sectional line A-A'. Figure 12

[0163] Referring to Figure 1 , Figure 12 and Figure 13 , a plurality of first isolation layers 111 can be formed on the lower conductive layer 107 at step S17.

[0164] Referring to Figure 12 and Figure 13 , the first isolation layers 111 can be formed on the lower conductive layer 107. Any two adjacent first isolation layers 111 can be insulated by the insulating mask layer 105. In some embodiments, the first isolation layers 111 can comprise a material different from the insulating mask layer 105. All the first isolation layers 111 can have the same thickness. The thickness of the first isolation layers 111 can be between about and about .

[0165] In some embodiments, the fabrication technique of the first isolation layers 111 can comprise thermal oxidation, for example. The first isolation layers 111 can comprise silicon oxide, for example. The second biasing layer 109 can be masked during the formation of the first isolation layers 109.

[0166] In some embodiments, the first isolation layers 111 can comprise a high dielectric constant material, an oxide, a nitride, an oxynitride, or a combination thereof. The high dielectric constant material can comprise a hafnium-containing material. The hafnium-containing material can be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof, for example. In some embodiments, the high dielectric constant material can be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof, for example. A plurality of interface layers (not shown) can be formed between the first isolation layers 111 and the lower conductive layer 107. The interface layers can have a thickness between about and about​ Between. In some embodiments, the interface layer may have a thickness between approximately To about between.

[0167] Figure 14 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 15 and Figure 16 An embodiment of this disclosure is illustrated along the edge Figure 14 Schematic diagram of cross-sections A-A' and B-B'. Figure 17 and Figure 18 An embodiment of this disclosure is illustrated along the edge Figure 14 Schematic diagram of cross-sections A-A' and B-B'.

[0168] Please refer to Figure 1 and Figure 14 to Figure 18 In step S19, the first conductive lines FL1, FL2, FL3, and FL4 may be formed on the first isolation layer 111.

[0169] Please refer to Figure 14 to Figure 16 In the cross-sectional view, first conductive lines FL1, FL2, FL3, and FL4 may be formed on the first insulating layer 111 and imposed on the insulating shielding layer 105. During the programming process, when multiple programming voltages are applied to the first conductive lines FL1, FL2, FL3, and FL4, the insulating shielding layer 105 may provide electrical insulation to the first well layer 103 to avoid damage to the insulating structure of the lower conductive layer 107 (e.g., the multiple PN junctions formed from the interface between the lower conductive layer 107 and the first well layer 103). For example, the programming voltage may be 5.5 volts, 6.0 volts, 6.5 volts, or any value between 5.2 volts and 6.5 volts.

[0170] In a top view, the first conductive lines FL1, FL2, FL3, and FL4 may be parallel to each other and may extend along a first direction parallel to the y-axis. Each of the first conductive lines FL1, FL2, FL3, and FL4 may be outside the boundary of the insulating shielding layer 105. In some embodiments, the distance between adjacent pairs of first conductive lines may be different. In some embodiments, the distance between adjacent pairs of first conductive lines may be the same.

[0171] In some embodiments, for example, the first conductive lines FL1, FL2, FL3, and FL4 may comprise polycrystalline silicon, polycrystalline silicon germanium, or a combination thereof. In some embodiments, the first conductive lines FL1, FL2, FL3, and FL4 may be doped with multiple dopants, such as phosphorus, arsenic, antimony, or boron. In some embodiments, the first conductive lines FL1, FL2, FL3, and FL4 may have the same electrical type as the lower conductive layer 107.

[0172] In some embodiments, each of the first conductive lines FL1, FL2, FL3, FL4 can be a stack structure. For example, each of the first conductive lines FL1, FL2, FL3, FL4 can include a lower layer and an upper layer formed on the lower layer. For example, the lower layer can include polysilicon, poly-silicon germanium, or a combination thereof. For example, the upper layer can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof.

[0173] The lower conductive layer 107, the first isolation layer 111, and the first conductive lines FL1, FL2, FL3, FL4 together configure a plurality of programmable cells P01, P02,..., P16 (as shown in FIG. 1C) in the programming region 305. Figure 26 and Figure 27 The programmable cells P01, P02,..., P16 together configure the programming array.

[0174] Referring to Figure 17 and Figure 18 An interlayer dielectric 401 can be formed on the substrate 101 to cover the insulating mask layer 105, the first isolation layer 111, and the first conductive lines FL1, FL2, FL3, FL4. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially planar surface for the following processing steps. For example, the interlayer dielectric 401 can include flowable oxide, tonen silazen, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, plasma enhanced tetra-ethyl orthosilicate, fluoridesilicate glass, carbon doped silicon oxide, organo silicate glass, porous polymeric material, or a combination thereof, but not limited thereto. The interlayer dielectric 401 can provide electrical insulation for the first conductive lines FL1, FL2, FL3, FL4 and structural support for the first conductive lines FL1, FL2, FL3, FL4 and the insulating mask layer 105.

[0175] Figure 19 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 20 A cross-sectional view schematic diagram of the intermediate semiconductor element along section line A-A’ according to an embodiment of the present disclosure is shown. Figure 19 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 21 A cross-sectional view schematic diagram of the intermediate semiconductor element along section line A-A’ according to an embodiment of the present disclosure is shown. Figure 22 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 23 A cross-sectional view schematic diagram of the intermediate semiconductor element along section line A-A’ and section line B-B’ according to an embodiment of the present disclosure is shown. Figure 21 A cross-sectional view schematic diagram of the intermediate semiconductor element along section line A-A’ and section line B-B’ according to an embodiment of the present disclosure is shown.

[0176] Referring to Figure 1 and Figure 19 to Figure 23 At step S21, second conductive lines SL1, SL2, SL3, SL4 can be formed on the substrate 101 to electrically couple to the lower conductive layer 107.

[0177] Referring to Figure 19 and Figure 20 A plurality of second conductive vias 201 can be formed along the ILD 401 and the first isolation layer 111 to electrically couple to the lower conductive layer 107. The second conductive vias 201 can be located on the programming region 305 and can be disposed adjacent to the first conductive lines FL1, FL2, FL3, FL4. Each upper surface of the second conductive vias 201 and each upper surface of the ILD 401 can be substantially coplanar. For example, the second conductive vias 201 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide, or combinations thereof. The second conductive vias 201 can be electrically connected to the lower conductive layer 107.

[0178] In some embodiments, each sidewall of the second conductive via 201 can have a sloped profile. In some embodiments, a width of the second conductive via 201 can gradually become wider from bottom to top along the direction Z. In some embodiments, the second conductive via 201 can have a uniform slope throughout.

[0179] Referring to Figure 21 to Figure 23A second interlayer dielectric 403 can be formed on the second conductive via 201 and the interlayer dielectric 401. The second interlayer dielectric 403 can comprise the same material as the interlayer dielectric 401, but is not limited thereto. For example, the second conductive lines SL1, SL2, SL3, SL4 can be formed by a damascene process. In a top view, the second conductive lines SL1, SL2, SL3, SL4 can be parallel to each other and can extend along a second direction, which is perpendicular to the first direction. In a cross-sectional view, the second conductive lines SL1, SL2, SL3, SL4 can be formed on the first conductive via 201 and in the interlayer dielectric 401. The second conductive lines SL1, SL2, SL3, SL4 can be electrically coupled to the lower conductive layer 107 through the second conductive via 201.

[0180] In some embodiments, for example, the second conductive lines SL1, SL2, SL3, SL4 can comprise titanium, tantalum, tungsten, copper, or aluminum. In some embodiments, the second conductive lines SL1, SL2, SL3, SL4 can be a stacked layer structure, including a BL lower conductive layer, a BL intermediate conductive layer formed on the BL lower conductive layer, and a BL upper conductive layer formed on the BL intermediate conductive layer. For example, the BL lower conductive layer can comprise one of a doped semiconductor material (e.g., doped silicon or doped germanium), a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). For example, the BL intermediate conductive layer can comprise a conductive metal nitride (e.g., titanium nitride or tantalum nitride). For example, the BL upper conductive layer can comprise a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0181] Figure 24 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 25 A cross-sectional view schematic diagram of a cross-section A-A’ of Figure 24 is shown. Figure 26 A top view schematic diagram of a semiconductor element 1A according to an embodiment of the present disclosure is shown. Figure 27 A cross-sectional view schematic diagram of a cross-section A-A’ of Figure 26 is shown.

[0182] Referring to Figure 1 and Figure 24 to Figure 27 , two first conductive layers 113 can be formed on the second conductive lines SL1, SL2, SL3, SL4 to electrically couple to the bias layers 109 at step S23.

[0183] Referring to Figure 24 and Figure 25An interlayer dielectric layer 405 can be formed on the interlayer dielectric 403. The interlayer dielectric 405 can comprise the same material as the interlayer dielectric 403, but is not limited thereto.

[0184] Referring to Figure 24 and Figure 25 A plurality of bias layer vias 203 can be formed along the interlayer dielectrics 401, 403, 405 to electrically connect to the bias layers 109. Meanwhile, a plurality of first conductive vias 205 can be formed along the interlayer dielectrics 401, 403, 405 to electrically connect to the respective upper ends of the first conductive lines FL1, FL2, FL3, FL4. The bias layer vias 203 and the first conductive vias 205 can have the same inclined sidewalls as the second conductive vias 201.

[0185] Referring to Figure 26 and Figure 27 An interlayer dielectric 407 can be formed on the interlayer dielectric 405. The interlayer dielectric 407 can comprise the same material as the interlayer dielectric 405, but is not limited thereto.

[0186] In a top view, the two first conductive layers 113 can be parallel to each other and can extend along the first direction. In a cross-sectional view, the two first conductive layers 113 can be formed on the bias layer vias 203 and in the interlayer dielectric 407. The two first conductive layers 113 can comprise a damascene process. For example, the two first conductive layers 113 can comprise titanium, tantalum, tungsten, copper, or aluminum. The two first conductive layers 113 can be electrically connected to the bias layers 109 through the bias layer vias 203.

[0187] During a program operation, the programmed programmable cells (selected programmable cells) can be determined by the reference voltage applied to the second conductive lines SL1, SL2, SL3, SL4 and the program voltage applied to the first conductive lines FL1, FL2, FL3, FL4. Generally, the first conductive line electrically coupled to the selected programmable cells is applied with a program voltage V P . The program voltage V P may be 5.5 volts, 6.0 volts, 6.5 volts, or any value between 5.2 volts and 6.5 volts. The voltage applied to the first conductive line not electrically coupled to the selected programmable cells can be set to at least half of the program voltage V P or 0 volts or close to 0 volts. The second conductive line electrically coupled to the selected programmable cells can be applied with a reference voltage V BL . The reference voltage V BLThe voltage applied to the second conductive lines that are not electrically coupled to the selected programmable cells can be set to zero or near zero. The voltage applied to the second conductive lines that are not electrically coupled to the selected programmable cells can be set to at least half of the programming voltage V P By applying different voltages to the first conductive lines and the second conductive lines, the programmable cells can be programmed one at a time or multiple programmable cells can be programmed simultaneously.

[0188] For example, when programmable cell P01 is programmed, the first conductive line FL1 can be set to a programming voltage of 6 volts, while the voltages of the first conductive lines FL2, FL3, FL4 can be set to 4 volts, the second conductive line SL1 can be grounded, and the voltages of the second conductive lines SL2, SL3, SL4 can be set to 4 volts. As a result of this programming scheme, a good voltage difference can be applied to the upper and lower surfaces of the first isolation layer 111 of programmable cell P01 to form a strong electric field. The resulting strong electric field in the first isolation layer 111 causes the first isolation layer 111 to breakdown. As a result, programmable cell P01 is blown and programmed.

[0189] As another example, when programmable cells P01, P10 are programmed, the first conductive line FL2 can be set to a programming voltage of 6 volts, while the voltages of the first conductive lines FL1, FL3, FL4 can be set to 4 volts, the second conductive lines SL1, SL3 can be grounded, and the voltages of the second conductive lines SL2, SL4 can be set to 4 volts. As a result of this programming scheme, strong electric fields can be formed in the first isolation layers 111 of programmable cells P02, P10, respectively. The resulting strong electric fields in the first isolation layers 111 cause the first isolation layers 111 to breakdown. As a result, programmable cells P02, P10 are blown and programmed simultaneously.

[0190] During operation of semiconductor element 1A, a bias voltage can be continuously applied to the bias layer 109 via the first conductive layer 113. The bias voltage can have a value that is less than the voltage (e.g., a reference voltage) applied to the lower conductive layers 107. The voltage difference between the bias voltage and the reference voltage can form a plurality of depletion regions around the lower conductive layers 107 to electrically insulate adjacent pairs of lower conductive layers 107. That is, no other electrically insulating structure, such as a dielectric layer, is needed between adjacent pairs of lower conductive layers 107. Accordingly, the uniformity of the thickness of the first isolation layer 111 can be improved due to the lack of interfering dielectric layers, such as shallow trench isolation. As a result, the reliability of programming of semiconductor element 1A can be improved.

[0191] Figure 28A cross-sectional view of a semiconductor device 1B along section line A-A' of FIG. 1B is shown in FIG. 2B. Figure 8 A cross-sectional view of a semiconductor device 1B along section line A-A' of FIG. 1B is shown in FIG. 2B. Figure 29 A top view of a semiconductor device 1B is shown in FIG. 2C. Figure 30 A cross-sectional view of a semiconductor device 1B along section line A-A' of FIG. 1B is shown in FIG. 2B. Figure 29 A cross-sectional view of a semiconductor device 1B along section line A-A' of FIG. 1B is shown in FIG. 2B. Figure 31 A top view of a semiconductor device 1B is shown in FIG. 2C. Figure 32 A cross-sectional view of a semiconductor device 1B along section line A-A' of FIG. 1B is shown in FIG. 2B. Figure 31 A cross-sectional view of a semiconductor device 1B along section line A-A' of FIG. 1B is shown in FIG. 2B.

[0192] Referring to FIG. 1A, Figure 28 an implantation mask layer 501 can be formed on the substrate 101 to cover the bias layer 109 and some portions of the lower conductive layer 107. For example, the two sides of the lower conductive layer 107 in Figure 28 may be covered by the implantation mask layer 501, and the lower conductive layer 107 in the middle of Figure 28 may be exposed. Next, a nitrogen implantation process can be performed on the exposed lower conductive layer 107. After the nitrogen implantation, the implantation mask layer 501 can be removed.

[0193] Referring to FIG. 1A, Figure 29 and Figure 30 For example, the fabrication techniques of the first isolation layer 111 and the second isolation layer 115 can include thermal oxidation. Due to the nitrogen implantation, the first isolation layer 111 and the second isolation layer 115 can have different thicknesses. The thickness of the first isolation layer 111 formed on the exposed lower conductive layer 107 during the nitrogen implantation process is thinner than the thickness of the second isolation layer 115 formed on the covered lower conductive layer 107 during the nitrogen implantation process. When the critical programming voltage can be affected by the thickness of the isolation layer, the programmable cells composed of the first isolation layer 111 and the second isolation layer 115 can have different critical programming voltages.

[0194] Referring to FIG. 1A, Figure 31 and Figure 32 The fabrication techniques of other elements of the semiconductor device 1B can include a procedure similar to that described in Figure 17 to Figure 27 In this embodiment, the programmable cells with different critical voltages (e.g., programmable cells P05, P06) can be used for different purposes.

[0195] Figure 33 A cross-sectional view of a semiconductor device 1C along section line A-A' of FIG. 1C is shown in FIG. 3B. Figure 31 A cross-sectional view of a semiconductor device 1C along section line A-A' of FIG. 1C is shown in FIG. 3B.

[0196] Please refer to Figure 33 Semiconductor element 1C may have similar characteristics to, for example Figure 32 The aforementioned structure. In Figure 33 Similar to or the same as Figure 32 The components are identified by similar component numbers, and their redundant descriptions have been omitted. Semiconductor component 1C may include a plurality of first spacers FLS. The first spacers FLS may be disposed on the sidewalls of the first conductive lines FL1, FL2, FL3, and FL4. In some embodiments, for example, the first spacers FLS may comprise a dielectric material that is different from the first isolation layer 111 or the second isolation layer 115. In some embodiments, for example, the first spacers FLS comprise silicon nitride. The first spacers FLS may provide additional electrical insulation to the first conductive lines FL1, FL2, FL3, and FL4. The first spacers FLS may also provide additional protection during the formation of the second conductive via 201.

[0197] Figure 34 A top view schematic diagram of a semiconductor element 1D illustrating another embodiment of the present disclosure is shown. Figure 35 Example of another embodiment of this disclosure Figure 34 A cross-sectional view of section line A-A'.

[0198] Please refer to Figure 34 and Figure 35 The semiconductor device 1D may have a plurality of second spacers SLS. The second spacers SLS may be disposed on the sidewalls of the second conductive lines SL1, SL2, SL3, and SL4. For example, the second spacers SLS may comprise silicon nitride, silicon oxynitride, or silicon nitride oxide. The second spacers SLS may provide additional electrical insulation to the second conductive lines SL1, SL2, SL3, and SL4.

[0199] Figure 36 to Figure 38 Examples of some semiconductor elements 1E, 1F, 1G along another embodiment of this disclosure Figure 26 A cross-sectional view of section line A-A'.

[0200] Please refer to Figure 36 Semiconductor element 1E may have similar characteristics to, for example Figure 27 The aforementioned structure. In Figure 36 Similar to or the same as Figure 27 The components are already identified with similar component numbers, and their redundant descriptions have been omitted.

[0201] Please refer to Figure 36semiconductor element 1E can include a plurality of tips 117. For ease of description, only one tip 117, one first isolation layer 111, and one lower conductive layer 107 are described. The tip 117 can be disposed between the lower conductive layer 107 and the first isolation layer 111. The tip 117 can have a cross-sectional profile that is triangular in shape. In some embodiments, the tip 117 can have a cross-sectional profile that is diamond-shaped, pentagon-shaped, or a shape having more than five sides. For example, the tip 117 can include silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, indium phosphide, or other group IV-IV, group III-V, or group II-VI semiconductor materials.

[0202] Referring to Figure 36 , the first isolation layer 111 can be disposed on the tip 117 and the lower conductive layer 107. The first isolation layer 111 can have a cap portion 111C and two flat portions 111F. The cap portion 111C can be disposed on both sides of the tip 117. The two flat portions 111F can correspond to the ends connected to the cap portion 111C, respectively. A thickness of the two flat portions 111F can be greater than or equal to a thickness of the cap portion 111C. In some embodiments, the thickness of the two flat portions 111F can be greater than the thickness of the cap portion 111C.

[0203] During programming of the semiconductor element 1E, the apex of the tip 117 can be the most vulnerable site because the electric field is concentrated at the sharp profile. Since the apex of the tip 117 can attain the highest electric field, the cap portion 111C can collapse to form a rupture point of the cap portion 111C adjacent to the apex of the tip 117, and can thereby cause a resistance reduction. Thus, the semiconductor element 1E can be blown and programmed. During programming, the location of the rupture point of the cap portion 111C can be easily confined to the location adjacent to the apex of the tip 117 having the highest electric field. As such, the reliability of programming of the semiconductor element 1E can be improved.

[0204] Referring to Figure 37 , the semiconductor element 1F can have a structure similar to that described in Figure 27 . In Figure 37 , elements similar to or the same as those in Figure 27 have been designated with similar element numbers, and repetitive descriptions thereof have been omitted.

[0205] Referring to Figure 37The semiconductor device 1F may include a first auxiliary layer 119. The first auxiliary layer 119 may be formed between the bias layer via 203 and the bias layer 109. The thickness of the first auxiliary layer 119 may be between approximately 2 nm and approximately 20 nm. For example, the first auxiliary layer 119 may comprise titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The first auxiliary layer 119 may reduce the resistance between the bias layer via 203 and the bias layer 109. Accordingly, the performance of the semiconductor device 1F may be improved.

[0206] Please refer to Figure 38 Semiconductor element 1G can have similar characteristics to, for example... Figure 27 The aforementioned structure. In Figure 38 Similar to or the same as Figure 27 The components are already identified with similar component numbers, and their redundant descriptions have been omitted.

[0207] Please refer to Figure 38 The semiconductor device 1G may include a deep well layer 121. In some embodiments, the deep well layer 121 may be disposed below a first well layer 103. In some embodiments, the deep well layer 121 may be disposed around the first well layer 103. The deep well layer 121 may have a second electrical type, which is opposite to the first electrical type of the first well layer 103. The doping concentration of the deep well layer 121 may be less than the doping concentration of the first well layer 103. For example, the doping concentration of the deep well layer 121 may be between approximately 1E16 / cm². 3 Up to approximately 1E18 / cm 3 Between. During a programming process, the presence of deep well layer 121 can effectively reduce read voltage offset, allowing for faster read speeds and lower read voltages, as well as reducing leakage current.

[0208] In some embodiments, substrate 101 may include an insulator-on-semiconductor structure comprising, from bottom to top, a handle substrate, an insulator layer, and an uppermost semiconductor material layer. The handle substrate and the uppermost semiconductor material layer contain the same materials as the aforementioned bulk semiconductor substrate. The insulator layer may be a crystalline or non-crystalline dielectric material, such as an oxide and / or nitride. For example, the insulator layer may be a dielectric oxide, such as silicon oxide. As another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. As yet another example, the insulator layer may include a stack of a dielectric oxide and a dielectric nitride, such as silicon oxide and a stack of silicon nitride or boron nitride in any order. The insulator layer may have a thickness between approximately 10 nm and approximately 200 nm.

[0209] One embodiment of the present disclosure provides a semiconductor device having a substrate; a first well layer in the substrate and having a first electrical type; a lower conductive layer in the first well layer and having a second electrical type opposite to the first electrical type; a first isolation layer on the lower conductive layer; an insulating mask layer on the substrate and surrounding the first isolation layer; a first conductive line on the first isolation layer; and a bias layer in the first well layer and spaced apart from the lower conductive layer. The lower conductive layer, the first isolation layer, and the first conductive line together configure a programmable cell.

[0210] One embodiment of the present disclosure provides a semiconductor device having a substrate including a first well region; a first well layer in the first well region and having a first electrical type; a plurality of lower conductive layers in the first well layer and spaced apart from each other, wherein the lower conductive layers have a second electrical type opposite to the first electrical type; a plurality of first isolation layers on the lower conductive layers; an insulating mask layer on the first well region and surrounding the first isolation layers; a plurality of first conductive lines on the first isolation layers and arranged parallel to each other; and a bias layer in the first well layer and spaced apart from the lower conductive layers. The lower conductive layers, the first isolation layers, and the first conductive lines together configure a plurality of programmable cells.

[0211] Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device, including providing a substrate; forming a first well layer in the substrate and having a first electrical type; forming an insulating mask layer on the first well layer; forming a plurality of mask openings along the insulating mask layer to expose portions of the first well layer; forming a plurality of lower conductive layers in the portions of the first well layer, wherein the lower conductive layers have a second electrical type opposite to the first electrical type; forming a bias layer in the first well layer and spaced apart from the lower conductive layers; forming a plurality of first isolation layers on the lower conductive layers; and forming a plurality of first conductive lines on the first isolation layers and arranged parallel to each other. The lower conductive layers, the first isolation layers, and the first conductive lines together configure a plurality of programmable cells.

[0212] Due to the design of the semiconductor device of the present disclosure, the lower conductive layer 107 is electrically insulated in the presence of a bias voltage applied to the first well layer 103. As such, a large area of the substrate 101 can be saved for more functional elements, such as programmable cells. In addition, the uniformity of the first isolation layer 111 can also be improved. As such, the reliability of the programmed semiconductor device 1A can be improved.

[0213] For clarity, some elements such as some interlayer dielectrics can be omitted in some of the top view figures. While the present disclosure has been particularly shown and described with references to particular embodiments, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes can be performed with different hardware or in a different order than shown and described. Other processes can be added or substituted for the processes described to achieve the same results.

[0214] Further, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of one or more embodiments of the application is intended not to limit the scope of the claims, but is intended to be illustrative of many alternatives that are available to one skilled in the art. Numerous modifications and adaptations will be apparent. Accordingly, the scope of the application is defined only by the following claims.

Claims

1. A semiconductor device, comprising: a substrate; a first well layer in the substrate and having a first electrical type; a lower conductive layer in the first well layer and having a second electrical type opposite to the first electrical type; a first isolation layer on the lower conductive layer; an insulating mask layer on the substrate and surrounding the first isolation layer; a first conductive line on the first isolation layer; a second conductive line on the lower conductive layer and electrically coupled to the lower conductive layer; and a bias layer in the first well layer and spaced apart from the lower conductive layer; wherein the lower conductive layer, the first isolation layer, and the first conductive line together configure a programmable cell.

2. The semiconductor device of claim 1, further comprising a first conductive layer on the bias layer and electrically coupled to the bias layer.

3. The semiconductor device of claim 2, wherein the bias layer has the same electrical type as the first well layer, and a doping concentration of the bias layer is greater than a doping concentration of the first well layer.

4. The semiconductor device of claim 3, wherein in a cross-sectional view, the first conductive line extends along a first direction, and the second conductive line extends along a second direction perpendicular to the first direction.

5. The semiconductor device of claim 4, wherein a thickness of the first isolation layer is between about 30 nm and about 70 nm.

6. The semiconductor device of claim 5, further comprising a first auxiliary layer on the bias layer; wherein the first auxiliary layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

7. The semiconductor device of claim 6, wherein a thickness of the first auxiliary layer is between about 2 nm and about 20 nm.

8. The semiconductor device of claim 5, further comprising a plurality of first gap spacers on sidewalls of the first conductive line; wherein the first gap spacers comprise a dielectric material different from the first isolation layer.

9. The semiconductor device of claim 5, further comprising a plurality of second gap spacers on sidewalls of the second conductive line; wherein the second gap spacers comprise silicon nitride, silicon oxynitride, or silicon oxynitride.

10. The semiconductor device of claim 5, further comprising a tip between the first isolation layer and the lower conductive layer; wherein the tip comprises silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, or indium phosphide.

11. The semiconductor device of claim 10, wherein the first isolation layer comprises a cap layer on the tip and a plurality of flat portions connected to two ends of the cap layer and on the lower conductive layer.

12. The semiconductor device of claim 5, further comprising a deep well layer around the first well layer and having the second electrical type.

13. A semiconductor device, comprising: a substrate comprising a first well region; a first well layer in the first well region and having a first electrical type; a lower conductive layer in the first well layer and having a second electrical type opposite to the first electrical type; a plurality of lower conductive layers disposed in the first well layer and spaced apart from each other, wherein the lower conductive layers have a second electrical type opposite to the first electrical type; a plurality of first isolation layers disposed on the lower conductive layers; an insulating mask layer disposed on the first well region and surrounding the first isolation layers; a plurality of first conductive lines disposed on the first isolation layers and parallel to each other; a plurality of second conductive lines disposed on the first conductive lines and parallel to each other, wherein the second conductive lines are electrically coupled to the lower conductive layers; and a bias layer disposed in the first well layer and spaced apart from the lower conductive layers. wherein the lower conductive layers, the first isolation layers, and the first conductive lines together configure a plurality of programmable cells.

14. The semiconductor element of claim 13, wherein the first isolation layers have the same thickness.

15. The semiconductor element of claim 13, wherein the first isolation layers have different thicknesses.

16. A method of fabricating a semiconductor element, comprising: providing a substrate; forming a first well layer in the substrate and having a first electrical type; forming an insulating mask layer on the first well layer; forming a plurality of mask openings along the insulating mask layer to expose portions of the first well layer; forming a plurality of lower conductive layers in the portions of the first well layer, wherein the lower conductive layers have a second electrical type opposite to the first electrical type; forming a bias layer in the first well layer and spaced apart from the lower conductive layers; forming a plurality of first isolation layers on the lower conductive layers; forming a plurality of first conductive lines on the first isolation layers and parallel to each other; and forming a plurality of second conductive lines on the first conductive lines to electrically couple to the lower conductive layers; wherein the lower conductive layers, the first isolation layers, and the first conductive lines together configure a plurality of programmable cells.

17. The method of fabricating a semiconductor element of claim 16, further comprising a step of forming a first conductive layer on the bias layer to electrically couple to the bias layer.

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